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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u23-20020a056a00099700b006884549adc8sm4359777pfg.29.2023.11.05.12.12.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Nov 2023 12:12:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699215146; x=1699819946; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ETzV90iWfq68Qou4N/sY5beJ+DnMwUACRile3KCErJo=; b=c/tckkRBdMEENGWtQTeFGjPBMuWh6eAyMR80+zQgH0cxmgNmpjCG0Yn3zE7imGlkXv 6a4Htvdrmv+kShKKhpqle1fRvLj/RDdk7qTkdhs+0MZSen6SEH1xStNp3IgSaClaLbml VEvyLsgZV2ynlrZEW5nCKdG8n1NlzPxFm1dL7Qji/uSdPs3+EktOvNl/xipFjGJBvcZp JSPj8Hj/ViUGuckB6NH+J7eOjsPH3q0W7JvqzTHE8CCqxUbTnP839aHoVtP5LKN15s/1 BCEmJWPmrw5Mm0geTqDAuRgUk7Vd0htKHid7h63hznkvRLCB+xLzx44QwetpjCgoWV4e gjBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699215146; x=1699819946; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ETzV90iWfq68Qou4N/sY5beJ+DnMwUACRile3KCErJo=; b=lvriPaO1PdHhQ9D1w79jQ/nYk2rKGZakL0mYWcxqP2u142Igyerd+FeZFBxUf01zOa Qbbw/qzFC1Jx3qxLeIfJGv7BJrCPoDmo1Lja4SwpCIYJ7uf8xiLXw/b+PqcNTxoc2HMj O26Cq8h66WTzrk8qJO9JBgoLy3hktpAkQ7laWaS+udG7y+ZLzukM8TdAFg7ftG28+Drr JCk/MiGNJ9qDEFnL93I/mxpZKUoASLq+OJENki1WTl5ER24FQL//XtQDrefrOgRB87si fvXPaz003Msz0/XBpBqJEUWD6wVBWnFk0pmZ3PQP0H4LQhyKaBgJa2OMWP2jEWfi+dGB 7Zsw== X-Gm-Message-State: AOJu0YzlZaOHRtDz48AvCMxfJ/oqMaPBcw6g4Cey3BxSBvxUHXbSQN78 GWI25/8qFgXlLMmzaUfAiDbhDJXr4oOBEp6AkIs= X-Google-Smtp-Source: AGHT+IGPz4gFEieby2z/5NorNxkKgympOf+8hfgPgAuThKymOFcqFEJtnye9AQ7Wt1NIXxtYyJPPwQ== X-Received: by 2002:a05:6a00:2e07:b0:6b3:f29c:dde1 with SMTP id fc7-20020a056a002e0700b006b3f29cdde1mr25550826pfb.21.1699215145656; Sun, 05 Nov 2023 12:12:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 02/21] target/sparc: Split psr and xcc into components Date: Sun, 5 Nov 2023 12:12:03 -0800 Message-Id: <20231105201222.202395-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231105201222.202395-1-richard.henderson@linaro.org> References: <20231105201222.202395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215365081100001 Content-Type: text/plain; charset="utf-8" Step in removing CC_OP: change the representation of CC_OP_FLAGS. The 8 bits are distributed between 6 variables, which should make it easy to keep up to date. The code within cc_helper.c is quite ugly but is only temporary. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- linux-user/sparc/target_cpu.h | 17 +- target/sparc/cpu.h | 30 ++- linux-user/sparc/cpu_loop.c | 6 +- target/sparc/cc_helper.c | 51 +++-- target/sparc/machine.c | 45 ++++- target/sparc/translate.c | 362 +++++++++++++--------------------- target/sparc/win_helper.c | 52 ++++- 7 files changed, 291 insertions(+), 272 deletions(-) diff --git a/linux-user/sparc/target_cpu.h b/linux-user/sparc/target_cpu.h index 1f4bed50f4..5f62c5eb75 100644 --- a/linux-user/sparc/target_cpu.h +++ b/linux-user/sparc/target_cpu.h @@ -26,6 +26,17 @@ # define TARGET_STACK_BIAS 0 #endif =20 +static void set_syscall_C(CPUSPARCState *env, bool val) +{ +#ifndef TARGET_SPARC64 + env->icc_C =3D val; +#elif defined(TARGET_ABI32) + env->icc_C =3D (uint64_t)val << 32; +#else + env->xcc_C =3D val; +#endif +} + static inline void cpu_clone_regs_child(CPUSPARCState *env, target_ulong n= ewsp, unsigned flags) { @@ -58,11 +69,7 @@ static inline void cpu_clone_regs_child(CPUSPARCState *e= nv, target_ulong newsp, * do the pc advance twice. */ env->regwptr[WREG_O0] =3D 0; -#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) - env->xcc &=3D ~PSR_CARRY; -#else - env->psr &=3D ~PSR_CARRY; -#endif + set_syscall_C(env, 0); env->pc =3D env->npc; env->npc =3D env->npc + 4; } diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 955329f6c9..ea8a04c6e3 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -149,7 +149,7 @@ enum { */ enum { CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ - CC_OP_FLAGS, /* all cc are back in status register */ + CC_OP_FLAGS, /* all cc are back in cc_*_[NZCV] registers */ CC_OP_DIV, /* modify N, Z and V, C =3D 0*/ CC_OP_ADD, /* modify all flags, CC_DST =3D res, CC_SRC =3D src1 */ CC_OP_ADDX, /* modify all flags, CC_DST =3D res, CC_SRC =3D src1 */ @@ -458,6 +458,32 @@ struct CPUArchState { target_ulong npc; /* next program counter */ target_ulong y; /* multiply/divide register */ =20 + /* + * Bit 31 is for icc, bit 63 for xcc. + * Other bits are garbage. + */ + target_long cc_N; + target_long cc_V; + + /* + * Z is represented as =3D=3D 0; any non-zero value is !Z. + * For sparc64, the high 32-bits of icc.Z are garbage. + */ + target_ulong icc_Z; +#ifdef TARGET_SPARC64 + target_ulong xcc_Z; +#endif + + /* + * For sparc32, icc.C is boolean. + * For sparc64, xcc.C is boolean; + * icc.C is bit 32 with other bits garbage. + */ + target_ulong icc_C; +#ifdef TARGET_SPARC64 + target_ulong xcc_C; +#endif + /* emulator internal flags handling */ target_ulong cc_src, cc_src2; target_ulong cc_dst; @@ -466,7 +492,6 @@ struct CPUArchState { target_ulong cond; /* conditional branch result (XXX: save it in a temporary register when possible) */ =20 - uint32_t psr; /* processor state register */ target_ulong fsr; /* FPU state register */ CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ uint32_t cwp; /* index of current register window (extracted @@ -522,7 +547,6 @@ struct CPUArchState { #define MAXTL_MAX 8 #define MAXTL_MASK (MAXTL_MAX - 1) trap_state ts[MAXTL_MAX]; - uint32_t xcc; /* Extended integer condition codes */ uint32_t asi; uint32_t pstate; uint32_t tl; diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index b36bb2574b..c1a2362041 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -197,10 +197,8 @@ static uint32_t do_getpsr(CPUSPARCState *env) /* Avoid ifdefs below for the abi32 and abi64 paths. */ #ifdef TARGET_ABI32 #define TARGET_TT_SYSCALL (TT_TRAP + 0x10) /* t_linux */ -#define syscall_cc psr #else #define TARGET_TT_SYSCALL (TT_TRAP + 0x6d) /* tl0_linux64 */ -#define syscall_cc xcc #endif =20 /* Avoid ifdefs below for the v9 and pre-v9 hw traps. */ @@ -240,10 +238,10 @@ void cpu_loop (CPUSPARCState *env) break; } if ((abi_ulong)ret >=3D (abi_ulong)(-515)) { - env->syscall_cc |=3D PSR_CARRY; + set_syscall_C(env, 1); ret =3D -ret; } else { - env->syscall_cc &=3D ~PSR_CARRY; + set_syscall_C(env, 0); } env->regwptr[0] =3D ret; /* next instruction */ diff --git a/target/sparc/cc_helper.c b/target/sparc/cc_helper.c index 7ad5b9b29e..46bec69d96 100644 --- a/target/sparc/cc_helper.c +++ b/target/sparc/cc_helper.c @@ -21,16 +21,6 @@ #include "cpu.h" #include "exec/helper-proto.h" =20 -static uint32_t compute_all_flags(CPUSPARCState *env) -{ - return env->psr & PSR_ICC; -} - -static uint32_t compute_C_flags(CPUSPARCState *env) -{ - return env->psr & PSR_CARRY; -} - static inline uint32_t get_NZ_icc(int32_t dst) { uint32_t ret =3D 0; @@ -44,16 +34,6 @@ static inline uint32_t get_NZ_icc(int32_t dst) } =20 #ifdef TARGET_SPARC64 -static uint32_t compute_all_flags_xcc(CPUSPARCState *env) -{ - return env->xcc & PSR_ICC; -} - -static uint32_t compute_C_flags_xcc(CPUSPARCState *env) -{ - return env->xcc & PSR_CARRY; -} - static inline uint32_t get_NZ_xcc(target_long dst) { uint32_t ret =3D 0; @@ -422,7 +402,6 @@ typedef struct CCTable { =20 static const CCTable icc_table[CC_OP_NB] =3D { /* CC_OP_DYNAMIC should never happen */ - [CC_OP_FLAGS] =3D { compute_all_flags, compute_C_flags }, [CC_OP_DIV] =3D { compute_all_div, compute_C_div }, [CC_OP_ADD] =3D { compute_all_add, compute_C_add }, [CC_OP_ADDX] =3D { compute_all_addx, compute_C_addx }, @@ -438,7 +417,6 @@ static const CCTable icc_table[CC_OP_NB] =3D { #ifdef TARGET_SPARC64 static const CCTable xcc_table[CC_OP_NB] =3D { /* CC_OP_DYNAMIC should never happen */ - [CC_OP_FLAGS] =3D { compute_all_flags_xcc, compute_C_flags_xcc }, [CC_OP_DIV] =3D { compute_all_logic_xcc, compute_C_logic }, [CC_OP_ADD] =3D { compute_all_add_xcc, compute_C_add_xcc }, [CC_OP_ADDX] =3D { compute_all_addx_xcc, compute_C_addx_xcc }, @@ -454,18 +432,37 @@ static const CCTable xcc_table[CC_OP_NB] =3D { =20 void helper_compute_psr(CPUSPARCState *env) { - uint32_t new_psr; + if (CC_OP =3D=3D CC_OP_FLAGS) { + return; + } =20 - new_psr =3D icc_table[CC_OP].compute_all(env); - env->psr =3D new_psr; + uint32_t icc =3D icc_table[CC_OP].compute_all(env); #ifdef TARGET_SPARC64 - new_psr =3D xcc_table[CC_OP].compute_all(env); - env->xcc =3D new_psr; + uint32_t xcc =3D xcc_table[CC_OP].compute_all(env); + + env->cc_N =3D deposit64(-(icc & PSR_NEG), 32, 32, -(xcc & PSR_NEG)); + env->cc_V =3D deposit64(-(icc & PSR_OVF), 32, 32, -(xcc & PSR_OVF)); + env->icc_C =3D (uint64_t)icc << (32 - PSR_CARRY_SHIFT); + env->xcc_C =3D (xcc >> PSR_CARRY_SHIFT) & 1; + env->xcc_Z =3D ~xcc & PSR_ZERO; +#else + env->cc_N =3D -(icc & PSR_NEG); + env->cc_V =3D -(icc & PSR_OVF); + env->icc_C =3D (icc >> PSR_CARRY_SHIFT) & 1; #endif + env->icc_Z =3D ~icc & PSR_ZERO; + CC_OP =3D CC_OP_FLAGS; } =20 uint32_t helper_compute_C_icc(CPUSPARCState *env) { + if (CC_OP =3D=3D CC_OP_FLAGS) { +#ifdef TARGET_SPARC64 + return extract64(env->icc_C, 32, 1); +#else + return env->icc_C; +#endif + } return icc_table[CC_OP].compute_c(env) >> PSR_CARRY_SHIFT; } diff --git a/target/sparc/machine.c b/target/sparc/machine.c index 274e1217df..44dfc07014 100644 --- a/target/sparc/machine.c +++ b/target/sparc/machine.c @@ -83,6 +83,42 @@ static const VMStateInfo vmstate_psr =3D { .put =3D put_psr, }; =20 +#ifdef TARGET_SPARC64 +static int get_xcc(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field) +{ + SPARCCPU *cpu =3D opaque; + CPUSPARCState *env =3D &cpu->env; + uint32_t val =3D qemu_get_be32(f); + + /* Do not clobber icc.[NV] */ + env->cc_N =3D deposit64(env->cc_N, 32, 32, -(val & PSR_NEG)); + env->cc_V =3D deposit64(env->cc_V, 32, 32, -(val & PSR_OVF)); + env->xcc_Z =3D ~val & PSR_ZERO; + env->xcc_C =3D (val >> PSR_CARRY_SHIFT) & 1; + + return 0; +} + +static int put_xcc(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field, JSONWriter *vmdesc) +{ + SPARCCPU *cpu =3D opaque; + CPUSPARCState *env =3D &cpu->env; + uint32_t val =3D cpu_get_ccr(env); + + /* Extract just xcc out of ccr and shift into legacy position. */ + qemu_put_be32(f, (val & 0xf0) << (20 - 4)); + return 0; +} + +static const VMStateInfo vmstate_xcc =3D { + .name =3D "xcc", + .get =3D get_xcc, + .put =3D put_xcc, +}; +#endif + static int cpu_pre_save(void *opaque) { SPARCCPU *cpu =3D opaque; @@ -155,7 +191,14 @@ const VMStateDescription vmstate_sparc_cpu =3D { VMSTATE_UINT32(env.mmu_version, SPARCCPU), VMSTATE_STRUCT_ARRAY(env.ts, SPARCCPU, MAXTL_MAX, 0, vmstate_trap_state, trap_state), - VMSTATE_UINT32(env.xcc, SPARCCPU), + { + .name =3D "xcc", + .version_id =3D 0, + .size =3D sizeof(uint32_t), + .info =3D &vmstate_xcc, + .flags =3D VMS_SINGLE, + .offset =3D 0, + }, VMSTATE_UINT32(env.asi, SPARCCPU), VMSTATE_UINT32(env.pstate, SPARCCPU), VMSTATE_UINT32(env.tl, SPARCCPU), diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 986a88c4e1..261f142636 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -107,19 +107,35 @@ static TCGv_ptr cpu_regwptr; static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst; static TCGv_i32 cpu_cc_op; -static TCGv_i32 cpu_psr; static TCGv cpu_fsr, cpu_pc, cpu_npc; static TCGv cpu_regs[32]; static TCGv cpu_y; static TCGv cpu_tbr; static TCGv cpu_cond; +static TCGv cpu_cc_N; +static TCGv cpu_cc_V; +static TCGv cpu_icc_Z; +static TCGv cpu_icc_C; #ifdef TARGET_SPARC64 -static TCGv_i32 cpu_xcc, cpu_fprs; +static TCGv cpu_xcc_Z; +static TCGv cpu_xcc_C; +static TCGv_i32 cpu_fprs; static TCGv cpu_gsr; #else # define cpu_fprs ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_gsr ({ qemu_build_not_reached(); (TCGv)NULL; }) #endif + +#ifdef TARGET_SPARC64 +#define cpu_cc_Z cpu_xcc_Z +#define cpu_cc_C cpu_xcc_C +#else +#define cpu_cc_Z cpu_icc_Z +#define cpu_cc_C cpu_icc_C +#define cpu_xcc_Z ({ qemu_build_not_reached(); NULL; }) +#define cpu_xcc_C ({ qemu_build_not_reached(); NULL; }) +#endif + /* Floating point registers */ static TCGv_i64 cpu_fpr[TARGET_DPREGS]; =20 @@ -366,31 +382,6 @@ static void gen_goto_tb(DisasContext *s, int tb_num, } } =20 -// XXX suboptimal -static void gen_mov_reg_N(TCGv reg, TCGv_i32 src) -{ - tcg_gen_extu_i32_tl(reg, src); - tcg_gen_extract_tl(reg, reg, PSR_NEG_SHIFT, 1); -} - -static void gen_mov_reg_Z(TCGv reg, TCGv_i32 src) -{ - tcg_gen_extu_i32_tl(reg, src); - tcg_gen_extract_tl(reg, reg, PSR_ZERO_SHIFT, 1); -} - -static void gen_mov_reg_V(TCGv reg, TCGv_i32 src) -{ - tcg_gen_extu_i32_tl(reg, src); - tcg_gen_extract_tl(reg, reg, PSR_OVF_SHIFT, 1); -} - -static void gen_mov_reg_C(TCGv reg, TCGv_i32 src) -{ - tcg_gen_extu_i32_tl(reg, src); - tcg_gen_extract_tl(reg, reg, PSR_CARRY_SHIFT, 1); -} - static void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) { tcg_gen_mov_tl(cpu_cc_src, src1); @@ -640,13 +631,11 @@ static void gen_op_mulscc(TCGv dst, TCGv src1, TCGv s= rc2) tcg_gen_deposit_tl(cpu_y, t0, cpu_cc_src, 31, 1); =20 // b1 =3D N ^ V; - gen_mov_reg_N(t0, cpu_psr); - gen_mov_reg_V(r_temp, cpu_psr); - tcg_gen_xor_tl(t0, t0, r_temp); + tcg_gen_xor_tl(t0, cpu_cc_N, cpu_cc_V); =20 // T0 =3D (b1 << 31) | (T0 >> 1); // src1 =3D T0; - tcg_gen_shli_tl(t0, t0, 31); + tcg_gen_andi_tl(t0, t0, 1u << 31); tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1); tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); =20 @@ -825,114 +814,12 @@ static void gen_op_eval_ba(TCGv dst) tcg_gen_movi_tl(dst, 1); } =20 -// Z -static void gen_op_eval_be(TCGv dst, TCGv_i32 src) -{ - gen_mov_reg_Z(dst, src); -} - -// Z | (N ^ V) -static void gen_op_eval_ble(TCGv dst, TCGv_i32 src) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_N(t0, src); - gen_mov_reg_V(dst, src); - tcg_gen_xor_tl(dst, dst, t0); - gen_mov_reg_Z(t0, src); - tcg_gen_or_tl(dst, dst, t0); -} - -// N ^ V -static void gen_op_eval_bl(TCGv dst, TCGv_i32 src) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_V(t0, src); - gen_mov_reg_N(dst, src); - tcg_gen_xor_tl(dst, dst, t0); -} - -// C | Z -static void gen_op_eval_bleu(TCGv dst, TCGv_i32 src) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_Z(t0, src); - gen_mov_reg_C(dst, src); - tcg_gen_or_tl(dst, dst, t0); -} - -// C -static void gen_op_eval_bcs(TCGv dst, TCGv_i32 src) -{ - gen_mov_reg_C(dst, src); -} - -// V -static void gen_op_eval_bvs(TCGv dst, TCGv_i32 src) -{ - gen_mov_reg_V(dst, src); -} - // 0 static void gen_op_eval_bn(TCGv dst) { tcg_gen_movi_tl(dst, 0); } =20 -// N -static void gen_op_eval_bneg(TCGv dst, TCGv_i32 src) -{ - gen_mov_reg_N(dst, src); -} - -// !Z -static void gen_op_eval_bne(TCGv dst, TCGv_i32 src) -{ - gen_mov_reg_Z(dst, src); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// !(Z | (N ^ V)) -static void gen_op_eval_bg(TCGv dst, TCGv_i32 src) -{ - gen_op_eval_ble(dst, src); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// !(N ^ V) -static void gen_op_eval_bge(TCGv dst, TCGv_i32 src) -{ - gen_op_eval_bl(dst, src); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// !(C | Z) -static void gen_op_eval_bgu(TCGv dst, TCGv_i32 src) -{ - gen_op_eval_bleu(dst, src); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// !C -static void gen_op_eval_bcc(TCGv dst, TCGv_i32 src) -{ - gen_mov_reg_C(dst, src); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// !N -static void gen_op_eval_bpos(TCGv dst, TCGv_i32 src) -{ - gen_mov_reg_N(dst, src); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// !V -static void gen_op_eval_bvc(TCGv dst, TCGv_i32 src) -{ - gen_mov_reg_V(dst, src); - tcg_gen_xori_tl(dst, dst, 0x1); -} - /* FPSR bit field FCC1 | FCC0: 0 =3D @@ -1249,34 +1136,22 @@ static void gen_compare(DisasCompare *cmp, bool xcc= , unsigned int cond, TCG_COND_ALWAYS, /* vc: !V -> 1 */ }; =20 - TCGv_i32 r_src; - TCGv r_dst; + TCGv t1, t2; =20 -#ifdef TARGET_SPARC64 - if (xcc) { - r_src =3D cpu_xcc; - } else { - r_src =3D cpu_psr; - } -#else - r_src =3D cpu_psr; -#endif + cmp->is_bool =3D false; =20 switch (dc->cc_op) { case CC_OP_LOGIC: cmp->cond =3D logic_cond[cond]; do_compare_dst_0: - cmp->is_bool =3D false; cmp->c2 =3D tcg_constant_tl(0); -#ifdef TARGET_SPARC64 - if (!xcc) { - cmp->c1 =3D tcg_temp_new(); - tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst); - break; + if (TARGET_LONG_BITS =3D=3D 32 || xcc) { + cmp->c1 =3D cpu_cc_dst; + } else { + cmp->c1 =3D t1 =3D tcg_temp_new(); + tcg_gen_ext32s_tl(t1, cpu_cc_dst); } -#endif - cmp->c1 =3D cpu_cc_dst; - break; + return; =20 case CC_OP_SUB: switch (cond) { @@ -1287,92 +1162,127 @@ static void gen_compare(DisasCompare *cmp, bool xc= c, unsigned int cond, =20 case 7: /* overflow */ case 15: /* !overflow */ - goto do_dynamic; + break; =20 default: cmp->cond =3D subcc_cond[cond]; - cmp->is_bool =3D false; -#ifdef TARGET_SPARC64 - if (!xcc) { + if (TARGET_LONG_BITS =3D=3D 32 || xcc) { + cmp->c1 =3D cpu_cc_src; + cmp->c2 =3D cpu_cc_src2; + } else { /* Note that sign-extension works for unsigned compares as long as both operands are sign-extended. */ - cmp->c1 =3D tcg_temp_new(); - cmp->c2 =3D tcg_temp_new(); - tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src); - tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2); - break; + cmp->c1 =3D t1 =3D tcg_temp_new(); + tcg_gen_ext32s_tl(t1, cpu_cc_src); + cmp->c2 =3D t2 =3D tcg_temp_new(); + tcg_gen_ext32s_tl(t2, cpu_cc_src2); } -#endif - cmp->c1 =3D cpu_cc_src; - cmp->c2 =3D cpu_cc_src2; - break; + return; } break; =20 default: - do_dynamic: gen_helper_compute_psr(tcg_env); dc->cc_op =3D CC_OP_FLAGS; - /* FALLTHRU */ + break; =20 case CC_OP_FLAGS: - /* We're going to generate a boolean result. */ - cmp->cond =3D TCG_COND_NE; - cmp->is_bool =3D true; - cmp->c1 =3D r_dst =3D tcg_temp_new(); - cmp->c2 =3D tcg_constant_tl(0); + break; + } =20 - switch (cond) { - case 0x0: - gen_op_eval_bn(r_dst); - break; - case 0x1: - gen_op_eval_be(r_dst, r_src); - break; - case 0x2: - gen_op_eval_ble(r_dst, r_src); - break; - case 0x3: - gen_op_eval_bl(r_dst, r_src); - break; - case 0x4: - gen_op_eval_bleu(r_dst, r_src); - break; - case 0x5: - gen_op_eval_bcs(r_dst, r_src); - break; - case 0x6: - gen_op_eval_bneg(r_dst, r_src); - break; - case 0x7: - gen_op_eval_bvs(r_dst, r_src); - break; - case 0x8: - gen_op_eval_ba(r_dst); - break; - case 0x9: - gen_op_eval_bne(r_dst, r_src); - break; - case 0xa: - gen_op_eval_bg(r_dst, r_src); - break; - case 0xb: - gen_op_eval_bge(r_dst, r_src); - break; - case 0xc: - gen_op_eval_bgu(r_dst, r_src); - break; - case 0xd: - gen_op_eval_bcc(r_dst, r_src); - break; - case 0xe: - gen_op_eval_bpos(r_dst, r_src); - break; - case 0xf: - gen_op_eval_bvc(r_dst, r_src); - break; + cmp->c1 =3D t1 =3D tcg_temp_new(); + cmp->c2 =3D tcg_constant_tl(0); + + switch (cond & 7) { + case 0x0: /* never */ + cmp->cond =3D TCG_COND_NEVER; + cmp->c1 =3D cmp->c2; + break; + + case 0x1: /* eq: Z */ + cmp->cond =3D TCG_COND_EQ; + if (TARGET_LONG_BITS =3D=3D 32 || xcc) { + tcg_gen_mov_tl(t1, cpu_cc_Z); + } else { + tcg_gen_ext32u_tl(t1, cpu_icc_Z); } break; + + case 0x2: /* le: Z | (N ^ V) */ + /* + * Simplify: + * cc_Z || (N ^ V) < 0 NE + * cc_Z && !((N ^ V) < 0) EQ + * cc_Z & ~((N ^ V) >> TLB) EQ + */ + cmp->cond =3D TCG_COND_EQ; + tcg_gen_xor_tl(t1, cpu_cc_N, cpu_cc_V); + tcg_gen_sextract_tl(t1, t1, xcc ? 63 : 31, 1); + tcg_gen_andc_tl(t1, xcc ? cpu_cc_Z : cpu_icc_Z, t1); + if (TARGET_LONG_BITS =3D=3D 64 && !xcc) { + tcg_gen_ext32u_tl(t1, t1); + } + break; + + case 0x3: /* lt: N ^ V */ + cmp->cond =3D TCG_COND_LT; + tcg_gen_xor_tl(t1, cpu_cc_N, cpu_cc_V); + if (TARGET_LONG_BITS =3D=3D 64 && !xcc) { + tcg_gen_ext32s_tl(t1, t1); + } + break; + + case 0x4: /* leu: Z | C */ + /* + * Simplify: + * cc_Z =3D=3D 0 || cc_C !=3D 0 NE + * cc_Z !=3D 0 && cc_C =3D=3D 0 EQ + * cc_Z & (cc_C ? 0 : -1) EQ + * cc_Z & (cc_C - 1) EQ + */ + cmp->cond =3D TCG_COND_EQ; + if (TARGET_LONG_BITS =3D=3D 32 || xcc) { + tcg_gen_subi_tl(t1, cpu_cc_C, 1); + tcg_gen_and_tl(t1, t1, cpu_cc_Z); + } else { + tcg_gen_extract_tl(t1, cpu_icc_C, 32, 1); + tcg_gen_subi_tl(t1, t1, 1); + tcg_gen_and_tl(t1, t1, cpu_icc_Z); + tcg_gen_ext32u_tl(t1, t1); + } + break; + + case 0x5: /* ltu: C */ + cmp->cond =3D TCG_COND_NE; + cmp->is_bool =3D true; + if (TARGET_LONG_BITS =3D=3D 32 || xcc) { + tcg_gen_mov_tl(t1, cpu_cc_C); + } else { + tcg_gen_extract_tl(t1, cpu_icc_C, 32, 1); + } + break; + + case 0x6: /* neg: N */ + cmp->cond =3D TCG_COND_LT; + if (TARGET_LONG_BITS =3D=3D 32 || xcc) { + tcg_gen_mov_tl(t1, cpu_cc_N); + } else { + tcg_gen_ext32s_tl(t1, cpu_cc_N); + } + break; + + case 0x7: /* vs: V */ + cmp->cond =3D TCG_COND_LT; + if (TARGET_LONG_BITS =3D=3D 32 || xcc) { + tcg_gen_mov_tl(t1, cpu_cc_V); + } else { + tcg_gen_ext32s_tl(t1, cpu_cc_V); + } + break; + } + if (cond & 8) { + cmp->cond =3D tcg_invert_cond(cmp->cond); + cmp->is_bool =3D false; } } =20 @@ -5513,17 +5423,21 @@ void sparc_tcg_init(void) =20 static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[= ] =3D { #ifdef TARGET_SPARC64 - { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" }, { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" }, #endif { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" }, - { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" }, }; =20 static const struct { TCGv *ptr; int off; const char *name; } rtl[] = =3D { #ifdef TARGET_SPARC64 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" }, + { &cpu_xcc_Z, offsetof(CPUSPARCState, xcc_Z), "xcc_Z" }, + { &cpu_xcc_C, offsetof(CPUSPARCState, xcc_C), "xcc_C" }, #endif + { &cpu_cc_N, offsetof(CPUSPARCState, cc_N), "cc_N" }, + { &cpu_cc_V, offsetof(CPUSPARCState, cc_V), "cc_V" }, + { &cpu_icc_Z, offsetof(CPUSPARCState, icc_Z), "icc_Z" }, + { &cpu_icc_C, offsetof(CPUSPARCState, icc_C), "icc_C" }, { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" }, { &cpu_cc_src, offsetof(CPUSPARCState, cc_src), "cc_src" }, { &cpu_cc_src2, offsetof(CPUSPARCState, cc_src2), "cc_src2" }, diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c index bf2c90c780..f0ff6bf5db 100644 --- a/target/sparc/win_helper.c +++ b/target/sparc/win_helper.c @@ -53,23 +53,44 @@ void cpu_set_cwp(CPUSPARCState *env, int new_cwp) =20 target_ulong cpu_get_psr(CPUSPARCState *env) { + target_ulong icc =3D 0; + helper_compute_psr(env); =20 + icc |=3D ((int32_t)env->cc_N < 0) << PSR_NEG_SHIFT; + icc |=3D ((int32_t)env->cc_V < 0) << PSR_OVF_SHIFT; + icc |=3D ((int32_t)env->icc_Z =3D=3D 0) << PSR_ZERO_SHIFT; + if (TARGET_LONG_BITS =3D=3D 64) { + icc |=3D extract64(env->icc_C, 32, 1) << PSR_CARRY_SHIFT; + } else { + icc |=3D env->icc_C << PSR_CARRY_SHIFT; + } + #if !defined(TARGET_SPARC64) - return env->version | (env->psr & PSR_ICC) | + return env->version | icc | (env->psref ? PSR_EF : 0) | (env->psrpil << 8) | (env->psrs ? PSR_S : 0) | (env->psrps ? PSR_PS : 0) | (env->psret ? PSR_ET : 0) | env->cwp; #else - return env->psr & PSR_ICC; + return icc; #endif } =20 void cpu_put_psr_icc(CPUSPARCState *env, target_ulong val) { - env->psr =3D val & PSR_ICC; + if (TARGET_LONG_BITS =3D=3D 64) { + /* Do not clobber xcc.[NV] */ + env->cc_N =3D deposit64(env->cc_N, 0, 32, -(val & PSR_NEG)); + env->cc_V =3D deposit64(env->cc_V, 0, 32, -(val & PSR_OVF)); + env->icc_C =3D -(val & PSR_CARRY); + } else { + env->cc_N =3D -(val & PSR_NEG); + env->cc_V =3D -(val & PSR_OVF); + env->icc_C =3D (val >> PSR_CARRY_SHIFT) & 1; + } + env->icc_Z =3D ~val & PSR_ZERO; } =20 void cpu_put_psr_raw(CPUSPARCState *env, target_ulong val) @@ -249,17 +270,32 @@ void helper_restored(CPUSPARCState *env) =20 target_ulong cpu_get_ccr(CPUSPARCState *env) { - target_ulong psr; + target_ulong ccr =3D 0; =20 - psr =3D cpu_get_psr(env); + helper_compute_psr(env); =20 - return ((env->xcc >> 20) << 4) | ((psr & PSR_ICC) >> 20); + ccr |=3D (env->icc_C >> 32) & 1; + ccr |=3D ((int32_t)env->cc_V < 0) << 1; + ccr |=3D ((int32_t)env->icc_Z =3D=3D 0) << 2; + ccr |=3D ((int32_t)env->cc_N < 0) << 3; + + ccr |=3D env->xcc_C << 4; + ccr |=3D (env->cc_V < 0) << 5; + ccr |=3D (env->xcc_Z =3D=3D 0) << 6; + ccr |=3D (env->cc_N < 0) << 7; + + return ccr; } =20 void cpu_put_ccr(CPUSPARCState *env, target_ulong val) { - env->xcc =3D (val >> 4) << 20; - env->psr =3D (val & 0xf) << 20; + env->cc_N =3D deposit64(-(val & 0x08), 32, 32, -(val & 0x80)); + env->cc_V =3D deposit64(-(val & 0x02), 32, 32, -(val & 0x20)); + env->icc_C =3D (uint64_t)val << 32; + env->xcc_C =3D (val >> 4) & 1; + env->icc_Z =3D ~val & 0x04; + env->xcc_Z =3D ~val & 0x40; + CC_OP =3D CC_OP_FLAGS; } =20 --=20 2.34.1