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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u23-20020a056a00099700b006884549adc8sm4359777pfg.29.2023.11.05.12.12.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Nov 2023 12:12:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699215159; x=1699819959; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tlzuFmbJ+lRCVWBnnRWRgKX8WhOt5plpowDBaUnKw9s=; b=HpMYmjXNp3q02Lc3fHCvQ2aFyHqjZ5hhg/HiNzmvHa1rCHzFaiten4BDlJpJ0FaqXJ ATOl+t3LTcEA1DWGve1W/3WoMh+10z85P4mOB3YYwWGTdzqBLgWm3HKWMsi/Bo1SuiZX NfiM+8diq9GtUNmQ3OKqT8hPo5kKqVyEGU+QrG8xNraZzaiH065x671IlUeHQFIPFn6n RrIA6sIhHt5+tpRQBl1JpZZQWs0SJ+nfHQjxnlJg+D/MRytip7n50azNnYRFRE2fQM5v tercrT86LDj0ERqGAXU/835wLFRGhOySovoRIlPlbbKILaSp6Rx1MVd7ba/au/kDCrr2 0Qxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699215159; x=1699819959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tlzuFmbJ+lRCVWBnnRWRgKX8WhOt5plpowDBaUnKw9s=; b=K6AL6qqaGtXoRntzq+wyexUs/mPamBLekUELNU2NAH2VLR5zKyM8bYEzqBAkavkNIc Xh6mxHr+5CJ17SbiK7pK15PruEyY4GnPMD4xmZMMMY/NBkGiub2tusRG6eI0DOktP1i2 dfgvyfx4vvjwjK2Qahe4QQVmqkUjephoPt8Jv37O/ygPEcTSNzAV1D6yKicKamdLDbnx dih4fiIOlbI/1A+OiydnU4zlFMZ5FR5QT/5lqVR4swE+7avoRUsCdxWeNoEOizYQfur9 vdYNndSVnvMx6R4HVDEPlTgmDlx1csSK8c1IVJ9eNKoJvgprQJ9R3HZOxprVvbRjr8zZ exNw== X-Gm-Message-State: AOJu0YzjFg88zJ4hKyq1m9IirltQ0GmTFqvYOAuP0aNA5bahCpoPlkSI bAYHMvycg+scnzmQZckZe10peGNkLk9c/4z2v1M= X-Google-Smtp-Source: AGHT+IGZngWQEO4itYmIFVmch8Ho89QeunkqMkuA2/okMhwQS2MLe4ZcH8x0+u7BRuNPiK7D1fticg== X-Received: by 2002:a05:6a00:391a:b0:68f:f38d:f76c with SMTP id fh26-20020a056a00391a00b0068ff38df76cmr23607474pfb.6.1699215159238; Sun, 05 Nov 2023 12:12:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 18/21] target/sparc: Discard cpu_cond at the end of each insn Date: Sun, 5 Nov 2023 12:12:19 -0800 Message-Id: <20231105201222.202395-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231105201222.202395-1-richard.henderson@linaro.org> References: <20231105201222.202395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215294935100003 Content-Type: text/plain; charset="utf-8" If the insn raises no exceptions, there will be no path in which cpu_cond is used, and so the computation may be optimized away. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 5c9a3d45fa..3564c6032e 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -171,6 +171,7 @@ typedef struct DisasContext { target_ulong jump_pc[2]; =20 int mem_idx; + bool cpu_cond_live; bool fpu_enabled; bool address_mask_32bit; #ifndef CONFIG_USER_ONLY @@ -912,6 +913,19 @@ static void gen_op_eval_fbo(TCGv dst, TCGv src, unsign= ed int fcc_offset) tcg_gen_xori_tl(dst, dst, 0x1); } =20 +static void finishing_insn(DisasContext *dc) +{ + /* + * From here, there is no future path through an unwinding exception. + * If the current insn cannot raise an exception, the computation of + * cpu_cond may be able to be elided. + */ + if (dc->cpu_cond_live) { + tcg_gen_discard_tl(cpu_cond); + dc->cpu_cond_live =3D false; + } +} + static void gen_generic_branch(DisasContext *dc) { TCGv npc0 =3D tcg_constant_tl(dc->jump_pc[0]); @@ -958,6 +972,7 @@ static void save_state(DisasContext *dc) =20 static void gen_exception(DisasContext *dc, int which) { + finishing_insn(dc); save_state(dc); gen_helper_raise_exception(tcg_env, tcg_constant_i32(which)); dc->base.is_jmp =3D DISAS_NORETURN; @@ -999,6 +1014,8 @@ static void gen_check_align(DisasContext *dc, TCGv add= r, int mask) =20 static void gen_mov_pc_npc(DisasContext *dc) { + finishing_insn(dc); + if (dc->npc & 3) { switch (dc->npc) { case JUMP_PC: @@ -2339,6 +2356,8 @@ static bool advance_pc(DisasContext *dc) { TCGLabel *l1; =20 + finishing_insn(dc); + if (dc->npc & 3) { switch (dc->npc) { case DYNAMIC_PC: @@ -2383,6 +2402,8 @@ static bool advance_jump_cond(DisasContext *dc, Disas= Compare *cmp, target_ulong dest =3D address_mask_i(dc, dc->pc + disp * 4); target_ulong npc; =20 + finishing_insn(dc); + if (cmp->cond =3D=3D TCG_COND_ALWAYS) { if (annul) { dc->pc =3D dest; @@ -2449,6 +2470,7 @@ static bool advance_jump_cond(DisasContext *dc, Disas= Compare *cmp, } else { tcg_gen_setcondi_tl(cmp->cond, cpu_cond, cmp->c1, cmp->c2); } + dc->cpu_cond_live =3D true; } } return true; @@ -2585,6 +2607,8 @@ static bool do_tcc(DisasContext *dc, int cond, int cc, tcg_gen_addi_i32(trap, trap, TT_TRAP); } =20 + finishing_insn(dc); + /* Trap always. */ if (cond =3D=3D 8) { save_state(dc); @@ -3201,6 +3225,7 @@ TRANS(WRSTICK_CMPR, 64, do_wr_special, a, supervisor(= dc), do_wrstick_cmpr) =20 static void do_wrpowerdown(DisasContext *dc, TCGv src) { + finishing_insn(dc); save_state(dc); gen_helper_power_down(tcg_env); } @@ -5080,6 +5105,8 @@ static void sparc_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cs) DisasDelayException *e, *e_next; bool may_lookup; =20 + finishing_insn(dc); + switch (dc->base.is_jmp) { case DISAS_NEXT: case DISAS_TOO_MANY: --=20 2.34.1