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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u23-20020a056a00099700b006884549adc8sm4359777pfg.29.2023.11.05.12.12.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Nov 2023 12:12:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699215145; x=1699819945; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qG+TirgfLO1yyR3v2seUl0zyqvQ6ZRohRxES3/K7nSo=; b=QmVv0FBq1qF2xTX+mHuACZURGPmJ0MOT9c7xIL54/kGoeYWS7aipdolChz+Wr8PrYX zMqDNH5+UsALub5cA1nYCDIV1J3bG1Cj2FYPCPr1fhw6VxmVYlb80Lpi8J/TVU9pGcFo sELufHuLNbU9Kg13MUs+m8Ucu+/S/2lX0rINVnhop+RPT52zkO9fgsWTPWcUgZ47Etvo SolvZCF1M2DhJvFp4A2/a564mEQ8OQRVDRq7ElKGsKMVGsWc3P/1GMNC1/zGGXoJu6AL UfpL8dl4Q1/lEzESQIbyJZ/O8gp3aSbEDB8U0DSdB6VCVtsXdHi6HmZwGzPTjz1beZz7 +FGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699215145; x=1699819945; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qG+TirgfLO1yyR3v2seUl0zyqvQ6ZRohRxES3/K7nSo=; b=iA3WPR1CVsIm6FvWdJGtt2PXe2lZx7KRZaa9Qm6Ldgix8WnoWxe1K2z3oDqNARO/eW QUnDrlGkdvx2Jst/P22/zSe3ojIsAKroa+RJZ9L2AMoqe4feCZoVafJn/DOMMGQXd4RG 5T1BgS3eqAihuqFPJpsxuzk61g0oLGBxyaaLV7VFEXClGwyyNdC+te/QR0uxDgO86HoI 0hxglhGRRlC9PSeMHToYI8GutMzIPOrNluUrhp9kFs+f/8GbW0rjNFW5V80xQWmKKGIr Cd/o/8aSRKjwfzLRoCZ5Pc6UVlywnzeaZm7todw7cWl7ieBJUFZuSdiXgjEGl4mO85CN /kYQ== X-Gm-Message-State: AOJu0Yxfeq08uNw5kuzgJeln6v4kzrGoh/vwcxDg7VeIN0IczKh7Wf03 tNh3fVqfi9BijjGM4osOwBzegG8gOkqbptk2+ww= X-Google-Smtp-Source: AGHT+IE+QV13dDnnZv0fozZBr3mFGe94x/jSn3hFrAreeYl0+TFJdNsLtQBs7UB3H2wWUsy4VXz0dQ== X-Received: by 2002:a05:6a21:7785:b0:180:db7b:23f2 with SMTP id bd5-20020a056a21778500b00180db7b23f2mr25375142pzc.61.1699215144694; Sun, 05 Nov 2023 12:12:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 01/21] target/sparc: Introduce cpu_put_psr_icc Date: Sun, 5 Nov 2023 12:12:02 -0800 Message-Id: <20231105201222.202395-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231105201222.202395-1-richard.henderson@linaro.org> References: <20231105201222.202395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215309008100001 Content-Type: text/plain; charset="utf-8" Isolate linux-user from changes to icc representation. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 1 + linux-user/sparc/signal.c | 2 +- target/sparc/win_helper.c | 7 ++++++- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 758a4e8aaa..955329f6c9 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -619,6 +619,7 @@ void sparc_restore_state_to_opc(CPUState *cs, /* win_helper.c */ target_ulong cpu_get_psr(CPUSPARCState *env1); void cpu_put_psr(CPUSPARCState *env1, target_ulong val); +void cpu_put_psr_icc(CPUSPARCState *env1, target_ulong val); void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val); #ifdef TARGET_SPARC64 void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate); diff --git a/linux-user/sparc/signal.c b/linux-user/sparc/signal.c index 2be9000b9e..dfcae707e0 100644 --- a/linux-user/sparc/signal.c +++ b/linux-user/sparc/signal.c @@ -164,7 +164,7 @@ static void restore_pt_regs(struct target_pt_regs *regs= , CPUSPARCState *env) */ uint32_t psr; __get_user(psr, ®s->psr); - env->psr =3D (psr & PSR_ICC) | (env->psr & ~PSR_ICC); + cpu_put_psr_icc(env, psr); #endif =20 /* Note that pc and npc are handled in the caller. */ diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c index 3a7c0ff943..bf2c90c780 100644 --- a/target/sparc/win_helper.c +++ b/target/sparc/win_helper.c @@ -67,9 +67,14 @@ target_ulong cpu_get_psr(CPUSPARCState *env) #endif } =20 -void cpu_put_psr_raw(CPUSPARCState *env, target_ulong val) +void cpu_put_psr_icc(CPUSPARCState *env, target_ulong val) { env->psr =3D val & PSR_ICC; +} + +void cpu_put_psr_raw(CPUSPARCState *env, target_ulong val) +{ + cpu_put_psr_icc(env, val); #if !defined(TARGET_SPARC64) env->psref =3D (val & PSR_EF) ? 1 : 0; env->psrpil =3D (val & PSR_PIL) >> 8; --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699215364; cv=none; d=zohomail.com; s=zohoarc; b=L4Tcz1GgM20yndUY6yDNStreMSDoKCwEzS6nQzs9VvNnH6ShBj6RWFSVcc/RP4tUF4V5J3sKkf+vJ21QGB5gKWVhPblp7Vh06E0ub9LGtFDl8Lt1LFW0jJAfzxs8FubtACbp3QiyuUjLuPKcdXNtub6woFuCm7kJDmtlk4haVfg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699215364; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ETzV90iWfq68Qou4N/sY5beJ+DnMwUACRile3KCErJo=; b=W2bmHkVy0dOzoQsTZ2J1yz/oh0rC6e3e3P7ChqVG/WXIyObHKQ5ZYP2SE8fBkp3Ijkx+NrQD9bF0OgKv6QIpxuOyhucA6q2JHaHTYQZLqgAeObpAslKlna6mD1+rRze6z9VYrcn2UnGyzjKHbgpYR90KWn9Pb2Lzn2mMdjaxT/4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699215364138527.1648745869473; Sun, 5 Nov 2023 12:16:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qzjU0-0003Bk-LI; Sun, 05 Nov 2023 15:12:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qzjTz-0003BA-Eo for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:31 -0500 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qzjTv-00027i-I4 for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:31 -0500 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-6c311ca94b4so3210975b3a.3 for ; Sun, 05 Nov 2023 12:12:26 -0800 (PST) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u23-20020a056a00099700b006884549adc8sm4359777pfg.29.2023.11.05.12.12.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Nov 2023 12:12:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699215146; x=1699819946; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ETzV90iWfq68Qou4N/sY5beJ+DnMwUACRile3KCErJo=; b=c/tckkRBdMEENGWtQTeFGjPBMuWh6eAyMR80+zQgH0cxmgNmpjCG0Yn3zE7imGlkXv 6a4Htvdrmv+kShKKhpqle1fRvLj/RDdk7qTkdhs+0MZSen6SEH1xStNp3IgSaClaLbml VEvyLsgZV2ynlrZEW5nCKdG8n1NlzPxFm1dL7Qji/uSdPs3+EktOvNl/xipFjGJBvcZp JSPj8Hj/ViUGuckB6NH+J7eOjsPH3q0W7JvqzTHE8CCqxUbTnP839aHoVtP5LKN15s/1 BCEmJWPmrw5Mm0geTqDAuRgUk7Vd0htKHid7h63hznkvRLCB+xLzx44QwetpjCgoWV4e gjBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699215146; x=1699819946; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ETzV90iWfq68Qou4N/sY5beJ+DnMwUACRile3KCErJo=; b=lvriPaO1PdHhQ9D1w79jQ/nYk2rKGZakL0mYWcxqP2u142Igyerd+FeZFBxUf01zOa Qbbw/qzFC1Jx3qxLeIfJGv7BJrCPoDmo1Lja4SwpCIYJ7uf8xiLXw/b+PqcNTxoc2HMj O26Cq8h66WTzrk8qJO9JBgoLy3hktpAkQ7laWaS+udG7y+ZLzukM8TdAFg7ftG28+Drr JCk/MiGNJ9qDEFnL93I/mxpZKUoASLq+OJENki1WTl5ER24FQL//XtQDrefrOgRB87si fvXPaz003Msz0/XBpBqJEUWD6wVBWnFk0pmZ3PQP0H4LQhyKaBgJa2OMWP2jEWfi+dGB 7Zsw== X-Gm-Message-State: AOJu0YzlZaOHRtDz48AvCMxfJ/oqMaPBcw6g4Cey3BxSBvxUHXbSQN78 GWI25/8qFgXlLMmzaUfAiDbhDJXr4oOBEp6AkIs= X-Google-Smtp-Source: AGHT+IGPz4gFEieby2z/5NorNxkKgympOf+8hfgPgAuThKymOFcqFEJtnye9AQ7Wt1NIXxtYyJPPwQ== X-Received: by 2002:a05:6a00:2e07:b0:6b3:f29c:dde1 with SMTP id fc7-20020a056a002e0700b006b3f29cdde1mr25550826pfb.21.1699215145656; Sun, 05 Nov 2023 12:12:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 02/21] target/sparc: Split psr and xcc into components Date: Sun, 5 Nov 2023 12:12:03 -0800 Message-Id: <20231105201222.202395-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231105201222.202395-1-richard.henderson@linaro.org> References: <20231105201222.202395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215365081100001 Content-Type: text/plain; charset="utf-8" Step in removing CC_OP: change the representation of CC_OP_FLAGS. The 8 bits are distributed between 6 variables, which should make it easy to keep up to date. The code within cc_helper.c is quite ugly but is only temporary. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- linux-user/sparc/target_cpu.h | 17 +- target/sparc/cpu.h | 30 ++- linux-user/sparc/cpu_loop.c | 6 +- target/sparc/cc_helper.c | 51 +++-- target/sparc/machine.c | 45 ++++- target/sparc/translate.c | 362 +++++++++++++--------------------- target/sparc/win_helper.c | 52 ++++- 7 files changed, 291 insertions(+), 272 deletions(-) diff --git a/linux-user/sparc/target_cpu.h b/linux-user/sparc/target_cpu.h index 1f4bed50f4..5f62c5eb75 100644 --- a/linux-user/sparc/target_cpu.h +++ b/linux-user/sparc/target_cpu.h @@ -26,6 +26,17 @@ # define TARGET_STACK_BIAS 0 #endif =20 +static void set_syscall_C(CPUSPARCState *env, bool val) +{ +#ifndef TARGET_SPARC64 + env->icc_C =3D val; +#elif defined(TARGET_ABI32) + env->icc_C =3D (uint64_t)val << 32; +#else + env->xcc_C =3D val; +#endif +} + static inline void cpu_clone_regs_child(CPUSPARCState *env, target_ulong n= ewsp, unsigned flags) { @@ -58,11 +69,7 @@ static inline void cpu_clone_regs_child(CPUSPARCState *e= nv, target_ulong newsp, * do the pc advance twice. */ env->regwptr[WREG_O0] =3D 0; -#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) - env->xcc &=3D ~PSR_CARRY; -#else - env->psr &=3D ~PSR_CARRY; -#endif + set_syscall_C(env, 0); env->pc =3D env->npc; env->npc =3D env->npc + 4; } diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 955329f6c9..ea8a04c6e3 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -149,7 +149,7 @@ enum { */ enum { CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ - CC_OP_FLAGS, /* all cc are back in status register */ + CC_OP_FLAGS, /* all cc are back in cc_*_[NZCV] registers */ CC_OP_DIV, /* modify N, Z and V, C =3D 0*/ CC_OP_ADD, /* modify all flags, CC_DST =3D res, CC_SRC =3D src1 */ CC_OP_ADDX, /* modify all flags, CC_DST =3D res, CC_SRC =3D src1 */ @@ -458,6 +458,32 @@ struct CPUArchState { target_ulong npc; /* next program counter */ target_ulong y; /* multiply/divide register */ =20 + /* + * Bit 31 is for icc, bit 63 for xcc. + * Other bits are garbage. + */ + target_long cc_N; + target_long cc_V; + + /* + * Z is represented as =3D=3D 0; any non-zero value is !Z. + * For sparc64, the high 32-bits of icc.Z are garbage. + */ + target_ulong icc_Z; +#ifdef TARGET_SPARC64 + target_ulong xcc_Z; +#endif + + /* + * For sparc32, icc.C is boolean. + * For sparc64, xcc.C is boolean; + * icc.C is bit 32 with other bits garbage. + */ + target_ulong icc_C; +#ifdef TARGET_SPARC64 + target_ulong xcc_C; +#endif + /* emulator internal flags handling */ target_ulong cc_src, cc_src2; target_ulong cc_dst; @@ -466,7 +492,6 @@ struct CPUArchState { target_ulong cond; /* conditional branch result (XXX: save it in a temporary register when possible) */ =20 - uint32_t psr; /* processor state register */ target_ulong fsr; /* FPU state register */ CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ uint32_t cwp; /* index of current register window (extracted @@ -522,7 +547,6 @@ struct CPUArchState { #define MAXTL_MAX 8 #define MAXTL_MASK (MAXTL_MAX - 1) trap_state ts[MAXTL_MAX]; - uint32_t xcc; /* Extended integer condition codes */ uint32_t asi; uint32_t pstate; uint32_t tl; diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index b36bb2574b..c1a2362041 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -197,10 +197,8 @@ static uint32_t do_getpsr(CPUSPARCState *env) /* Avoid ifdefs below for the abi32 and abi64 paths. */ #ifdef TARGET_ABI32 #define TARGET_TT_SYSCALL (TT_TRAP + 0x10) /* t_linux */ -#define syscall_cc psr #else #define TARGET_TT_SYSCALL (TT_TRAP + 0x6d) /* tl0_linux64 */ -#define syscall_cc xcc #endif =20 /* Avoid ifdefs below for the v9 and pre-v9 hw traps. */ @@ -240,10 +238,10 @@ void cpu_loop (CPUSPARCState *env) break; } if ((abi_ulong)ret >=3D (abi_ulong)(-515)) { - env->syscall_cc |=3D PSR_CARRY; + set_syscall_C(env, 1); ret =3D -ret; } else { - env->syscall_cc &=3D ~PSR_CARRY; + set_syscall_C(env, 0); } env->regwptr[0] =3D ret; /* next instruction */ diff --git a/target/sparc/cc_helper.c b/target/sparc/cc_helper.c index 7ad5b9b29e..46bec69d96 100644 --- a/target/sparc/cc_helper.c +++ b/target/sparc/cc_helper.c @@ -21,16 +21,6 @@ #include "cpu.h" #include "exec/helper-proto.h" =20 -static uint32_t compute_all_flags(CPUSPARCState *env) -{ - return env->psr & PSR_ICC; -} - -static uint32_t compute_C_flags(CPUSPARCState *env) -{ - return env->psr & PSR_CARRY; -} - static inline uint32_t get_NZ_icc(int32_t dst) { uint32_t ret =3D 0; @@ -44,16 +34,6 @@ static inline uint32_t get_NZ_icc(int32_t dst) } =20 #ifdef TARGET_SPARC64 -static uint32_t compute_all_flags_xcc(CPUSPARCState *env) -{ - return env->xcc & PSR_ICC; -} - -static uint32_t compute_C_flags_xcc(CPUSPARCState *env) -{ - return env->xcc & PSR_CARRY; -} - static inline uint32_t get_NZ_xcc(target_long dst) { uint32_t ret =3D 0; @@ -422,7 +402,6 @@ typedef struct CCTable { =20 static const CCTable icc_table[CC_OP_NB] =3D { /* CC_OP_DYNAMIC should never happen */ - [CC_OP_FLAGS] =3D { compute_all_flags, compute_C_flags }, [CC_OP_DIV] =3D { compute_all_div, compute_C_div }, [CC_OP_ADD] =3D { compute_all_add, compute_C_add }, [CC_OP_ADDX] =3D { compute_all_addx, compute_C_addx }, @@ -438,7 +417,6 @@ static const CCTable icc_table[CC_OP_NB] =3D { #ifdef TARGET_SPARC64 static const CCTable xcc_table[CC_OP_NB] =3D { /* CC_OP_DYNAMIC should never happen */ - [CC_OP_FLAGS] =3D { compute_all_flags_xcc, compute_C_flags_xcc }, [CC_OP_DIV] =3D { compute_all_logic_xcc, compute_C_logic }, [CC_OP_ADD] =3D { compute_all_add_xcc, compute_C_add_xcc }, [CC_OP_ADDX] =3D { compute_all_addx_xcc, compute_C_addx_xcc }, @@ -454,18 +432,37 @@ static const CCTable xcc_table[CC_OP_NB] =3D { =20 void helper_compute_psr(CPUSPARCState *env) { - uint32_t new_psr; + if (CC_OP =3D=3D CC_OP_FLAGS) { + return; + } =20 - new_psr =3D icc_table[CC_OP].compute_all(env); - env->psr =3D new_psr; + uint32_t icc =3D icc_table[CC_OP].compute_all(env); #ifdef TARGET_SPARC64 - new_psr =3D xcc_table[CC_OP].compute_all(env); - env->xcc =3D new_psr; + uint32_t xcc =3D xcc_table[CC_OP].compute_all(env); + + env->cc_N =3D deposit64(-(icc & PSR_NEG), 32, 32, -(xcc & PSR_NEG)); + env->cc_V =3D deposit64(-(icc & PSR_OVF), 32, 32, -(xcc & PSR_OVF)); + env->icc_C =3D (uint64_t)icc << (32 - PSR_CARRY_SHIFT); + env->xcc_C =3D (xcc >> PSR_CARRY_SHIFT) & 1; + env->xcc_Z =3D ~xcc & PSR_ZERO; +#else + env->cc_N =3D -(icc & PSR_NEG); + env->cc_V =3D -(icc & PSR_OVF); + env->icc_C =3D (icc >> PSR_CARRY_SHIFT) & 1; #endif + env->icc_Z =3D ~icc & PSR_ZERO; + CC_OP =3D CC_OP_FLAGS; } =20 uint32_t helper_compute_C_icc(CPUSPARCState *env) { + if (CC_OP =3D=3D CC_OP_FLAGS) { +#ifdef TARGET_SPARC64 + return extract64(env->icc_C, 32, 1); +#else + return env->icc_C; +#endif + } return icc_table[CC_OP].compute_c(env) >> PSR_CARRY_SHIFT; } diff --git a/target/sparc/machine.c b/target/sparc/machine.c index 274e1217df..44dfc07014 100644 --- a/target/sparc/machine.c +++ b/target/sparc/machine.c @@ -83,6 +83,42 @@ static const VMStateInfo vmstate_psr =3D { .put =3D put_psr, }; =20 +#ifdef TARGET_SPARC64 +static int get_xcc(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field) +{ + SPARCCPU *cpu =3D opaque; + CPUSPARCState *env =3D &cpu->env; + uint32_t val =3D qemu_get_be32(f); + + /* Do not clobber icc.[NV] */ + env->cc_N =3D deposit64(env->cc_N, 32, 32, -(val & PSR_NEG)); + env->cc_V =3D deposit64(env->cc_V, 32, 32, -(val & PSR_OVF)); + env->xcc_Z =3D ~val & PSR_ZERO; + env->xcc_C =3D (val >> PSR_CARRY_SHIFT) & 1; + + return 0; +} + +static int put_xcc(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field, JSONWriter *vmdesc) +{ + SPARCCPU *cpu =3D opaque; + CPUSPARCState *env =3D &cpu->env; + uint32_t val =3D cpu_get_ccr(env); + + /* Extract just xcc out of ccr and shift into legacy position. */ + qemu_put_be32(f, (val & 0xf0) << (20 - 4)); + return 0; +} + +static const VMStateInfo vmstate_xcc =3D { + .name =3D "xcc", + .get =3D get_xcc, + .put =3D put_xcc, +}; +#endif + static int cpu_pre_save(void *opaque) { SPARCCPU *cpu =3D opaque; @@ -155,7 +191,14 @@ const VMStateDescription vmstate_sparc_cpu =3D { VMSTATE_UINT32(env.mmu_version, SPARCCPU), VMSTATE_STRUCT_ARRAY(env.ts, SPARCCPU, MAXTL_MAX, 0, vmstate_trap_state, trap_state), - VMSTATE_UINT32(env.xcc, SPARCCPU), + { + .name =3D "xcc", + .version_id =3D 0, + .size =3D sizeof(uint32_t), + .info =3D &vmstate_xcc, + .flags =3D VMS_SINGLE, + .offset =3D 0, + }, VMSTATE_UINT32(env.asi, SPARCCPU), VMSTATE_UINT32(env.pstate, SPARCCPU), VMSTATE_UINT32(env.tl, SPARCCPU), diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 986a88c4e1..261f142636 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -107,19 +107,35 @@ static TCGv_ptr cpu_regwptr; static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst; static TCGv_i32 cpu_cc_op; -static TCGv_i32 cpu_psr; static TCGv cpu_fsr, cpu_pc, cpu_npc; static TCGv cpu_regs[32]; static TCGv cpu_y; static TCGv cpu_tbr; static TCGv cpu_cond; +static TCGv cpu_cc_N; +static TCGv cpu_cc_V; +static TCGv cpu_icc_Z; +static TCGv cpu_icc_C; #ifdef TARGET_SPARC64 -static TCGv_i32 cpu_xcc, cpu_fprs; +static TCGv cpu_xcc_Z; +static TCGv cpu_xcc_C; +static TCGv_i32 cpu_fprs; static TCGv cpu_gsr; #else # define cpu_fprs ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_gsr ({ qemu_build_not_reached(); (TCGv)NULL; }) #endif + +#ifdef TARGET_SPARC64 +#define cpu_cc_Z cpu_xcc_Z +#define cpu_cc_C cpu_xcc_C +#else +#define cpu_cc_Z cpu_icc_Z +#define cpu_cc_C cpu_icc_C +#define cpu_xcc_Z ({ qemu_build_not_reached(); NULL; }) +#define cpu_xcc_C ({ qemu_build_not_reached(); NULL; }) +#endif + /* Floating point registers */ static TCGv_i64 cpu_fpr[TARGET_DPREGS]; =20 @@ -366,31 +382,6 @@ static void gen_goto_tb(DisasContext *s, int tb_num, } } =20 -// XXX suboptimal -static void gen_mov_reg_N(TCGv reg, TCGv_i32 src) -{ - tcg_gen_extu_i32_tl(reg, src); - tcg_gen_extract_tl(reg, reg, PSR_NEG_SHIFT, 1); -} - -static void gen_mov_reg_Z(TCGv reg, TCGv_i32 src) -{ - tcg_gen_extu_i32_tl(reg, src); - tcg_gen_extract_tl(reg, reg, PSR_ZERO_SHIFT, 1); -} - -static void gen_mov_reg_V(TCGv reg, TCGv_i32 src) -{ - tcg_gen_extu_i32_tl(reg, src); - tcg_gen_extract_tl(reg, reg, PSR_OVF_SHIFT, 1); -} - -static void gen_mov_reg_C(TCGv reg, TCGv_i32 src) -{ - tcg_gen_extu_i32_tl(reg, src); - tcg_gen_extract_tl(reg, reg, PSR_CARRY_SHIFT, 1); -} - static void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) { tcg_gen_mov_tl(cpu_cc_src, src1); @@ -640,13 +631,11 @@ static void gen_op_mulscc(TCGv dst, TCGv src1, TCGv s= rc2) tcg_gen_deposit_tl(cpu_y, t0, cpu_cc_src, 31, 1); =20 // b1 =3D N ^ V; - gen_mov_reg_N(t0, cpu_psr); - gen_mov_reg_V(r_temp, cpu_psr); - tcg_gen_xor_tl(t0, t0, r_temp); + tcg_gen_xor_tl(t0, cpu_cc_N, cpu_cc_V); =20 // T0 =3D (b1 << 31) | (T0 >> 1); // src1 =3D T0; - tcg_gen_shli_tl(t0, t0, 31); + tcg_gen_andi_tl(t0, t0, 1u << 31); tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1); tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); =20 @@ -825,114 +814,12 @@ static void gen_op_eval_ba(TCGv dst) tcg_gen_movi_tl(dst, 1); } =20 -// Z -static void gen_op_eval_be(TCGv dst, TCGv_i32 src) -{ - gen_mov_reg_Z(dst, src); -} - -// Z | (N ^ V) -static void gen_op_eval_ble(TCGv dst, TCGv_i32 src) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_N(t0, src); - gen_mov_reg_V(dst, src); - tcg_gen_xor_tl(dst, dst, t0); - gen_mov_reg_Z(t0, src); - tcg_gen_or_tl(dst, dst, t0); -} - -// N ^ V -static void gen_op_eval_bl(TCGv dst, TCGv_i32 src) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_V(t0, src); - gen_mov_reg_N(dst, src); - tcg_gen_xor_tl(dst, dst, t0); -} - -// C | Z -static void gen_op_eval_bleu(TCGv dst, TCGv_i32 src) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_Z(t0, src); - gen_mov_reg_C(dst, src); - tcg_gen_or_tl(dst, dst, t0); -} - -// C -static void gen_op_eval_bcs(TCGv dst, TCGv_i32 src) -{ - gen_mov_reg_C(dst, src); -} - -// V -static void gen_op_eval_bvs(TCGv dst, TCGv_i32 src) -{ - gen_mov_reg_V(dst, src); -} - // 0 static void gen_op_eval_bn(TCGv dst) { tcg_gen_movi_tl(dst, 0); } =20 -// N -static void gen_op_eval_bneg(TCGv dst, TCGv_i32 src) -{ - gen_mov_reg_N(dst, src); -} - -// !Z -static void gen_op_eval_bne(TCGv dst, TCGv_i32 src) -{ - gen_mov_reg_Z(dst, src); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// !(Z | (N ^ V)) -static void gen_op_eval_bg(TCGv dst, TCGv_i32 src) -{ - gen_op_eval_ble(dst, src); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// !(N ^ V) -static void gen_op_eval_bge(TCGv dst, TCGv_i32 src) -{ - gen_op_eval_bl(dst, src); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// !(C | Z) -static void gen_op_eval_bgu(TCGv dst, TCGv_i32 src) -{ - gen_op_eval_bleu(dst, src); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// !C -static void gen_op_eval_bcc(TCGv dst, TCGv_i32 src) -{ - gen_mov_reg_C(dst, src); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// !N -static void gen_op_eval_bpos(TCGv dst, TCGv_i32 src) -{ - gen_mov_reg_N(dst, src); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// !V -static void gen_op_eval_bvc(TCGv dst, TCGv_i32 src) -{ - gen_mov_reg_V(dst, src); - tcg_gen_xori_tl(dst, dst, 0x1); -} - /* FPSR bit field FCC1 | FCC0: 0 =3D @@ -1249,34 +1136,22 @@ static void gen_compare(DisasCompare *cmp, bool xcc= , unsigned int cond, TCG_COND_ALWAYS, /* vc: !V -> 1 */ }; =20 - TCGv_i32 r_src; - TCGv r_dst; + TCGv t1, t2; =20 -#ifdef TARGET_SPARC64 - if (xcc) { - r_src =3D cpu_xcc; - } else { - r_src =3D cpu_psr; - } -#else - r_src =3D cpu_psr; -#endif + cmp->is_bool =3D false; =20 switch (dc->cc_op) { case CC_OP_LOGIC: cmp->cond =3D logic_cond[cond]; do_compare_dst_0: - cmp->is_bool =3D false; cmp->c2 =3D tcg_constant_tl(0); -#ifdef TARGET_SPARC64 - if (!xcc) { - cmp->c1 =3D tcg_temp_new(); - tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst); - break; + if (TARGET_LONG_BITS =3D=3D 32 || xcc) { + cmp->c1 =3D cpu_cc_dst; + } else { + cmp->c1 =3D t1 =3D tcg_temp_new(); + tcg_gen_ext32s_tl(t1, cpu_cc_dst); } -#endif - cmp->c1 =3D cpu_cc_dst; - break; + return; =20 case CC_OP_SUB: switch (cond) { @@ -1287,92 +1162,127 @@ static void gen_compare(DisasCompare *cmp, bool xc= c, unsigned int cond, =20 case 7: /* overflow */ case 15: /* !overflow */ - goto do_dynamic; + break; =20 default: cmp->cond =3D subcc_cond[cond]; - cmp->is_bool =3D false; -#ifdef TARGET_SPARC64 - if (!xcc) { + if (TARGET_LONG_BITS =3D=3D 32 || xcc) { + cmp->c1 =3D cpu_cc_src; + cmp->c2 =3D cpu_cc_src2; + } else { /* Note that sign-extension works for unsigned compares as long as both operands are sign-extended. */ - cmp->c1 =3D tcg_temp_new(); - cmp->c2 =3D tcg_temp_new(); - tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src); - tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2); - break; + cmp->c1 =3D t1 =3D tcg_temp_new(); + tcg_gen_ext32s_tl(t1, cpu_cc_src); + cmp->c2 =3D t2 =3D tcg_temp_new(); + tcg_gen_ext32s_tl(t2, cpu_cc_src2); } -#endif - cmp->c1 =3D cpu_cc_src; - cmp->c2 =3D cpu_cc_src2; - break; + return; } break; =20 default: - do_dynamic: gen_helper_compute_psr(tcg_env); dc->cc_op =3D CC_OP_FLAGS; - /* FALLTHRU */ + break; =20 case CC_OP_FLAGS: - /* We're going to generate a boolean result. */ - cmp->cond =3D TCG_COND_NE; - cmp->is_bool =3D true; - cmp->c1 =3D r_dst =3D tcg_temp_new(); - cmp->c2 =3D tcg_constant_tl(0); + break; + } =20 - switch (cond) { - case 0x0: - gen_op_eval_bn(r_dst); - break; - case 0x1: - gen_op_eval_be(r_dst, r_src); - break; - case 0x2: - gen_op_eval_ble(r_dst, r_src); - break; - case 0x3: - gen_op_eval_bl(r_dst, r_src); - break; - case 0x4: - gen_op_eval_bleu(r_dst, r_src); - break; - case 0x5: - gen_op_eval_bcs(r_dst, r_src); - break; - case 0x6: - gen_op_eval_bneg(r_dst, r_src); - break; - case 0x7: - gen_op_eval_bvs(r_dst, r_src); - break; - case 0x8: - gen_op_eval_ba(r_dst); - break; - case 0x9: - gen_op_eval_bne(r_dst, r_src); - break; - case 0xa: - gen_op_eval_bg(r_dst, r_src); - break; - case 0xb: - gen_op_eval_bge(r_dst, r_src); - break; - case 0xc: - gen_op_eval_bgu(r_dst, r_src); - break; - case 0xd: - gen_op_eval_bcc(r_dst, r_src); - break; - case 0xe: - gen_op_eval_bpos(r_dst, r_src); - break; - case 0xf: - gen_op_eval_bvc(r_dst, r_src); - break; + cmp->c1 =3D t1 =3D tcg_temp_new(); + cmp->c2 =3D tcg_constant_tl(0); + + switch (cond & 7) { + case 0x0: /* never */ + cmp->cond =3D TCG_COND_NEVER; + cmp->c1 =3D cmp->c2; + break; + + case 0x1: /* eq: Z */ + cmp->cond =3D TCG_COND_EQ; + if (TARGET_LONG_BITS =3D=3D 32 || xcc) { + tcg_gen_mov_tl(t1, cpu_cc_Z); + } else { + tcg_gen_ext32u_tl(t1, cpu_icc_Z); } break; + + case 0x2: /* le: Z | (N ^ V) */ + /* + * Simplify: + * cc_Z || (N ^ V) < 0 NE + * cc_Z && !((N ^ V) < 0) EQ + * cc_Z & ~((N ^ V) >> TLB) EQ + */ + cmp->cond =3D TCG_COND_EQ; + tcg_gen_xor_tl(t1, cpu_cc_N, cpu_cc_V); + tcg_gen_sextract_tl(t1, t1, xcc ? 63 : 31, 1); + tcg_gen_andc_tl(t1, xcc ? cpu_cc_Z : cpu_icc_Z, t1); + if (TARGET_LONG_BITS =3D=3D 64 && !xcc) { + tcg_gen_ext32u_tl(t1, t1); + } + break; + + case 0x3: /* lt: N ^ V */ + cmp->cond =3D TCG_COND_LT; + tcg_gen_xor_tl(t1, cpu_cc_N, cpu_cc_V); + if (TARGET_LONG_BITS =3D=3D 64 && !xcc) { + tcg_gen_ext32s_tl(t1, t1); + } + break; + + case 0x4: /* leu: Z | C */ + /* + * Simplify: + * cc_Z =3D=3D 0 || cc_C !=3D 0 NE + * cc_Z !=3D 0 && cc_C =3D=3D 0 EQ + * cc_Z & (cc_C ? 0 : -1) EQ + * cc_Z & (cc_C - 1) EQ + */ + cmp->cond =3D TCG_COND_EQ; + if (TARGET_LONG_BITS =3D=3D 32 || xcc) { + tcg_gen_subi_tl(t1, cpu_cc_C, 1); + tcg_gen_and_tl(t1, t1, cpu_cc_Z); + } else { + tcg_gen_extract_tl(t1, cpu_icc_C, 32, 1); + tcg_gen_subi_tl(t1, t1, 1); + tcg_gen_and_tl(t1, t1, cpu_icc_Z); + tcg_gen_ext32u_tl(t1, t1); + } + break; + + case 0x5: /* ltu: C */ + cmp->cond =3D TCG_COND_NE; + cmp->is_bool =3D true; + if (TARGET_LONG_BITS =3D=3D 32 || xcc) { + tcg_gen_mov_tl(t1, cpu_cc_C); + } else { + tcg_gen_extract_tl(t1, cpu_icc_C, 32, 1); + } + break; + + case 0x6: /* neg: N */ + cmp->cond =3D TCG_COND_LT; + if (TARGET_LONG_BITS =3D=3D 32 || xcc) { + tcg_gen_mov_tl(t1, cpu_cc_N); + } else { + tcg_gen_ext32s_tl(t1, cpu_cc_N); + } + break; + + case 0x7: /* vs: V */ + cmp->cond =3D TCG_COND_LT; + if (TARGET_LONG_BITS =3D=3D 32 || xcc) { + tcg_gen_mov_tl(t1, cpu_cc_V); + } else { + tcg_gen_ext32s_tl(t1, cpu_cc_V); + } + break; + } + if (cond & 8) { + cmp->cond =3D tcg_invert_cond(cmp->cond); + cmp->is_bool =3D false; } } =20 @@ -5513,17 +5423,21 @@ void sparc_tcg_init(void) =20 static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[= ] =3D { #ifdef TARGET_SPARC64 - { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" }, { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" }, #endif { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" }, - { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" }, }; =20 static const struct { TCGv *ptr; int off; const char *name; } rtl[] = =3D { #ifdef TARGET_SPARC64 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" }, + { &cpu_xcc_Z, offsetof(CPUSPARCState, xcc_Z), "xcc_Z" }, + { &cpu_xcc_C, offsetof(CPUSPARCState, xcc_C), "xcc_C" }, #endif + { &cpu_cc_N, offsetof(CPUSPARCState, cc_N), "cc_N" }, + { &cpu_cc_V, offsetof(CPUSPARCState, cc_V), "cc_V" }, + { &cpu_icc_Z, offsetof(CPUSPARCState, icc_Z), "icc_Z" }, + { &cpu_icc_C, offsetof(CPUSPARCState, icc_C), "icc_C" }, { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" }, { &cpu_cc_src, offsetof(CPUSPARCState, cc_src), "cc_src" }, { &cpu_cc_src2, offsetof(CPUSPARCState, cc_src2), "cc_src2" }, diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c index bf2c90c780..f0ff6bf5db 100644 --- a/target/sparc/win_helper.c +++ b/target/sparc/win_helper.c @@ -53,23 +53,44 @@ void cpu_set_cwp(CPUSPARCState *env, int new_cwp) =20 target_ulong cpu_get_psr(CPUSPARCState *env) { + target_ulong icc =3D 0; + helper_compute_psr(env); =20 + icc |=3D ((int32_t)env->cc_N < 0) << PSR_NEG_SHIFT; + icc |=3D ((int32_t)env->cc_V < 0) << PSR_OVF_SHIFT; + icc |=3D ((int32_t)env->icc_Z =3D=3D 0) << PSR_ZERO_SHIFT; + if (TARGET_LONG_BITS =3D=3D 64) { + icc |=3D extract64(env->icc_C, 32, 1) << PSR_CARRY_SHIFT; + } else { + icc |=3D env->icc_C << PSR_CARRY_SHIFT; + } + #if !defined(TARGET_SPARC64) - return env->version | (env->psr & PSR_ICC) | + return env->version | icc | (env->psref ? PSR_EF : 0) | (env->psrpil << 8) | (env->psrs ? PSR_S : 0) | (env->psrps ? PSR_PS : 0) | (env->psret ? PSR_ET : 0) | env->cwp; #else - return env->psr & PSR_ICC; + return icc; #endif } =20 void cpu_put_psr_icc(CPUSPARCState *env, target_ulong val) { - env->psr =3D val & PSR_ICC; + if (TARGET_LONG_BITS =3D=3D 64) { + /* Do not clobber xcc.[NV] */ + env->cc_N =3D deposit64(env->cc_N, 0, 32, -(val & PSR_NEG)); + env->cc_V =3D deposit64(env->cc_V, 0, 32, -(val & PSR_OVF)); + env->icc_C =3D -(val & PSR_CARRY); + } else { + env->cc_N =3D -(val & PSR_NEG); + env->cc_V =3D -(val & PSR_OVF); + env->icc_C =3D (val >> PSR_CARRY_SHIFT) & 1; + } + env->icc_Z =3D ~val & PSR_ZERO; } =20 void cpu_put_psr_raw(CPUSPARCState *env, target_ulong val) @@ -249,17 +270,32 @@ void helper_restored(CPUSPARCState *env) =20 target_ulong cpu_get_ccr(CPUSPARCState *env) { - target_ulong psr; + target_ulong ccr =3D 0; =20 - psr =3D cpu_get_psr(env); + helper_compute_psr(env); =20 - return ((env->xcc >> 20) << 4) | ((psr & PSR_ICC) >> 20); + ccr |=3D (env->icc_C >> 32) & 1; + ccr |=3D ((int32_t)env->cc_V < 0) << 1; + ccr |=3D ((int32_t)env->icc_Z =3D=3D 0) << 2; + ccr |=3D ((int32_t)env->cc_N < 0) << 3; + + ccr |=3D env->xcc_C << 4; + ccr |=3D (env->cc_V < 0) << 5; + ccr |=3D (env->xcc_Z =3D=3D 0) << 6; + ccr |=3D (env->cc_N < 0) << 7; + + return ccr; } =20 void cpu_put_ccr(CPUSPARCState *env, target_ulong val) { - env->xcc =3D (val >> 4) << 20; - env->psr =3D (val & 0xf) << 20; + env->cc_N =3D deposit64(-(val & 0x08), 32, 32, -(val & 0x80)); + env->cc_V =3D deposit64(-(val & 0x02), 32, 32, -(val & 0x20)); + env->icc_C =3D (uint64_t)val << 32; + env->xcc_C =3D (val >> 4) & 1; + env->icc_Z =3D ~val & 0x04; + env->xcc_Z =3D ~val & 0x40; + CC_OP =3D CC_OP_FLAGS; } =20 --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699215309; cv=none; d=zohomail.com; s=zohoarc; b=go4N9NV7WhrL7q9x9IdWBfrxvzw7GkCeq76b/kVwpUmWZtUzKsYY4Jvd+FszrqvqLwsN/mF9vOh9ckCFVs1KoufSpIsCsGFyrXUTkiZaEZX/aona4aQNDZp4I83ZwtrwwawEGbm5jE3QN77jvzZBWZ8oyxiqD4fzGzhKwcDqcRY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699215309; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=G+GbngnMW6dV1sogxAl0SpJAATwXgEo/1Lj1GEu+6gM=; b=TCFoV35W07Vr0zkC8Ugqok7p53pbhWMNK4EHtXHxiQm+ZER/VKO30CNSU/m/pe7jOqfjXO6x/4DE84lgvuwT84OXcnieFb/Mt8cIhomTiHqcKFvK43Q14PSfm2WLFmEUyFvHOKyQYWS7q4Vecnk/Fu9XQOKhXpootpGJYcvykf4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699215309338775.3974116845586; Sun, 5 Nov 2023 12:15:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qzjTy-0003Av-Hv; Sun, 05 Nov 2023 15:12:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qzjTx-0003AD-L1 for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:29 -0500 Received: from mail-oi1-x236.google.com ([2607:f8b0:4864:20::236]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qzjTv-00027o-Oc for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:29 -0500 Received: by mail-oi1-x236.google.com with SMTP id 5614622812f47-3b2e330033fso2357395b6e.3 for ; Sun, 05 Nov 2023 12:12:27 -0800 (PST) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215310973100012 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 1 - target/sparc/cc_helper.c | 14 +-------- target/sparc/translate.c | 66 ++++++++++++++++------------------------ 3 files changed, 28 insertions(+), 53 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index ea8a04c6e3..202c34f7ca 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -159,7 +159,6 @@ enum { CC_OP_SUBX, /* modify all flags, CC_DST =3D res, CC_SRC =3D src1 */ CC_OP_TSUB, /* modify all flags, CC_DST =3D res, CC_SRC =3D src1 */ CC_OP_TSUBTV, /* modify all flags except V, CC_DST =3D res, CC_SRC = =3D src1 */ - CC_OP_LOGIC, /* modify N and Z, C =3D V =3D 0, CC_DST =3D res */ CC_OP_NB, }; =20 diff --git a/target/sparc/cc_helper.c b/target/sparc/cc_helper.c index 46bec69d96..1622300a14 100644 --- a/target/sparc/cc_helper.c +++ b/target/sparc/cc_helper.c @@ -378,16 +378,6 @@ static uint32_t compute_all_tsubtv(CPUSPARCState *env) return ret; } =20 -static uint32_t compute_all_logic(CPUSPARCState *env) -{ - return get_NZ_icc(CC_DST); -} - -static uint32_t compute_C_logic(CPUSPARCState *env) -{ - return 0; -} - #ifdef TARGET_SPARC64 static uint32_t compute_all_logic_xcc(CPUSPARCState *env) { @@ -411,13 +401,12 @@ static const CCTable icc_table[CC_OP_NB] =3D { [CC_OP_SUBX] =3D { compute_all_subx, compute_C_subx }, [CC_OP_TSUB] =3D { compute_all_tsub, compute_C_sub }, [CC_OP_TSUBTV] =3D { compute_all_tsubtv, compute_C_sub }, - [CC_OP_LOGIC] =3D { compute_all_logic, compute_C_logic }, }; =20 #ifdef TARGET_SPARC64 static const CCTable xcc_table[CC_OP_NB] =3D { /* CC_OP_DYNAMIC should never happen */ - [CC_OP_DIV] =3D { compute_all_logic_xcc, compute_C_logic }, + [CC_OP_DIV] =3D { compute_all_logic_xcc, compute_C_div }, [CC_OP_ADD] =3D { compute_all_add_xcc, compute_C_add_xcc }, [CC_OP_ADDX] =3D { compute_all_addx_xcc, compute_C_addx_xcc }, [CC_OP_TADD] =3D { compute_all_add_xcc, compute_C_add_xcc }, @@ -426,7 +415,6 @@ static const CCTable xcc_table[CC_OP_NB] =3D { [CC_OP_SUBX] =3D { compute_all_subx_xcc, compute_C_subx_xcc }, [CC_OP_TSUB] =3D { compute_all_sub_xcc, compute_C_sub_xcc }, [CC_OP_TSUBTV] =3D { compute_all_sub_xcc, compute_C_sub_xcc }, - [CC_OP_LOGIC] =3D { compute_all_logic_xcc, compute_C_logic }, }; #endif =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 261f142636..b11d89343b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1117,48 +1117,24 @@ static void gen_compare(DisasCompare *cmp, bool xcc= , unsigned int cond, -1, /* no overflow */ }; =20 - static int logic_cond[16] =3D { - TCG_COND_NEVER, - TCG_COND_EQ, /* eq: Z */ - TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */ - TCG_COND_LT, /* lt: N ^ V -> N */ - TCG_COND_EQ, /* leu: C | Z -> Z */ - TCG_COND_NEVER, /* ltu: C -> 0 */ - TCG_COND_LT, /* neg: N */ - TCG_COND_NEVER, /* vs: V -> 0 */ - TCG_COND_ALWAYS, - TCG_COND_NE, /* ne: !Z */ - TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */ - TCG_COND_GE, /* ge: !(N ^ V) -> !N */ - TCG_COND_NE, /* gtu: !(C | Z) -> !Z */ - TCG_COND_ALWAYS, /* geu: !C -> 1 */ - TCG_COND_GE, /* pos: !N */ - TCG_COND_ALWAYS, /* vc: !V -> 1 */ - }; - TCGv t1, t2; =20 cmp->is_bool =3D false; =20 switch (dc->cc_op) { - case CC_OP_LOGIC: - cmp->cond =3D logic_cond[cond]; - do_compare_dst_0: - cmp->c2 =3D tcg_constant_tl(0); - if (TARGET_LONG_BITS =3D=3D 32 || xcc) { - cmp->c1 =3D cpu_cc_dst; - } else { - cmp->c1 =3D t1 =3D tcg_temp_new(); - tcg_gen_ext32s_tl(t1, cpu_cc_dst); - } - return; - case CC_OP_SUB: switch (cond) { case 6: /* neg */ case 14: /* pos */ cmp->cond =3D (cond =3D=3D 6 ? TCG_COND_LT : TCG_COND_GE); - goto do_compare_dst_0; + cmp->c2 =3D tcg_constant_tl(0); + if (TARGET_LONG_BITS =3D=3D 32 || xcc) { + cmp->c1 =3D cpu_cc_dst; + } else { + cmp->c1 =3D t1 =3D tcg_temp_new(); + tcg_gen_ext32s_tl(t1, cpu_cc_dst); + } + return; =20 case 7: /* overflow */ case 15: /* !overflow */ @@ -3652,7 +3628,8 @@ TRANS(NOP_v9, 64, trans_NOP, a) =20 static bool do_arith_int(DisasContext *dc, arg_r_r_ri_cc *a, int cc_op, void (*func)(TCGv, TCGv, TCGv), - void (*funci)(TCGv, TCGv, target_long)) + void (*funci)(TCGv, TCGv, target_long), + bool logic_cc) { TCGv dst, src1; =20 @@ -3661,7 +3638,9 @@ static bool do_arith_int(DisasContext *dc, arg_r_r_ri= _cc *a, int cc_op, return false; } =20 - if (a->cc) { + if (logic_cc) { + dst =3D cpu_cc_N; + } else if (a->cc && cc_op > CC_OP_FLAGS) { dst =3D cpu_cc_dst; } else { dst =3D gen_dest_gpr(dc, a->rd); @@ -3677,6 +3656,17 @@ static bool do_arith_int(DisasContext *dc, arg_r_r_r= i_cc *a, int cc_op, } else { func(dst, src1, cpu_regs[a->rs2_or_imm]); } + + if (logic_cc) { + if (TARGET_LONG_BITS =3D=3D 64) { + tcg_gen_mov_tl(cpu_icc_Z, cpu_cc_N); + tcg_gen_movi_tl(cpu_icc_C, 0); + } + tcg_gen_mov_tl(cpu_cc_Z, cpu_cc_N); + tcg_gen_movi_tl(cpu_cc_C, 0); + tcg_gen_movi_tl(cpu_cc_V, 0); + } + gen_store_gpr(dc, a->rd, dst); =20 if (a->cc) { @@ -3693,16 +3683,16 @@ static bool do_arith(DisasContext *dc, arg_r_r_ri_c= c *a, int cc_op, { if (a->cc) { assert(cc_op >=3D 0); - return do_arith_int(dc, a, cc_op, func_cc, NULL); + return do_arith_int(dc, a, cc_op, func_cc, NULL, false); } - return do_arith_int(dc, a, cc_op, func, funci); + return do_arith_int(dc, a, cc_op, func, funci, false); } =20 static bool do_logic(DisasContext *dc, arg_r_r_ri_cc *a, void (*func)(TCGv, TCGv, TCGv), void (*funci)(TCGv, TCGv, target_long)) { - return do_arith_int(dc, a, CC_OP_LOGIC, func, funci); + return do_arith_int(dc, a, CC_OP_FLAGS, func, funci, a->cc); } =20 TRANS(ADD, ALL, do_arith, a, CC_OP_ADD, @@ -3754,7 +3744,6 @@ static bool trans_ADDC(DisasContext *dc, arg_r_r_ri_c= c *a) { switch (dc->cc_op) { case CC_OP_DIV: - case CC_OP_LOGIC: /* Carry is known to be zero. Fall back to plain ADD. */ return do_arith(dc, a, CC_OP_ADD, tcg_gen_add_tl, tcg_gen_addi_tl, gen_op_add_cc); @@ -3778,7 +3767,6 @@ static bool trans_SUBC(DisasContext *dc, arg_r_r_ri_c= c *a) { switch (dc->cc_op) { case CC_OP_DIV: - case CC_OP_LOGIC: /* Carry is known to be zero. Fall back to plain SUB. */ return do_arith(dc, a, CC_OP_SUB, tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_sub_cc); --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699215295; cv=none; d=zohomail.com; s=zohoarc; b=k2Xu4MxEP7NHxA21mki6e5l91I+o1Qnhe7AK+TSAsWAE6j74d3JnUDsqq3SyqXVA2f1W9ENJjJT2FRsWjXNgOqI0domyjxGWMja7JWzIehBHZrmgUne/crqUeqfRax1JKqsvh9Y2dSdEb6cOseiOazuG3w+BOM+2m9suB0IsWfY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699215295; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mfDnd1VBHVT7dNbMDcpBms0JCPxWtw5Xo9ZcnrHrk30=; b=gng+cirJMFKJWh5YtuGJIyS7+SyEEFRl1E+orpSX7AzyNxd43HWdvs9YaEo1R2DVzoHvcBqDnOxLKG4YtUuK0LufmnDPid3Y7Gyfmgjrj5CqXhmQiu9ouH0syx815g7+QXDjpVeo2tmDGFqUteN5l5LZiuJWNZgpBBaMUB/5rqo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16992152959081001.5571719371466; Sun, 5 Nov 2023 12:14:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qzjUC-0003Rs-Ln; Sun, 05 Nov 2023 15:12:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qzjU9-0003Pi-Ql for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:41 -0500 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qzjTx-000288-1c for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:41 -0500 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-6b3c2607d9bso3078737b3a.1 for ; Sun, 05 Nov 2023 12:12:28 -0800 (PST) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u23-20020a056a00099700b006884549adc8sm4359777pfg.29.2023.11.05.12.12.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Nov 2023 12:12:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699215147; x=1699819947; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mfDnd1VBHVT7dNbMDcpBms0JCPxWtw5Xo9ZcnrHrk30=; b=lsGOsAxEUv2r2SRq2OqtnhUogp8ZyDmCiLDVgGZSNbsayIpGU/wp8e8VhOjqAxvyBo 66nwk8DB4eKLkmrr7RVcB/v2rWXBQSTRcTRnkY3i+3gsnwxJf51prMMD0EXEGCyoig+c 3rPWjfgOZ7qfAIMFSfWaU1f9Tk31e7LnvEht0BYxJdW7zwuNocIs4T/1x9HMAyECEtYN PN/xNytR8SeNBXhV7FZtsBFhIqkb48QGN/InAUAOzwgExpBdCJAnjjutkWqLScVOckur UyktuhyQLCiv6QaXG6981OHiT/OCkqG6oIL+B3im/msQAXo3r8jcuahDhTNm4fVCqoYJ tdVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699215147; x=1699819947; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mfDnd1VBHVT7dNbMDcpBms0JCPxWtw5Xo9ZcnrHrk30=; b=o2KEIhgZHNcME8YpJKwfBteob48ZAHV6WEPFFNarWT56pgxAp9dwN8KPkDc5D+Cqup AOiASgiunD8FdXfOEStJxQpNx+4RvUW0ZEZG6bljmC1KHLTlSCXkb2U1VTQE3hWuUyVh nYbLqlpyqvODAG/s3DOhGH9rZ1EpPH6bHpCIX/EIEwKfy7algC/Xp8umiSgMuy3fZfxJ PG+obKXzGfduIz+QUbNhXUSBwNatlsvjyZyXdaKUZyFuWeWAb/h08T4P5OBduMdDphYJ udedJ3DOMrOtpEdcvnuZqbKzllAaeuEo4B6Zug3f3l47JYHD19RccBoPhknDxEK8g1SS wodA== X-Gm-Message-State: AOJu0YyXL4gFcQhkwiQdxFUamRhWjT1jn5/QujjL7+rub9mw5h6tcBEQ T9rC882xeeGughaMtKFUgPIhRmTXoBtnkv9toiI= X-Google-Smtp-Source: AGHT+IHbtSoikb3ZzCKUfSVaVcxB+viy6bSD4g0e76A/uphAsulj049cATQKyvNprxdlpjPehciedA== X-Received: by 2002:a05:6a00:2e28:b0:68e:41e9:10be with SMTP id fc40-20020a056a002e2800b0068e41e910bemr26215550pfb.20.1699215147535; Sun, 05 Nov 2023 12:12:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 04/21] target/sparc: Remove CC_OP_DIV Date: Sun, 5 Nov 2023 12:12:05 -0800 Message-Id: <20231105201222.202395-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231105201222.202395-1-richard.henderson@linaro.org> References: <20231105201222.202395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215296906100007 Content-Type: text/plain; charset="utf-8" Return both result and overflow from helper_[us]div. Compute all flags explicitly in gen_op_[us]divcc. Marginally improve the INT64_MIN special case in helper_sdiv. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 1 - target/sparc/helper.h | 6 +-- target/sparc/cc_helper.c | 33 ------------- target/sparc/helper.c | 101 ++++++++++++++------------------------- target/sparc/translate.c | 70 ++++++++++++++++++++++----- 5 files changed, 97 insertions(+), 114 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 202c34f7ca..b16d53b91f 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -150,7 +150,6 @@ enum { enum { CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ CC_OP_FLAGS, /* all cc are back in cc_*_[NZCV] registers */ - CC_OP_DIV, /* modify N, Z and V, C =3D 0*/ CC_OP_ADD, /* modify all flags, CC_DST =3D res, CC_SRC =3D src1 */ CC_OP_ADDX, /* modify all flags, CC_DST =3D res, CC_SRC =3D src1 */ CC_OP_TADD, /* modify all flags, CC_DST =3D res, CC_SRC =3D src1 */ diff --git a/target/sparc/helper.h b/target/sparc/helper.h index dd1721a340..a7b0079c3b 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -27,10 +27,8 @@ DEF_HELPER_FLAGS_2(tick_set_limit, TCG_CALL_NO_RWG, void= , ptr, i64) DEF_HELPER_1(debug, void, env) DEF_HELPER_1(save, void, env) DEF_HELPER_1(restore, void, env) -DEF_HELPER_3(udiv, tl, env, tl, tl) -DEF_HELPER_3(udiv_cc, tl, env, tl, tl) -DEF_HELPER_3(sdiv, tl, env, tl, tl) -DEF_HELPER_3(sdiv_cc, tl, env, tl, tl) +DEF_HELPER_FLAGS_3(udiv, TCG_CALL_NO_WG, i64, env, tl, tl) +DEF_HELPER_FLAGS_3(sdiv, TCG_CALL_NO_WG, i64, env, tl, tl) DEF_HELPER_3(taddcctv, tl, env, tl, tl) DEF_HELPER_3(tsubcctv, tl, env, tl, tl) #ifdef TARGET_SPARC64 diff --git a/target/sparc/cc_helper.c b/target/sparc/cc_helper.c index 1622300a14..5400dfec15 100644 --- a/target/sparc/cc_helper.c +++ b/target/sparc/cc_helper.c @@ -47,30 +47,6 @@ static inline uint32_t get_NZ_xcc(target_long dst) } #endif =20 -static inline uint32_t get_V_div_icc(target_ulong src2) -{ - uint32_t ret =3D 0; - - if (src2 !=3D 0) { - ret =3D PSR_OVF; - } - return ret; -} - -static uint32_t compute_all_div(CPUSPARCState *env) -{ - uint32_t ret; - - ret =3D get_NZ_icc(CC_DST); - ret |=3D get_V_div_icc(CC_SRC2); - return ret; -} - -static uint32_t compute_C_div(CPUSPARCState *env) -{ - return 0; -} - static inline uint32_t get_C_add_icc(uint32_t dst, uint32_t src1) { uint32_t ret =3D 0; @@ -378,13 +354,6 @@ static uint32_t compute_all_tsubtv(CPUSPARCState *env) return ret; } =20 -#ifdef TARGET_SPARC64 -static uint32_t compute_all_logic_xcc(CPUSPARCState *env) -{ - return get_NZ_xcc(CC_DST); -} -#endif - typedef struct CCTable { uint32_t (*compute_all)(CPUSPARCState *env); /* return all the flags */ uint32_t (*compute_c)(CPUSPARCState *env); /* return the C flag */ @@ -392,7 +361,6 @@ typedef struct CCTable { =20 static const CCTable icc_table[CC_OP_NB] =3D { /* CC_OP_DYNAMIC should never happen */ - [CC_OP_DIV] =3D { compute_all_div, compute_C_div }, [CC_OP_ADD] =3D { compute_all_add, compute_C_add }, [CC_OP_ADDX] =3D { compute_all_addx, compute_C_addx }, [CC_OP_TADD] =3D { compute_all_tadd, compute_C_add }, @@ -406,7 +374,6 @@ static const CCTable icc_table[CC_OP_NB] =3D { #ifdef TARGET_SPARC64 static const CCTable xcc_table[CC_OP_NB] =3D { /* CC_OP_DYNAMIC should never happen */ - [CC_OP_DIV] =3D { compute_all_logic_xcc, compute_C_div }, [CC_OP_ADD] =3D { compute_all_add_xcc, compute_C_add_xcc }, [CC_OP_ADDX] =3D { compute_all_addx_xcc, compute_C_addx_xcc }, [CC_OP_TADD] =3D { compute_all_add_xcc, compute_C_add_xcc }, diff --git a/target/sparc/helper.c b/target/sparc/helper.c index 2bcdc81d54..53eec693dd 100644 --- a/target/sparc/helper.c +++ b/target/sparc/helper.c @@ -81,79 +81,52 @@ void helper_tick_set_limit(void *opaque, uint64_t limit) } #endif =20 -static target_ulong do_udiv(CPUSPARCState *env, target_ulong a, - target_ulong b, int cc, uintptr_t ra) +uint64_t helper_udiv(CPUSPARCState *env, target_ulong a, target_ulong b) { - int overflow =3D 0; - uint64_t x0; - uint32_t x1; + uint64_t a64 =3D (uint32_t)a | ((uint64_t)env->y << 32); + uint32_t b32 =3D b; + uint32_t r; =20 - x0 =3D (a & 0xffffffff) | ((int64_t) (env->y) << 32); - x1 =3D (b & 0xffffffff); - - if (x1 =3D=3D 0) { - cpu_raise_exception_ra(env, TT_DIV_ZERO, ra); + if (b32 =3D=3D 0) { + cpu_raise_exception_ra(env, TT_DIV_ZERO, GETPC()); } =20 - x0 =3D x0 / x1; - if (x0 > UINT32_MAX) { - x0 =3D UINT32_MAX; - overflow =3D 1; + a64 /=3D b32; + r =3D a64; + if (unlikely(a64 > UINT32_MAX)) { + return -1; /* r =3D UINT32_MAX, v =3D 1 */ + } + return r; +} + +uint64_t helper_sdiv(CPUSPARCState *env, target_ulong a, target_ulong b) +{ + int64_t a64 =3D (uint32_t)a | ((uint64_t)env->y << 32); + int32_t b32 =3D b; + int32_t r; + + if (b32 =3D=3D 0) { + cpu_raise_exception_ra(env, TT_DIV_ZERO, GETPC()); } =20 - if (cc) { - env->cc_src2 =3D overflow; - } - return x0; -} - -target_ulong helper_udiv(CPUSPARCState *env, target_ulong a, target_ulong = b) -{ - return do_udiv(env, a, b, 0, GETPC()); -} - -target_ulong helper_udiv_cc(CPUSPARCState *env, target_ulong a, target_ulo= ng b) -{ - return do_udiv(env, a, b, 1, GETPC()); -} - -static target_ulong do_sdiv(CPUSPARCState *env, target_ulong a, - target_ulong b, int cc, uintptr_t ra) -{ - int overflow =3D 0; - int64_t x0; - int32_t x1; - - x0 =3D (a & 0xffffffff) | ((int64_t) (env->y) << 32); - x1 =3D (b & 0xffffffff); - - if (x1 =3D=3D 0) { - cpu_raise_exception_ra(env, TT_DIV_ZERO, ra); - } else if (x1 =3D=3D -1 && x0 =3D=3D INT64_MIN) { - x0 =3D INT32_MAX; - overflow =3D 1; - } else { - x0 =3D x0 / x1; - if ((int32_t) x0 !=3D x0) { - x0 =3D x0 < 0 ? INT32_MIN : INT32_MAX; - overflow =3D 1; - } + if (unlikely(a64 =3D=3D INT64_MIN)) { + /* + * Special case INT64_MIN / -1 is required to avoid trap on x86 ho= st. + * However, with a dividend of INT64_MIN, there is no 32-bit divis= or + * which can yield a 32-bit result: + * INT64_MIN / INT32_MIN =3D 0x1_0000_0000 + * INT64_MIN / INT32_MAX =3D -0x1_0000_0002 + * Therefore we know we must overflow and saturate. + */ + return (uint32_t)(b32 < 0 ? INT32_MAX : INT32_MIN) | (-1ull << 32); } =20 - if (cc) { - env->cc_src2 =3D overflow; + a64 /=3D b; + r =3D a64; + if (unlikely(r !=3D a64)) { + return (uint32_t)(a64 < 0 ? INT32_MIN : INT32_MAX) | (-1ull << 32); } - return x0; -} - -target_ulong helper_sdiv(CPUSPARCState *env, target_ulong a, target_ulong = b) -{ - return do_sdiv(env, a, b, 0, GETPC()); -} - -target_ulong helper_sdiv_cc(CPUSPARCState *env, target_ulong a, target_ulo= ng b) -{ - return do_sdiv(env, a, b, 1, GETPC()); + return (uint32_t)r; } =20 #ifdef TARGET_SPARC64 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index b11d89343b..fa4bad6d1f 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -693,22 +693,76 @@ static void gen_op_sdivx(TCGv dst, TCGv src1, TCGv sr= c2) =20 static void gen_op_udiv(TCGv dst, TCGv src1, TCGv src2) { +#ifdef TARGET_SPARC64 gen_helper_udiv(dst, tcg_env, src1, src2); + tcg_gen_ext32u_tl(dst, dst); +#else + TCGv_i64 t64 =3D tcg_temp_new_i64(); + gen_helper_udiv(t64, tcg_env, src1, src2); + tcg_gen_trunc_i64_tl(dst, t64); +#endif } =20 static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2) { +#ifdef TARGET_SPARC64 gen_helper_sdiv(dst, tcg_env, src1, src2); + tcg_gen_ext32s_tl(dst, dst); +#else + TCGv_i64 t64 =3D tcg_temp_new_i64(); + gen_helper_sdiv(t64, tcg_env, src1, src2); + tcg_gen_trunc_i64_tl(dst, t64); +#endif } =20 static void gen_op_udivcc(TCGv dst, TCGv src1, TCGv src2) { - gen_helper_udiv_cc(dst, tcg_env, src1, src2); + TCGv_i64 t64; + +#ifdef TARGET_SPARC64 + t64 =3D cpu_cc_V; +#else + t64 =3D tcg_temp_new_i64(); +#endif + + gen_helper_udiv(t64, tcg_env, src1, src2); + +#ifdef TARGET_SPARC64 + tcg_gen_ext32u_tl(cpu_cc_N, t64); + tcg_gen_shri_tl(cpu_cc_V, t64, 32); + tcg_gen_mov_tl(cpu_icc_Z, cpu_cc_N); + tcg_gen_movi_tl(cpu_icc_C, 0); +#else + tcg_gen_extr_i64_tl(cpu_cc_N, cpu_cc_V, t64); +#endif + tcg_gen_mov_tl(cpu_cc_Z, cpu_cc_N); + tcg_gen_movi_tl(cpu_cc_C, 0); + tcg_gen_mov_tl(dst, cpu_cc_N); } =20 static void gen_op_sdivcc(TCGv dst, TCGv src1, TCGv src2) { - gen_helper_sdiv_cc(dst, tcg_env, src1, src2); + TCGv_i64 t64; + +#ifdef TARGET_SPARC64 + t64 =3D cpu_cc_V; +#else + t64 =3D tcg_temp_new_i64(); +#endif + + gen_helper_sdiv(t64, tcg_env, src1, src2); + +#ifdef TARGET_SPARC64 + tcg_gen_ext32s_tl(cpu_cc_N, t64); + tcg_gen_shri_tl(cpu_cc_V, t64, 32); + tcg_gen_mov_tl(cpu_icc_Z, cpu_cc_N); + tcg_gen_movi_tl(cpu_icc_C, 0); +#else + tcg_gen_extr_i64_tl(cpu_cc_N, cpu_cc_V, t64); +#endif + tcg_gen_mov_tl(cpu_cc_Z, cpu_cc_N); + tcg_gen_movi_tl(cpu_cc_C, 0); + tcg_gen_mov_tl(dst, cpu_cc_N); } =20 static void gen_op_taddcctv(TCGv dst, TCGv src1, TCGv src2) @@ -3717,8 +3771,8 @@ TRANS(SMUL, MUL, do_logic, a, gen_op_smul, NULL) =20 TRANS(UDIVX, 64, do_arith, a, -1, gen_op_udivx, NULL, NULL) TRANS(SDIVX, 64, do_arith, a, -1, gen_op_sdivx, NULL, NULL) -TRANS(UDIV, DIV, do_arith, a, CC_OP_DIV, gen_op_udiv, NULL, gen_op_udivcc) -TRANS(SDIV, DIV, do_arith, a, CC_OP_DIV, gen_op_sdiv, NULL, gen_op_sdivcc) +TRANS(UDIV, DIV, do_arith, a, CC_OP_FLAGS, gen_op_udiv, NULL, gen_op_udivc= c) +TRANS(SDIV, DIV, do_arith, a, CC_OP_FLAGS, gen_op_sdiv, NULL, gen_op_sdivc= c) =20 /* TODO: Should have feature bit -- comes in with UltraSparc T2. */ TRANS(POPC, 64, do_arith, a, -1, gen_op_popc, NULL, NULL) @@ -3743,10 +3797,6 @@ static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc= *a) static bool trans_ADDC(DisasContext *dc, arg_r_r_ri_cc *a) { switch (dc->cc_op) { - case CC_OP_DIV: - /* Carry is known to be zero. Fall back to plain ADD. */ - return do_arith(dc, a, CC_OP_ADD, - tcg_gen_add_tl, tcg_gen_addi_tl, gen_op_add_cc); case CC_OP_ADD: case CC_OP_TADD: case CC_OP_TADDTV: @@ -3766,10 +3816,6 @@ static bool trans_ADDC(DisasContext *dc, arg_r_r_ri_= cc *a) static bool trans_SUBC(DisasContext *dc, arg_r_r_ri_cc *a) { switch (dc->cc_op) { - case CC_OP_DIV: - /* Carry is known to be zero. Fall back to plain SUB. */ - return do_arith(dc, a, CC_OP_SUB, - tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_sub_cc); case CC_OP_ADD: case CC_OP_TADD: case CC_OP_TADDTV: --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699215343; cv=none; d=zohomail.com; s=zohoarc; b=k3accNyYYLzd5zToDs9ykJHRH2t2V6kh6DWdm2GVDsI547c2ols3ze8aTbR7t6eyzJrxCanbBd4qADOX+h925ZN1sk9+e9vzki2Ty7dkHdNhXE6RD8AnPR56zCDXemrMNVl+iceiW4/P4SWsinv+eMeak8sg41aY6ifTV+KGWDg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699215343; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=yQpQdg+Ve47t9/0/acUoknVWsHwfL0jjHwsIbvpzlWw=; b=j8O8s33oym3F6vNnTIR1uZOR3NV6yW9XYIpUcPuwjg/3g298hc5PHJYC7DopFwHfziPrSq22c0RTrhxGovZ+whbDkahi4+iukV8WS0ZTRQhKPASY7JlBx6+l/5BNj+qloePHcEiaTjYaKJmayviZsVW7DhDoJLeoGtqtxEYB9wM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699215343051332.47081448689164; Sun, 5 Nov 2023 12:15:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qzjU3-0003Dp-8Q; Sun, 05 Nov 2023 15:12:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qzjU1-0003CD-E4 for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:33 -0500 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qzjTy-00028D-Pc for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:33 -0500 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-6c115026985so3978633b3a.1 for ; Sun, 05 Nov 2023 12:12:29 -0800 (PST) Received: from stoup.. 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Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 3 - target/sparc/cc_helper.c | 92 --------------- target/sparc/translate.c | 247 ++++++++++++++------------------------- 3 files changed, 87 insertions(+), 255 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index b16d53b91f..4ee8e2dc92 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -150,9 +150,6 @@ enum { enum { CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ CC_OP_FLAGS, /* all cc are back in cc_*_[NZCV] registers */ - CC_OP_ADD, /* modify all flags, CC_DST =3D res, CC_SRC =3D src1 */ - CC_OP_ADDX, /* modify all flags, CC_DST =3D res, CC_SRC =3D src1 */ - CC_OP_TADD, /* modify all flags, CC_DST =3D res, CC_SRC =3D src1 */ CC_OP_TADDTV, /* modify all flags except V, CC_DST =3D res, CC_SRC = =3D src1 */ CC_OP_SUB, /* modify all flags, CC_DST =3D res, CC_SRC =3D src1 */ CC_OP_SUBX, /* modify all flags, CC_DST =3D res, CC_SRC =3D src1 */ diff --git a/target/sparc/cc_helper.c b/target/sparc/cc_helper.c index 5400dfec15..55bac722d2 100644 --- a/target/sparc/cc_helper.c +++ b/target/sparc/cc_helper.c @@ -57,28 +57,6 @@ static inline uint32_t get_C_add_icc(uint32_t dst, uint3= 2_t src1) return ret; } =20 -static inline uint32_t get_C_addx_icc(uint32_t dst, uint32_t src1, - uint32_t src2) -{ - uint32_t ret =3D 0; - - if (((src1 & src2) | (~dst & (src1 | src2))) & (1U << 31)) { - ret =3D PSR_CARRY; - } - return ret; -} - -static inline uint32_t get_V_add_icc(uint32_t dst, uint32_t src1, - uint32_t src2) -{ - uint32_t ret =3D 0; - - if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1U << 31)) { - ret =3D PSR_OVF; - } - return ret; -} - #ifdef TARGET_SPARC64 static inline uint32_t get_C_add_xcc(target_ulong dst, target_ulong src1) { @@ -90,17 +68,6 @@ static inline uint32_t get_C_add_xcc(target_ulong dst, t= arget_ulong src1) return ret; } =20 -static inline uint32_t get_C_addx_xcc(target_ulong dst, target_ulong src1, - target_ulong src2) -{ - uint32_t ret =3D 0; - - if (((src1 & src2) | (~dst & (src1 | src2))) & (1ULL << 63)) { - ret =3D PSR_CARRY; - } - return ret; -} - static inline uint32_t get_V_add_xcc(target_ulong dst, target_ulong src1, target_ulong src2) { @@ -128,53 +95,11 @@ static uint32_t compute_C_add_xcc(CPUSPARCState *env) } #endif =20 -static uint32_t compute_all_add(CPUSPARCState *env) -{ - uint32_t ret; - - ret =3D get_NZ_icc(CC_DST); - ret |=3D get_C_add_icc(CC_DST, CC_SRC); - ret |=3D get_V_add_icc(CC_DST, CC_SRC, CC_SRC2); - return ret; -} - static uint32_t compute_C_add(CPUSPARCState *env) { return get_C_add_icc(CC_DST, CC_SRC); } =20 -#ifdef TARGET_SPARC64 -static uint32_t compute_all_addx_xcc(CPUSPARCState *env) -{ - uint32_t ret; - - ret =3D get_NZ_xcc(CC_DST); - ret |=3D get_C_addx_xcc(CC_DST, CC_SRC, CC_SRC2); - ret |=3D get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2); - return ret; -} - -static uint32_t compute_C_addx_xcc(CPUSPARCState *env) -{ - return get_C_addx_xcc(CC_DST, CC_SRC, CC_SRC2); -} -#endif - -static uint32_t compute_all_addx(CPUSPARCState *env) -{ - uint32_t ret; - - ret =3D get_NZ_icc(CC_DST); - ret |=3D get_C_addx_icc(CC_DST, CC_SRC, CC_SRC2); - ret |=3D get_V_add_icc(CC_DST, CC_SRC, CC_SRC2); - return ret; -} - -static uint32_t compute_C_addx(CPUSPARCState *env) -{ - return get_C_addx_icc(CC_DST, CC_SRC, CC_SRC2); -} - static inline uint32_t get_V_tag_icc(target_ulong src1, target_ulong src2) { uint32_t ret =3D 0; @@ -185,17 +110,6 @@ static inline uint32_t get_V_tag_icc(target_ulong src1= , target_ulong src2) return ret; } =20 -static uint32_t compute_all_tadd(CPUSPARCState *env) -{ - uint32_t ret; - - ret =3D get_NZ_icc(CC_DST); - ret |=3D get_C_add_icc(CC_DST, CC_SRC); - ret |=3D get_V_add_icc(CC_DST, CC_SRC, CC_SRC2); - ret |=3D get_V_tag_icc(CC_SRC, CC_SRC2); - return ret; -} - static uint32_t compute_all_taddtv(CPUSPARCState *env) { uint32_t ret; @@ -361,9 +275,6 @@ typedef struct CCTable { =20 static const CCTable icc_table[CC_OP_NB] =3D { /* CC_OP_DYNAMIC should never happen */ - [CC_OP_ADD] =3D { compute_all_add, compute_C_add }, - [CC_OP_ADDX] =3D { compute_all_addx, compute_C_addx }, - [CC_OP_TADD] =3D { compute_all_tadd, compute_C_add }, [CC_OP_TADDTV] =3D { compute_all_taddtv, compute_C_add }, [CC_OP_SUB] =3D { compute_all_sub, compute_C_sub }, [CC_OP_SUBX] =3D { compute_all_subx, compute_C_subx }, @@ -374,9 +285,6 @@ static const CCTable icc_table[CC_OP_NB] =3D { #ifdef TARGET_SPARC64 static const CCTable xcc_table[CC_OP_NB] =3D { /* CC_OP_DYNAMIC should never happen */ - [CC_OP_ADD] =3D { compute_all_add_xcc, compute_C_add_xcc }, - [CC_OP_ADDX] =3D { compute_all_addx_xcc, compute_C_addx_xcc }, - [CC_OP_TADD] =3D { compute_all_add_xcc, compute_C_add_xcc }, [CC_OP_TADDTV] =3D { compute_all_add_xcc, compute_C_add_xcc }, [CC_OP_SUB] =3D { compute_all_sub_xcc, compute_C_sub_xcc }, [CC_OP_SUBX] =3D { compute_all_subx_xcc, compute_C_subx_xcc }, diff --git a/target/sparc/translate.c b/target/sparc/translate.c index fa4bad6d1f..cf121a237d 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -382,33 +382,71 @@ static void gen_goto_tb(DisasContext *s, int tb_num, } } =20 -static void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) +static TCGv gen_carry32(void) { - tcg_gen_mov_tl(cpu_cc_src, src1); - tcg_gen_mov_tl(cpu_cc_src2, src2); - tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); - tcg_gen_mov_tl(dst, cpu_cc_dst); + if (TARGET_LONG_BITS =3D=3D 64) { + TCGv t =3D tcg_temp_new(); + tcg_gen_extract_tl(t, cpu_icc_C, 32, 1); + return t; + } + return cpu_icc_C; } =20 -static TCGv_i32 gen_add32_carry32(void) +static void gen_op_addcc_int(TCGv dst, TCGv src1, TCGv src2, TCGv cin) { - TCGv_i32 carry_32, cc_src1_32, cc_src2_32; + TCGv z =3D tcg_constant_tl(0); =20 - /* Carry is computed from a previous add: (dst < src) */ -#if TARGET_LONG_BITS =3D=3D 64 - cc_src1_32 =3D tcg_temp_new_i32(); - cc_src2_32 =3D tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_dst); - tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src); -#else - cc_src1_32 =3D cpu_cc_dst; - cc_src2_32 =3D cpu_cc_src; -#endif + if (cin) { + tcg_gen_add2_tl(cpu_cc_N, cpu_cc_C, src1, z, cin, z); + tcg_gen_add2_tl(cpu_cc_N, cpu_cc_C, cpu_cc_N, cpu_cc_C, src2, z); + } else { + tcg_gen_add2_tl(cpu_cc_N, cpu_cc_C, src1, z, src2, z); + } + tcg_gen_xor_tl(cpu_cc_Z, src1, src2); + tcg_gen_xor_tl(cpu_cc_V, cpu_cc_N, src2); + tcg_gen_andc_tl(cpu_cc_V, cpu_cc_V, cpu_cc_Z); + if (TARGET_LONG_BITS =3D=3D 64) { + /* + * Carry-in to bit 32 is result ^ src1 ^ src2. + * We already have the src xor term in Z, from computation of V. + */ + tcg_gen_xor_tl(cpu_icc_C, cpu_cc_Z, cpu_cc_N); + tcg_gen_mov_tl(cpu_icc_Z, cpu_cc_N); + } + tcg_gen_mov_tl(cpu_cc_Z, cpu_cc_N); + tcg_gen_mov_tl(dst, cpu_cc_N); +} =20 - carry_32 =3D tcg_temp_new_i32(); - tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32); +static void gen_op_addcc(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_addcc_int(dst, src1, src2, NULL); +} =20 - return carry_32; +static void gen_op_taddcc(TCGv dst, TCGv src1, TCGv src2) +{ + TCGv t =3D tcg_temp_new(); + + /* Save the tag bits around modification of dst. */ + tcg_gen_or_tl(t, src1, src2); + + gen_op_addcc(dst, src1, src2); + + /* Incorprate tag bits into icc.V */ + tcg_gen_andi_tl(t, t, 3); + tcg_gen_neg_tl(t, t); + tcg_gen_ext32u_tl(t, t); + tcg_gen_or_tl(cpu_cc_V, cpu_cc_V, t); +} + +static void gen_op_addc(TCGv dst, TCGv src1, TCGv src2) +{ + tcg_gen_add_tl(dst, src1, src2); + tcg_gen_add_tl(dst, dst, gen_carry32()); +} + +static void gen_op_addccc(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_addcc_int(dst, src1, src2, gen_carry32()); } =20 static TCGv_i32 gen_sub32_carry32(void) @@ -432,89 +470,6 @@ static TCGv_i32 gen_sub32_carry32(void) return carry_32; } =20 -static void gen_op_addc_int(TCGv dst, TCGv src1, TCGv src2, - TCGv_i32 carry_32, bool update_cc) -{ - tcg_gen_add_tl(dst, src1, src2); - -#ifdef TARGET_SPARC64 - TCGv carry =3D tcg_temp_new(); - tcg_gen_extu_i32_tl(carry, carry_32); - tcg_gen_add_tl(dst, dst, carry); -#else - tcg_gen_add_i32(dst, dst, carry_32); -#endif - - if (update_cc) { - tcg_debug_assert(dst =3D=3D cpu_cc_dst); - tcg_gen_mov_tl(cpu_cc_src, src1); - tcg_gen_mov_tl(cpu_cc_src2, src2); - } -} - -static void gen_op_addc_int_add(TCGv dst, TCGv src1, TCGv src2, bool updat= e_cc) -{ - TCGv discard; - - if (TARGET_LONG_BITS =3D=3D 64) { - gen_op_addc_int(dst, src1, src2, gen_add32_carry32(), update_cc); - return; - } - - /* - * We can re-use the host's hardware carry generation by using - * an ADD2 opcode. We discard the low part of the output. - * Ideally we'd combine this operation with the add that - * generated the carry in the first place. - */ - discard =3D tcg_temp_new(); - tcg_gen_add2_tl(discard, dst, cpu_cc_src, src1, cpu_cc_src2, src2); - - if (update_cc) { - tcg_debug_assert(dst =3D=3D cpu_cc_dst); - tcg_gen_mov_tl(cpu_cc_src, src1); - tcg_gen_mov_tl(cpu_cc_src2, src2); - } -} - -static void gen_op_addc_add(TCGv dst, TCGv src1, TCGv src2) -{ - gen_op_addc_int_add(dst, src1, src2, false); -} - -static void gen_op_addccc_add(TCGv dst, TCGv src1, TCGv src2) -{ - gen_op_addc_int_add(dst, src1, src2, true); -} - -static void gen_op_addc_sub(TCGv dst, TCGv src1, TCGv src2) -{ - gen_op_addc_int(dst, src1, src2, gen_sub32_carry32(), false); -} - -static void gen_op_addccc_sub(TCGv dst, TCGv src1, TCGv src2) -{ - gen_op_addc_int(dst, src1, src2, gen_sub32_carry32(), true); -} - -static void gen_op_addc_int_generic(TCGv dst, TCGv src1, TCGv src2, - bool update_cc) -{ - TCGv_i32 carry_32 =3D tcg_temp_new_i32(); - gen_helper_compute_C_icc(carry_32, tcg_env); - gen_op_addc_int(dst, src1, src2, carry_32, update_cc); -} - -static void gen_op_addc_generic(TCGv dst, TCGv src1, TCGv src2) -{ - gen_op_addc_int_generic(dst, src1, src2, false); -} - -static void gen_op_addccc_generic(TCGv dst, TCGv src1, TCGv src2) -{ - gen_op_addc_int_generic(dst, src1, src2, true); -} - static void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) { tcg_gen_mov_tl(cpu_cc_src, src1); @@ -545,16 +500,6 @@ static void gen_op_subc_int(TCGv dst, TCGv src1, TCGv = src2, } } =20 -static void gen_op_subc_add(TCGv dst, TCGv src1, TCGv src2) -{ - gen_op_subc_int(dst, src1, src2, gen_add32_carry32(), false); -} - -static void gen_op_subccc_add(TCGv dst, TCGv src1, TCGv src2) -{ - gen_op_subc_int(dst, src1, src2, gen_add32_carry32(), true); -} - static void gen_op_subc_int_sub(TCGv dst, TCGv src1, TCGv src2, bool updat= e_cc) { TCGv discard; @@ -609,39 +554,39 @@ static void gen_op_subccc_generic(TCGv dst, TCGv src1= , TCGv src2) =20 static void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) { - TCGv r_temp, zero, t0; + TCGv zero =3D tcg_constant_tl(0); + TCGv t_src1 =3D tcg_temp_new(); + TCGv t_src2 =3D tcg_temp_new(); + TCGv t0 =3D tcg_temp_new(); =20 - r_temp =3D tcg_temp_new(); - t0 =3D tcg_temp_new(); + tcg_gen_ext32u_tl(t_src1, src1); + tcg_gen_ext32u_tl(t_src2, src2); =20 - /* old op: - if (!(env->y & 1)) - T1 =3D 0; - */ - zero =3D tcg_constant_tl(0); - tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff); - tcg_gen_andi_tl(r_temp, cpu_y, 0x1); - tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff); - tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero, - zero, cpu_cc_src2); + /* + * if (!(env->y & 1)) + * src2 =3D 0; + */ + tcg_gen_andi_tl(t0, cpu_y, 0x1); + tcg_gen_movcond_tl(TCG_COND_EQ, t_src2, t0, zero, zero, t_src2); =20 - // b2 =3D T0 & 1; - // env->y =3D (b2 << 31) | (env->y >> 1); + /* + * b2 =3D src1 & 1; + * y =3D (b2 << 31) | (y >> 1); + */ tcg_gen_extract_tl(t0, cpu_y, 1, 31); - tcg_gen_deposit_tl(cpu_y, t0, cpu_cc_src, 31, 1); + tcg_gen_deposit_tl(cpu_y, t0, src1, 31, 1); =20 // b1 =3D N ^ V; tcg_gen_xor_tl(t0, cpu_cc_N, cpu_cc_V); =20 - // T0 =3D (b1 << 31) | (T0 >> 1); - // src1 =3D T0; + /* + * src1 =3D (b1 << 31) | (src1 >> 1) + */ tcg_gen_andi_tl(t0, t0, 1u << 31); - tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1); - tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); + tcg_gen_shri_tl(t_src1, t_src1, 1); + tcg_gen_or_tl(t_src1, t_src1, t0); =20 - tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); - - tcg_gen_mov_tl(dst, cpu_cc_dst); + gen_op_addcc(dst, t_src1, t_src2); } =20 static void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext) @@ -3749,12 +3694,12 @@ static bool do_logic(DisasContext *dc, arg_r_r_ri_c= c *a, return do_arith_int(dc, a, CC_OP_FLAGS, func, funci, a->cc); } =20 -TRANS(ADD, ALL, do_arith, a, CC_OP_ADD, - tcg_gen_add_tl, tcg_gen_addi_tl, gen_op_add_cc) +TRANS(ADD, ALL, do_arith, a, CC_OP_FLAGS, + tcg_gen_add_tl, tcg_gen_addi_tl, gen_op_addcc) TRANS(SUB, ALL, do_arith, a, CC_OP_SUB, tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_sub_cc) =20 -TRANS(TADDcc, ALL, do_arith, a, CC_OP_TADD, NULL, NULL, gen_op_add_cc) +TRANS(TADDcc, ALL, do_arith, a, CC_OP_FLAGS, NULL, NULL, gen_op_taddcc) TRANS(TSUBcc, ALL, do_arith, a, CC_OP_TSUB, NULL, NULL, gen_op_sub_cc) TRANS(TADDccTV, ALL, do_arith, a, CC_OP_TADDTV, NULL, NULL, gen_op_taddcct= v) TRANS(TSUBccTV, ALL, do_arith, a, CC_OP_TSUBTV, NULL, NULL, gen_op_tsubcct= v) @@ -3796,31 +3741,13 @@ static bool trans_OR(DisasContext *dc, arg_r_r_ri_c= c *a) =20 static bool trans_ADDC(DisasContext *dc, arg_r_r_ri_cc *a) { - switch (dc->cc_op) { - case CC_OP_ADD: - case CC_OP_TADD: - case CC_OP_TADDTV: - return do_arith(dc, a, CC_OP_ADDX, - gen_op_addc_add, NULL, gen_op_addccc_add); - case CC_OP_SUB: - case CC_OP_TSUB: - case CC_OP_TSUBTV: - return do_arith(dc, a, CC_OP_ADDX, - gen_op_addc_sub, NULL, gen_op_addccc_sub); - default: - return do_arith(dc, a, CC_OP_ADDX, - gen_op_addc_generic, NULL, gen_op_addccc_generic); - } + update_psr(dc); + return do_arith(dc, a, CC_OP_FLAGS, gen_op_addc, NULL, gen_op_addccc); } =20 static bool trans_SUBC(DisasContext *dc, arg_r_r_ri_cc *a) { switch (dc->cc_op) { - case CC_OP_ADD: - case CC_OP_TADD: - case CC_OP_TADDTV: - return do_arith(dc, a, CC_OP_SUBX, - gen_op_subc_add, NULL, gen_op_subccc_add); case CC_OP_SUB: case CC_OP_TSUB: case CC_OP_TSUBTV: @@ -3835,7 +3762,7 @@ static bool trans_SUBC(DisasContext *dc, arg_r_r_ri_c= c *a) static bool trans_MULScc(DisasContext *dc, arg_r_r_ri_cc *a) { update_psr(dc); - return do_arith(dc, a, CC_OP_ADD, NULL, NULL, gen_op_mulscc); + return do_arith(dc, a, CC_OP_FLAGS, NULL, NULL, gen_op_mulscc); } =20 static bool gen_edge(DisasContext *dc, arg_r_r_r *a, --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u23-20020a056a00099700b006884549adc8sm4359777pfg.29.2023.11.05.12.12.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Nov 2023 12:12:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699215149; x=1699819949; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=stMYGoZRgleysnGySsVwfhS7UeFFRKuKyGfp9j97in4=; b=tsPxpLQictrvEZHwV/OMGMEvhXH+YZAryGFaOBQiibq4ZTs+GlsyHO+L/8dsUZP2pP 60sWR+Wt+QMlQ/Ey747sNVmxVhYofdLB7tmWrCfrXfCCchf5uvhqrjDtea4U/Df4CS/y wY2DSbpunlkL3NGLD2NucV6sC/j5zGD+8EZZkX1vaedWkknkJ1qqwFGDvKQLzaqgRPxX W9lZ3rcog3ZmTn2sM9i57jhNDWgKBm8cGhzIx5f714+bO0RQ3Wmi66kl3EO4M1Gjoqm6 AJJ+GjpV2wJghBwXgajE0AsmsUh6bLaCxi8hW4fABFIlP4ac7QwMd5UcoS0r0G9/6X0s FKbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699215149; x=1699819949; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=stMYGoZRgleysnGySsVwfhS7UeFFRKuKyGfp9j97in4=; b=qKjVzb3pX0Oh21G8MAFKtACku+KUWrA87yBUvj+xH5jyn/1yeH205gglGLZa8q8BgO J3c0bDCgo77B+5k/33vICdDzTAx5NEW+Y6TkwiYWAFA2V137TLuOAeEeP/T3cPiA1sUH 96Lk3qF2CSOECA3bBZTqxJqPYVmJdSS2zFEYJKmbB4WdJF4ZSFZOOlDppB0QPTojwz4Y O9UurlbGJ/sde3rmpJdNmfjfw4qsRzvDLTS+gWD3mGli9VOneC/uz3U+4STc/a/xhj+z e/k1MNuObbKk1TWdZe+4Xzseq5Y4kZ8glnNW1/m929WzZmmXHXNleaUT3UbfGExSz9hU TvtQ== X-Gm-Message-State: AOJu0Yy3FbLGcGwuAOAC1F/Sx4et3ShEF7nP9E7NN1MiCXf192EY2s5a PZqpRe6D2ngGd15iBC+4zVqbngGDPGm0bAM2YuM= X-Google-Smtp-Source: AGHT+IFbO75Gzl4GHwne12FNniijtGApAyq0tb5n2F2hCuJoz63mayIQcdk4N0vzPC3kmIj+DAsCdQ== X-Received: by 2002:a05:6a00:134b:b0:6be:1f19:e604 with SMTP id k11-20020a056a00134b00b006be1f19e604mr34549028pfu.21.1699215149262; Sun, 05 Nov 2023 12:12:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 06/21] target/sparc: Remove CC_OP_SUB, CC_OP_SUBX, CC_OP_TSUB Date: Sun, 5 Nov 2023 12:12:07 -0800 Message-Id: <20231105201222.202395-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231105201222.202395-1-richard.henderson@linaro.org> References: <20231105201222.202395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215280860100003 Content-Type: text/plain; charset="utf-8" These are all related and implementable with common code. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 3 - target/sparc/cc_helper.c | 103 -------------------- target/sparc/translate.c | 203 +++++++++------------------------------ 3 files changed, 45 insertions(+), 264 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 4ee8e2dc92..9884bd416a 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -151,9 +151,6 @@ enum { CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ CC_OP_FLAGS, /* all cc are back in cc_*_[NZCV] registers */ CC_OP_TADDTV, /* modify all flags except V, CC_DST =3D res, CC_SRC = =3D src1 */ - CC_OP_SUB, /* modify all flags, CC_DST =3D res, CC_SRC =3D src1 */ - CC_OP_SUBX, /* modify all flags, CC_DST =3D res, CC_SRC =3D src1 */ - CC_OP_TSUB, /* modify all flags, CC_DST =3D res, CC_SRC =3D src1 */ CC_OP_TSUBTV, /* modify all flags except V, CC_DST =3D res, CC_SRC = =3D src1 */ CC_OP_NB, }; diff --git a/target/sparc/cc_helper.c b/target/sparc/cc_helper.c index 55bac722d2..20d451aa65 100644 --- a/target/sparc/cc_helper.c +++ b/target/sparc/cc_helper.c @@ -100,16 +100,6 @@ static uint32_t compute_C_add(CPUSPARCState *env) return get_C_add_icc(CC_DST, CC_SRC); } =20 -static inline uint32_t get_V_tag_icc(target_ulong src1, target_ulong src2) -{ - uint32_t ret =3D 0; - - if ((src1 | src2) & 0x3) { - ret =3D PSR_OVF; - } - return ret; -} - static uint32_t compute_all_taddtv(CPUSPARCState *env) { uint32_t ret; @@ -129,29 +119,6 @@ static inline uint32_t get_C_sub_icc(uint32_t src1, ui= nt32_t src2) return ret; } =20 -static inline uint32_t get_C_subx_icc(uint32_t dst, uint32_t src1, - uint32_t src2) -{ - uint32_t ret =3D 0; - - if (((~src1 & src2) | (dst & (~src1 | src2))) & (1U << 31)) { - ret =3D PSR_CARRY; - } - return ret; -} - -static inline uint32_t get_V_sub_icc(uint32_t dst, uint32_t src1, - uint32_t src2) -{ - uint32_t ret =3D 0; - - if (((src1 ^ src2) & (src1 ^ dst)) & (1U << 31)) { - ret =3D PSR_OVF; - } - return ret; -} - - #ifdef TARGET_SPARC64 static inline uint32_t get_C_sub_xcc(target_ulong src1, target_ulong src2) { @@ -163,17 +130,6 @@ static inline uint32_t get_C_sub_xcc(target_ulong src1= , target_ulong src2) return ret; } =20 -static inline uint32_t get_C_subx_xcc(target_ulong dst, target_ulong src1, - target_ulong src2) -{ - uint32_t ret =3D 0; - - if (((~src1 & src2) | (dst & (~src1 | src2))) & (1ULL << 63)) { - ret =3D PSR_CARRY; - } - return ret; -} - static inline uint32_t get_V_sub_xcc(target_ulong dst, target_ulong src1, target_ulong src2) { @@ -201,64 +157,11 @@ static uint32_t compute_C_sub_xcc(CPUSPARCState *env) } #endif =20 -static uint32_t compute_all_sub(CPUSPARCState *env) -{ - uint32_t ret; - - ret =3D get_NZ_icc(CC_DST); - ret |=3D get_C_sub_icc(CC_SRC, CC_SRC2); - ret |=3D get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2); - return ret; -} - static uint32_t compute_C_sub(CPUSPARCState *env) { return get_C_sub_icc(CC_SRC, CC_SRC2); } =20 -#ifdef TARGET_SPARC64 -static uint32_t compute_all_subx_xcc(CPUSPARCState *env) -{ - uint32_t ret; - - ret =3D get_NZ_xcc(CC_DST); - ret |=3D get_C_subx_xcc(CC_DST, CC_SRC, CC_SRC2); - ret |=3D get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2); - return ret; -} - -static uint32_t compute_C_subx_xcc(CPUSPARCState *env) -{ - return get_C_subx_xcc(CC_DST, CC_SRC, CC_SRC2); -} -#endif - -static uint32_t compute_all_subx(CPUSPARCState *env) -{ - uint32_t ret; - - ret =3D get_NZ_icc(CC_DST); - ret |=3D get_C_subx_icc(CC_DST, CC_SRC, CC_SRC2); - ret |=3D get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2); - return ret; -} - -static uint32_t compute_C_subx(CPUSPARCState *env) -{ - return get_C_subx_icc(CC_DST, CC_SRC, CC_SRC2); -} - -static uint32_t compute_all_tsub(CPUSPARCState *env) -{ - uint32_t ret; - - ret =3D get_NZ_icc(CC_DST); - ret |=3D get_C_sub_icc(CC_SRC, CC_SRC2); - ret |=3D get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2); - ret |=3D get_V_tag_icc(CC_SRC, CC_SRC2); - return ret; -} - static uint32_t compute_all_tsubtv(CPUSPARCState *env) { uint32_t ret; @@ -276,9 +179,6 @@ typedef struct CCTable { static const CCTable icc_table[CC_OP_NB] =3D { /* CC_OP_DYNAMIC should never happen */ [CC_OP_TADDTV] =3D { compute_all_taddtv, compute_C_add }, - [CC_OP_SUB] =3D { compute_all_sub, compute_C_sub }, - [CC_OP_SUBX] =3D { compute_all_subx, compute_C_subx }, - [CC_OP_TSUB] =3D { compute_all_tsub, compute_C_sub }, [CC_OP_TSUBTV] =3D { compute_all_tsubtv, compute_C_sub }, }; =20 @@ -286,9 +186,6 @@ static const CCTable icc_table[CC_OP_NB] =3D { static const CCTable xcc_table[CC_OP_NB] =3D { /* CC_OP_DYNAMIC should never happen */ [CC_OP_TADDTV] =3D { compute_all_add_xcc, compute_C_add_xcc }, - [CC_OP_SUB] =3D { compute_all_sub_xcc, compute_C_sub_xcc }, - [CC_OP_SUBX] =3D { compute_all_subx_xcc, compute_C_subx_xcc }, - [CC_OP_TSUB] =3D { compute_all_sub_xcc, compute_C_sub_xcc }, [CC_OP_TSUBTV] =3D { compute_all_sub_xcc, compute_C_sub_xcc }, }; #endif diff --git a/target/sparc/translate.c b/target/sparc/translate.c index cf121a237d..d119ce4c94 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -449,107 +449,58 @@ static void gen_op_addccc(TCGv dst, TCGv src1, TCGv = src2) gen_op_addcc_int(dst, src1, src2, gen_carry32()); } =20 -static TCGv_i32 gen_sub32_carry32(void) +static void gen_op_subcc_int(TCGv dst, TCGv src1, TCGv src2, TCGv cin) { - TCGv_i32 carry_32, cc_src1_32, cc_src2_32; + TCGv z =3D tcg_constant_tl(0); =20 - /* Carry is computed from a previous borrow: (src1 < src2) */ -#if TARGET_LONG_BITS =3D=3D 64 - cc_src1_32 =3D tcg_temp_new_i32(); - cc_src2_32 =3D tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_src); - tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src2); -#else - cc_src1_32 =3D cpu_cc_src; - cc_src2_32 =3D cpu_cc_src2; + if (cin) { + tcg_gen_sub2_tl(cpu_cc_N, cpu_cc_C, src1, z, cin, z); + tcg_gen_sub2_tl(cpu_cc_N, cpu_cc_C, cpu_cc_N, cpu_cc_C, src2, z); + } else { + tcg_gen_sub2_tl(cpu_cc_N, cpu_cc_C, src1, z, src2, z); + } + tcg_gen_neg_tl(cpu_cc_C, cpu_cc_C); + tcg_gen_xor_tl(cpu_cc_Z, src1, src2); + tcg_gen_xor_tl(cpu_cc_V, cpu_cc_N, src1); + tcg_gen_and_tl(cpu_cc_V, cpu_cc_V, cpu_cc_Z); +#ifdef TARGET_SPARC64 + tcg_gen_xor_tl(cpu_icc_C, cpu_cc_Z, cpu_cc_N); + tcg_gen_mov_tl(cpu_icc_Z, cpu_cc_N); #endif - - carry_32 =3D tcg_temp_new_i32(); - tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32); - - return carry_32; + tcg_gen_mov_tl(cpu_cc_Z, cpu_cc_N); + tcg_gen_mov_tl(dst, cpu_cc_N); } =20 -static void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) +static void gen_op_subcc(TCGv dst, TCGv src1, TCGv src2) { - tcg_gen_mov_tl(cpu_cc_src, src1); - tcg_gen_mov_tl(cpu_cc_src2, src2); - tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); - tcg_gen_mov_tl(dst, cpu_cc_dst); + gen_op_subcc_int(dst, src1, src2, NULL); } =20 -static void gen_op_subc_int(TCGv dst, TCGv src1, TCGv src2, - TCGv_i32 carry_32, bool update_cc) +static void gen_op_tsubcc(TCGv dst, TCGv src1, TCGv src2) { - TCGv carry; + TCGv t =3D tcg_temp_new(); =20 -#if TARGET_LONG_BITS =3D=3D 64 - carry =3D tcg_temp_new(); - tcg_gen_extu_i32_i64(carry, carry_32); -#else - carry =3D carry_32; -#endif + /* Save the tag bits around modification of dst. */ + tcg_gen_or_tl(t, src1, src2); =20 + gen_op_subcc(dst, src1, src2); + + /* Incorprate tag bits into icc.V */ + tcg_gen_andi_tl(t, t, 3); + tcg_gen_neg_tl(t, t); + tcg_gen_ext32u_tl(t, t); + tcg_gen_or_tl(cpu_cc_V, cpu_cc_V, t); +} + +static void gen_op_subc(TCGv dst, TCGv src1, TCGv src2) +{ tcg_gen_sub_tl(dst, src1, src2); - tcg_gen_sub_tl(dst, dst, carry); - - if (update_cc) { - tcg_debug_assert(dst =3D=3D cpu_cc_dst); - tcg_gen_mov_tl(cpu_cc_src, src1); - tcg_gen_mov_tl(cpu_cc_src2, src2); - } + tcg_gen_sub_tl(dst, dst, gen_carry32()); } =20 -static void gen_op_subc_int_sub(TCGv dst, TCGv src1, TCGv src2, bool updat= e_cc) +static void gen_op_subccc(TCGv dst, TCGv src1, TCGv src2) { - TCGv discard; - - if (TARGET_LONG_BITS =3D=3D 64) { - gen_op_subc_int(dst, src1, src2, gen_sub32_carry32(), update_cc); - return; - } - - /* - * We can re-use the host's hardware carry generation by using - * a SUB2 opcode. We discard the low part of the output. - */ - discard =3D tcg_temp_new(); - tcg_gen_sub2_tl(discard, dst, cpu_cc_src, src1, cpu_cc_src2, src2); - - if (update_cc) { - tcg_debug_assert(dst =3D=3D cpu_cc_dst); - tcg_gen_mov_tl(cpu_cc_src, src1); - tcg_gen_mov_tl(cpu_cc_src2, src2); - } -} - -static void gen_op_subc_sub(TCGv dst, TCGv src1, TCGv src2) -{ - gen_op_subc_int_sub(dst, src1, src2, false); -} - -static void gen_op_subccc_sub(TCGv dst, TCGv src1, TCGv src2) -{ - gen_op_subc_int_sub(dst, src1, src2, true); -} - -static void gen_op_subc_int_generic(TCGv dst, TCGv src1, TCGv src2, - bool update_cc) -{ - TCGv_i32 carry_32 =3D tcg_temp_new_i32(); - - gen_helper_compute_C_icc(carry_32, tcg_env); - gen_op_subc_int(dst, src1, src2, carry_32, update_cc); -} - -static void gen_op_subc_generic(TCGv dst, TCGv src1, TCGv src2) -{ - gen_op_subc_int_generic(dst, src1, src2, false); -} - -static void gen_op_subccc_generic(TCGv dst, TCGv src1, TCGv src2) -{ - gen_op_subc_int_generic(dst, src1, src2, true); + gen_op_subcc_int(dst, src1, src2, gen_carry32()); } =20 static void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) @@ -1097,65 +1048,11 @@ static void gen_op_next_insn(void) static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond, DisasContext *dc) { - static int subcc_cond[16] =3D { - TCG_COND_NEVER, - TCG_COND_EQ, - TCG_COND_LE, - TCG_COND_LT, - TCG_COND_LEU, - TCG_COND_LTU, - -1, /* neg */ - -1, /* overflow */ - TCG_COND_ALWAYS, - TCG_COND_NE, - TCG_COND_GT, - TCG_COND_GE, - TCG_COND_GTU, - TCG_COND_GEU, - -1, /* pos */ - -1, /* no overflow */ - }; - TCGv t1, t2; =20 cmp->is_bool =3D false; =20 switch (dc->cc_op) { - case CC_OP_SUB: - switch (cond) { - case 6: /* neg */ - case 14: /* pos */ - cmp->cond =3D (cond =3D=3D 6 ? TCG_COND_LT : TCG_COND_GE); - cmp->c2 =3D tcg_constant_tl(0); - if (TARGET_LONG_BITS =3D=3D 32 || xcc) { - cmp->c1 =3D cpu_cc_dst; - } else { - cmp->c1 =3D t1 =3D tcg_temp_new(); - tcg_gen_ext32s_tl(t1, cpu_cc_dst); - } - return; - - case 7: /* overflow */ - case 15: /* !overflow */ - break; - - default: - cmp->cond =3D subcc_cond[cond]; - if (TARGET_LONG_BITS =3D=3D 32 || xcc) { - cmp->c1 =3D cpu_cc_src; - cmp->c2 =3D cpu_cc_src2; - } else { - /* Note that sign-extension works for unsigned compares as - long as both operands are sign-extended. */ - cmp->c1 =3D t1 =3D tcg_temp_new(); - tcg_gen_ext32s_tl(t1, cpu_cc_src); - cmp->c2 =3D t2 =3D tcg_temp_new(); - tcg_gen_ext32s_tl(t2, cpu_cc_src2); - } - return; - } - break; - default: gen_helper_compute_psr(tcg_env); dc->cc_op =3D CC_OP_FLAGS; @@ -3696,11 +3593,11 @@ static bool do_logic(DisasContext *dc, arg_r_r_ri_c= c *a, =20 TRANS(ADD, ALL, do_arith, a, CC_OP_FLAGS, tcg_gen_add_tl, tcg_gen_addi_tl, gen_op_addcc) -TRANS(SUB, ALL, do_arith, a, CC_OP_SUB, - tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_sub_cc) +TRANS(SUB, ALL, do_arith, a, CC_OP_FLAGS, + tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_subcc) =20 TRANS(TADDcc, ALL, do_arith, a, CC_OP_FLAGS, NULL, NULL, gen_op_taddcc) -TRANS(TSUBcc, ALL, do_arith, a, CC_OP_TSUB, NULL, NULL, gen_op_sub_cc) +TRANS(TSUBcc, ALL, do_arith, a, CC_OP_FLAGS, NULL, NULL, gen_op_tsubcc) TRANS(TADDccTV, ALL, do_arith, a, CC_OP_TADDTV, NULL, NULL, gen_op_taddcct= v) TRANS(TSUBccTV, ALL, do_arith, a, CC_OP_TSUBTV, NULL, NULL, gen_op_tsubcct= v) =20 @@ -3747,16 +3644,8 @@ static bool trans_ADDC(DisasContext *dc, arg_r_r_ri_= cc *a) =20 static bool trans_SUBC(DisasContext *dc, arg_r_r_ri_cc *a) { - switch (dc->cc_op) { - case CC_OP_SUB: - case CC_OP_TSUB: - case CC_OP_TSUBTV: - return do_arith(dc, a, CC_OP_SUBX, - gen_op_subc_sub, NULL, gen_op_subccc_sub); - default: - return do_arith(dc, a, CC_OP_SUBX, - gen_op_subc_generic, NULL, gen_op_subccc_generic); - } + update_psr(dc); + return do_arith(dc, a, CC_OP_FLAGS, gen_op_subc, NULL, gen_op_subccc); } =20 static bool trans_MULScc(DisasContext *dc, arg_r_r_ri_cc *a) @@ -3777,11 +3666,9 @@ static bool gen_edge(DisasContext *dc, arg_r_r_r *a, s2 =3D gen_load_gpr(dc, a->rs2); =20 if (cc) { - tcg_gen_mov_tl(cpu_cc_src, s1); - tcg_gen_mov_tl(cpu_cc_src2, s2); - tcg_gen_sub_tl(cpu_cc_dst, s1, s2); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); - dc->cc_op =3D CC_OP_SUB; + gen_op_subcc(cpu_cc_N, s1, s2); + tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); + dc->cc_op =3D CC_OP_FLAGS; } =20 /* --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699215245; cv=none; d=zohomail.com; s=zohoarc; b=aLkZCUoYcWP404DyjRi6giVttcTvDfYEwPvnSYQnnRK1vQ/mjtbKV0NP8rScseuopXOISJjYczTp9jEdO1AS11sRJVgDi1KvwCxhPnmxfGIQ3XyhcYzJChuj8ttKGwBcQPBC71kUqXQBIpgYzYERb0SKITak7k0E+uUQRkYWHgE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699215245; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=g+litbE/JVF7sKFOm6jcQPKszjKzSd1Rnr6YSqXhSKw=; b=MNn9hKSk68/WZQKjK4WrUkpf5xlp4wYZ0+iCC/juD2wuRGEOxIGMJN+WlphksINYwl3dl70PF5cEK2NutDJuHNL5ug625vk3/rafuTHPAOxKrX3iZymzwzjPbSWKF73kYZM9HOYyyfaFqlr5RhcxOpzQCbnaqrYvg7U7mPszSvQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169921524566246.316563315349526; Sun, 5 Nov 2023 12:14:05 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qzjU2-0003DI-Ju; Sun, 05 Nov 2023 15:12:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qzjU1-0003CC-CA for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:33 -0500 Received: from mail-il1-x134.google.com ([2607:f8b0:4864:20::134]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qzjTz-00028U-AD for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:33 -0500 Received: by mail-il1-x134.google.com with SMTP id e9e14a558f8ab-357ccaf982eso15550175ab.0 for ; Sun, 05 Nov 2023 12:12:30 -0800 (PST) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::134; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215246780100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 2 - target/sparc/cc_helper.c | 190 +-------------------------------------- target/sparc/helper.c | 36 ++++++-- target/sparc/translate.c | 4 +- 4 files changed, 32 insertions(+), 200 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 9884bd416a..a7999eaab5 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -150,8 +150,6 @@ enum { enum { CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ CC_OP_FLAGS, /* all cc are back in cc_*_[NZCV] registers */ - CC_OP_TADDTV, /* modify all flags except V, CC_DST =3D res, CC_SRC = =3D src1 */ - CC_OP_TSUBTV, /* modify all flags except V, CC_DST =3D res, CC_SRC = =3D src1 */ CC_OP_NB, }; =20 diff --git a/target/sparc/cc_helper.c b/target/sparc/cc_helper.c index 20d451aa65..05f1479aea 100644 --- a/target/sparc/cc_helper.c +++ b/target/sparc/cc_helper.c @@ -21,198 +21,12 @@ #include "cpu.h" #include "exec/helper-proto.h" =20 -static inline uint32_t get_NZ_icc(int32_t dst) -{ - uint32_t ret =3D 0; - - if (dst =3D=3D 0) { - ret =3D PSR_ZERO; - } else if (dst < 0) { - ret =3D PSR_NEG; - } - return ret; -} - -#ifdef TARGET_SPARC64 -static inline uint32_t get_NZ_xcc(target_long dst) -{ - uint32_t ret =3D 0; - - if (!dst) { - ret =3D PSR_ZERO; - } else if (dst < 0) { - ret =3D PSR_NEG; - } - return ret; -} -#endif - -static inline uint32_t get_C_add_icc(uint32_t dst, uint32_t src1) -{ - uint32_t ret =3D 0; - - if (dst < src1) { - ret =3D PSR_CARRY; - } - return ret; -} - -#ifdef TARGET_SPARC64 -static inline uint32_t get_C_add_xcc(target_ulong dst, target_ulong src1) -{ - uint32_t ret =3D 0; - - if (dst < src1) { - ret =3D PSR_CARRY; - } - return ret; -} - -static inline uint32_t get_V_add_xcc(target_ulong dst, target_ulong src1, - target_ulong src2) -{ - uint32_t ret =3D 0; - - if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1ULL << 63)) { - ret =3D PSR_OVF; - } - return ret; -} - -static uint32_t compute_all_add_xcc(CPUSPARCState *env) -{ - uint32_t ret; - - ret =3D get_NZ_xcc(CC_DST); - ret |=3D get_C_add_xcc(CC_DST, CC_SRC); - ret |=3D get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2); - return ret; -} - -static uint32_t compute_C_add_xcc(CPUSPARCState *env) -{ - return get_C_add_xcc(CC_DST, CC_SRC); -} -#endif - -static uint32_t compute_C_add(CPUSPARCState *env) -{ - return get_C_add_icc(CC_DST, CC_SRC); -} - -static uint32_t compute_all_taddtv(CPUSPARCState *env) -{ - uint32_t ret; - - ret =3D get_NZ_icc(CC_DST); - ret |=3D get_C_add_icc(CC_DST, CC_SRC); - return ret; -} - -static inline uint32_t get_C_sub_icc(uint32_t src1, uint32_t src2) -{ - uint32_t ret =3D 0; - - if (src1 < src2) { - ret =3D PSR_CARRY; - } - return ret; -} - -#ifdef TARGET_SPARC64 -static inline uint32_t get_C_sub_xcc(target_ulong src1, target_ulong src2) -{ - uint32_t ret =3D 0; - - if (src1 < src2) { - ret =3D PSR_CARRY; - } - return ret; -} - -static inline uint32_t get_V_sub_xcc(target_ulong dst, target_ulong src1, - target_ulong src2) -{ - uint32_t ret =3D 0; - - if (((src1 ^ src2) & (src1 ^ dst)) & (1ULL << 63)) { - ret =3D PSR_OVF; - } - return ret; -} - -static uint32_t compute_all_sub_xcc(CPUSPARCState *env) -{ - uint32_t ret; - - ret =3D get_NZ_xcc(CC_DST); - ret |=3D get_C_sub_xcc(CC_SRC, CC_SRC2); - ret |=3D get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2); - return ret; -} - -static uint32_t compute_C_sub_xcc(CPUSPARCState *env) -{ - return get_C_sub_xcc(CC_SRC, CC_SRC2); -} -#endif - -static uint32_t compute_C_sub(CPUSPARCState *env) -{ - return get_C_sub_icc(CC_SRC, CC_SRC2); -} - -static uint32_t compute_all_tsubtv(CPUSPARCState *env) -{ - uint32_t ret; - - ret =3D get_NZ_icc(CC_DST); - ret |=3D get_C_sub_icc(CC_SRC, CC_SRC2); - return ret; -} - -typedef struct CCTable { - uint32_t (*compute_all)(CPUSPARCState *env); /* return all the flags */ - uint32_t (*compute_c)(CPUSPARCState *env); /* return the C flag */ -} CCTable; - -static const CCTable icc_table[CC_OP_NB] =3D { - /* CC_OP_DYNAMIC should never happen */ - [CC_OP_TADDTV] =3D { compute_all_taddtv, compute_C_add }, - [CC_OP_TSUBTV] =3D { compute_all_tsubtv, compute_C_sub }, -}; - -#ifdef TARGET_SPARC64 -static const CCTable xcc_table[CC_OP_NB] =3D { - /* CC_OP_DYNAMIC should never happen */ - [CC_OP_TADDTV] =3D { compute_all_add_xcc, compute_C_add_xcc }, - [CC_OP_TSUBTV] =3D { compute_all_sub_xcc, compute_C_sub_xcc }, -}; -#endif - void helper_compute_psr(CPUSPARCState *env) { if (CC_OP =3D=3D CC_OP_FLAGS) { return; } - - uint32_t icc =3D icc_table[CC_OP].compute_all(env); -#ifdef TARGET_SPARC64 - uint32_t xcc =3D xcc_table[CC_OP].compute_all(env); - - env->cc_N =3D deposit64(-(icc & PSR_NEG), 32, 32, -(xcc & PSR_NEG)); - env->cc_V =3D deposit64(-(icc & PSR_OVF), 32, 32, -(xcc & PSR_OVF)); - env->icc_C =3D (uint64_t)icc << (32 - PSR_CARRY_SHIFT); - env->xcc_C =3D (xcc >> PSR_CARRY_SHIFT) & 1; - env->xcc_Z =3D ~xcc & PSR_ZERO; -#else - env->cc_N =3D -(icc & PSR_NEG); - env->cc_V =3D -(icc & PSR_OVF); - env->icc_C =3D (icc >> PSR_CARRY_SHIFT) & 1; -#endif - env->icc_Z =3D ~icc & PSR_ZERO; - - CC_OP =3D CC_OP_FLAGS; + g_assert_not_reached(); } =20 uint32_t helper_compute_C_icc(CPUSPARCState *env) @@ -224,5 +38,5 @@ uint32_t helper_compute_C_icc(CPUSPARCState *env) return env->icc_C; #endif } - return icc_table[CC_OP].compute_c(env) >> PSR_CARRY_SHIFT; + g_assert_not_reached(); } diff --git a/target/sparc/helper.c b/target/sparc/helper.c index 53eec693dd..6117e99b55 100644 --- a/target/sparc/helper.c +++ b/target/sparc/helper.c @@ -156,7 +156,7 @@ uint64_t helper_udivx(CPUSPARCState *env, uint64_t a, u= int64_t b) target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1, target_ulong src2) { - target_ulong dst; + target_ulong dst, v; =20 /* Tag overflow occurs if either input has bits 0 or 1 set. */ if ((src1 | src2) & 3) { @@ -166,13 +166,23 @@ target_ulong helper_taddcctv(CPUSPARCState *env, targ= et_ulong src1, dst =3D src1 + src2; =20 /* Tag overflow occurs if the addition overflows. */ - if (~(src1 ^ src2) & (src1 ^ dst) & (1u << 31)) { + v =3D ~(src1 ^ src2) & (src1 ^ dst); + if (v & (1u << 31)) { goto tag_overflow; } =20 /* Only modify the CC after any exceptions have been generated. */ - env->cc_src =3D src1; - env->cc_src2 =3D src2; + env->cc_V =3D v; + env->cc_N =3D dst; + env->icc_Z =3D dst; +#ifdef TARGET_SPARC64 + env->xcc_Z =3D dst; + env->icc_C =3D dst ^ src1 ^ src2; + env->xcc_C =3D dst < src1; +#else + env->icc_C =3D dst < src1; +#endif + return dst; =20 tag_overflow: @@ -182,7 +192,7 @@ target_ulong helper_taddcctv(CPUSPARCState *env, target= _ulong src1, target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1, target_ulong src2) { - target_ulong dst; + target_ulong dst, v; =20 /* Tag overflow occurs if either input has bits 0 or 1 set. */ if ((src1 | src2) & 3) { @@ -192,13 +202,23 @@ target_ulong helper_tsubcctv(CPUSPARCState *env, targ= et_ulong src1, dst =3D src1 - src2; =20 /* Tag overflow occurs if the subtraction overflows. */ - if ((src1 ^ src2) & (src1 ^ dst) & (1u << 31)) { + v =3D (src1 ^ src2) & (src1 ^ dst); + if (v & (1u << 31)) { goto tag_overflow; } =20 /* Only modify the CC after any exceptions have been generated. */ - env->cc_src =3D src1; - env->cc_src2 =3D src2; + env->cc_V =3D v; + env->cc_N =3D dst; + env->icc_Z =3D dst; +#ifdef TARGET_SPARC64 + env->xcc_Z =3D dst; + env->icc_C =3D dst ^ src1 ^ src2; + env->xcc_C =3D src1 < src2; +#else + env->icc_C =3D src1 < src2; +#endif + return dst; =20 tag_overflow: diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d119ce4c94..7703166ebd 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -3598,8 +3598,8 @@ TRANS(SUB, ALL, do_arith, a, CC_OP_FLAGS, =20 TRANS(TADDcc, ALL, do_arith, a, CC_OP_FLAGS, NULL, NULL, gen_op_taddcc) TRANS(TSUBcc, ALL, do_arith, a, CC_OP_FLAGS, NULL, NULL, gen_op_tsubcc) -TRANS(TADDccTV, ALL, do_arith, a, CC_OP_TADDTV, NULL, NULL, gen_op_taddcct= v) -TRANS(TSUBccTV, ALL, do_arith, a, CC_OP_TSUBTV, NULL, NULL, gen_op_tsubcct= v) +TRANS(TADDccTV, ALL, do_arith, a, CC_OP_FLAGS, NULL, NULL, gen_op_taddcctv) +TRANS(TSUBccTV, ALL, do_arith, a, CC_OP_FLAGS, NULL, NULL, gen_op_tsubcctv) =20 TRANS(AND, ALL, do_logic, a, tcg_gen_and_tl, tcg_gen_andi_tl) TRANS(XOR, ALL, do_logic, a, tcg_gen_xor_tl, tcg_gen_xori_tl) --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u23-20020a056a00099700b006884549adc8sm4359777pfg.29.2023.11.05.12.12.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Nov 2023 12:12:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699215151; x=1699819951; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2xyyes3ZakXDRiJSSgaeY1fewbXiDL1R2SRhILheNoQ=; b=JxyChpz9rVqFm2VxYqlc251bowrFMB6GuHB5l41nli5/sxkkHKplRiA1AT2jLuZe30 PUEh5FcQr6q7Y7gFhDfqir6Ew1zV4hSqrxMW/bGILFjBB8nAjk4Y4BefbEpEl99bgKyi XcbRPF2Gi4VYkIGRO+L6De1VZc9xxSkU8tz4OY74XgzEacQEPAa9Zvl6RQiyYAJqY3kd LLkimNei8ylS2cclVbVcEtbsfQ4E9/Mb6VESTpolzTosyx3CybENVQ8pIAfq2Si5ugW5 b2VEzF2t/9hNEz0I1M3fflVq61MuYbF30J8VZnRdTqJbFPAO8I2n3/tpAHSzCQjOUIMk EceQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699215151; x=1699819951; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2xyyes3ZakXDRiJSSgaeY1fewbXiDL1R2SRhILheNoQ=; b=Zix8vQybOxj9u+KpG/W3dW7XVTksxog03j8lbX1aBDsq5eeJJzp+3lr+5YB9t4zFjo EDgerXAisiLBKfbQrre4XPImqp1DFGvioiIyCb+m3YHd+Y1DUH6a+cHZ/Uk+IfaIqJXz EokUCMF3TmS9smTJAcVIQAy55Y3oMETujK5mElucavN4eHnqcc2P/x/T4kXUOOV3c4jr ls9A76cqoNATuDByPyNLEXpQ7p1rVD+HHPlR5bJaMW5t45SVGWlsltlcLt5sx1C3I4eu HG4bdNfv4MheYafVC78xWldqX9RE0/9ahkeOTHYdim7fj6hAnlREJytwn4BeymK1G8KO fVbw== X-Gm-Message-State: AOJu0YzqSGdYIk025j8px9C14Tj5hmYCa5xj8QdlrwxbDmrElkbpD+Rs HYWSOlKamGGEGXx3xGhGRyLnELDifV/QA8zHjdI= X-Google-Smtp-Source: AGHT+IEbkocbwl35KWREutKMffno5UftA1I2TAjOKv4mvZYWKeOMcVBjTpGGMPDqdITZrgnEQjh1Ow== X-Received: by 2002:a05:6a00:218d:b0:6b2:5992:9e89 with SMTP id h13-20020a056a00218d00b006b259929e89mr32430023pfi.9.1699215150890; Sun, 05 Nov 2023 12:12:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 08/21] target/sparc: Remove CC_OP leftovers Date: Sun, 5 Nov 2023 12:12:09 -0800 Message-Id: <20231105201222.202395-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231105201222.202395-1-richard.henderson@linaro.org> References: <20231105201222.202395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215282932100007 Content-Type: text/plain; charset="utf-8" All instructions have been converted to generate full condition codes explicitly. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 21 ------- target/sparc/helper.h | 2 - linux-user/sparc/cpu_loop.c | 5 -- target/sparc/cc_helper.c | 42 ------------- target/sparc/cpu.c | 1 - target/sparc/int32_helper.c | 5 -- target/sparc/int64_helper.c | 5 -- target/sparc/translate.c | 115 ++++++++---------------------------- target/sparc/win_helper.c | 7 --- target/sparc/meson.build | 1 - 10 files changed, 26 insertions(+), 178 deletions(-) delete mode 100644 target/sparc/cc_helper.c diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index a7999eaab5..3e361a5b75 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -137,22 +137,6 @@ enum { #define PSR_CWP 0x1f #endif =20 -#define CC_SRC (env->cc_src) -#define CC_SRC2 (env->cc_src2) -#define CC_DST (env->cc_dst) -#define CC_OP (env->cc_op) - -/* Even though lazy evaluation of CPU condition codes tends to be less - * important on RISC systems where condition codes are only updated - * when explicitly requested, SPARC uses it to update 32-bit and 64-bit - * condition codes. - */ -enum { - CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ - CC_OP_FLAGS, /* all cc are back in cc_*_[NZCV] registers */ - CC_OP_NB, -}; - /* Trap base register */ #define TBR_BASE_MASK 0xfffff000 =20 @@ -474,11 +458,6 @@ struct CPUArchState { target_ulong xcc_C; #endif =20 - /* emulator internal flags handling */ - target_ulong cc_src, cc_src2; - target_ulong cc_dst; - uint32_t cc_op; - target_ulong cond; /* conditional branch result (XXX: save it in a temporary register when possible) */ =20 diff --git a/target/sparc/helper.h b/target/sparc/helper.h index a7b0079c3b..decd94c0d6 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -148,5 +148,3 @@ VIS_CMPHELPER(cmpne) #undef F_HELPER_0_1 #undef VIS_HELPER #undef VIS_CMPHELPER -DEF_HELPER_1(compute_psr, void, env) -DEF_HELPER_FLAGS_1(compute_C_icc, TCG_CALL_NO_WG_SE, i32, env) diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index c1a2362041..3c1bde00dd 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -222,11 +222,6 @@ void cpu_loop (CPUSPARCState *env) cpu_exec_end(cs); process_queued_cpu_work(cs); =20 - /* Compute PSR before exposing state. */ - if (env->cc_op !=3D CC_OP_FLAGS) { - cpu_get_psr(env); - } - switch (trapnr) { case TARGET_TT_SYSCALL: ret =3D do_syscall (env, env->gregs[1], diff --git a/target/sparc/cc_helper.c b/target/sparc/cc_helper.c deleted file mode 100644 index 05f1479aea..0000000000 --- a/target/sparc/cc_helper.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Helpers for lazy condition code handling - * - * Copyright (c) 2003-2005 Fabrice Bellard - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "exec/helper-proto.h" - -void helper_compute_psr(CPUSPARCState *env) -{ - if (CC_OP =3D=3D CC_OP_FLAGS) { - return; - } - g_assert_not_reached(); -} - -uint32_t helper_compute_C_icc(CPUSPARCState *env) -{ - if (CC_OP =3D=3D CC_OP_FLAGS) { -#ifdef TARGET_SPARC64 - return extract64(env->icc_C, 32, 1); -#else - return env->icc_C; -#endif - } - g_assert_not_reached(); -} diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index bb1a155510..befa7fc4eb 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -46,7 +46,6 @@ static void sparc_cpu_reset_hold(Object *obj) env->wim =3D 1; #endif env->regwptr =3D env->regbase + (env->cwp * 16); - CC_OP =3D CC_OP_FLAGS; #if defined(CONFIG_USER_ONLY) #ifdef TARGET_SPARC64 env->cleanwin =3D env->nwindows - 2; diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c index 82e8418e46..1563613582 100644 --- a/target/sparc/int32_helper.c +++ b/target/sparc/int32_helper.c @@ -103,11 +103,6 @@ void sparc_cpu_do_interrupt(CPUState *cs) CPUSPARCState *env =3D &cpu->env; int cwp, intno =3D cs->exception_index; =20 - /* Compute PSR before exposing state. */ - if (env->cc_op !=3D CC_OP_FLAGS) { - cpu_get_psr(env); - } - if (qemu_loglevel_mask(CPU_LOG_INT)) { static int count; const char *name; diff --git a/target/sparc/int64_helper.c b/target/sparc/int64_helper.c index 793e57c536..1b4155f5f3 100644 --- a/target/sparc/int64_helper.c +++ b/target/sparc/int64_helper.c @@ -135,11 +135,6 @@ void sparc_cpu_do_interrupt(CPUState *cs) int intno =3D cs->exception_index; trap_state *tsptr; =20 - /* Compute PSR before exposing state. */ - if (env->cc_op !=3D CC_OP_FLAGS) { - cpu_get_psr(env); - } - #ifdef DEBUG_PCALL if (qemu_loglevel_mask(CPU_LOG_INT)) { static int count; diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 7703166ebd..7c4fcf8326 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -105,8 +105,6 @@ =20 /* global register indexes */ static TCGv_ptr cpu_regwptr; -static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst; -static TCGv_i32 cpu_cc_op; static TCGv cpu_fsr, cpu_pc, cpu_npc; static TCGv cpu_regs[32]; static TCGv cpu_y; @@ -172,7 +170,6 @@ typedef struct DisasContext { #endif #endif =20 - uint32_t cc_op; /* current CC operation */ sparc_def_t *def; #ifdef TARGET_SPARC64 int fprs_dirty; @@ -962,14 +959,6 @@ static void save_npc(DisasContext *dc) } } =20 -static void update_psr(DisasContext *dc) -{ - if (dc->cc_op !=3D CC_OP_FLAGS) { - dc->cc_op =3D CC_OP_FLAGS; - gen_helper_compute_psr(tcg_env); - } -} - static void save_state(DisasContext *dc) { tcg_gen_movi_tl(cpu_pc, dc->pc); @@ -1048,20 +1037,9 @@ static void gen_op_next_insn(void) static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond, DisasContext *dc) { - TCGv t1, t2; + TCGv t1; =20 cmp->is_bool =3D false; - - switch (dc->cc_op) { - default: - gen_helper_compute_psr(tcg_env); - dc->cc_op =3D CC_OP_FLAGS; - break; - - case CC_OP_FLAGS: - break; - } - cmp->c1 =3D t1 =3D tcg_temp_new(); cmp->c2 =3D tcg_constant_tl(0); =20 @@ -2739,7 +2717,6 @@ TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_= rd_leon3_config) =20 static TCGv do_rdccr(DisasContext *dc, TCGv dst) { - update_psr(dc); gen_helper_rdccr(dst, tcg_env); return dst; } @@ -2852,7 +2829,6 @@ TRANS(RDSTRAND_STATUS, HYPV, do_rd_special, true, a->= rd, do_rdstrand_status) =20 static TCGv do_rdpsr(DisasContext *dc, TCGv dst) { - update_psr(dc); gen_helper_rdpsr(dst, tcg_env); return dst; } @@ -3257,8 +3233,6 @@ TRANS(WRPOWERDOWN, POWERDOWN, do_wr_special, a, super= visor(dc), do_wrpowerdown) static void do_wrpsr(DisasContext *dc, TCGv src) { gen_helper_wrpsr(tcg_env, src); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); - dc->cc_op =3D CC_OP_FLAGS; dc->base.is_jmp =3D DISAS_EXIT; } =20 @@ -3522,7 +3496,7 @@ static bool trans_NOP(DisasContext *dc, arg_NOP *a) TRANS(NOP_v7, 32, trans_NOP, a) TRANS(NOP_v9, 64, trans_NOP, a) =20 -static bool do_arith_int(DisasContext *dc, arg_r_r_ri_cc *a, int cc_op, +static bool do_arith_int(DisasContext *dc, arg_r_r_ri_cc *a, void (*func)(TCGv, TCGv, TCGv), void (*funci)(TCGv, TCGv, target_long), bool logic_cc) @@ -3536,8 +3510,6 @@ static bool do_arith_int(DisasContext *dc, arg_r_r_ri= _cc *a, int cc_op, =20 if (logic_cc) { dst =3D cpu_cc_N; - } else if (a->cc && cc_op > CC_OP_FLAGS) { - dst =3D cpu_cc_dst; } else { dst =3D gen_dest_gpr(dc, a->rd); } @@ -3564,42 +3536,36 @@ static bool do_arith_int(DisasContext *dc, arg_r_r_= ri_cc *a, int cc_op, } =20 gen_store_gpr(dc, a->rd, dst); - - if (a->cc) { - tcg_gen_movi_i32(cpu_cc_op, cc_op); - dc->cc_op =3D cc_op; - } return advance_pc(dc); } =20 -static bool do_arith(DisasContext *dc, arg_r_r_ri_cc *a, int cc_op, +static bool do_arith(DisasContext *dc, arg_r_r_ri_cc *a, void (*func)(TCGv, TCGv, TCGv), void (*funci)(TCGv, TCGv, target_long), void (*func_cc)(TCGv, TCGv, TCGv)) { if (a->cc) { - assert(cc_op >=3D 0); - return do_arith_int(dc, a, cc_op, func_cc, NULL, false); + return do_arith_int(dc, a, func_cc, NULL, false); } - return do_arith_int(dc, a, cc_op, func, funci, false); + return do_arith_int(dc, a, func, funci, false); } =20 static bool do_logic(DisasContext *dc, arg_r_r_ri_cc *a, void (*func)(TCGv, TCGv, TCGv), void (*funci)(TCGv, TCGv, target_long)) { - return do_arith_int(dc, a, CC_OP_FLAGS, func, funci, a->cc); + return do_arith_int(dc, a, func, funci, a->cc); } =20 -TRANS(ADD, ALL, do_arith, a, CC_OP_FLAGS, - tcg_gen_add_tl, tcg_gen_addi_tl, gen_op_addcc) -TRANS(SUB, ALL, do_arith, a, CC_OP_FLAGS, - tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_subcc) +TRANS(ADD, ALL, do_arith, a, tcg_gen_add_tl, tcg_gen_addi_tl, gen_op_addcc) +TRANS(SUB, ALL, do_arith, a, tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_subcc) +TRANS(ADDC, ALL, do_arith, a, gen_op_addc, NULL, gen_op_addccc) +TRANS(SUBC, ALL, do_arith, a, gen_op_subc, NULL, gen_op_subccc) =20 -TRANS(TADDcc, ALL, do_arith, a, CC_OP_FLAGS, NULL, NULL, gen_op_taddcc) -TRANS(TSUBcc, ALL, do_arith, a, CC_OP_FLAGS, NULL, NULL, gen_op_tsubcc) -TRANS(TADDccTV, ALL, do_arith, a, CC_OP_FLAGS, NULL, NULL, gen_op_taddcctv) -TRANS(TSUBccTV, ALL, do_arith, a, CC_OP_FLAGS, NULL, NULL, gen_op_tsubcctv) +TRANS(TADDcc, ALL, do_arith, a, NULL, NULL, gen_op_taddcc) +TRANS(TSUBcc, ALL, do_arith, a, NULL, NULL, gen_op_tsubcc) +TRANS(TADDccTV, ALL, do_arith, a, NULL, NULL, gen_op_taddcctv) +TRANS(TSUBccTV, ALL, do_arith, a, NULL, NULL, gen_op_tsubcctv) =20 TRANS(AND, ALL, do_logic, a, tcg_gen_and_tl, tcg_gen_andi_tl) TRANS(XOR, ALL, do_logic, a, tcg_gen_xor_tl, tcg_gen_xori_tl) @@ -3607,17 +3573,18 @@ TRANS(ANDN, ALL, do_logic, a, tcg_gen_andc_tl, NULL) TRANS(ORN, ALL, do_logic, a, tcg_gen_orc_tl, NULL) TRANS(XORN, ALL, do_logic, a, tcg_gen_eqv_tl, NULL) =20 -TRANS(MULX, 64, do_arith, a, -1, tcg_gen_mul_tl, tcg_gen_muli_tl, NULL) +TRANS(MULX, 64, do_arith, a, tcg_gen_mul_tl, tcg_gen_muli_tl, NULL) TRANS(UMUL, MUL, do_logic, a, gen_op_umul, NULL) TRANS(SMUL, MUL, do_logic, a, gen_op_smul, NULL) +TRANS(MULScc, ALL, do_arith, a, NULL, NULL, gen_op_mulscc) =20 -TRANS(UDIVX, 64, do_arith, a, -1, gen_op_udivx, NULL, NULL) -TRANS(SDIVX, 64, do_arith, a, -1, gen_op_sdivx, NULL, NULL) -TRANS(UDIV, DIV, do_arith, a, CC_OP_FLAGS, gen_op_udiv, NULL, gen_op_udivc= c) -TRANS(SDIV, DIV, do_arith, a, CC_OP_FLAGS, gen_op_sdiv, NULL, gen_op_sdivc= c) +TRANS(UDIVX, 64, do_arith, a, gen_op_udivx, NULL, NULL) +TRANS(SDIVX, 64, do_arith, a, gen_op_sdivx, NULL, NULL) +TRANS(UDIV, DIV, do_arith, a, gen_op_udiv, NULL, gen_op_udivcc) +TRANS(SDIV, DIV, do_arith, a, gen_op_sdiv, NULL, gen_op_sdivcc) =20 /* TODO: Should have feature bit -- comes in with UltraSparc T2. */ -TRANS(POPC, 64, do_arith, a, -1, gen_op_popc, NULL, NULL) +TRANS(POPC, 64, do_arith, a, gen_op_popc, NULL, NULL) =20 static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a) { @@ -3636,24 +3603,6 @@ static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc= *a) return do_logic(dc, a, tcg_gen_or_tl, tcg_gen_ori_tl); } =20 -static bool trans_ADDC(DisasContext *dc, arg_r_r_ri_cc *a) -{ - update_psr(dc); - return do_arith(dc, a, CC_OP_FLAGS, gen_op_addc, NULL, gen_op_addccc); -} - -static bool trans_SUBC(DisasContext *dc, arg_r_r_ri_cc *a) -{ - update_psr(dc); - return do_arith(dc, a, CC_OP_FLAGS, gen_op_subc, NULL, gen_op_subccc); -} - -static bool trans_MULScc(DisasContext *dc, arg_r_r_ri_cc *a) -{ - update_psr(dc); - return do_arith(dc, a, CC_OP_FLAGS, NULL, NULL, gen_op_mulscc); -} - static bool gen_edge(DisasContext *dc, arg_r_r_r *a, int width, bool cc, bool left) { @@ -3667,8 +3616,6 @@ static bool gen_edge(DisasContext *dc, arg_r_r_r *a, =20 if (cc) { gen_op_subcc(cpu_cc_N, s1, s2); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); - dc->cc_op =3D CC_OP_FLAGS; } =20 /* @@ -5080,7 +5027,6 @@ static void sparc_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) =20 dc->pc =3D dc->base.pc_first; dc->npc =3D (target_ulong)dc->base.tb->cs_base; - dc->cc_op =3D CC_OP_DYNAMIC; dc->mem_idx =3D dc->base.tb->flags & TB_FLAG_MMU_MASK; dc->def =3D &env->def; dc->fpu_enabled =3D tb_fpu_enabled(dc->base.tb->flags); @@ -5269,13 +5215,6 @@ void sparc_tcg_init(void) "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62", }; =20 - static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[= ] =3D { -#ifdef TARGET_SPARC64 - { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" }, -#endif - { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" }, - }; - static const struct { TCGv *ptr; int off; const char *name; } rtl[] = =3D { #ifdef TARGET_SPARC64 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" }, @@ -5287,9 +5226,6 @@ void sparc_tcg_init(void) { &cpu_icc_Z, offsetof(CPUSPARCState, icc_Z), "icc_Z" }, { &cpu_icc_C, offsetof(CPUSPARCState, icc_C), "icc_C" }, { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" }, - { &cpu_cc_src, offsetof(CPUSPARCState, cc_src), "cc_src" }, - { &cpu_cc_src2, offsetof(CPUSPARCState, cc_src2), "cc_src2" }, - { &cpu_cc_dst, offsetof(CPUSPARCState, cc_dst), "cc_dst" }, { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" }, { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" }, { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" }, @@ -5303,10 +5239,6 @@ void sparc_tcg_init(void) offsetof(CPUSPARCState, regwptr), "regwptr"); =20 - for (i =3D 0; i < ARRAY_SIZE(r32); ++i) { - *r32[i].ptr =3D tcg_global_mem_new_i32(tcg_env, r32[i].off, r32[i]= .name); - } - for (i =3D 0; i < ARRAY_SIZE(rtl); ++i) { *rtl[i].ptr =3D tcg_global_mem_new(tcg_env, rtl[i].off, rtl[i].nam= e); } @@ -5329,6 +5261,11 @@ void sparc_tcg_init(void) offsetof(CPUSPARCState, fpr[i]= ), fregnames[i]); } + +#ifdef TARGET_SPARC64 + cpu_fprs =3D tcg_global_mem_new_i32(tcg_env, + offsetof(CPUSPARCState, fprs), "fprs= "); +#endif } =20 void sparc_restore_state_to_opc(CPUState *cs, diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c index f0ff6bf5db..16d1c70fe7 100644 --- a/target/sparc/win_helper.c +++ b/target/sparc/win_helper.c @@ -55,8 +55,6 @@ target_ulong cpu_get_psr(CPUSPARCState *env) { target_ulong icc =3D 0; =20 - helper_compute_psr(env); - icc |=3D ((int32_t)env->cc_N < 0) << PSR_NEG_SHIFT; icc |=3D ((int32_t)env->cc_V < 0) << PSR_OVF_SHIFT; icc |=3D ((int32_t)env->icc_Z =3D=3D 0) << PSR_ZERO_SHIFT; @@ -103,7 +101,6 @@ void cpu_put_psr_raw(CPUSPARCState *env, target_ulong v= al) env->psrps =3D (val & PSR_PS) ? 1 : 0; env->psret =3D (val & PSR_ET) ? 1 : 0; #endif - env->cc_op =3D CC_OP_FLAGS; #if !defined(TARGET_SPARC64) cpu_set_cwp(env, val & PSR_CWP); #endif @@ -272,8 +269,6 @@ target_ulong cpu_get_ccr(CPUSPARCState *env) { target_ulong ccr =3D 0; =20 - helper_compute_psr(env); - ccr |=3D (env->icc_C >> 32) & 1; ccr |=3D ((int32_t)env->cc_V < 0) << 1; ccr |=3D ((int32_t)env->icc_Z =3D=3D 0) << 2; @@ -295,8 +290,6 @@ void cpu_put_ccr(CPUSPARCState *env, target_ulong val) env->xcc_C =3D (val >> 4) & 1; env->icc_Z =3D ~val & 0x04; env->xcc_Z =3D ~val & 0x40; - - CC_OP =3D CC_OP_FLAGS; } =20 target_ulong cpu_get_cwp64(CPUSPARCState *env) diff --git a/target/sparc/meson.build b/target/sparc/meson.build index c316773db6..46289c8669 100644 --- a/target/sparc/meson.build +++ b/target/sparc/meson.build @@ -3,7 +3,6 @@ gen =3D decodetree.process('insns.decode') sparc_ss =3D ss.source_set() sparc_ss.add(gen) sparc_ss.add(files( - 'cc_helper.c', 'cpu.c', 'fop_helper.c', 'gdbstub.c', --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u23-20020a056a00099700b006884549adc8sm4359777pfg.29.2023.11.05.12.12.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Nov 2023 12:12:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699215151; x=1699819951; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fgIxHuiUR0KbU50wGlTRe50Tyohq8BBHuIGeTYCLasg=; b=Iv0hlws/PehyuotA02pgfn9UuK2isSDMONm+vv+SSI/IBvkWomL2ps6CZbmlcNG15l I/LgBNd+eahkyVKGXbM35oSbl3Almg46fEqtHlO7k6SYXy+KYT2FNxcDEurIUqTN8gY+ HC82Xo7kz/p3o2iVOGs+PsUSHY/r4Fa7CJ0jlLWfOwXt+Blws+dTq+AVMpkUsPwd7z03 TzXtCYJDpLjjBSTn29VC8q1tduFBF+10FYKx4Ouyp6EZioUBo4qbLl733FPqyQBJWq1p TXnJNIPItcmBj5LREJh9VjFDd4mgg0/wURCophEvpi0nc3Rl/j8AygJKoZ50fsvGpANc 4h2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699215151; x=1699819951; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fgIxHuiUR0KbU50wGlTRe50Tyohq8BBHuIGeTYCLasg=; b=CKK+CECFzJX20PWl29A2Ki8CRrNkEvm2EakWLPa81mQftBPQrvyeGFq/gIh+OxeQVY IZcYjguJc3Fu2TQackAfLlFqcJeee2LSOcOrU1Je5CWIaptVexs8MFm41notbzThzOqa 3Dn+SKdvMICdo4vtI/I2ZSBnN2bkR7TAciGbBctNcthyuNYeMYEfROYtYODQeA3dwG+X wQj4P4oniJF8btSP/hII9nvuionGJ6h0GDfhLH1yEi4AsEyM9hsSqHBVpwxmeFbd7Qb/ VqP1k5GEuwpjsLr7sr00q8hCWK3oa9cdeyD6AhmIhZKo/ubCMAJ17lgjcaAllcVaw9xu LcxA== X-Gm-Message-State: AOJu0YyNsnRHT9RSnU6exLwjTxPYvjx6F7d6VqmU8PfhuakJAoEI5gDD FSKMAWJbJkkrX1yZ8w0kDnLHWSMJBTdJ4Le2KXs= X-Google-Smtp-Source: AGHT+IGINTc/WiNvPduwKrhG6AJ6YUo0RqD+M83qnLItj+nWjEMFUtVLP/4pPpRBLewncf0bQYTH4Q== X-Received: by 2002:a05:6a00:1a8a:b0:690:cae9:714d with SMTP id e10-20020a056a001a8a00b00690cae9714dmr7042611pfv.13.1699215151675; Sun, 05 Nov 2023 12:12:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 09/21] target/sparc: Remove DisasCompare.is_bool Date: Sun, 5 Nov 2023 12:12:10 -0800 Message-Id: <20231105201222.202395-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231105201222.202395-1-richard.henderson@linaro.org> References: <20231105201222.202395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215379074100003 Content-Type: text/plain; charset="utf-8" Since we're going to feed cpu_cond to another comparison, we don't reqire a boolean value -- anything non-zero is sufficient. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 22 +++++++--------------- 1 file changed, 7 insertions(+), 15 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 7c4fcf8326..464f1607e3 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -180,7 +180,6 @@ typedef struct DisasContext { =20 typedef struct { TCGCond cond; - bool is_bool; TCGv c1, c2; } DisasCompare; =20 @@ -1039,7 +1038,6 @@ static void gen_compare(DisasCompare *cmp, bool xcc, = unsigned int cond, { TCGv t1; =20 - cmp->is_bool =3D false; cmp->c1 =3D t1 =3D tcg_temp_new(); cmp->c2 =3D tcg_constant_tl(0); =20 @@ -1104,7 +1102,6 @@ static void gen_compare(DisasCompare *cmp, bool xcc, = unsigned int cond, =20 case 0x5: /* ltu: C */ cmp->cond =3D TCG_COND_NE; - cmp->is_bool =3D true; if (TARGET_LONG_BITS =3D=3D 32 || xcc) { tcg_gen_mov_tl(t1, cpu_cc_C); } else { @@ -1132,7 +1129,6 @@ static void gen_compare(DisasCompare *cmp, bool xcc, = unsigned int cond, } if (cond & 8) { cmp->cond =3D tcg_invert_cond(cmp->cond); - cmp->is_bool =3D false; } } =20 @@ -1143,7 +1139,6 @@ static void gen_fcompare(DisasCompare *cmp, unsigned = int cc, unsigned int cond) =20 /* For now we still generate a straight boolean result. */ cmp->cond =3D TCG_COND_NE; - cmp->is_bool =3D true; cmp->c1 =3D r_dst =3D tcg_temp_new(); cmp->c2 =3D tcg_constant_tl(0); =20 @@ -1230,7 +1225,6 @@ static const TCGCond gen_tcg_cond_reg[8] =3D { static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src) { cmp->cond =3D tcg_invert_cond(gen_tcg_cond_reg[cond]); - cmp->is_bool =3D false; cmp->c1 =3D r_src; cmp->c2 =3D tcg_constant_tl(0); } @@ -2232,18 +2226,14 @@ static void gen_fmovs(DisasContext *dc, DisasCompar= e *cmp, int rd, int rs) { #ifdef TARGET_SPARC64 TCGv_i32 c32, zero, dst, s1, s2; + TCGv_i64 c64 =3D tcg_temp_new_i64(); =20 /* We have two choices here: extend the 32 bit data and use movcond_i6= 4, or fold the comparison down to 32 bits and use movcond_i32. Choose the later. */ c32 =3D tcg_temp_new_i32(); - if (cmp->is_bool) { - tcg_gen_extrl_i64_i32(c32, cmp->c1); - } else { - TCGv_i64 c64 =3D tcg_temp_new_i64(); - tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2); - tcg_gen_extrl_i64_i32(c32, c64); - } + tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2); + tcg_gen_extrl_i64_i32(c32, c64); =20 s1 =3D gen_load_fpr_F(dc, rs); s2 =3D gen_load_fpr_F(dc, rd); @@ -2445,8 +2435,10 @@ static bool advance_jump_cond(DisasContext *dc, Disa= sCompare *cmp, dc->jump_pc[0] =3D dest; dc->jump_pc[1] =3D npc + 4; dc->npc =3D JUMP_PC; - if (cmp->is_bool) { - tcg_gen_mov_tl(cpu_cond, cmp->c1); + + /* The condition for cpu_cond is always NE -- normalize. */ + if (cmp->cond =3D=3D TCG_COND_NE) { + tcg_gen_xor_tl(cpu_cond, cmp->c1, cmp->c2); } else { tcg_gen_setcond_tl(cmp->cond, cpu_cond, cmp->c1, cmp->c2); } --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699215360; cv=none; d=zohomail.com; s=zohoarc; b=YBaEgodvc72+Sqi6lWTmCssF3TE9Xlt06r45NTaJoiHTcMB7l3E4og5wPBEWB5lA0SOLAvZjDg3U2gQmxHc9i+YDL4zKEY2iYawKFhtEJPleqgtVUnlZSw+vagYNO/qVqXHTuZSY6QlmXvl+QrvOgNMbcNVOs1bK7qTejyzVJkk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699215360; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bkAbPNyjzsZeyxWh+5iNiCPTFDeY/R9h3v6lIAuzON8=; b=Qef+fLGcANWScPMPIam4KQxhHhxNTm+l+DiQeVYTR++kNBzYxMqHmIWvuirikRmb+6F5ZS3IDZrMJT92LI18gnMpLHYIQdnd9cFpelFKjjJ0Mjk4N7hOGqLaqfapsaemrvenMwaGv5ol+6igo/kAT+X3pysblpNC6EjZk2wPSXE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699215360803361.32162293939086; Sun, 5 Nov 2023 12:16:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qzjU5-0003N0-8l; Sun, 05 Nov 2023 15:12:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qzjU3-0003J1-N7 for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:35 -0500 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qzjU1-000294-VA for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:35 -0500 Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-5b980391d70so2927748a12.0 for ; Sun, 05 Nov 2023 12:12:33 -0800 (PST) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u23-20020a056a00099700b006884549adc8sm4359777pfg.29.2023.11.05.12.12.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Nov 2023 12:12:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699215152; x=1699819952; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bkAbPNyjzsZeyxWh+5iNiCPTFDeY/R9h3v6lIAuzON8=; b=AMT6Cm+Ski86UkB8bYk+KHg4hrXUp3MY1yuWLyznqyp07RB59nznixJ0kHkJppEAl8 87ZdYyAPwJ9oicNeHJPcXmOQiCR3zljDIyMMWMxbDFp2LB5CxmfQGXDuzushfnj0aGoM 0xpZjJnrSkDH46jDFnv7Vss8+wrjZAvghNjS0dJ9Ogn867ZTLdeXW9kxE59yjXeMOgGb 5xAUI+4uP1YiIfzFn71n1ilsBE4cDo1H+onY9y5p00nWv7LnYEKHaYx6pGDRoaFEy5F+ cv8J8FYyZzrBpW/mcDKjzwkhSeZOO318bLg2rmMEDBHiIkG1bDecjpzE8d2EqEOn7Cxx A8QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699215152; x=1699819952; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bkAbPNyjzsZeyxWh+5iNiCPTFDeY/R9h3v6lIAuzON8=; b=oZDs9GbsX5bNLTyOV/ak9z8/BboqyjL9Usa4wW4+KXGz+k+FtWqWydL2Oskf/C3lf4 ZwUHf0rF6rkj+pc88XchTADr0oU91V+kvb6hgmlZQxnWrin0mUkhrQxFUyzh9b1T3e+4 3CL6CC9GGVOM5//6TB5Bl9/hXVS0hh8/7mvZxIGRaFd6oGl05Ro3GmJDVN2WTsu5Jg1L l9zZu1L2DQrquSMdnF693uiiozGjvuPN4vwj5TJUVedV6x/2WOBOu0pLJbwiJrfWc0sb 6hOTH9mTyU6EzviDyGpyEPTm6g8yDiD59GAVD74dcCMSR/FqloYErIPVasozgdeseerA XJuA== X-Gm-Message-State: AOJu0YwgvR8ZwjqrCGBgeq5cpEToiCMpcP/sIshtCJaaUxlQlb/5IZj8 XnTiGMXTrKM1+X2oI4fd+I7aNKHZmzWBRoSdWfY= X-Google-Smtp-Source: AGHT+IFeZSznT93nptHrFB6AA9wHTYl3UJ9sg4jL3xASFUi88aBjzua6Y4GZsv+bfSwG3iuCs5OzGg== X-Received: by 2002:a05:6a20:a220:b0:17b:e0a3:f6f4 with SMTP id u32-20020a056a20a22000b0017be0a3f6f4mr20241438pzk.25.1699215152488; Sun, 05 Nov 2023 12:12:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 10/21] target/sparc: Change DisasCompare.c2 to int Date: Sun, 5 Nov 2023 12:12:11 -0800 Message-Id: <20231105201222.202395-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231105201222.202395-1-richard.henderson@linaro.org> References: <20231105201222.202395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215361110100001 Content-Type: text/plain; charset="utf-8" We don't require c2 to be variable, so emphasize that. We don't currently require c2 to be non-zero, but that will change. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 464f1607e3..a405512e6c 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -180,7 +180,8 @@ typedef struct DisasContext { =20 typedef struct { TCGCond cond; - TCGv c1, c2; + TCGv c1; + int c2; } DisasCompare; =20 // This function uses non-native bit order @@ -1039,12 +1040,12 @@ static void gen_compare(DisasCompare *cmp, bool xcc= , unsigned int cond, TCGv t1; =20 cmp->c1 =3D t1 =3D tcg_temp_new(); - cmp->c2 =3D tcg_constant_tl(0); + cmp->c2 =3D 0; =20 switch (cond & 7) { case 0x0: /* never */ cmp->cond =3D TCG_COND_NEVER; - cmp->c1 =3D cmp->c2; + cmp->c1 =3D tcg_constant_tl(0); break; =20 case 0x1: /* eq: Z */ @@ -1140,7 +1141,7 @@ static void gen_fcompare(DisasCompare *cmp, unsigned = int cc, unsigned int cond) /* For now we still generate a straight boolean result. */ cmp->cond =3D TCG_COND_NE; cmp->c1 =3D r_dst =3D tcg_temp_new(); - cmp->c2 =3D tcg_constant_tl(0); + cmp->c2 =3D 0; =20 switch (cc) { default: @@ -1226,7 +1227,7 @@ static void gen_compare_reg(DisasCompare *cmp, int co= nd, TCGv r_src) { cmp->cond =3D tcg_invert_cond(gen_tcg_cond_reg[cond]); cmp->c1 =3D r_src; - cmp->c2 =3D tcg_constant_tl(0); + cmp->c2 =3D 0; } =20 static void gen_op_clear_ieee_excp_and_FTT(void) @@ -2232,7 +2233,7 @@ static void gen_fmovs(DisasContext *dc, DisasCompare = *cmp, int rd, int rs) or fold the comparison down to 32 bits and use movcond_i32. Choose the later. */ c32 =3D tcg_temp_new_i32(); - tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2); + tcg_gen_setcondi_i64(cmp->cond, c64, cmp->c1, cmp->c2); tcg_gen_extrl_i64_i32(c32, c64); =20 s1 =3D gen_load_fpr_F(dc, rs); @@ -2252,7 +2253,7 @@ static void gen_fmovd(DisasContext *dc, DisasCompare = *cmp, int rd, int rs) { #ifdef TARGET_SPARC64 TCGv_i64 dst =3D gen_dest_fpr_D(dc, rd); - tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2, + tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, tcg_constant_tl(cmp->c2), gen_load_fpr_D(dc, rs), gen_load_fpr_D(dc, rd)); gen_store_fpr_D(dc, rd, dst); @@ -2266,10 +2267,11 @@ static void gen_fmovq(DisasContext *dc, DisasCompar= e *cmp, int rd, int rs) #ifdef TARGET_SPARC64 int qd =3D QFPREG(rd); int qs =3D QFPREG(rs); + TCGv c2 =3D tcg_constant_tl(cmp->c2); =20 - tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2, + tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, c2, cpu_fpr[qs / 2], cpu_fpr[qd / 2]); - tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2, + tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, c2, cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]); =20 gen_update_fprs_dirty(dc, qd); @@ -2409,7 +2411,7 @@ static bool advance_jump_cond(DisasContext *dc, Disas= Compare *cmp, if (annul) { TCGLabel *l1 =3D gen_new_label(); =20 - tcg_gen_brcond_tl(tcg_invert_cond(cmp->cond), cmp->c1, cmp->c2, l1= ); + tcg_gen_brcondi_tl(tcg_invert_cond(cmp->cond), cmp->c1, cmp->c2, l= 1); gen_goto_tb(dc, 0, npc, dest); gen_set_label(l1); gen_goto_tb(dc, 1, npc + 4, npc + 8); @@ -2423,7 +2425,7 @@ static bool advance_jump_cond(DisasContext *dc, Disas= Compare *cmp, tcg_gen_mov_tl(cpu_pc, cpu_npc); tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); tcg_gen_movcond_tl(cmp->cond, cpu_npc, - cmp->c1, cmp->c2, + cmp->c1, tcg_constant_tl(cmp->c2), tcg_constant_tl(dest), cpu_npc); dc->pc =3D npc; break; @@ -2438,9 +2440,9 @@ static bool advance_jump_cond(DisasContext *dc, Disas= Compare *cmp, =20 /* The condition for cpu_cond is always NE -- normalize. */ if (cmp->cond =3D=3D TCG_COND_NE) { - tcg_gen_xor_tl(cpu_cond, cmp->c1, cmp->c2); + tcg_gen_xori_tl(cpu_cond, cmp->c1, cmp->c2); } else { - tcg_gen_setcond_tl(cmp->cond, cpu_cond, cmp->c1, cmp->c2); + tcg_gen_setcondi_tl(cmp->cond, cpu_cond, cmp->c1, cmp->c2); } } } @@ -2612,7 +2614,7 @@ static bool do_tcc(DisasContext *dc, int cond, int cc, flush_cond(dc); lab =3D delay_exceptionv(dc, trap); gen_compare(&cmp, cc, cond, dc); - tcg_gen_brcond_tl(cmp.cond, cmp.c1, cmp.c2, lab); + tcg_gen_brcondi_tl(cmp.cond, cmp.c1, cmp.c2, lab); =20 return advance_pc(dc); } @@ -3849,8 +3851,9 @@ static TCGv gen_rs2_or_imm(DisasContext *dc, bool imm= , int rs2_or_imm) static bool do_mov_cond(DisasContext *dc, DisasCompare *cmp, int rd, TCGv = src2) { TCGv dst =3D gen_load_gpr(dc, rd); + TCGv c2 =3D tcg_constant_tl(cmp->c2); =20 - tcg_gen_movcond_tl(cmp->cond, dst, cmp->c1, cmp->c2, src2, dst); + tcg_gen_movcond_tl(cmp->cond, dst, cmp->c1, c2, src2, dst); gen_store_gpr(dc, rd, dst); return advance_pc(dc); } --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u23-20020a056a00099700b006884549adc8sm4359777pfg.29.2023.11.05.12.12.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Nov 2023 12:12:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699215153; x=1699819953; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e5NGkRly/imKlA1fWYWgSM7Jy/zMxKilvyVfLnp3U18=; b=dBlWN6Q5SqxfFxjcvxdCHFdDRxzCwh/mtFNXriLSeF37+0BqB/qiV4J0rM9S+/+ewz G0R//R6hfR4IxVsnHwH8iFs1MgIgxu2QgsqeaxBLmsFIZ3Fq+FpdRh9cjir1C3O96rAX 3RUVIYQYsCgwx/NXxfC4yZEYBxFeQ70LmW36Fl9hFTvVr6DyhYudL39JJje1MgMrDHdt iq9zgHQWZcOT4fq5Q4KDqRJ3zmzf+WJvCqMmMCakJ3OY2VpYN994ZnUwqr4IpdxtaDrF YQNOJCoMPE04idJzqHCIQAxNnVftKZcnyXQMNFZrgSrANNgZInS2/aNnLu20oqKhv7N9 LZow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699215153; x=1699819953; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e5NGkRly/imKlA1fWYWgSM7Jy/zMxKilvyVfLnp3U18=; b=KV5HqH9Lf1NXUbmWUHWWyekTuhlb8ZMS2NlSSxuA0G2WgYsiAFJQFBwidmiFeFov1O hxI2Lz1Ad11IlzbmzhyGpRxf026xHDyNCPB7sy3G/fhqLkkmkK3EQ+btJM//ncZOSukG rOzsyCeS45f5k9+M1jpx1TzgCPwCPpyKszFaMHodZ/KlyX2HGwkz1jR3OuxVZejL3/ES RZ3jkNYilgfvJesjd2hfqYjRglG9yWsuPTOzx2giOXe3BD6s2fGwqCB3MAIg9qUHU+/J VwC6RQWU77Tkn6CFQHzCKCF+cqWZn0E1B8/ge2Ou/u23aQZfZ9ASaq9UXLu6EfjBsXxR +JHQ== X-Gm-Message-State: AOJu0Yz+c9CqZAdihvze+TN/Yb5qhOqOS0zxXtJCUGWYOuJGT8NM/ZLD 8mpQoDp+SzoqEo8h5o7np9Op+fEflzos3Sgsfkk= X-Google-Smtp-Source: AGHT+IGeyIKUJboAKluS4sK2RG1pHwDpDWbYw+jBvUEsAbDT10pHh8cUjjKuQSi60E7suZAdqXtLrw== X-Received: by 2002:a05:6808:1822:b0:3b2:ef72:f59e with SMTP id bh34-20020a056808182200b003b2ef72f59emr31421493oib.24.1699215153423; Sun, 05 Nov 2023 12:12:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 11/21] target/sparc: Always copy conditions into a new temporary Date: Sun, 5 Nov 2023 12:12:12 -0800 Message-Id: <20231105201222.202395-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231105201222.202395-1-richard.henderson@linaro.org> References: <20231105201222.202395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215220707100007 Content-Type: text/plain; charset="utf-8" This will allow the condition to live across changes to the global cc variables. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index a405512e6c..dd6d43d1f1 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1226,8 +1226,9 @@ static const TCGCond gen_tcg_cond_reg[8] =3D { static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src) { cmp->cond =3D tcg_invert_cond(gen_tcg_cond_reg[cond]); - cmp->c1 =3D r_src; + cmp->c1 =3D tcg_temp_new(); cmp->c2 =3D 0; + tcg_gen_mov_tl(cmp->c1, r_src); } =20 static void gen_op_clear_ieee_excp_and_FTT(void) --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699215235; cv=none; d=zohomail.com; s=zohoarc; b=HaO+LmMkHblgaYWewV7GLwmaSvcLZFYJB2MzC8ON/H3pq20PsbnvtW+CmebMTdO9gV4yTeJFCgx3gVJy2xAaTTD4zL9LL62iv2uZZIn6p2A4bgfz8qwFfn2z8rb+rqull43AhBRYZKSbEYFHHwzDtroD2a/gBB2vPciaFuM8OTw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699215235; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Q/NWt8/HhimxMcEILduOpW+WrJNp6qIGvrXM1RdrtRk=; b=QSkU1jP/ci0uq2cuOSqhhkYDCmRKlNdTYz1vF5kOAAN4nZaAH7LLysA8jzDd8nZLvPiryDFFWM3vKuZ6pTgSZZXk/7QLrPUj76moZm6SCntPcimirtE3esS0do4DNAFpO8mTxRfxfCXrTJ5DmYqbpNil1bvDOZ3pCAhuMykm4+o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699215235454241.7861602140399; Sun, 5 Nov 2023 12:13:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qzjU6-0003O0-QV; Sun, 05 Nov 2023 15:12:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qzjU5-0003Ng-Tz for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:37 -0500 Received: from mail-oo1-xc34.google.com ([2607:f8b0:4864:20::c34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qzjU3-00029h-Cw for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:37 -0500 Received: by mail-oo1-xc34.google.com with SMTP id 006d021491bc7-581e5a9413bso2182917eaf.1 for ; Sun, 05 Nov 2023 12:12:34 -0800 (PST) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u23-20020a056a00099700b006884549adc8sm4359777pfg.29.2023.11.05.12.12.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Nov 2023 12:12:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699215154; x=1699819954; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q/NWt8/HhimxMcEILduOpW+WrJNp6qIGvrXM1RdrtRk=; b=OY2Db6rTciKYaJtAZzLVqvWKSfDnB4cCVlbLieJz2rRCa7555N0q7xLobUPmWBO6Kt gl2GJrJeVPZz+OHOFlU8Zva5Ea7J2ek20Odzu4QfX3NylTrZpvfEKgw7XG2qKELUQtfb 1Ns/MwgAr6bLFGgtmmveUC9hQrZzr6SUORedFDmokcBIu49DfPS05Gq42GguW+KR8iqf 50+q9M/bFtf1oRh+YDpw5g97ZSdWvaw9DOyG0MGqoEmAYQMhR14gbHtbcUBEg99GLvn8 Fo0OvhaBG/1+ulP6tPiUYYEmhxnBCTu0JtDLgEYuRk4N5dI4/4Bgd2SVwXkY6v1CrKov OH2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699215154; x=1699819954; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q/NWt8/HhimxMcEILduOpW+WrJNp6qIGvrXM1RdrtRk=; b=LmzVf/p4xCvgwFrQxS657xz/kmK2cxrJiaG9ApXkXoRexOun+81NjULKiEDEQLRr6S xAzUL61t60iWJA/0F2phZcRX2Yn9zllX4IiiScshS2ItZ6hknWiG6wHQxqmf1kRTgO/a 3baLIE4pSpxZ0Vf5avf9OFubjhd/COlUdKHh+YnOucipeY8DrCgVUwtGaUrIEE9VWczS CvX0bZK6Xfmp3f6AKwq/iS0+Xc5CSg3Bavx9FZUop6nyGanBmc1Q2wPxnEBByAsQwPG1 yRWgr0sB/a2ZVcAemN3Od6c2F3CPrX47brSk6Rgl9y4V3d+h6eedr/w1AEgYleDQlp8t zFZg== X-Gm-Message-State: AOJu0YzTUZlwUAzBx64/fAM8lg8j242raR6j0Hn5+NzyjbTTIeUWwnCL JzccKivJOQwDlI7E01uKA5a8LMPf3NKoEZT3s6w= X-Google-Smtp-Source: AGHT+IEXFIfjmAwL9fpWfGMRrowI3+8Rl8kzBxE+zbE9hiXrATR8LfUcpw2YxS8eWhlgvFj/cZsS8A== X-Received: by 2002:a54:4887:0:b0:3a8:6693:135d with SMTP id r7-20020a544887000000b003a86693135dmr28588957oic.49.1699215154141; Sun, 05 Nov 2023 12:12:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 12/21] target/sparc: Do flush_cond in advance_jump_cond Date: Sun, 5 Nov 2023 12:12:13 -0800 Message-Id: <20231105201222.202395-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231105201222.202395-1-richard.henderson@linaro.org> References: <20231105201222.202395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c34; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215236842100002 Content-Type: text/plain; charset="utf-8" Do this here instead of in each caller. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index dd6d43d1f1..2e7deb5e33 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2407,7 +2407,10 @@ static bool advance_jump_uncond_always(DisasContext = *dc, bool annul, static bool advance_jump_cond(DisasContext *dc, DisasCompare *cmp, bool annul, target_ulong dest) { - target_ulong npc =3D dc->npc; + target_ulong npc; + + flush_cond(dc); + npc =3D dc->npc; =20 if (annul) { TCGLabel *l1 =3D gen_new_label(); @@ -2481,8 +2484,6 @@ static bool do_bpcc(DisasContext *dc, arg_bcc *a) case 0x8: return advance_jump_uncond_always(dc, a->a, target); default: - flush_cond(dc); - gen_compare(&cmp, a->cc, a->cond, dc); return advance_jump_cond(dc, &cmp, a->a, target); } @@ -2505,8 +2506,6 @@ static bool do_fbpfcc(DisasContext *dc, arg_bcc *a) case 0x8: return advance_jump_uncond_always(dc, a->a, target); default: - flush_cond(dc); - gen_fcompare(&cmp, a->cc, a->cond); return advance_jump_cond(dc, &cmp, a->a, target); } @@ -2527,7 +2526,6 @@ static bool trans_BPr(DisasContext *dc, arg_BPr *a) return false; } =20 - flush_cond(dc); gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1)); return advance_jump_cond(dc, &cmp, a->a, target); } --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699215284; cv=none; d=zohomail.com; s=zohoarc; b=f+cRj0r+xClesvuIyzZ/z08hyc6tAfeHSR3u8g9iRZZnE1U9gx7CqvwjTiISgkdRjA8RyvtTCDhzUsy9tuE0y5a1/gsaek1CYCUYSw1VXrKMzIbIjVPxHohCcOo9/0y9uWcSGnW1yzA/cTCEO8aJoMpFptlrObw/oxf8J6g88vg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699215284; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=XHJ3cfI2sXHgMNE5o/c/XelGrRA35h8Xfg71kYgqG0o=; b=kr9GnSj7Ta288P8c7O3Yr7CUTVg5Ldn8FjxG0kB1uza0idoe7LWtmqxDg0vuCdXFeW80i6nkF6J2h1Z3awDVulpobMhE3fr4OxaZHoxIThFyp7SiRAfTs59IAcGQ5Bo8RlwX+BeViZ2BkXxoTa7XapyE+eqKgx9HKGXPsiID/+Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699215284330343.39362253687045; Sun, 5 Nov 2023 12:14:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qzjU7-0003O3-Ew; Sun, 05 Nov 2023 15:12:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qzjU6-0003Nn-7W for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:38 -0500 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qzjU4-00029w-NJ for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:37 -0500 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-6ba54c3ed97so3975345b3a.2 for ; Sun, 05 Nov 2023 12:12:35 -0800 (PST) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u23-20020a056a00099700b006884549adc8sm4359777pfg.29.2023.11.05.12.12.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Nov 2023 12:12:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699215155; x=1699819955; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XHJ3cfI2sXHgMNE5o/c/XelGrRA35h8Xfg71kYgqG0o=; b=XWVmnAhCaHBvZ5KNmspNnmOUlSg+qpYuyfqgvXKmKU4mIWGH8lue6ehFZAVm3KlPAW iDpYQbtgpOYyqYwxomPpj6QHdtn8+8nPSX5SWGrWHfqvH150gMq0TSTvjwdwvEJRA0tj cmYLjaMzFopLzx5mhm460wOyeDUSWReghSQP+Bt8DKtVX6Nz3VgYrfbmXJSHHJlVDgmq /sI+zrpI6lZuEe9ut11zNnjFDMO3CP/Qw4nCzpb/Di3QhEtITPGjUqnI/NFeG2h5EVpf T3y3tVSKXrVnNaiYFpYNn4JdUOJBN/AL3YuTsap7T8hBIX5CJpAKg5kVxym36tOKO9gH 51EQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699215155; x=1699819955; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XHJ3cfI2sXHgMNE5o/c/XelGrRA35h8Xfg71kYgqG0o=; b=azauj3NtlcbL0Xu047qL1xkUBmWvKoHqWu9eqZiWqziVg/vJBDaKrk52HRr19SQUkx zsvgI7bWbp8pztQZwruqL1Ni0GJiM8jOdEnUOnY9uFLgqAAN/0gSkDTQVlWL3yzQs5SC EqZPUWKyU+LCwd4q7IspFjy2cj5bhAtqCytS5Byb4KfWfuinvgRfPMaw+yeLvXRcUsqo KRixifdWfv5gfhMHfCdO7lzmHRdb10Ea+76ngyhrVp+38kLUkYa71HAKrgRV2sGSkU/K PUsBC30pETQvwwaNjr1yNgP5gje5ifjYI9JPwv8IE5mQkqgRCTEBG1fv7AYmPYNFLjhm Su8g== X-Gm-Message-State: AOJu0YwiE9Z2M4FMWv+7xDxF2eVhehR9l1b/QkFuxYkgM2/SXxSqGEqX w1xMySOwUW8NDPPaUaE59xEw61KvMVazUep7ESQ= X-Google-Smtp-Source: AGHT+IH4lMEqMIC3izXUxuM2mi3v//t+36T7EDvD0BNp/nAUr6xr4avsIqIDZburFF8qdO3EYrNSIw== X-Received: by 2002:a05:6a00:b8e:b0:68a:5395:7aa5 with SMTP id g14-20020a056a000b8e00b0068a53957aa5mr31996329pfj.17.1699215154931; Sun, 05 Nov 2023 12:12:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 13/21] target/sparc: Merge gen_branch2 into advance_pc Date: Sun, 5 Nov 2023 12:12:14 -0800 Message-Id: <20231105201222.202395-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231105201222.202395-1-richard.henderson@linaro.org> References: <20231105201222.202395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215284881100009 Content-Type: text/plain; charset="utf-8" The function had only one caller. Canonicalize the cpu_cond test to TCG_COND_NE, the "natural" sense of its value. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 2e7deb5e33..e134ba8821 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -908,19 +908,6 @@ static void gen_op_eval_fbo(TCGv dst, TCGv src, unsign= ed int fcc_offset) tcg_gen_xori_tl(dst, dst, 0x1); } =20 -static void gen_branch2(DisasContext *dc, target_ulong pc1, - target_ulong pc2, TCGv r_cond) -{ - TCGLabel *l1 =3D gen_new_label(); - - tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1); - - gen_goto_tb(dc, 0, pc1, pc1 + 4); - - gen_set_label(l1); - gen_goto_tb(dc, 1, pc2, pc2 + 4); -} - static void gen_generic_branch(DisasContext *dc) { TCGv npc0 =3D tcg_constant_tl(dc->jump_pc[0]); @@ -2352,6 +2339,8 @@ static int extract_qfpreg(DisasContext *dc, int x) /* Default case for non jump instructions. */ static bool advance_pc(DisasContext *dc) { + TCGLabel *l1; + if (dc->npc & 3) { switch (dc->npc) { case DYNAMIC_PC: @@ -2359,11 +2348,22 @@ static bool advance_pc(DisasContext *dc) dc->pc =3D dc->npc; gen_op_next_insn(); break; + case JUMP_PC: /* we can do a static jump */ - gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); + l1 =3D gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cond, 0, l1); + + /* jump not taken */ + gen_goto_tb(dc, 1, dc->jump_pc[1], dc->jump_pc[1] + 4); + + /* jump taken */ + gen_set_label(l1); + gen_goto_tb(dc, 0, dc->jump_pc[0], dc->jump_pc[0] + 4); + dc->base.is_jmp =3D DISAS_NORETURN; break; + default: g_assert_not_reached(); } --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16992152178491015.4999936442853; Sun, 5 Nov 2023 12:13:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qzjU9-0003PR-1Q; Sun, 05 Nov 2023 15:12:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qzjU7-0003O4-DI for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:39 -0500 Received: from mail-oi1-x231.google.com ([2607:f8b0:4864:20::231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qzjU5-0002AC-RL for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:39 -0500 Received: by mail-oi1-x231.google.com with SMTP id 5614622812f47-3b2b1af964dso2546617b6e.1 for ; Sun, 05 Nov 2023 12:12:37 -0800 (PST) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u23-20020a056a00099700b006884549adc8sm4359777pfg.29.2023.11.05.12.12.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Nov 2023 12:12:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699215156; x=1699819956; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TFSCl5lnV2U9VXq8eQaIzYhW+oJcX4r3EEzkiMuRW8Q=; b=YnQx0Y1Kk+MI3wAaE1eCCUCQ/hzSeW6nEHpveCX994v7Tns4JBGCr9fDZ32iaWORpk EGDKIt1tPoi98AUR0+VmJeWz/rpkD8O5V77WuqLHn7CLeC+lHOwPXW/WVrDRNbu2MRJZ 4ZQXT+SkEoxDbZ30yd93SNGhTmitbDZUlz+mvfVDiN7L1uLcFvBcWxYnIftkQIlbWUvh ZqVJE1Gq9Y+nCE307kAfcnfGGe0rvsGUAr1JbwY8Mitq6ylO/mLXu41CxTmeOqkwgZbX IgsNex4MPojngJCCz7/2iDQfNcpm+WPU97CmJyehinhWyKyrwNtCIwMwgLOTWHGEP0HO x7Xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699215156; x=1699819956; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TFSCl5lnV2U9VXq8eQaIzYhW+oJcX4r3EEzkiMuRW8Q=; b=AcbtiILXQHqbWKInmadQtBup2AO5DKWIjK9Hov3+Dv2RVl+mZ7y2gm5M91Ua6dVTx7 /hj9yptARzzF7JF22KzQxIfyQJvlWiwg5eTHPSEyw99K3EJZNzqzVxK85TGHZdA+i/pi W06lP2TVWU/Pk0CXfleq5CCu2a16FLLRkiB6WzR+ASNIN9UljSuU2kkdbQ4AiKYl2784 I4ekuvv3y73FsDdRg8zRizVr1NKZomevLHYqkeHJ/hawyVZmvLrPuGaIxi2ko4MPDJRk QVnMBjZWCLESi9vp3ui8OJLasqfUlNL039bWLofRWKI8bDiD4URYGODnL4FNFthOTupl n3gQ== X-Gm-Message-State: AOJu0Yzvu6ebpnZwhTrWGToq7dx0TuDTFdDnVrC8TXBWWBC1eX8r/5hn PhDzeP64k27npnCFUCPO1gq86slD8lU+vMW3bhI= X-Google-Smtp-Source: AGHT+IFbaauyyYaT+U6dKKoOXXlznGjFB066RdK2LeWrGIbHqO3w4qPQiD2l/He3ykVIbzpVjkDBDw== X-Received: by 2002:a05:6808:189c:b0:3b5:9541:cb43 with SMTP id bi28-20020a056808189c00b003b59541cb43mr9291154oib.14.1699215155774; Sun, 05 Nov 2023 12:12:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 14/21] target/sparc: Merge advance_jump_uncond_{never, always} into advance_jump_cond Date: Sun, 5 Nov 2023 12:12:15 -0800 Message-Id: <20231105201222.202395-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231105201222.202395-1-richard.henderson@linaro.org> References: <20231105201222.202395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1699215218928100003 Content-Type: text/plain; charset="utf-8" Handle these via TCG_COND_{ALWAYS,NEVER}. Allow dc->npc to be variable, using gen_mov_pc_npc. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 74 ++++++++++++++++------------------------ 1 file changed, 30 insertions(+), 44 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index e134ba8821..cbee5435a3 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2378,37 +2378,37 @@ static bool advance_pc(DisasContext *dc) * Major opcodes 00 and 01 -- branches, call, and sethi */ =20 -static bool advance_jump_uncond_never(DisasContext *dc, bool annul) -{ - if (annul) { - dc->pc =3D dc->npc + 4; - dc->npc =3D dc->pc + 4; - } else { - dc->pc =3D dc->npc; - dc->npc =3D dc->pc + 4; - } - return true; -} - -static bool advance_jump_uncond_always(DisasContext *dc, bool annul, - target_ulong dest) -{ - if (annul) { - dc->pc =3D dest; - dc->npc =3D dest + 4; - } else { - dc->pc =3D dc->npc; - dc->npc =3D dest; - tcg_gen_mov_tl(cpu_pc, cpu_npc); - } - return true; -} - static bool advance_jump_cond(DisasContext *dc, DisasCompare *cmp, bool annul, target_ulong dest) { target_ulong npc; =20 + if (cmp->cond =3D=3D TCG_COND_ALWAYS) { + if (annul) { + dc->pc =3D dest; + dc->npc =3D dest + 4; + } else { + gen_mov_pc_npc(dc); + dc->npc =3D dest; + } + return true; + } + + if (cmp->cond =3D=3D TCG_COND_NEVER) { + npc =3D dc->npc; + if (npc & 3) { + gen_mov_pc_npc(dc); + if (annul) { + tcg_gen_addi_tl(cpu_pc, cpu_pc, 4); + } + tcg_gen_addi_tl(cpu_npc, cpu_pc, 4); + } else { + dc->pc =3D npc + (annul ? 4 : 0); + dc->npc =3D dc->pc + 4; + } + return true; + } + flush_cond(dc); npc =3D dc->npc; =20 @@ -2478,15 +2478,8 @@ static bool do_bpcc(DisasContext *dc, arg_bcc *a) target_long target =3D address_mask_i(dc, dc->pc + a->i * 4); DisasCompare cmp; =20 - switch (a->cond) { - case 0x0: - return advance_jump_uncond_never(dc, a->a); - case 0x8: - return advance_jump_uncond_always(dc, a->a, target); - default: - gen_compare(&cmp, a->cc, a->cond, dc); - return advance_jump_cond(dc, &cmp, a->a, target); - } + gen_compare(&cmp, a->cc, a->cond, dc); + return advance_jump_cond(dc, &cmp, a->a, target); } =20 TRANS(Bicc, ALL, do_bpcc, a) @@ -2500,15 +2493,8 @@ static bool do_fbpfcc(DisasContext *dc, arg_bcc *a) if (gen_trap_ifnofpu(dc)) { return true; } - switch (a->cond) { - case 0x0: - return advance_jump_uncond_never(dc, a->a); - case 0x8: - return advance_jump_uncond_always(dc, a->a, target); - default: - gen_fcompare(&cmp, a->cc, a->cond); - return advance_jump_cond(dc, &cmp, a->a, target); - } + gen_fcompare(&cmp, a->cc, a->cond); + return advance_jump_cond(dc, &cmp, a->a, target); } =20 TRANS(FBPfcc, 64, do_fbpfcc, a) --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699215234; cv=none; d=zohomail.com; s=zohoarc; b=LW9OQuL1kggM6tK+7yzSh2v4X5J3a+dMySdA9S4E+CKytKPbGN2J0cB/aJ6yKsGDiJYv6WrTqQ9iNTdefY/Zf+cUtGg5REwVHG946u1R2Nd0v5pLuMBWs9AyE9hpn4TqHGuUy7/N3Af8BcheqN187NvASR5k3VDzRECvYemRnlM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699215234; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=J1YIzqOFSgMcnN6BcwtNadmOERabr9cbQIvdlvZH1EA=; b=ctLbf/kHxGtAiWcS9pkL2Jxjk4I8TuIJb17VVJhSgeYJE/YONEZTCZt0Sh6MF9D+TRGMEQ8VcgyvoYQmkkZ48vKdqlIx7EBAhuD7pWoNJPfvD5y2FSDd8Zykde1H6jjWHJLqgXUvlJAkfRUq7O0Osy0d9AO2Wk/XFDnj+rfgTV8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699215234531273.511708241008; Sun, 5 Nov 2023 12:13:54 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qzjUB-0003RA-IW; Sun, 05 Nov 2023 15:12:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qzjU7-0003O5-Ep for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:39 -0500 Received: from mail-oi1-x232.google.com ([2607:f8b0:4864:20::232]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qzjU5-0002AE-QA for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:39 -0500 Received: by mail-oi1-x232.google.com with SMTP id 5614622812f47-3b2e44c7941so2521057b6e.2 for ; Sun, 05 Nov 2023 12:12:37 -0800 (PST) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215236868100006 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index cbee5435a3..1233911b69 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2379,8 +2379,9 @@ static bool advance_pc(DisasContext *dc) */ =20 static bool advance_jump_cond(DisasContext *dc, DisasCompare *cmp, - bool annul, target_ulong dest) + bool annul, int disp) { + target_ulong dest =3D address_mask_i(dc, dc->pc + disp * 4); target_ulong npc; =20 if (cmp->cond =3D=3D TCG_COND_ALWAYS) { @@ -2475,11 +2476,10 @@ static bool gen_trap_float128(DisasContext *dc) =20 static bool do_bpcc(DisasContext *dc, arg_bcc *a) { - target_long target =3D address_mask_i(dc, dc->pc + a->i * 4); DisasCompare cmp; =20 gen_compare(&cmp, a->cc, a->cond, dc); - return advance_jump_cond(dc, &cmp, a->a, target); + return advance_jump_cond(dc, &cmp, a->a, a->i); } =20 TRANS(Bicc, ALL, do_bpcc, a) @@ -2487,14 +2487,13 @@ TRANS(BPcc, 64, do_bpcc, a) =20 static bool do_fbpfcc(DisasContext *dc, arg_bcc *a) { - target_long target =3D address_mask_i(dc, dc->pc + a->i * 4); DisasCompare cmp; =20 if (gen_trap_ifnofpu(dc)) { return true; } gen_fcompare(&cmp, a->cc, a->cond); - return advance_jump_cond(dc, &cmp, a->a, target); + return advance_jump_cond(dc, &cmp, a->a, a->i); } =20 TRANS(FBPfcc, 64, do_fbpfcc, a) @@ -2502,7 +2501,6 @@ TRANS(FBfcc, ALL, do_fbpfcc, a) =20 static bool trans_BPr(DisasContext *dc, arg_BPr *a) { - target_long target =3D address_mask_i(dc, dc->pc + a->i * 4); DisasCompare cmp; =20 if (!avail_64(dc)) { @@ -2513,7 +2511,7 @@ static bool trans_BPr(DisasContext *dc, arg_BPr *a) } =20 gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1)); - return advance_jump_cond(dc, &cmp, a->a, target); + return advance_jump_cond(dc, &cmp, a->a, a->i); } =20 static bool trans_CALL(DisasContext *dc, arg_CALL *a) --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699215320; cv=none; d=zohomail.com; s=zohoarc; b=RON40oenJVSXeM4hjnmUXxMz9nJFwTFdXUJ4+3T2NWc0pWiNmslw1fYjfhLpEOYqQOH9v9KDG+zdw8iS3JkaZeXtuRc3+PwQdwVOylGSHgs9U+7AAbhl9xgTIC6mUTxPt19uhRlqnxziTctd4BHu6lf2qSP5lv5DlOm1Jn9hMgg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215321042100002 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 1233911b69..0bbe4cff3b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1015,12 +1015,6 @@ static void gen_mov_pc_npc(DisasContext *dc) } } =20 -static void gen_op_next_insn(void) -{ - tcg_gen_mov_tl(cpu_pc, cpu_npc); - tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); -} - static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond, DisasContext *dc) { @@ -2346,7 +2340,8 @@ static bool advance_pc(DisasContext *dc) case DYNAMIC_PC: case DYNAMIC_PC_LOOKUP: dc->pc =3D dc->npc; - gen_op_next_insn(); + tcg_gen_mov_tl(cpu_pc, cpu_npc); + tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); break; =20 case JUMP_PC: --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699215235; cv=none; d=zohomail.com; s=zohoarc; b=RIqW6C2iyrVlBBskCqQmOpkaMYUDLBfZGuWVnSd04yy4O7LR2aogz4FxWaIPO1Row+rtJHEgssbeAgeEwUYAJE2Cyere6Tsb8aypg3aKCWRayUvhGaagRyYtDzdvAmUroFxjJEPq/2wbLB8WDs6Wm+NV7AjDuxXoMBqBFsvkmMY= ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u23-20020a056a00099700b006884549adc8sm4359777pfg.29.2023.11.05.12.12.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Nov 2023 12:12:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699215158; x=1699819958; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DKj41VweZhjCF7fzIbibfC9ijUJvX4oDkwTltCV+TME=; b=K3CQE2wvFSRpvj1EZTY1UPGO9PeYcdRnw8QlZIs52tSwgcpcZZvswiBuBUCY87ju3M ivLSKhjK7iVpiuCEFOe95K0jRvzUurMonjFzW5DOf14m50s+GN+kD3QmSY67Uy4CErgR /pwgY2/umcxAW1RqBCh5o0Q957IWc7SDeyVeQClINMksO7CAN+tU3l02/W9P8CvjlDMb t3nSvpW2M8u13y5p5OZ6wIe43QfZSKKOu+NqLsP5nCq1T8GfD4r/v0En0b1xNnmb4+n/ O8OsaFtiRarqXY/vOXMrfP9nzzW6Fjv2IvamA0fabEhWt1/sS/Dg5QbpDZQOUc9gOdvc tBdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699215158; x=1699819958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DKj41VweZhjCF7fzIbibfC9ijUJvX4oDkwTltCV+TME=; b=aX8c09phHQcAdZpdULRVIIvafhp8peEYPDiGtorTdOIAlFDnt6rebnf16BhzRuancL cGJPeMZHic718PqZmGx7OiTzc578iPlH09J4bnGy+TGKbUZZ2lbyZQYdkyTyJJKqvOme d+x4UREg8hOMXfUCjQIyLFyDBtXgfFRjmMLIvcqWWb6apfedv8e2JtnLGTaJu3X0YlwN 9Bt46B63FUC2ghQGrWYpOCx2dEwQIty0ULRPcZ4a+49CWmVeZVsLta6lUxPxXx0h+SJK yCU52w3AHqYEGjGicwFx8UXcq5UgSOatZ5MIP6wVPn2wfeXgvfl1B6P8BLB0XBCOeH/B rq4A== X-Gm-Message-State: AOJu0YzNRj3kf3cZQdk/nirv2ZIk7Q+uWHFdYdRTXW0xCFWNYHtZIUaY 7gI5y8Gf2/9ce53eosmNWxAYBB5lh1PyVN4wV6k= X-Google-Smtp-Source: AGHT+IEW5G3ItXzj7A2reyTnTB+/038x2br1u+Xe2gbDvXI3pmqYJgIUubjv1Ft9+XkyS0XoxJgZ0w== X-Received: by 2002:a05:6602:1607:b0:7a9:afab:b984 with SMTP id x7-20020a056602160700b007a9afabb984mr33204503iow.17.1699215158442; Sun, 05 Nov 2023 12:12:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 17/21] target/sparc: Record entire jump condition in DisasContext Date: Sun, 5 Nov 2023 12:12:18 -0800 Message-Id: <20231105201222.202395-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231105201222.202395-1-richard.henderson@linaro.org> References: <20231105201222.202395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::d32; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215236848100003 Content-Type: text/plain; charset="utf-8" Use the original condition instead of consuming cpu_cond, which will now only be live along exception paths. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 0bbe4cff3b..5c9a3d45fa 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -146,6 +146,12 @@ static TCGv_i64 cpu_fpr[TARGET_DPREGS]; # define env64_field_offsetof(X) ({ qemu_build_not_reached(); 0; }) #endif =20 +typedef struct DisasCompare { + TCGCond cond; + TCGv c1; + int c2; +} DisasCompare; + typedef struct DisasDelayException { struct DisasDelayException *next; TCGLabel *lab; @@ -159,7 +165,11 @@ typedef struct DisasContext { DisasContextBase base; target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC = */ target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */ - target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ + + /* Used when JUMP_PC value is used. */ + DisasCompare jump; + target_ulong jump_pc[2]; + int mem_idx; bool fpu_enabled; bool address_mask_32bit; @@ -178,12 +188,6 @@ typedef struct DisasContext { DisasDelayException *delay_excp_list; } DisasContext; =20 -typedef struct { - TCGCond cond; - TCGv c1; - int c2; -} DisasCompare; - // This function uses non-native bit order #define GET_FIELD(X, FROM, TO) \ ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) @@ -912,9 +916,9 @@ static void gen_generic_branch(DisasContext *dc) { TCGv npc0 =3D tcg_constant_tl(dc->jump_pc[0]); TCGv npc1 =3D tcg_constant_tl(dc->jump_pc[1]); - TCGv zero =3D tcg_constant_tl(0); + TCGv c2 =3D tcg_constant_tl(dc->jump.c2); =20 - tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1); + tcg_gen_movcond_tl(dc->jump.cond, cpu_npc, dc->jump.c1, c2, npc0, npc1= ); } =20 /* call this function before using the condition register as it may @@ -2347,7 +2351,7 @@ static bool advance_pc(DisasContext *dc) case JUMP_PC: /* we can do a static jump */ l1 =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cond, 0, l1); + tcg_gen_brcondi_tl(dc->jump.cond, dc->jump.c1, dc->jump.c2, l1= ); =20 /* jump not taken */ gen_goto_tb(dc, 1, dc->jump_pc[1], dc->jump_pc[1] + 4); @@ -2434,9 +2438,10 @@ static bool advance_jump_cond(DisasContext *dc, Disa= sCompare *cmp, } } else { dc->pc =3D npc; + dc->npc =3D JUMP_PC; + dc->jump =3D *cmp; dc->jump_pc[0] =3D dest; dc->jump_pc[1] =3D npc + 4; - dc->npc =3D JUMP_PC; =20 /* The condition for cpu_cond is always NE -- normalize. */ if (cmp->cond =3D=3D TCG_COND_NE) { --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699215293; cv=none; d=zohomail.com; s=zohoarc; b=NDvm2zeEWWYwWHHtUdnuK6jtptvtZ7t65o5owlVLV/jlaNnER/YlqYWceISWYKTSP+cS6B456gJ928pz+Pv0FF5OHWMQflXeiWrQIDPQOWObmWYnTsi5CNmMEEwUBBRpldUVFay8I6NNnGAbMNu+vyvBjr/7IwjaSy5nbENTk3A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699215293; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=tlzuFmbJ+lRCVWBnnRWRgKX8WhOt5plpowDBaUnKw9s=; b=hjF4i/r4HCNbWD4es73pZXAroZJlV8XcCe3UKBE/0GoGrUPAk/D3XbIingCPK0D7psT8MsmHlxPgL+EsaPd6ub2I3Uq7ugjoqPjpyp6q/F4vNNajP+BpXJ5KIJ0WdTkybIRqAIzSc8EAoZiE+11LZPQNkKVMYHc99IAvwYCfrl8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699215293072220.53596847748247; Sun, 5 Nov 2023 12:14:53 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qzjUC-0003Rb-4U; Sun, 05 Nov 2023 15:12:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qzjUA-0003QX-CL for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:42 -0500 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qzjU8-0002As-Mv for qemu-devel@nongnu.org; Sun, 05 Nov 2023 15:12:42 -0500 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-6b3c2607d9bso3078771b3a.1 for ; Sun, 05 Nov 2023 12:12:40 -0800 (PST) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u23-20020a056a00099700b006884549adc8sm4359777pfg.29.2023.11.05.12.12.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Nov 2023 12:12:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699215159; x=1699819959; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tlzuFmbJ+lRCVWBnnRWRgKX8WhOt5plpowDBaUnKw9s=; b=HpMYmjXNp3q02Lc3fHCvQ2aFyHqjZ5hhg/HiNzmvHa1rCHzFaiten4BDlJpJ0FaqXJ ATOl+t3LTcEA1DWGve1W/3WoMh+10z85P4mOB3YYwWGTdzqBLgWm3HKWMsi/Bo1SuiZX NfiM+8diq9GtUNmQ3OKqT8hPo5kKqVyEGU+QrG8xNraZzaiH065x671IlUeHQFIPFn6n RrIA6sIhHt5+tpRQBl1JpZZQWs0SJ+nfHQjxnlJg+D/MRytip7n50azNnYRFRE2fQM5v tercrT86LDj0ERqGAXU/835wLFRGhOySovoRIlPlbbKILaSp6Rx1MVd7ba/au/kDCrr2 0Qxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699215159; x=1699819959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tlzuFmbJ+lRCVWBnnRWRgKX8WhOt5plpowDBaUnKw9s=; b=K6AL6qqaGtXoRntzq+wyexUs/mPamBLekUELNU2NAH2VLR5zKyM8bYEzqBAkavkNIc Xh6mxHr+5CJ17SbiK7pK15PruEyY4GnPMD4xmZMMMY/NBkGiub2tusRG6eI0DOktP1i2 dfgvyfx4vvjwjK2Qahe4QQVmqkUjephoPt8Jv37O/ygPEcTSNzAV1D6yKicKamdLDbnx dih4fiIOlbI/1A+OiydnU4zlFMZ5FR5QT/5lqVR4swE+7avoRUsCdxWeNoEOizYQfur9 vdYNndSVnvMx6R4HVDEPlTgmDlx1csSK8c1IVJ9eNKoJvgprQJ9R3HZOxprVvbRjr8zZ exNw== X-Gm-Message-State: AOJu0YzjFg88zJ4hKyq1m9IirltQ0GmTFqvYOAuP0aNA5bahCpoPlkSI bAYHMvycg+scnzmQZckZe10peGNkLk9c/4z2v1M= X-Google-Smtp-Source: AGHT+IGZngWQEO4itYmIFVmch8Ho89QeunkqMkuA2/okMhwQS2MLe4ZcH8x0+u7BRuNPiK7D1fticg== X-Received: by 2002:a05:6a00:391a:b0:68f:f38d:f76c with SMTP id fh26-20020a056a00391a00b0068ff38df76cmr23607474pfb.6.1699215159238; Sun, 05 Nov 2023 12:12:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 18/21] target/sparc: Discard cpu_cond at the end of each insn Date: Sun, 5 Nov 2023 12:12:19 -0800 Message-Id: <20231105201222.202395-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231105201222.202395-1-richard.henderson@linaro.org> References: <20231105201222.202395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215294935100003 Content-Type: text/plain; charset="utf-8" If the insn raises no exceptions, there will be no path in which cpu_cond is used, and so the computation may be optimized away. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 5c9a3d45fa..3564c6032e 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -171,6 +171,7 @@ typedef struct DisasContext { target_ulong jump_pc[2]; =20 int mem_idx; + bool cpu_cond_live; bool fpu_enabled; bool address_mask_32bit; #ifndef CONFIG_USER_ONLY @@ -912,6 +913,19 @@ static void gen_op_eval_fbo(TCGv dst, TCGv src, unsign= ed int fcc_offset) tcg_gen_xori_tl(dst, dst, 0x1); } =20 +static void finishing_insn(DisasContext *dc) +{ + /* + * From here, there is no future path through an unwinding exception. + * If the current insn cannot raise an exception, the computation of + * cpu_cond may be able to be elided. + */ + if (dc->cpu_cond_live) { + tcg_gen_discard_tl(cpu_cond); + dc->cpu_cond_live =3D false; + } +} + static void gen_generic_branch(DisasContext *dc) { TCGv npc0 =3D tcg_constant_tl(dc->jump_pc[0]); @@ -958,6 +972,7 @@ static void save_state(DisasContext *dc) =20 static void gen_exception(DisasContext *dc, int which) { + finishing_insn(dc); save_state(dc); gen_helper_raise_exception(tcg_env, tcg_constant_i32(which)); dc->base.is_jmp =3D DISAS_NORETURN; @@ -999,6 +1014,8 @@ static void gen_check_align(DisasContext *dc, TCGv add= r, int mask) =20 static void gen_mov_pc_npc(DisasContext *dc) { + finishing_insn(dc); + if (dc->npc & 3) { switch (dc->npc) { case JUMP_PC: @@ -2339,6 +2356,8 @@ static bool advance_pc(DisasContext *dc) { TCGLabel *l1; =20 + finishing_insn(dc); + if (dc->npc & 3) { switch (dc->npc) { case DYNAMIC_PC: @@ -2383,6 +2402,8 @@ static bool advance_jump_cond(DisasContext *dc, Disas= Compare *cmp, target_ulong dest =3D address_mask_i(dc, dc->pc + disp * 4); target_ulong npc; =20 + finishing_insn(dc); + if (cmp->cond =3D=3D TCG_COND_ALWAYS) { if (annul) { dc->pc =3D dest; @@ -2449,6 +2470,7 @@ static bool advance_jump_cond(DisasContext *dc, Disas= Compare *cmp, } else { tcg_gen_setcondi_tl(cmp->cond, cpu_cond, cmp->c1, cmp->c2); } + dc->cpu_cond_live =3D true; } } return true; @@ -2585,6 +2607,8 @@ static bool do_tcc(DisasContext *dc, int cond, int cc, tcg_gen_addi_i32(trap, trap, TT_TRAP); } =20 + finishing_insn(dc); + /* Trap always. */ if (cond =3D=3D 8) { save_state(dc); @@ -3201,6 +3225,7 @@ TRANS(WRSTICK_CMPR, 64, do_wr_special, a, supervisor(= dc), do_wrstick_cmpr) =20 static void do_wrpowerdown(DisasContext *dc, TCGv src) { + finishing_insn(dc); save_state(dc); gen_helper_power_down(tcg_env); } @@ -5080,6 +5105,8 @@ static void sparc_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cs) DisasDelayException *e, *e_next; bool may_lookup; =20 + finishing_insn(dc); + switch (dc->base.is_jmp) { case DISAS_NEXT: case DISAS_TOO_MANY: --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215381122100005 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/helper.h | 4 -- target/sparc/insns.decode | 4 +- target/sparc/helper.c | 24 --------- target/sparc/translate.c | 109 +++++++++++++++++++++++++++++++++----- 4 files changed, 97 insertions(+), 44 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index decd94c0d6..55eff66283 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -31,10 +31,6 @@ DEF_HELPER_FLAGS_3(udiv, TCG_CALL_NO_WG, i64, env, tl, t= l) DEF_HELPER_FLAGS_3(sdiv, TCG_CALL_NO_WG, i64, env, tl, tl) DEF_HELPER_3(taddcctv, tl, env, tl, tl) DEF_HELPER_3(tsubcctv, tl, env, tl, tl) -#ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_3(sdivx, TCG_CALL_NO_WG, s64, env, s64, s64) -DEF_HELPER_FLAGS_3(udivx, TCG_CALL_NO_WG, i64, env, i64, i64) -#endif #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, int, i32) DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 0552f1447d..52f54b87cc 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -182,8 +182,8 @@ UMUL 10 ..... 0.1010 ..... . ............. = @r_r_ri_cc SMUL 10 ..... 0.1011 ..... . ............. @r_r_ri_cc MULScc 10 ..... 100100 ..... . ............. @r_r_ri_cc1 =20 -UDIVX 10 ..... 001101 ..... . ............. @r_r_ri_cc0 -SDIVX 10 ..... 101101 ..... . ............. @r_r_ri_cc0 +UDIVX 10 ..... 001101 ..... . ............. @r_r_ri +SDIVX 10 ..... 101101 ..... . ............. @r_r_ri UDIV 10 ..... 0.1110 ..... . ............. @r_r_ri_cc SDIV 10 ..... 0.1111 ..... . ............. @r_r_ri_cc =20 diff --git a/target/sparc/helper.c b/target/sparc/helper.c index 6117e99b55..bd10b60e4b 100644 --- a/target/sparc/helper.c +++ b/target/sparc/helper.c @@ -129,30 +129,6 @@ uint64_t helper_sdiv(CPUSPARCState *env, target_ulong = a, target_ulong b) return (uint32_t)r; } =20 -#ifdef TARGET_SPARC64 -int64_t helper_sdivx(CPUSPARCState *env, int64_t a, int64_t b) -{ - if (b =3D=3D 0) { - /* Raise divide by zero trap. */ - cpu_raise_exception_ra(env, TT_DIV_ZERO, GETPC()); - } else if (b =3D=3D -1) { - /* Avoid overflow trap with i386 divide insn. */ - return -a; - } else { - return a / b; - } -} - -uint64_t helper_udivx(CPUSPARCState *env, uint64_t a, uint64_t b) -{ - if (b =3D=3D 0) { - /* Raise divide by zero trap. */ - cpu_raise_exception_ra(env, TT_DIV_ZERO, GETPC()); - } - return a / b; -} -#endif - target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1, target_ulong src2) { diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 3564c6032e..95cc4c71f4 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -51,12 +51,10 @@ # define gen_helper_restored(E) qemu_build_not_reached() # define gen_helper_retry(E) qemu_build_not_reached() # define gen_helper_saved(E) qemu_build_not_reached() -# define gen_helper_sdivx(D, E, A, B) qemu_build_not_reached() # define gen_helper_set_softint(E, S) qemu_build_not_reached() # define gen_helper_tick_get_count(D, E, T, C) qemu_build_not_reached() # define gen_helper_tick_set_count(P, S) qemu_build_not_reached() # define gen_helper_tick_set_limit(P, S) qemu_build_not_reached() -# define gen_helper_udivx(D, E, A, B) qemu_build_not_reached() # define gen_helper_wrccr(E, S) qemu_build_not_reached() # define gen_helper_wrcwp(E, S) qemu_build_not_reached() # define gen_helper_wrgl(E, S) qemu_build_not_reached() @@ -579,16 +577,6 @@ static void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) gen_op_multiply(dst, src1, src2, 1); } =20 -static void gen_op_udivx(TCGv dst, TCGv src1, TCGv src2) -{ - gen_helper_udivx(dst, tcg_env, src1, src2); -} - -static void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) -{ - gen_helper_sdivx(dst, tcg_env, src1, src2); -} - static void gen_op_udiv(TCGv dst, TCGv src1, TCGv src2) { #ifdef TARGET_SPARC64 @@ -3580,8 +3568,6 @@ TRANS(UMUL, MUL, do_logic, a, gen_op_umul, NULL) TRANS(SMUL, MUL, do_logic, a, gen_op_smul, NULL) TRANS(MULScc, ALL, do_arith, a, NULL, NULL, gen_op_mulscc) =20 -TRANS(UDIVX, 64, do_arith, a, gen_op_udivx, NULL, NULL) -TRANS(SDIVX, 64, do_arith, a, gen_op_sdivx, NULL, NULL) TRANS(UDIV, DIV, do_arith, a, gen_op_udiv, NULL, gen_op_udivcc) TRANS(SDIV, DIV, do_arith, a, gen_op_sdiv, NULL, gen_op_sdivcc) =20 @@ -3605,6 +3591,101 @@ static bool trans_OR(DisasContext *dc, arg_r_r_ri_c= c *a) return do_logic(dc, a, tcg_gen_or_tl, tcg_gen_ori_tl); } =20 +static bool trans_UDIVX(DisasContext *dc, arg_r_r_ri *a) +{ + TCGv dst, src1, src2; + + if (!avail_64(dc)) { + return false; + } + /* For simplicity, we under-decoded the rs2 form. */ + if (!a->imm && a->rs2_or_imm & ~0x1f) { + return false; + } + + if (unlikely(a->rs2_or_imm =3D=3D 0)) { + gen_exception(dc, TT_DIV_ZERO); + return true; + } + + if (a->imm) { + src2 =3D tcg_constant_tl(a->rs2_or_imm); + } else { + TCGLabel *lab; + + finishing_insn(dc); + flush_cond(dc); + + lab =3D delay_exception(dc, TT_DIV_ZERO); + src2 =3D cpu_regs[a->rs2_or_imm]; + tcg_gen_brcondi_tl(TCG_COND_EQ, src2, 0, lab); + } + + dst =3D gen_dest_gpr(dc, a->rd); + src1 =3D gen_load_gpr(dc, a->rs1); + + tcg_gen_divu_tl(dst, src1, src2); + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); +} + +static bool trans_SDIVX(DisasContext *dc, arg_r_r_ri *a) +{ + TCGv dst, src1, src2; + + if (!avail_64(dc)) { + return false; + } + /* For simplicity, we under-decoded the rs2 form. */ + if (!a->imm && a->rs2_or_imm & ~0x1f) { + return false; + } + + if (unlikely(a->rs2_or_imm =3D=3D 0)) { + gen_exception(dc, TT_DIV_ZERO); + return true; + } + + dst =3D gen_dest_gpr(dc, a->rd); + src1 =3D gen_load_gpr(dc, a->rs1); + + if (a->imm) { + if (unlikely(a->rs2_or_imm =3D=3D -1)) { + tcg_gen_neg_tl(dst, src1); + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); + } + src2 =3D tcg_constant_tl(a->rs2_or_imm); + } else { + TCGLabel *lab; + TCGv t1, t2; + + finishing_insn(dc); + flush_cond(dc); + + lab =3D delay_exception(dc, TT_DIV_ZERO); + src2 =3D cpu_regs[a->rs2_or_imm]; + tcg_gen_brcondi_tl(TCG_COND_EQ, src2, 0, lab); + + /* + * Need to avoid INT64_MIN / -1, which will trap on x86 host. + * Set SRC2 to 1 as a new divisor, to produce the correct result. + */ + t1 =3D tcg_temp_new(); + t2 =3D tcg_temp_new(); + tcg_gen_setcondi_tl(TCG_COND_EQ, t1, src1, (target_long)INT64_MIN); + tcg_gen_setcondi_tl(TCG_COND_EQ, t2, src2, -1); + tcg_gen_and_tl(t1, t1, t2); + tcg_gen_movcond_tl(TCG_COND_NE, t1, t1, tcg_constant_tl(0), + tcg_constant_tl(1), src2); + src2 =3D t1; + } + + tcg_gen_div_tl(dst, src1, src2); + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); +} + static bool gen_edge(DisasContext *dc, arg_r_r_r *a, int width, bool cc, bool left) { --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215310953100011 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +- target/sparc/translate.c | 67 +++++++++++++++++++++++++++++++-------- 2 files changed, 56 insertions(+), 14 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 52f54b87cc..2d26404cb2 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -184,7 +184,8 @@ MULScc 10 ..... 100100 ..... . ............. = @r_r_ri_cc1 =20 UDIVX 10 ..... 001101 ..... . ............. @r_r_ri SDIVX 10 ..... 101101 ..... . ............. @r_r_ri -UDIV 10 ..... 0.1110 ..... . ............. @r_r_ri_cc +UDIV 10 ..... 001110 ..... . ............. @r_r_ri +UDIVcc 10 ..... 011110 ..... . ............. @r_r_ri_cc1 SDIV 10 ..... 0.1111 ..... . ............. @r_r_ri_cc =20 TADDcc 10 ..... 100000 ..... . ............. @r_r_ri_cc1 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 95cc4c71f4..4b7d943bae 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -577,18 +577,6 @@ static void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) gen_op_multiply(dst, src1, src2, 1); } =20 -static void gen_op_udiv(TCGv dst, TCGv src1, TCGv src2) -{ -#ifdef TARGET_SPARC64 - gen_helper_udiv(dst, tcg_env, src1, src2); - tcg_gen_ext32u_tl(dst, dst); -#else - TCGv_i64 t64 =3D tcg_temp_new_i64(); - gen_helper_udiv(t64, tcg_env, src1, src2); - tcg_gen_trunc_i64_tl(dst, t64); -#endif -} - static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2) { #ifdef TARGET_SPARC64 @@ -3568,7 +3556,7 @@ TRANS(UMUL, MUL, do_logic, a, gen_op_umul, NULL) TRANS(SMUL, MUL, do_logic, a, gen_op_smul, NULL) TRANS(MULScc, ALL, do_arith, a, NULL, NULL, gen_op_mulscc) =20 -TRANS(UDIV, DIV, do_arith, a, gen_op_udiv, NULL, gen_op_udivcc) +TRANS(UDIVcc, DIV, do_arith, a, NULL, NULL, gen_op_udivcc) TRANS(SDIV, DIV, do_arith, a, gen_op_sdiv, NULL, gen_op_sdivcc) =20 /* TODO: Should have feature bit -- comes in with UltraSparc T2. */ @@ -3591,6 +3579,59 @@ static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc= *a) return do_logic(dc, a, tcg_gen_or_tl, tcg_gen_ori_tl); } =20 +static bool trans_UDIV(DisasContext *dc, arg_r_r_ri *a) +{ + TCGv_i64 t1, t2; + TCGv dst; + + if (!avail_DIV(dc)) { + return false; + } + /* For simplicity, we under-decoded the rs2 form. */ + if (!a->imm && a->rs2_or_imm & ~0x1f) { + return false; + } + + if (unlikely(a->rs2_or_imm =3D=3D 0)) { + gen_exception(dc, TT_DIV_ZERO); + return true; + } + + if (a->imm) { + t2 =3D tcg_constant_i64((uint32_t)a->rs2_or_imm); + } else { + TCGLabel *lab; + TCGv_i32 n2; + + finishing_insn(dc); + flush_cond(dc); + + n2 =3D tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(n2, cpu_regs[a->rs2_or_imm]); + + lab =3D delay_exception(dc, TT_DIV_ZERO); + tcg_gen_brcondi_i32(TCG_COND_EQ, n2, 0, lab); + + t2 =3D tcg_temp_new_i64(); +#ifdef TARGET_SPARC64 + tcg_gen_ext32u_i64(t2, cpu_regs[a->rs2_or_imm]); +#else + tcg_gen_extu_i32_i64(t2, cpu_regs[a->rs2_or_imm]); +#endif + } + + t1 =3D tcg_temp_new_i64(); + tcg_gen_concat_tl_i64(t1, gen_load_gpr(dc, a->rs1), cpu_y); + + tcg_gen_divu_i64(t1, t1, t2); + tcg_gen_umin_i64(t1, t1, tcg_constant_i64(UINT32_MAX)); + + dst =3D gen_dest_gpr(dc, a->rd); + tcg_gen_trunc_i64_tl(dst, t1); + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); +} + static bool trans_UDIVX(DisasContext *dc, arg_r_r_ri *a) { TCGv dst, src1, src2; --=20 2.34.1 From nobody Wed Nov 27 10:41:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699215309; cv=none; d=zohomail.com; s=zohoarc; b=iKrEcnPX0tM1vdIw+J/xO9xOFHmalGqsynPfW27TrC5xBagY4n+J4o3dhfZpPQhmvxWWSvZSnzjediu0pixgloEkyKUpqC9AdHB7fteUZy92jj+RhteiqwSbUSXwWYXUnjyFKfvdE88L249Yhmxf1yBxa+MwPTJ3wAtLCQA7xNc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699215309; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u23-20020a056a00099700b006884549adc8sm4359777pfg.29.2023.11.05.12.12.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Nov 2023 12:12:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699215161; x=1699819961; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zrjDe++U+z4NdbdSF1KpBffvXljDcXxDhfAmqkSfyJ4=; b=ccEvUWLJ1geJr8FNp3N3ZY0fx53DMyMV3bXR0nGsjHccfbQl7KYixdJc0WfANJGpUh MjgS+lQ6aey4mLAd8VONgdiE46Pl9DbWHRZY/x9KJQTce6DG7DicrZ2IS91U5dXhIkDk 90gf/g5iSsQjplgtLIhfr32XdSmA7BHlF92S7jHrB2mgaT8pddzP/gUHg92CsQaB6nGx NoBoNCmnAw37NomxFLk2TyfHrqilB9tZH486XSJsetYSbpV6CKUq7LX7qHULa8JapCCd 0AVsQ753ZKbr92Goo302lpBNXeqDvew4auRLWX7Gqt0QKhtYV3Gl2qFZ7h28JUaJinoS DQ3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699215161; x=1699819961; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zrjDe++U+z4NdbdSF1KpBffvXljDcXxDhfAmqkSfyJ4=; b=LAEvTriB4A314sPLtbLkDH9nm9N8Mh8abPFD4VPHKEQuWhamiSEXa8C6Nd3wreDHM5 JVKFfkVhV2Bq8YE/2WjHY2S//MPEVFFPZQSMz4nSUalLhL+Haj7RlUhYIuvvAw/3g250 E7RVrloN9L7x7RsuHUXsCAcfEKyxXH5d7hySGZO/7/PJpCyACecoyyeYS/QtdYmQHIYB dDvICvrAC26AakzaoPBUn9Z++89mORHc4ZydXj3sYawaUbyIVzoo14xwvCJLT+dkKqVe w6D6qO8WLzNJVoZzUOGOTcGSjAkWSYap9q2Y7mEazlHSTmuGZJjntJWHgbAFujuupaw4 dU5Q== X-Gm-Message-State: AOJu0YxIFikViViXsaZFB3UHKW2AiBlI4v4TOco2LGUoyvy3CO25LpDU E9dwO8TZ9xI5NvQlrR8r7e3PmS9fc5UmYV5NtTI= X-Google-Smtp-Source: AGHT+IHUdu0A4ylO7riK+BNYhVC0t/hIpsrLw4M7O8hCD/52tmLCci1hAlRKHVDRWTCLb3Giu0Bltw== X-Received: by 2002:a05:6808:5d0:b0:3b2:e0fa:61e4 with SMTP id d16-20020a05680805d000b003b2e0fa61e4mr30063879oij.25.1699215161530; Sun, 05 Nov 2023 12:12:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 21/21] target/sparc: Check for invalid cond in gen_compare_reg Date: Sun, 5 Nov 2023 12:12:22 -0800 Message-Id: <20231105201222.202395-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231105201222.202395-1-richard.henderson@linaro.org> References: <20231105201222.202395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699215311023100014 Content-Type: text/plain; charset="utf-8" Consolidate the test here; drop the "inverted logic". Fix MOVr and FMOVR, which were missing the invalid test. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 45 +++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 4b7d943bae..6fc333a6b8 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1189,24 +1189,29 @@ static void gen_fcompare(DisasCompare *cmp, unsigne= d int cc, unsigned int cond) } } =20 -// Inverted logic -static const TCGCond gen_tcg_cond_reg[8] =3D { - TCG_COND_NEVER, /* reserved */ - TCG_COND_NE, - TCG_COND_GT, - TCG_COND_GE, - TCG_COND_NEVER, /* reserved */ - TCG_COND_EQ, - TCG_COND_LE, - TCG_COND_LT, -}; - -static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src) +static bool gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src) { - cmp->cond =3D tcg_invert_cond(gen_tcg_cond_reg[cond]); + static const TCGCond cond_reg[4] =3D { + TCG_COND_NEVER, /* reserved */ + TCG_COND_EQ, + TCG_COND_LE, + TCG_COND_LT, + }; + TCGCond tcond; + + if ((cond & 3) =3D=3D 0) { + return false; + } + tcond =3D cond_reg[cond & 3]; + if (cond & 4) { + tcond =3D tcg_invert_cond(tcond); + } + + cmp->cond =3D tcond; cmp->c1 =3D tcg_temp_new(); cmp->c2 =3D 0; tcg_gen_mov_tl(cmp->c1, r_src); + return true; } =20 static void gen_op_clear_ieee_excp_and_FTT(void) @@ -2504,11 +2509,9 @@ static bool trans_BPr(DisasContext *dc, arg_BPr *a) if (!avail_64(dc)) { return false; } - if (gen_tcg_cond_reg[a->cond] =3D=3D TCG_COND_NEVER) { + if (!gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1))) { return false; } - - gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1)); return advance_jump_cond(dc, &cmp, a->a, a->i); } =20 @@ -4020,7 +4023,9 @@ static bool trans_MOVR(DisasContext *dc, arg_MOVR *a) if (src2 =3D=3D NULL) { return false; } - gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1)); + if (!gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1))) { + return false; + } return do_mov_cond(dc, &cmp, a->rd, src2); } =20 @@ -5007,6 +5012,9 @@ static bool do_fmovr(DisasContext *dc, arg_FMOVRs *a,= bool is_128, { DisasCompare cmp; =20 + if (!gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1))) { + return false; + } if (gen_trap_ifnofpu(dc)) { return true; } @@ -5015,7 +5023,6 @@ static bool do_fmovr(DisasContext *dc, arg_FMOVRs *a,= bool is_128, } =20 gen_op_clear_ieee_excp_and_FTT(); - gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1)); func(dc, &cmp, a->rd, a->rs2); return advance_pc(dc); } --=20 2.34.1