From nobody Wed Nov 27 14:39:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699033288; cv=none; d=zohomail.com; s=zohoarc; b=BE5iwiaLZtOLRFtjw/1wDOBPPQv6ZqeDwjau1ljOXdV8kaMfK6O2w7CWJytgiOJ7kkiF2swh9iT+yAY5U/z3f053dThWhsZJSvc3uFWFnfAYiK2NwG9FSF8F6YiuM4ffBjO4E3Ga0yY0ZKEWd4pq88OJQE+kPLEwjcGAW+8U5zA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699033288; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=QRppr0jtETveHLOhJJnBGFSQpLGg4IDz6r7ulJ5/PtI=; b=NYHD7uTbqa1T+y/wK0rQ1/TXdeNozQ0bOaI4+hGb2cRjDytKU4jV6UobL8c+lxXmMDLO0OODzvXT7a0zEji88lJvvbuQ1V27C9JtcuKlYYBSJnFOnkr3Y+EkqyzGYQ68onRFGHEwvHjzKO2Y6JRrfAiSDCVI3dn8fMDGg6vaWOo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699033288401700.1638704706417; Fri, 3 Nov 2023 10:41:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyy8y-0005Ur-Pb; Fri, 03 Nov 2023 13:39:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyy8P-0005FY-6R for qemu-devel@nongnu.org; Fri, 03 Nov 2023 13:39:05 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyy8G-0003WT-44 for qemu-devel@nongnu.org; Fri, 03 Nov 2023 13:38:59 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1cc3bc5df96so19363805ad.2 for ; Fri, 03 Nov 2023 10:38:55 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id c10-20020a170902c1ca00b001c0cb2aa2easm1628267plc.121.2023.11.03.10.38.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 10:38:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699033135; x=1699637935; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QRppr0jtETveHLOhJJnBGFSQpLGg4IDz6r7ulJ5/PtI=; b=SK1d2TE+bxllUmx1kSsJdzSfCWx7LWk3kbO7msBG7d6ijwCrhk9+zCyf0Khxoldc02 Ey+ftPJUIAxK+tOz7Cx1U20M3Og1yX3Or5QrJxqk8KkgHE3JFHSWhWWHigWQrVdqgiar dRytO9CL7bFfaWZYiKocMj8K09fErpISDTiQoeaHMUnGdkAMPzvkCW1JNnj3LzG/rbta 0Ek7PDuom9Sq/K01fWRMXFyNT7NveoqIRB234lksCNv9OCKxEomZbMnKKw5KoEC4i7aR IblcRBQ8BlnC5P/GRWXtjorxCDo0bAc4isjBKHpB7rd4Q9lLqT1zzlvlHcY0BNW2vel1 OKoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699033135; x=1699637935; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QRppr0jtETveHLOhJJnBGFSQpLGg4IDz6r7ulJ5/PtI=; b=kL+VcSmtxK7OWjS+cWNRDRlW8UFQRPDra9lT8tk+GHvKjg94sj5esgvGXAoEyKyx8p QR5/DVSbWNtPBbd/lB/oRsO5e1haEn3QjtMSaf7LPjURTAItS8hEwyzhmmSzVZr9g1VV nte25G9zZCXf4ND4fhbA2P30ecIDyh2vD5F0gGPceDdJNtZXVxYIJH7c2Y5cIDwKoocu 8dQxFpU+hMYNzTmhojcZN78FLv3lT/aRK14Mg7sIe4rKbu3Tr9adScHPKid9cN6S7Y4K CXhVnG86pCPrdOIBngt/pBjoSNMYoUSnRaEmoXV5yr2Izw4ebkLAJJof5HCuXngtV5ia iMFg== X-Gm-Message-State: AOJu0YzSQTKu1UlcUdHtjqpZaiaZEOPvPjRYxGFzcRHQJwEUENYoNnXa F1u2sWubKKjgoy3wXppdWifeN1a7G7L94MOg6Xs= X-Google-Smtp-Source: AGHT+IEvzDI+ys8/yLNogzX4K72kDoMe0uvQlcvNtGnzrELEZAm5kxVRqBRerK+VvExsCZW6AvZtiw== X-Received: by 2002:a17:902:e84a:b0:1cc:4a47:1fe5 with SMTP id t10-20020a170902e84a00b001cc4a471fe5mr15633706plg.59.1699033134770; Fri, 03 Nov 2023 10:38:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH 15/22] target/sparc: Introduce cpu_get_fsr, cpu_put_fsr Date: Fri, 3 Nov 2023 10:38:34 -0700 Message-Id: <20231103173841.33651-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103173841.33651-1-richard.henderson@linaro.org> References: <20231103173841.33651-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033288677100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/sparc/cpu.h | 4 +++- target/sparc/helper.h | 1 + linux-user/sparc/cpu_loop.c | 2 +- linux-user/sparc/signal.c | 14 +++++++++----- target/sparc/cpu.c | 5 +++-- target/sparc/fop_helper.c | 21 ++++++++++++++++++-- target/sparc/gdbstub.c | 8 ++++---- target/sparc/machine.c | 38 +++++++++++++++++++++++++++++++++++-- target/sparc/translate.c | 7 ++++++- 9 files changed, 82 insertions(+), 18 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 446b38f3df..33c7d31fef 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -605,7 +605,9 @@ void sparc_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data); =20 -/* cpu-exec.c */ +/* fop_helper.c */ +target_ulong cpu_get_fsr(CPUSPARCState *); +void cpu_put_fsr(CPUSPARCState *, target_ulong); =20 /* win_helper.c */ target_ulong cpu_get_psr(CPUSPARCState *env1); diff --git a/target/sparc/helper.h b/target/sparc/helper.h index f7aeb31169..cc8db50d75 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -36,6 +36,7 @@ DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, = int, i32) DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32) #endif DEF_HELPER_FLAGS_1(check_ieee_exceptions, TCG_CALL_NO_WG, tl, env) +DEF_HELPER_FLAGS_1(get_fsr, TCG_CALL_NO_WG_SE, tl, env) DEF_HELPER_FLAGS_2(set_fsr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_RWG, f32, env, f32) DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_RWG, f64, env, f64) diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index 3c1bde00dd..50424a54df 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -293,7 +293,7 @@ void cpu_loop (CPUSPARCState *env) case TT_FP_EXCP: { int code =3D TARGET_FPE_FLTUNK; - target_ulong fsr =3D env->fsr; + target_ulong fsr =3D cpu_get_fsr(env); =20 if ((fsr & FSR_FTT_MASK) =3D=3D FSR_FTT_IEEE_EXCP) { if (fsr & FSR_NVC) { diff --git a/linux-user/sparc/signal.c b/linux-user/sparc/signal.c index dfcae707e0..c2dc1000e2 100644 --- a/linux-user/sparc/signal.c +++ b/linux-user/sparc/signal.c @@ -199,20 +199,21 @@ static void save_fpu(struct target_siginfo_fpu *fpu, = CPUSPARCState *env) for (i =3D 0; i < 32; ++i) { __put_user(env->fpr[i].ll, &fpu->si_double_regs[i]); } - __put_user(env->fsr, &fpu->si_fsr); + __put_user(cpu_get_fsr(env), &fpu->si_fsr); __put_user(env->gsr, &fpu->si_gsr); __put_user(env->fprs, &fpu->si_fprs); #else for (i =3D 0; i < 16; ++i) { __put_user(env->fpr[i].ll, &fpu->si_double_regs[i]); } - __put_user(env->fsr, &fpu->si_fsr); + __put_user(cpu_get_fsr(env), &fpu->si_fsr); __put_user(0, &fpu->si_fpqdepth); #endif } =20 static void restore_fpu(struct target_siginfo_fpu *fpu, CPUSPARCState *env) { + target_ulong fsr; int i; =20 #ifdef TARGET_SPARC64 @@ -230,15 +231,16 @@ static void restore_fpu(struct target_siginfo_fpu *fp= u, CPUSPARCState *env) __get_user(env->fpr[i].ll, &fpu->si_double_regs[i]); } } - __get_user(env->fsr, &fpu->si_fsr); __get_user(env->gsr, &fpu->si_gsr); env->fprs |=3D fprs; #else for (i =3D 0; i < 16; ++i) { __get_user(env->fpr[i].ll, &fpu->si_double_regs[i]); } - __get_user(env->fsr, &fpu->si_fsr); #endif + + __get_user(fsr, &fpu->si_fsr); + cpu_put_fsr(env, fsr); } =20 #ifdef TARGET_ARCH_HAS_SETUP_FRAME @@ -662,6 +664,7 @@ void sparc64_set_context(CPUSPARCState *env) __get_user(fenab, &(fpup->mcfpu_enab)); if (fenab) { abi_ulong fprs; + abi_ulong fsr; =20 /* * We use the FPRS from the guest only in deciding whether @@ -690,7 +693,8 @@ void sparc64_set_context(CPUSPARCState *env) __get_user(env->fpr[i].ll, &(fpup->mcfpu_fregs.dregs[i])); } } - __get_user(env->fsr, &(fpup->mcfpu_fsr)); + __get_user(fsr, &(fpup->mcfpu_fsr)); + cpu_put_fsr(env, fsr); __get_user(env->gsr, &(fpup->mcfpu_gsr)); } unlock_user_struct(ucp, ucp_addr, 0); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index befa7fc4eb..69dfa1dd4e 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -670,7 +670,7 @@ static void sparc_cpu_dump_state(CPUState *cs, FILE *f,= int flags) env->cansave, env->canrestore, env->otherwin, env->wstate, env->cleanwin, env->nwindows - 1 - env->cwp); qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: %01= 6x\n", - env->fsr, env->y, env->fprs); + cpu_get_fsr(env), env->y, env->fprs); =20 #else qemu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env)); @@ -679,7 +679,7 @@ static void sparc_cpu_dump_state(CPUState *cs, FILE *f,= int flags) env->psrps ? 'P' : '-', env->psret ? 'E' : '-', env->wim); qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n", - env->fsr, env->y); + cpu_get_fsr(env), env->y); #endif qemu_fprintf(f, "\n"); } @@ -770,6 +770,7 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error= **errp) env->version |=3D env->def.maxtl << 8; env->version |=3D env->def.nwindows - 1; #endif + cpu_put_fsr(env, 0); =20 cpu_exec_realizefn(cs, &local_err); if (local_err !=3D NULL) { diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 7353a61237..70b38011d2 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -347,10 +347,22 @@ GEN_FCMP(fcmpeq_fcc3, float128, 26, 1); #undef GEN_FCMP_T #undef GEN_FCMP =20 -static void set_fsr(CPUSPARCState *env, target_ulong fsr) +target_ulong cpu_get_fsr(CPUSPARCState *env) +{ + return env->fsr; +} + +target_ulong helper_get_fsr(CPUSPARCState *env) +{ + return cpu_get_fsr(env); +} + +static void set_fsr_nonsplit(CPUSPARCState *env, target_ulong fsr) { int rnd_mode; =20 + env->fsr =3D fsr; + switch (fsr & FSR_RD_MASK) { case FSR_RD_NEAREST: rnd_mode =3D float_round_nearest_even; @@ -369,7 +381,12 @@ static void set_fsr(CPUSPARCState *env, target_ulong f= sr) set_float_rounding_mode(rnd_mode, &env->fp_status); } =20 +void cpu_put_fsr(CPUSPARCState *env, target_ulong fsr) +{ + set_fsr_nonsplit(env, fsr); +} + void helper_set_fsr(CPUSPARCState *env, target_ulong fsr) { - set_fsr(env, fsr); + set_fsr_nonsplit(env, fsr); } diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index a1c8fdc4d5..d1586b2392 100644 --- a/target/sparc/gdbstub.c +++ b/target/sparc/gdbstub.c @@ -64,7 +64,7 @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) case 69: return gdb_get_rega(mem_buf, env->npc); case 70: - return gdb_get_rega(mem_buf, env->fsr); + return gdb_get_rega(mem_buf, cpu_get_fsr(env)); case 71: return gdb_get_rega(mem_buf, 0); /* csr */ default: @@ -94,7 +94,7 @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) ((env->pstate & 0xfff) << 8) | cpu_get_cwp64(env)); case 83: - return gdb_get_regl(mem_buf, env->fsr); + return gdb_get_regl(mem_buf, cpu_get_fsr(env)); case 84: return gdb_get_regl(mem_buf, env->fprs); case 85: @@ -156,7 +156,7 @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t = *mem_buf, int n) env->npc =3D tmp; break; case 70: - env->fsr =3D tmp; + cpu_put_fsr(env, tmp); break; default: return 0; @@ -191,7 +191,7 @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t = *mem_buf, int n) cpu_put_cwp64(env, tmp & 0xff); break; case 83: - env->fsr =3D tmp; + cpu_put_fsr(env, tmp); break; case 84: env->fprs =3D tmp; diff --git a/target/sparc/machine.c b/target/sparc/machine.c index 44dfc07014..e46f15adb8 100644 --- a/target/sparc/machine.c +++ b/target/sparc/machine.c @@ -83,6 +83,34 @@ static const VMStateInfo vmstate_psr =3D { .put =3D put_psr, }; =20 +static int get_fsr(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field) +{ + SPARCCPU *cpu =3D opaque; + CPUSPARCState *env =3D &cpu->env; + target_ulong val =3D qemu_get_betl(f); + + cpu_put_fsr(env, val); + return 0; +} + +static int put_fsr(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field, JSONWriter *vmdesc) +{ + SPARCCPU *cpu =3D opaque; + CPUSPARCState *env =3D &cpu->env; + target_ulong val =3D cpu_get_fsr(env); + + qemu_put_betl(f, val); + return 0; +} + +static const VMStateInfo vmstate_fsr =3D { + .name =3D "fsr", + .get =3D get_fsr, + .put =3D put_fsr, +}; + #ifdef TARGET_SPARC64 static int get_xcc(QEMUFile *f, void *opaque, size_t size, const VMStateField *field) @@ -157,7 +185,6 @@ const VMStateDescription vmstate_sparc_cpu =3D { VMSTATE_UINTTL(env.npc, SPARCCPU), VMSTATE_UINTTL(env.y, SPARCCPU), { - .name =3D "psr", .version_id =3D 0, .size =3D sizeof(uint32_t), @@ -165,7 +192,14 @@ const VMStateDescription vmstate_sparc_cpu =3D { .flags =3D VMS_SINGLE, .offset =3D 0, }, - VMSTATE_UINTTL(env.fsr, SPARCCPU), + { + .name =3D "fsr", + .version_id =3D 0, + .size =3D sizeof(target_ulong), + .info =3D &vmstate_fsr, + .flags =3D VMS_SINGLE, + .offset =3D 0, + }, VMSTATE_UINTTL(env.tbr, SPARCCPU), VMSTATE_INT32(env.interrupt_index, SPARCCPU), VMSTATE_UINT32(env.pil_in, SPARCCPU), diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 99482df256..1d5f36dafc 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4417,13 +4417,18 @@ TRANS(LDXFSR, 64, do_ldfsr, a, MO_TEUQ, FSR_LDXFSR_= MASK, FSR_LDXFSR_OLDMASK) static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop) { TCGv addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + TCGv fsr; + if (addr =3D=3D NULL) { return false; } if (gen_trap_ifnofpu(dc)) { return true; } - tcg_gen_qemu_st_tl(cpu_fsr, addr, dc->mem_idx, mop | MO_ALIGN); + + fsr =3D tcg_temp_new(); + gen_helper_get_fsr(fsr, tcg_env); + tcg_gen_qemu_st_tl(fsr, addr, dc->mem_idx, mop | MO_ALIGN); return advance_pc(dc); } =20 --=20 2.34.1