From nobody Wed Nov 27 11:39:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699033180028316.74124918089626; Fri, 3 Nov 2023 10:39:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyy8K-0005E9-2F; Fri, 03 Nov 2023 13:39:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyy86-0005CX-Dh for qemu-devel@nongnu.org; Fri, 03 Nov 2023 13:38:51 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyy84-0003PM-S2 for qemu-devel@nongnu.org; Fri, 03 Nov 2023 13:38:46 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1cc1e1e74beso20903295ad.1 for ; Fri, 03 Nov 2023 10:38:44 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id c10-20020a170902c1ca00b001c0cb2aa2easm1628267plc.121.2023.11.03.10.38.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 10:38:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699033123; x=1699637923; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GM4yi8JDoIUa/uFJ4SLpCDL0xOthmcrPMIQLarXEt64=; b=LOP+h6t/F9JAstmc5JZPfBVOGA3KLBdqZHWbwQyRDVt/rmyxP0I6t8Z3ySBNMG6SUx ZMRNc7eA4S/fWO2EPUj/FOxP5Jpe8oQt4YSTLwMih7zobHURa/apo7s1UEy3vtBXn8i5 ojpNlE/QyqfGBdVdNkOF5AXi+e8TboBCGkox2zmiYGnlBwOy0wD0disYmg+a6CoAzuZt 6SQTfextLbCT1W+XI7VgVAw+j02jVB0RcxC1bVkvMJ0f87iX5EBuIlq21y4MyrnV2fjk G6LejZ596Ogq4QpfdpasPio5S6Vbmocij26aJaveIDercQsmbElmLK7EpnrbAfRC22RO i+dQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699033123; x=1699637923; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GM4yi8JDoIUa/uFJ4SLpCDL0xOthmcrPMIQLarXEt64=; b=bkCmFtmRtsOoTEw3qByFpiog7I8SNhtMboZXXhlUQuILMU9iKM4jkg2SAB8Zq57mts AJhzS81DD/4z5w07yFHbXfmtoO34pBnLlxglHmfMSnBfOIFrayKtObrNiWHPcTEP2uRu PA5NdGSdnZ1EkngI9UWOSgX8Mr0mlMQYURdC6QUMASJwE25777H3Rd2MB+6y4NoMhUoz iRvHxXkZhMmeDUq/G01vPBdnSaEI+AGygWiiDCscvslSTiljAZogggwjx8nZT3mcl0PC MGuvpygL5413bqqchxmgFOpZxY0sOdnFSwobBXxeynbM275QW58m0gsoBf0+XsBJZzm0 LnDg== X-Gm-Message-State: AOJu0YxBK6uIRqAEYvdsWRQO+Eno8svHdrEHaEKggeR+U/N8bGLBnbPH 7JsEC6WDZarR6sRih2epYGZEH+caNDHq6THIVXo= X-Google-Smtp-Source: AGHT+IHOk48jy14fX83WEuJxAdXjoEHD3tkjw89aTo9x+RRQ39gTPKMGR9SbUvR3dUaf6SJI5iWzEQ== X-Received: by 2002:a17:902:e744:b0:1cc:4e46:3e45 with SMTP id p4-20020a170902e74400b001cc4e463e45mr17924387plf.49.1699033123255; Fri, 03 Nov 2023 10:38:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH 01/22] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BCOPY Date: Fri, 3 Nov 2023 10:38:20 -0700 Message-Id: <20231103173841.33651-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103173841.33651-1-richard.henderson@linaro.org> References: <20231103173841.33651-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1699033182211100005 Content-Type: text/plain; charset="utf-8" Align the operation to the 32-byte cacheline. Use 2 pair of i128 instead of 8 pair of i32. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland --- target/sparc/translate.c | 43 +++++++++++++++++++++++----------------- 1 file changed, 25 insertions(+), 18 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 6fc333a6b8..5d55856a54 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1727,28 +1727,35 @@ static void gen_st_asi(DisasContext *dc, DisasASI *= da, TCGv src, TCGv addr) =20 case GET_ASI_BCOPY: assert(TARGET_LONG_BITS =3D=3D 32); - /* Copy 32 bytes from the address in SRC to ADDR. */ - /* ??? The original qemu code suggests 4-byte alignment, dropping - the low bits, but the only place I can see this used is in the - Linux kernel with 32 byte alignment, which would make more sense - as a cacheline-style operation. */ + /* + * Copy 32 bytes from the address in SRC to ADDR. + * + * From Ross RT625 hyperSPARC manual, section 4.6: + * "Block Copy and Block Fill will work only on cache line boundar= ies." + * + * It does not specify if an unaliged address is truncated or trap= ped. + * Previous qemu behaviour was to truncate to 4 byte alignment, wh= ich + * is obviously wrong. The only place I can see this used is in t= he + * Linux kernel which begins with page alignment, advancing by 32, + * so is always aligned. Assume truncation as the simpler option. + * + * Since the loads and stores are paired, allow the copy to happen + * in the host endianness. The copy need not be atomic. + */ { + MemOp mop =3D MO_128 | MO_ATOM_IFALIGN_PAIR; TCGv saddr =3D tcg_temp_new(); TCGv daddr =3D tcg_temp_new(); - TCGv four =3D tcg_constant_tl(4); - TCGv_i32 tmp =3D tcg_temp_new_i32(); - int i; + TCGv_i128 tmp =3D tcg_temp_new_i128(); =20 - tcg_gen_andi_tl(saddr, src, -4); - tcg_gen_andi_tl(daddr, addr, -4); - for (i =3D 0; i < 32; i +=3D 4) { - /* Since the loads and stores are paired, allow the - copy to happen in the host endianness. */ - tcg_gen_qemu_ld_i32(tmp, saddr, da->mem_idx, MO_UL); - tcg_gen_qemu_st_i32(tmp, daddr, da->mem_idx, MO_UL); - tcg_gen_add_tl(saddr, saddr, four); - tcg_gen_add_tl(daddr, daddr, four); - } + tcg_gen_andi_tl(saddr, src, -32); + tcg_gen_andi_tl(daddr, addr, -32); + tcg_gen_qemu_ld_i128(tmp, saddr, da->mem_idx, mop); + tcg_gen_qemu_st_i128(tmp, daddr, da->mem_idx, mop); + tcg_gen_addi_tl(saddr, saddr, 16); + tcg_gen_addi_tl(daddr, daddr, 16); + tcg_gen_qemu_ld_i128(tmp, saddr, da->mem_idx, mop); + tcg_gen_qemu_st_i128(tmp, daddr, da->mem_idx, mop); } break; =20 --=20 2.34.1 From nobody Wed Nov 27 11:39:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699033186032798.1555175835573; Fri, 3 Nov 2023 10:39:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyy8p-0005MK-UD; Fri, 03 Nov 2023 13:39:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyy87-0005Ca-Nn for qemu-devel@nongnu.org; Fri, 03 Nov 2023 13:38:51 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyy85-0003PV-LT for qemu-devel@nongnu.org; Fri, 03 Nov 2023 13:38:47 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1cc34c3420bso24362375ad.3 for ; Fri, 03 Nov 2023 10:38:45 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id c10-20020a170902c1ca00b001c0cb2aa2easm1628267plc.121.2023.11.03.10.38.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 10:38:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699033124; x=1699637924; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UnxzRLyh1Ovb0jBBq5BLp/EkhnbEZyAfrEjqimnt3ZM=; b=x/RnFx/IZ0gP6HY01H2UiE2ty/rHcv0DOt02Agam+WY8OkXdK8ZzRjQZLcGzwVjZam 7V1bzFwPWxvjPPBhig/NN6lgG3uWV7brjlofNTS+ugvfjFmzJHG6mNlhIkh1ZWWQJalT vbadnbFiel7mcpmLX6Qw7kLBfVHyx+MT3q63bZYbk1vmmAwiVlSCZ3ePVDFxpVhrHEYN m70hVnToLrUmgygsfh5uYtd+D/2waNc6j/imqbgedWb+DWTNlziu36Ax0677HyGXyEnU xW0LiZ+MpaMF8+gekhIH128cCLg7hup9hxt1S72XUYGyP9w6jNkkbre7kOQu9JyKOWci mOBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699033124; x=1699637924; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UnxzRLyh1Ovb0jBBq5BLp/EkhnbEZyAfrEjqimnt3ZM=; b=Jh3Megmy5qdJ5u6hA0mWMDLBUsD2asSm0Kp0WgcbUv2SywAQkLuimZvfAjjejs9ojQ pa5GZ7HTJcXHK1g17WPnWGOjbGpR2PfIpn8xZ4iCWLeJ4H0FsyoP9BMUg6WOd3LHE8oq /EQFr5dY1euEDTN7gLadSqt4pMt/MYXSo3BgGk/rWPs79xocpmMI8VFrbE8YnIGal8J0 lI119EjfRFq0c2yrNEcSfj0FQlGGxGGKz+6hZwvbfmhcqgCweVw6R4jf/Ys/falPTUmM Aa6hCjVf3kybuV00dnJuSXwHDbW6Ev0Q4kbXoVn+/yWyLGmVDXnOezvkzyvdTNfA/47B 0vDg== X-Gm-Message-State: AOJu0YzlSLbvlur2PAEixInqhwV34OVnqlEwl9TFDO47hPnovBc1ZfqT 83bxshT6qPCyR/PZ1RuTIGwWj8Tkj2OTo2GdRm0= X-Google-Smtp-Source: AGHT+IE0fbr/IquvHWA6L8JLVIyzFAD33QMtAZ0baPC7fHOHEBugHgy4g5kw7gXU5AR/3yY+atq/UQ== X-Received: by 2002:a17:903:246:b0:1cc:b09a:b811 with SMTP id j6-20020a170903024600b001ccb09ab811mr1113486plh.14.1699033124065; Fri, 03 Nov 2023 10:38:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH 02/22] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BFILL Date: Fri, 3 Nov 2023 10:38:21 -0700 Message-Id: <20231103173841.33651-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103173841.33651-1-richard.henderson@linaro.org> References: <20231103173841.33651-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1699033188127100003 Content-Type: text/plain; charset="utf-8" Align the operation to the 32-byte cacheline. Use 2 i128 instead of 4 i64. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland --- target/sparc/translate.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 5d55856a54..713ac5bbae 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2172,23 +2172,22 @@ static void gen_stda_asi(DisasContext *dc, DisasASI= *da, TCGv addr, int rd) =20 case GET_ASI_BFILL: assert(TARGET_LONG_BITS =3D=3D 32); - /* Store 32 bytes of T64 to ADDR. */ - /* ??? The original qemu code suggests 8-byte alignment, dropping - the low bits, but the only place I can see this used is in the - Linux kernel with 32 byte alignment, which would make more sense - as a cacheline-style operation. */ + /* + * Store 32 bytes of [rd:rd+1] to ADDR. + * See comments for GET_ASI_COPY above. + */ { - TCGv_i64 t64 =3D tcg_temp_new_i64(); - TCGv d_addr =3D tcg_temp_new(); - TCGv eight =3D tcg_constant_tl(8); - int i; + MemOp mop =3D MO_TE | MO_128 | MO_ATOM_IFALIGN_PAIR; + TCGv_i64 t8 =3D tcg_temp_new_i64(); + TCGv_i128 t16 =3D tcg_temp_new_i128(); + TCGv daddr =3D tcg_temp_new(); =20 - tcg_gen_concat_tl_i64(t64, lo, hi); - tcg_gen_andi_tl(d_addr, addr, -8); - for (i =3D 0; i < 32; i +=3D 8) { - tcg_gen_qemu_st_i64(t64, d_addr, da->mem_idx, da->memop); - tcg_gen_add_tl(d_addr, d_addr, eight); - } + tcg_gen_concat_tl_i64(t8, lo, hi); + tcg_gen_concat_i64_i128(t16, t8, t8); + tcg_gen_andi_tl(daddr, addr, -32); + tcg_gen_qemu_st_i128(t16, daddr, da->mem_idx, mop); + tcg_gen_addi_tl(daddr, daddr, 16); + tcg_gen_qemu_st_i128(t16, daddr, da->mem_idx, mop); } break; =20 --=20 2.34.1 From nobody Wed Nov 27 11:39:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699033365; cv=none; d=zohomail.com; s=zohoarc; b=dyO809FbRzMFsV80D+QbgN0AZZjJxtdkoAN+74I1xRnBn8LCCq0GKMH5pTqmMWtvF3MUBI566c//fUdYOM5D6lPBtNZ1P/ckVVQ+FqcBnPC/X8fa9uLinoa99ivFeYKMVyaXz4SUJVK+zE3UmOIC77uG8sKdQNt+vpWw2Z/sBe8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699033365; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=196HkJqsXRP9ZkYEyhMzcP9OWyBAk1XF71YuvBdwdd0=; b=LlSw79A85jFEZKWnhGOyZVX7cGs0uFNxS4mgpx1FMYewY43tdKoOSf0Ue9IPdgEb4cqZhdzW8QirZ6CItL6wpUxhOsx5m0d1y32QaIFa+84fHlnFcyIEqVw05NQk4GMpH8ssvcpdVRpL3J3DnZRra5AhY16yUtUbTsr1rcQ8j5s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699033365438218.857309207492; Fri, 3 Nov 2023 10:42:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyy8O-0005FX-NR; Fri, 03 Nov 2023 13:39:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyy89-0005Ck-HK for qemu-devel@nongnu.org; Fri, 03 Nov 2023 13:38:51 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyy87-0003Pb-SL for qemu-devel@nongnu.org; Fri, 03 Nov 2023 13:38:49 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1cc5b705769so20985665ad.0 for ; Fri, 03 Nov 2023 10:38:46 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id c10-20020a170902c1ca00b001c0cb2aa2easm1628267plc.121.2023.11.03.10.38.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 10:38:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699033125; x=1699637925; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=196HkJqsXRP9ZkYEyhMzcP9OWyBAk1XF71YuvBdwdd0=; b=FjPT1VJp+hpVgtR/RvxXX+utqgpZgNovtqMpic858z1TzRQEJ2SfYrb8B/Tzr+0CsH DMLkESlupLvwe81e4AIJoy855EOBN485yRKtCr7ZFyBTdL8huH1Mema1glN4vRlbpg+Q N4Z2IkgO/fmqEHnwwLyYbnq0qWvAc7SCbiEucz/ym0hxUGJ5sdeJF9zA9HHU+DOv1I7C c3k5QT83iO+ZcSX8ZiumJrS/8ol7CD5JKngr0aDD3t4xYTUeExYEDi6nLIVD66p+e9G2 q/6x8cYA50DmHUSUfkq4KpkGUthrsQalo3p6tET85HjQMXS0bsFy2OXANS72YeHpWqB9 A6Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699033125; x=1699637925; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=196HkJqsXRP9ZkYEyhMzcP9OWyBAk1XF71YuvBdwdd0=; b=fCZhmqQeLC3Rz93YRRGbJpV+wOA5/DZSRD+ykEaK5CuTpK3BRq/Ro34d5Uw8BQSDIY OCJv6fLkg4GPk2yN9fJ8Z9i4nwsblkPQFRWHkN0faY8wTpKP+kQ24vn38qfbsRu6NsBR h/KgrfadkWrKqsbruWAkvahZF8AQhYtKhR1knQCIHSsKlEsvTPMtBr02CLUShIXqryHN jKHNKtl09lHjAJN6c+jRclfT/CWwthrv55TLgZxMrXVJ6B3vGGRbDhydSYcEO3Pztwyx GYPUo+y2pTEAHuOdHd2zNT4yfbixCr3WbwH7pqxZ95PgVgsypLIir0Def/pOgABfaNgA AhXQ== X-Gm-Message-State: AOJu0YzCyLPiptWV2Kd1GJuReRF4VRhHEfBL5U9LCMUMku9rdE8eCGLH nhS2VkHxCDfDjw6wxGqQFZgWkVwSZuvUmn0eIkI= X-Google-Smtp-Source: AGHT+IH6yrNqrkfeqByyj2XfR7kiL+ByYcuxYAlENDC04C04z37HgLt3ecR0RDC9J1pUi5Spxi/EpA== X-Received: by 2002:a17:902:ec84:b0:1cc:4cb0:d273 with SMTP id x4-20020a170902ec8400b001cc4cb0d273mr18059350plg.56.1699033125170; Fri, 03 Nov 2023 10:38:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH 03/22] target/sparc: Remove gen_dest_fpr_F Date: Fri, 3 Nov 2023 10:38:22 -0700 Message-Id: <20231103173841.33651-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103173841.33651-1-richard.henderson@linaro.org> References: <20231103173841.33651-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033366976100005 Content-Type: text/plain; charset="utf-8" Replace with tcg_temp_new_i32. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/sparc/translate.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 713ac5bbae..cdc85be807 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -246,11 +246,6 @@ static void gen_store_fpr_F(DisasContext *dc, unsigned= int dst, TCGv_i32 v) gen_update_fprs_dirty(dc, dst); } =20 -static TCGv_i32 gen_dest_fpr_F(DisasContext *dc) -{ - return tcg_temp_new_i32(); -} - static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src) { src =3D DFPREG(src); @@ -1873,7 +1868,7 @@ static void gen_ldf_asi(DisasContext *dc, DisasASI *d= a, MemOp orig_size, memop |=3D MO_ALIGN_4; switch (size) { case MO_32: - d32 =3D gen_dest_fpr_F(dc); + d32 =3D tcg_temp_new_i32(); tcg_gen_qemu_ld_i32(d32, addr, da->mem_idx, memop); gen_store_fpr_F(dc, rd, d32); break; @@ -1938,7 +1933,7 @@ static void gen_ldf_asi(DisasContext *dc, DisasASI *d= a, MemOp orig_size, case MO_32: d64 =3D tcg_temp_new_i64(); gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop); - d32 =3D gen_dest_fpr_F(dc); + d32 =3D tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(d32, d64); gen_store_fpr_F(dc, rd, d32); break; @@ -2228,7 +2223,7 @@ static void gen_fmovs(DisasContext *dc, DisasCompare = *cmp, int rd, int rs) =20 s1 =3D gen_load_fpr_F(dc, rs); s2 =3D gen_load_fpr_F(dc, rd); - dst =3D gen_dest_fpr_F(dc); + dst =3D tcg_temp_new_i32(); zero =3D tcg_constant_i32(0); =20 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2); @@ -4497,7 +4492,7 @@ static bool do_fd(DisasContext *dc, arg_r_r *a, return true; } =20 - dst =3D gen_dest_fpr_F(dc); + dst =3D tcg_temp_new_i32(); src =3D gen_load_fpr_D(dc, a->rs); func(dst, src); gen_store_fpr_F(dc, a->rd, dst); @@ -4539,7 +4534,7 @@ static bool do_env_fd(DisasContext *dc, arg_r_r *a, } =20 gen_op_clear_ieee_excp_and_FTT(); - dst =3D gen_dest_fpr_F(dc); + dst =3D tcg_temp_new_i32(); src =3D gen_load_fpr_D(dc, a->rs); func(dst, tcg_env, src); gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); @@ -4697,7 +4692,7 @@ static bool do_env_fq(DisasContext *dc, arg_r_r *a, =20 gen_op_clear_ieee_excp_and_FTT(); gen_op_load_fpr_QT1(QFPREG(a->rs)); - dst =3D gen_dest_fpr_F(dc); + dst =3D tcg_temp_new_i32(); func(dst, tcg_env); gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_F(dc, a->rd, dst); --=20 2.34.1 From nobody Wed Nov 27 11:39:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699033214; cv=none; d=zohomail.com; s=zohoarc; b=bhIz12bEYaAbI6VU6JyMV4G8cQbHZ9KUCauxUSDFGvATOqnacvOvxcXNIUmy/BZy7s8i0GZp8muuw0Xf19TBlaI3s/K3xykC3SISS63N6dMQA9w/afBUvdQFh8v3lKl58buDj5imNWcUqX1THvEQDeWRG/zCVMDUOb2vbK2VUAE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699033214; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=OdTkIb+503ZSVLnr9dPJXCHToqhEgA9RiLgl/i9QaPQ=; b=Ntk22qt3OqroDdL7FYZhY2QvxSYPB/nYmFXhCvpMVMXAKRTA0TmDqf+lcqgVMsA55/buOwKEB6q/bWab13oFo73QIJvyRKnxER66T5cpYSldnkYPhSQte8hJIFvQr3lhPH+q0ZvTlPM7btlCc8s+w+W7vxHs4pctxO1wocqz3SY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699033214837749.2437378680463; Fri, 3 Nov 2023 10:40:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyy8p-0005ML-VK; Fri, 03 Nov 2023 13:39:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyy8B-0005Cp-U7 for qemu-devel@nongnu.org; Fri, 03 Nov 2023 13:38:52 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyy89-0003Po-Cb for qemu-devel@nongnu.org; Fri, 03 Nov 2023 13:38:50 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1cc37fb1310so19316105ad.1 for ; Fri, 03 Nov 2023 10:38:47 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id c10-20020a170902c1ca00b001c0cb2aa2easm1628267plc.121.2023.11.03.10.38.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 10:38:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699033126; x=1699637926; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OdTkIb+503ZSVLnr9dPJXCHToqhEgA9RiLgl/i9QaPQ=; b=uY621na4szzzrtYeV6PRQqi/KmYmRV3c88n74dWFqdrQMpWAfD7p7e24fBw56T+2EL uQXuIFSwsN9VLkMUHmffL5hMFI8yNvtHYkUprH6ZB4xFPI8xwbiuOH7VwEtBeJ9Y2ssY ZFp9JXtwWwWjjcCmIYCqFdYIRY56qHQdE9VqqFD2qoU5DR4IqTaHxqRoIT6iZm45kYN9 o+89w0CkfVeFtEqU8yJ7Vc0mRyHsWvld8aij5KAlqyeBg3PQL4fBtMH4OChOyIFAQzTC v6RTJWxLJ01QLhX6ja/76WBu9d4xIzbASci1ge/45ef7RPNI1/tGMGhdCLwjxAOEb9lo 731w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699033126; x=1699637926; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OdTkIb+503ZSVLnr9dPJXCHToqhEgA9RiLgl/i9QaPQ=; b=Mj1cu6E7M5WPsp87Or/1Aibabkldmp5Myq0nXaXjN+Tg5mT/YDrxa3EXDyPxS0j88J hu/LPOe0evw44XW1floU7RKPr1HD5F4IpCslQyDdz3i1jfjRK/Qk+l7HSQykULO2GMyE UktcBAx7UjILREZDyeyh2G4SNjdzwLxJywW5vzGG9lZmsURaa++EbRuD1EbXH+8/07ie bhiEPQEBeiBWKotStNAYbEKpTx1DMyxIvvTS6Nl57qytVraUHRgGrOLVuPDS9LCcVk1U Pvz14w82j6yXrkuWFBt/fvJ1QrnESDwbDPpNlbZHH7G4OgmyWFkpaOM9nD6bEenrJ1Xy 2hJw== X-Gm-Message-State: AOJu0Yyyurcf0hDm+zTlNEgdWreDhn9X2XwWBXc6lhwJeA6w1JQhPWOG 0fJqLb0t38Ml0lA9IDAO7QID+nS2qBCwqrHiq6U= X-Google-Smtp-Source: AGHT+IFn/DGM943zafMLx7gST/jiSa3cSoCvBYxDmjgbc1otBg8ND36/eMEK0FF8mERpUacqAVy08g== X-Received: by 2002:a17:902:6b48:b0:1c5:8401:356c with SMTP id g8-20020a1709026b4800b001c58401356cmr17866119plt.62.1699033125929; Fri, 03 Nov 2023 10:38:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH 04/22] target/sparc: Introduce gen_{load,store}_fpr_Q Date: Fri, 3 Nov 2023 10:38:23 -0700 Message-Id: <20231103173841.33651-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103173841.33651-1-richard.henderson@linaro.org> References: <20231103173841.33651-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033216456100003 Content-Type: text/plain; charset="utf-8" Use them for trans_FMOVq. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/sparc/translate.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index cdc85be807..0e494d3ebd 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -264,6 +264,22 @@ static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsig= ned int dst) return cpu_fpr[DFPREG(dst) / 2]; } =20 +static TCGv_i128 gen_load_fpr_Q(DisasContext *dc, unsigned int src) +{ + TCGv_i128 ret =3D tcg_temp_new_i128(); + + src =3D QFPREG(src); + tcg_gen_concat_i64_i128(ret, cpu_fpr[src / 2 + 1], cpu_fpr[src / 2]); + return ret; +} + +static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst, TCGv_i128 = v) +{ + dst =3D DFPREG(dst); + tcg_gen_extr_i128_i64(cpu_fpr[dst / 2 + 1], cpu_fpr[dst / 2], v); + gen_update_fprs_dirty(dc, dst); +} + static void gen_op_load_fpr_QT0(unsigned int src) { tcg_gen_st_i64(cpu_fpr[src / 2], tcg_env, offsetof(CPUSPARCState, qt0)= + @@ -4615,7 +4631,7 @@ TRANS(FsTOx, 64, do_env_df, a, gen_helper_fstox) =20 static bool trans_FMOVq(DisasContext *dc, arg_FMOVq *a) { - int rd, rs; + TCGv_i128 t; =20 if (!avail_64(dc)) { return false; @@ -4628,11 +4644,8 @@ static bool trans_FMOVq(DisasContext *dc, arg_FMOVq = *a) } =20 gen_op_clear_ieee_excp_and_FTT(); - rd =3D QFPREG(a->rd); - rs =3D QFPREG(a->rs); - tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]); - tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]); - gen_update_fprs_dirty(dc, rd); + t =3D gen_load_fpr_Q(dc, a->rs); + gen_store_fpr_Q(dc, a->rd, t); return advance_pc(dc); } =20 --=20 2.34.1 From nobody Wed Nov 27 11:39:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699033300; cv=none; d=zohomail.com; s=zohoarc; b=jhmkp4zr6fyrjtOppzCeRbNn4YUuz+axRCj/N0etl03vNhVEXOn/d0Y7far4lXxiWw5YbJyrpT/5RipTnHJsNta56YvDzbA6gYghrZgAczghIK2t044naZ79bhdK14XNU7FnQz76TWM44e01tI9xLwTDmX8bc1bbQyDkZGa8wig= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699033300; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nwGB6UqbrFaBrfPKz5OCrw7rrJ0PEN4BU/Qe8d0GrsU=; b=MR3nYA7KhDKJjiVECEepBEqWgopni5/4bPybvpD7+YQwMHghOYWLicx71NshPwzlAFM8EnEs31hIZUlfjcoBhF3NRpuLxCsyUrhXSmIvd0vzCT8gJXH6wtLOvHmmuJ8/dgVuHOoXh/hSDR3OthRzOACpuCYKzQ5xcFnDzcIwves= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699033300960301.62738328964224; Fri, 3 Nov 2023 10:41:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyy8v-0005Oh-Hi; Fri, 03 Nov 2023 13:39:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyy8I-0005El-CN for qemu-devel@nongnu.org; Fri, 03 Nov 2023 13:39:00 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyy88-0003QO-Ux for qemu-devel@nongnu.org; Fri, 03 Nov 2023 13:38:56 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1cc9784dbc1so12678485ad.2 for ; Fri, 03 Nov 2023 10:38:48 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id c10-20020a170902c1ca00b001c0cb2aa2easm1628267plc.121.2023.11.03.10.38.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 10:38:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699033127; x=1699637927; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nwGB6UqbrFaBrfPKz5OCrw7rrJ0PEN4BU/Qe8d0GrsU=; b=puJkXJRb1xU6U5EYWWWgdmCrLjphfURcjWO3L3/YYmoQDC7dkU2FjZLpOQaXRoN0dT 0PCksuV4z/4fIPEHVAeKgyZMoCrrdcZX8RoVqYTsObUcG19iYFdhZu2gsGbfqi5ROD/f eIbV411/iCoiRoENd8p5qCszgeUmEkKQ94ydwGI+8ZUVB1Pj/EgITY/N2PqTZKheVGYG jR9O4/sAFdHNVl0IvOwI7znguFEmGLQYa0c2nKVSyIVDmP7PcAYEkK5KHe8MFDak+9ck zEH0v9jU2GVHvs616RhFqLjPXSWVJOXzhIIrcornpfY98rbGrwqbO7RIZ8KibnYqr6Qo JOtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699033127; x=1699637927; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nwGB6UqbrFaBrfPKz5OCrw7rrJ0PEN4BU/Qe8d0GrsU=; b=SRrSKO/rhBBd4uuiVJJ4zkdFUAmmhEkDMyjh+4Kr85GDcRbJVg0B90rdGsbENGktW2 lWVDTi89vqSMKigMhf8mO2I8lbQ8VgmZ7VQIFJ1YygK2oFV11VPKot6791xdOjseFcJR hao1H3G7xdeO6/hq6nnEm1vu9lnoO6rP4XN22yFE0nDWY0YdbAw8CYkVIvDOMGHjYDS3 W/4LiwSBRjUnZ6Y30O4GX3RON4Eh8uWX+2IIBvvCLVWXV8XRZzKI7Ipc8cjHtJzgwU/Y pN7l0nNycX4Cyx46zIaDI7kj/CrFG9uCd7LtiQLJzOI9VsMVa9u5xBUUXgoX//pcYkPZ 9Osg== X-Gm-Message-State: AOJu0YwY0Lh5Kn7x0xtTK1S5kdcrD3QOAYbQ/SpNhAoNKBqNgbtREtJe 2x2mOM12ZqVLVDHek6urQrjrSw7wyQx6yTEZPiA= X-Google-Smtp-Source: AGHT+IFQ9f4yrJr44TkIrMidbxZzTqECWlmvras9W09gnyF8dE6rC8oPhVx0Dm5BOkWEdBhWiq8ydw== X-Received: by 2002:a17:902:d4c3:b0:1cc:6ab6:df26 with SMTP id o3-20020a170902d4c300b001cc6ab6df26mr12688510plg.49.1699033126976; Fri, 03 Nov 2023 10:38:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH 05/22] target/sparc: Inline FNEG, FABS Date: Fri, 3 Nov 2023 10:38:24 -0700 Message-Id: <20231103173841.33651-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103173841.33651-1-richard.henderson@linaro.org> References: <20231103173841.33651-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033302799100003 Content-Type: text/plain; charset="utf-8" These are simple bit manipulation insns. Begin using i128 for float128. Implement FMOVq with do_qq. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 6 ---- target/sparc/fop_helper.c | 34 --------------------- target/sparc/translate.c | 62 +++++++++++++++++++-------------------- 3 files changed, 30 insertions(+), 72 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 55eff66283..74a1575d21 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -37,7 +37,6 @@ DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl,= i64, int, i32) #endif DEF_HELPER_FLAGS_1(check_ieee_exceptions, TCG_CALL_NO_WG, tl, env) DEF_HELPER_FLAGS_2(set_fsr, TCG_CALL_NO_RWG, void, env, tl) -DEF_HELPER_FLAGS_1(fabss, TCG_CALL_NO_RWG_SE, f32, f32) DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_RWG, f32, env, f32) DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_RWG, f64, env, f64) DEF_HELPER_FLAGS_3(fcmps, TCG_CALL_NO_WG, tl, env, f32, f32) @@ -48,7 +47,6 @@ DEF_HELPER_FLAGS_1(fsqrtq, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_1(fcmpq, TCG_CALL_NO_WG, tl, env) DEF_HELPER_FLAGS_1(fcmpeq, TCG_CALL_NO_WG, tl, env) #ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_1(fabsd, TCG_CALL_NO_RWG_SE, f64, f64) DEF_HELPER_FLAGS_3(fcmps_fcc1, TCG_CALL_NO_WG, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmps_fcc2, TCG_CALL_NO_WG, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmps_fcc3, TCG_CALL_NO_WG, tl, env, f32, f32) @@ -61,7 +59,6 @@ DEF_HELPER_FLAGS_3(fcmpes_fcc3, TCG_CALL_NO_WG, tl, env, = f32, f32) DEF_HELPER_FLAGS_3(fcmped_fcc1, TCG_CALL_NO_WG, tl, env, f64, f64) DEF_HELPER_FLAGS_3(fcmped_fcc2, TCG_CALL_NO_WG, tl, env, f64, f64) DEF_HELPER_FLAGS_3(fcmped_fcc3, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_1(fabsq, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_1(fcmpq_fcc1, TCG_CALL_NO_WG, tl, env) DEF_HELPER_FLAGS_1(fcmpq_fcc2, TCG_CALL_NO_WG, tl, env) DEF_HELPER_FLAGS_1(fcmpq_fcc3, TCG_CALL_NO_WG, tl, env) @@ -90,15 +87,12 @@ DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_RWG, f32, env, f3= 2, f32) DEF_HELPER_FLAGS_3(fsmuld, TCG_CALL_NO_RWG, f64, env, f32, f32) DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_RWG, void, env, f64, f64) =20 -DEF_HELPER_FLAGS_1(fnegs, TCG_CALL_NO_RWG_SE, f32, f32) DEF_HELPER_FLAGS_2(fitod, TCG_CALL_NO_RWG_SE, f64, env, s32) DEF_HELPER_FLAGS_2(fitoq, TCG_CALL_NO_RWG, void, env, s32) =20 DEF_HELPER_FLAGS_2(fitos, TCG_CALL_NO_RWG, f32, env, s32) =20 #ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_1(fnegd, TCG_CALL_NO_RWG_SE, f64, f64) -DEF_HELPER_FLAGS_1(fnegq, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(fxtos, TCG_CALL_NO_RWG, f32, env, s64) DEF_HELPER_FLAGS_2(fxtod, TCG_CALL_NO_RWG, f64, env, s64) DEF_HELPER_FLAGS_2(fxtoq, TCG_CALL_NO_RWG, void, env, s64) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 0f8aa3abcd..d6fb769769 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -114,23 +114,6 @@ void helper_fdmulq(CPUSPARCState *env, float64 src1, f= loat64 src2) &env->fp_status); } =20 -float32 helper_fnegs(float32 src) -{ - return float32_chs(src); -} - -#ifdef TARGET_SPARC64 -float64 helper_fnegd(float64 src) -{ - return float64_chs(src); -} - -F_HELPER(neg, q) -{ - QT0 =3D float128_chs(QT1); -} -#endif - /* Integer to float conversion. */ float32 helper_fitos(CPUSPARCState *env, int32_t src) { @@ -229,23 +212,6 @@ int64_t helper_fqtox(CPUSPARCState *env) } #endif =20 -float32 helper_fabss(float32 src) -{ - return float32_abs(src); -} - -#ifdef TARGET_SPARC64 -float64 helper_fabsd(float64 src) -{ - return float64_abs(src); -} - -void helper_fabsq(CPUSPARCState *env) -{ - QT0 =3D float128_abs(QT1); -} -#endif - float32 helper_fsqrts(CPUSPARCState *env, float32 src) { return float32_sqrt(src, &env->fp_status); diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 0e494d3ebd..254f185b83 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -43,9 +43,7 @@ #else # define gen_helper_clear_softint(E, S) qemu_build_not_reached() # define gen_helper_done(E) qemu_build_not_reached() -# define gen_helper_fabsd(D, S) qemu_build_not_reached() # define gen_helper_flushw(E) qemu_build_not_reached() -# define gen_helper_fnegd(D, S) qemu_build_not_reached() # define gen_helper_rdccr(D, E) qemu_build_not_reached() # define gen_helper_rdcwp(D, E) qemu_build_not_reached() # define gen_helper_restored(E) qemu_build_not_reached() @@ -61,7 +59,6 @@ # define gen_helper_write_softint(E, S) qemu_build_not_reached() # define gen_helper_wrpil(E, S) qemu_build_not_reached() # define gen_helper_wrpstate(E, S) qemu_build_not_reached() -# define gen_helper_fabsq ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpeq16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpeq32 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpgt16 ({ qemu_build_not_reached(); NULL= ; }) @@ -79,7 +76,6 @@ # define gen_helper_fmul8x16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fmuld8sux16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fmuld8ulx16 ({ qemu_build_not_reached(); NULL= ; }) -# define gen_helper_fnegq ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fpmerge ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fqtox ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fstox ({ qemu_build_not_reached(); NULL= ; }) @@ -1239,13 +1235,13 @@ static void gen_op_fmovs(TCGv_i32 dst, TCGv_i32 src) static void gen_op_fnegs(TCGv_i32 dst, TCGv_i32 src) { gen_op_clear_ieee_excp_and_FTT(); - gen_helper_fnegs(dst, src); + tcg_gen_xori_i32(dst, src, 1u << 31); } =20 static void gen_op_fabss(TCGv_i32 dst, TCGv_i32 src) { gen_op_clear_ieee_excp_and_FTT(); - gen_helper_fabss(dst, src); + tcg_gen_andi_i32(dst, src, ~(1u << 31)); } =20 static void gen_op_fmovd(TCGv_i64 dst, TCGv_i64 src) @@ -1257,13 +1253,33 @@ static void gen_op_fmovd(TCGv_i64 dst, TCGv_i64 src) static void gen_op_fnegd(TCGv_i64 dst, TCGv_i64 src) { gen_op_clear_ieee_excp_and_FTT(); - gen_helper_fnegd(dst, src); + tcg_gen_xori_i64(dst, src, 1ull << 63); } =20 static void gen_op_fabsd(TCGv_i64 dst, TCGv_i64 src) { gen_op_clear_ieee_excp_and_FTT(); - gen_helper_fabsd(dst, src); + tcg_gen_andi_i64(dst, src, ~(1ull << 63)); +} + +static void gen_op_fnegq(TCGv_i128 dst, TCGv_i128 src) +{ + TCGv_i64 l =3D tcg_temp_new_i64(); + TCGv_i64 h =3D tcg_temp_new_i64(); + + tcg_gen_extr_i128_i64(l, h, src); + tcg_gen_xori_i64(h, h, 1ull << 63); + tcg_gen_concat_i64_i128(dst, l, h); +} + +static void gen_op_fabsq(TCGv_i128 dst, TCGv_i128 src) +{ + TCGv_i64 l =3D tcg_temp_new_i64(); + TCGv_i64 h =3D tcg_temp_new_i64(); + + tcg_gen_extr_i128_i64(l, h, src); + tcg_gen_andi_i64(h, h, ~(1ull << 63)); + tcg_gen_concat_i64_i128(dst, l, h); } =20 #ifdef TARGET_SPARC64 @@ -4629,13 +4645,11 @@ TRANS(FiTOd, ALL, do_env_df, a, gen_helper_fitod) TRANS(FsTOd, ALL, do_env_df, a, gen_helper_fstod) TRANS(FsTOx, 64, do_env_df, a, gen_helper_fstox) =20 -static bool trans_FMOVq(DisasContext *dc, arg_FMOVq *a) +static bool do_qq(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i128, TCGv_i128)) { TCGv_i128 t; =20 - if (!avail_64(dc)) { - return false; - } if (gen_trap_ifnofpu(dc)) { return true; } @@ -4645,30 +4659,14 @@ static bool trans_FMOVq(DisasContext *dc, arg_FMOVq= *a) =20 gen_op_clear_ieee_excp_and_FTT(); t =3D gen_load_fpr_Q(dc, a->rs); + func(t, t); gen_store_fpr_Q(dc, a->rd, t); return advance_pc(dc); } =20 -static bool do_qq(DisasContext *dc, arg_r_r *a, - void (*func)(TCGv_env)) -{ - if (gen_trap_ifnofpu(dc)) { - return true; - } - if (gen_trap_float128(dc)) { - return true; - } - - gen_op_clear_ieee_excp_and_FTT(); - gen_op_load_fpr_QT1(QFPREG(a->rs)); - func(tcg_env); - gen_op_store_QT0_fpr(QFPREG(a->rd)); - gen_update_fprs_dirty(dc, QFPREG(a->rd)); - return advance_pc(dc); -} - -TRANS(FNEGq, 64, do_qq, a, gen_helper_fnegq) -TRANS(FABSq, 64, do_qq, a, gen_helper_fabsq) +TRANS(FMOVq, 64, do_qq, a, tcg_gen_mov_i128) +TRANS(FNEGq, 64, do_qq, a, gen_op_fnegq) +TRANS(FABSq, 64, do_qq, a, gen_op_fabsq) =20 static bool do_env_qq(DisasContext *dc, arg_r_r *a, void (*func)(TCGv_env)) --=20 2.34.1 From nobody Wed Nov 27 11:39:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699033296; cv=none; d=zohomail.com; s=zohoarc; b=WRpuur7WB76AczjWVvqJ4u9Liq2snIjwBRtqHL31Ff1i3Wd5SAe2m1diKT/ZQiaHeOOEBMxbCt32PiYRUpyA32Ou4OmEzr/mNUunKYX9BHVs5HN72mZZeYboLXDD5iK+65Wo6a0njd/SC49bIJAPqhsz2/EGbBBjkttX/qlGQcE= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033296774100008 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 2 +- target/sparc/fop_helper.c | 26 ++++++++++++++++++++++++-- target/sparc/translate.c | 12 +++++++----- 3 files changed, 32 insertions(+), 8 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 74a1575d21..eea2fa570c 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -43,7 +43,7 @@ DEF_HELPER_FLAGS_3(fcmps, TCG_CALL_NO_WG, tl, env, f32, f= 32) DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, tl, env, f64, f64) DEF_HELPER_FLAGS_3(fcmpes, TCG_CALL_NO_WG, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_1(fsqrtq, TCG_CALL_NO_RWG, void, env) +DEF_HELPER_FLAGS_2(fsqrtq, TCG_CALL_NO_RWG, i128, env, i128) DEF_HELPER_FLAGS_1(fcmpq, TCG_CALL_NO_WG, tl, env) DEF_HELPER_FLAGS_1(fcmpeq, TCG_CALL_NO_WG, tl, env) #ifdef TARGET_SPARC64 diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index d6fb769769..d639e50965 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -26,6 +26,28 @@ #define QT0 (env->qt0) #define QT1 (env->qt1) =20 +static inline float128 f128_in(Int128 i) +{ + union { + Int128 i; + float128 f; + } u; + + u.i =3D i; + return u.f; +} + +static inline Int128 f128_ret(float128 f) +{ + union { + Int128 i; + float128 f; + } u; + + u.f =3D f; + return u.i; +} + static target_ulong do_check_ieee_exceptions(CPUSPARCState *env, uintptr_t= ra) { target_ulong status =3D get_float_exception_flags(&env->fp_status); @@ -222,9 +244,9 @@ float64 helper_fsqrtd(CPUSPARCState *env, float64 src) return float64_sqrt(src, &env->fp_status); } =20 -void helper_fsqrtq(CPUSPARCState *env) +Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) { - QT0 =3D float128_sqrt(QT1, &env->fp_status); + return f128_ret(float128_sqrt(f128_in(src), &env->fp_status)); } =20 #define GEN_FCMP(name, size, reg1, reg2, FS, E) \ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 254f185b83..6c08bf909e 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4669,8 +4669,10 @@ TRANS(FNEGq, 64, do_qq, a, gen_op_fnegq) TRANS(FABSq, 64, do_qq, a, gen_op_fabsq) =20 static bool do_env_qq(DisasContext *dc, arg_r_r *a, - void (*func)(TCGv_env)) + void (*func)(TCGv_i128, TCGv_env, TCGv_i128)) { + TCGv_i128 t; + if (gen_trap_ifnofpu(dc)) { return true; } @@ -4679,11 +4681,11 @@ static bool do_env_qq(DisasContext *dc, arg_r_r *a, } =20 gen_op_clear_ieee_excp_and_FTT(); - gen_op_load_fpr_QT1(QFPREG(a->rs)); - func(tcg_env); + + t =3D gen_load_fpr_Q(dc, a->rs); + func(t, tcg_env, t); gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - gen_op_store_QT0_fpr(QFPREG(a->rd)); - gen_update_fprs_dirty(dc, QFPREG(a->rd)); + gen_store_fpr_Q(dc, a->rd, t); return advance_pc(dc); } =20 --=20 2.34.1 From nobody Wed Nov 27 11:39:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699033254; cv=none; d=zohomail.com; s=zohoarc; b=S37uBQcNkr4+U8VIPYD+8vxxhpDqy6QO64JieXN+2L2Z/N7EKx4x84GpGef2/67OCx9h0R/ThxTBs23t5tlYksJUQ110FMhE288eydpKZx0K2gPXMNyOWLVav+ZbNn1TMTWGh6tqMesnOUDBhJVRZ8Cc/FHhVMGfmTGNr5AbV24= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033254620100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 12 +++++------- target/sparc/fop_helper.c | 29 ++++++++++++++--------------- target/sparc/translate.c | 13 +++++++------ 3 files changed, 26 insertions(+), 28 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index eea2fa570c..0a030fc908 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -67,17 +67,16 @@ DEF_HELPER_FLAGS_1(fcmpeq_fcc2, TCG_CALL_NO_WG, tl, env) DEF_HELPER_FLAGS_1(fcmpeq_fcc3, TCG_CALL_NO_WG, tl, env) #endif DEF_HELPER_2(raise_exception, noreturn, env, int) -#define F_HELPER_0_1(name) \ - DEF_HELPER_FLAGS_1(f ## name, TCG_CALL_NO_RWG, void, env) =20 DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_RWG, f64, env, f64, f64) DEF_HELPER_FLAGS_3(fsubd, TCG_CALL_NO_RWG, f64, env, f64, f64) DEF_HELPER_FLAGS_3(fmuld, TCG_CALL_NO_RWG, f64, env, f64, f64) DEF_HELPER_FLAGS_3(fdivd, TCG_CALL_NO_RWG, f64, env, f64, f64) -F_HELPER_0_1(addq) -F_HELPER_0_1(subq) -F_HELPER_0_1(mulq) -F_HELPER_0_1(divq) + +DEF_HELPER_FLAGS_3(faddq, TCG_CALL_NO_RWG, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(fsubq, TCG_CALL_NO_RWG, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(fmulq, TCG_CALL_NO_RWG, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(fdivq, TCG_CALL_NO_RWG, i128, env, i128, i128) =20 DEF_HELPER_FLAGS_3(fadds, TCG_CALL_NO_RWG, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fsubs, TCG_CALL_NO_RWG, f32, env, f32, f32) @@ -135,6 +134,5 @@ VIS_CMPHELPER(cmpeq) VIS_CMPHELPER(cmple) VIS_CMPHELPER(cmpne) #endif -#undef F_HELPER_0_1 #undef VIS_HELPER #undef VIS_CMPHELPER diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index d639e50965..ceb64d802f 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -98,22 +98,22 @@ target_ulong helper_check_ieee_exceptions(CPUSPARCState= *env) return do_check_ieee_exceptions(env, GETPC()); } =20 -#define F_HELPER(name, p) void helper_f##name##p(CPUSPARCState *env) - -#define F_BINOP(name) \ +#define F_BINOP(name) \ float32 helper_f ## name ## s (CPUSPARCState *env, float32 src1, \ - float32 src2) \ - { \ - return float32_ ## name (src1, src2, &env->fp_status); \ - } \ + float32 src2) \ + { \ + return float32_ ## name (src1, src2, &env->fp_status); \ + } \ float64 helper_f ## name ## d (CPUSPARCState * env, float64 src1,\ - float64 src2) \ - { \ - return float64_ ## name (src1, src2, &env->fp_status); \ - } \ - F_HELPER(name, q) \ - { \ - QT0 =3D float128_ ## name (QT0, QT1, &env->fp_status); \ + float64 src2) \ + { \ + return float64_ ## name (src1, src2, &env->fp_status); \ + } \ + Int128 helper_f ## name ## q(CPUSPARCState * env, Int128 src1, \ + Int128 src2) \ + { \ + return f128_ret(float128_ ## name (f128_in(src1), f128_in(src2), \ + &env->fp_status)); \ } =20 F_BINOP(add); @@ -168,7 +168,6 @@ void helper_fxtoq(CPUSPARCState *env, int64_t src) QT0 =3D int64_to_float128(src, &env->fp_status); } #endif -#undef F_HELPER =20 /* floating point conversion */ float32 helper_fdtos(CPUSPARCState *env, float64 src) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 6c08bf909e..437f54ff19 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4976,8 +4976,10 @@ static bool do_dddd(DisasContext *dc, arg_r_r_r *a, TRANS(PDIST, VIS1, do_dddd, a, gen_helper_pdist) =20 static bool do_env_qqq(DisasContext *dc, arg_r_r_r *a, - void (*func)(TCGv_env)) + void (*func)(TCGv_i128, TCGv_env, TCGv_i128, TCGv_i= 128)) { + TCGv_i128 src1, src2; + if (gen_trap_ifnofpu(dc)) { return true; } @@ -4986,12 +4988,11 @@ static bool do_env_qqq(DisasContext *dc, arg_r_r_r = *a, } =20 gen_op_clear_ieee_excp_and_FTT(); - gen_op_load_fpr_QT0(QFPREG(a->rs1)); - gen_op_load_fpr_QT1(QFPREG(a->rs2)); - func(tcg_env); + src1 =3D gen_load_fpr_Q(dc, a->rs1); + src2 =3D gen_load_fpr_Q(dc, a->rs2); + func(src1, tcg_env, src1, src2); gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033182213100006 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 4 ++-- target/sparc/fop_helper.c | 8 ++++---- target/sparc/translate.c | 7 ++++--- 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 0a030fc908..e770107eb0 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -98,13 +98,13 @@ DEF_HELPER_FLAGS_2(fxtoq, TCG_CALL_NO_RWG, void, env, s= 64) #endif DEF_HELPER_FLAGS_2(fdtos, TCG_CALL_NO_RWG, f32, env, f64) DEF_HELPER_FLAGS_2(fstod, TCG_CALL_NO_RWG, f64, env, f32) -DEF_HELPER_FLAGS_1(fqtos, TCG_CALL_NO_RWG, f32, env) +DEF_HELPER_FLAGS_2(fqtos, TCG_CALL_NO_RWG, f32, env, i128) DEF_HELPER_FLAGS_2(fstoq, TCG_CALL_NO_RWG, void, env, f32) DEF_HELPER_FLAGS_1(fqtod, TCG_CALL_NO_RWG, f64, env) DEF_HELPER_FLAGS_2(fdtoq, TCG_CALL_NO_RWG, void, env, f64) DEF_HELPER_FLAGS_2(fstoi, TCG_CALL_NO_RWG, s32, env, f32) DEF_HELPER_FLAGS_2(fdtoi, TCG_CALL_NO_RWG, s32, env, f64) -DEF_HELPER_FLAGS_1(fqtoi, TCG_CALL_NO_RWG, s32, env) +DEF_HELPER_FLAGS_2(fqtoi, TCG_CALL_NO_RWG, s32, env, i128) #ifdef TARGET_SPARC64 DEF_HELPER_FLAGS_2(fstox, TCG_CALL_NO_RWG, s64, env, f32) DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_RWG, s64, env, f64) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index ceb64d802f..657a14575d 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -180,9 +180,9 @@ float64 helper_fstod(CPUSPARCState *env, float32 src) return float32_to_float64(src, &env->fp_status); } =20 -float32 helper_fqtos(CPUSPARCState *env) +float32 helper_fqtos(CPUSPARCState *env, Int128 src) { - return float128_to_float32(QT1, &env->fp_status); + return float128_to_float32(f128_in(src), &env->fp_status); } =20 void helper_fstoq(CPUSPARCState *env, float32 src) @@ -211,9 +211,9 @@ int32_t helper_fdtoi(CPUSPARCState *env, float64 src) return float64_to_int32_round_to_zero(src, &env->fp_status); } =20 -int32_t helper_fqtoi(CPUSPARCState *env) +int32_t helper_fqtoi(CPUSPARCState *env, Int128 src) { - return float128_to_int32_round_to_zero(QT1, &env->fp_status); + return float128_to_int32_round_to_zero(f128_in(src), &env->fp_status); } =20 #ifdef TARGET_SPARC64 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 437f54ff19..34a774c8ef 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4692,8 +4692,9 @@ static bool do_env_qq(DisasContext *dc, arg_r_r *a, TRANS(FSQRTq, ALL, do_env_qq, a, gen_helper_fsqrtq) =20 static bool do_env_fq(DisasContext *dc, arg_r_r *a, - void (*func)(TCGv_i32, TCGv_env)) + void (*func)(TCGv_i32, TCGv_env, TCGv_i128)) { + TCGv_i128 src; TCGv_i32 dst; =20 if (gen_trap_ifnofpu(dc)) { @@ -4704,9 +4705,9 @@ static bool do_env_fq(DisasContext *dc, arg_r_r *a, } =20 gen_op_clear_ieee_excp_and_FTT(); - gen_op_load_fpr_QT1(QFPREG(a->rs)); + src =3D gen_load_fpr_Q(dc, a->rs); dst =3D tcg_temp_new_i32(); - func(dst, tcg_env); + func(dst, tcg_env, src); gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_F(dc, a->rd, dst); return advance_pc(dc); --=20 2.34.1 From nobody Wed Nov 27 11:39:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699033294; cv=none; d=zohomail.com; s=zohoarc; b=hGQ5fYHZU+vFE7jaoV4MyhD6Vg1g4pjqrUY2/bUQSuLkOCc8mybCpon3bjZF+bZTV4OVQLiXhWCklfdTx20IB5FbxfgMS5mbI1nS6x1D6wLy9qJV4MPsHvQlzLT6nRr/kCyBac3vP2trKyTgVxA2TjJ/NjGOKLFhxuQlIC/JdVo= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033294738100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 4 ++-- target/sparc/fop_helper.c | 8 ++++---- target/sparc/translate.c | 7 ++++--- 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index e770107eb0..4cb3451878 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -100,7 +100,7 @@ DEF_HELPER_FLAGS_2(fdtos, TCG_CALL_NO_RWG, f32, env, f6= 4) DEF_HELPER_FLAGS_2(fstod, TCG_CALL_NO_RWG, f64, env, f32) DEF_HELPER_FLAGS_2(fqtos, TCG_CALL_NO_RWG, f32, env, i128) DEF_HELPER_FLAGS_2(fstoq, TCG_CALL_NO_RWG, void, env, f32) -DEF_HELPER_FLAGS_1(fqtod, TCG_CALL_NO_RWG, f64, env) +DEF_HELPER_FLAGS_2(fqtod, TCG_CALL_NO_RWG, f64, env, i128) DEF_HELPER_FLAGS_2(fdtoq, TCG_CALL_NO_RWG, void, env, f64) DEF_HELPER_FLAGS_2(fstoi, TCG_CALL_NO_RWG, s32, env, f32) DEF_HELPER_FLAGS_2(fdtoi, TCG_CALL_NO_RWG, s32, env, f64) @@ -108,7 +108,7 @@ DEF_HELPER_FLAGS_2(fqtoi, TCG_CALL_NO_RWG, s32, env, i1= 28) #ifdef TARGET_SPARC64 DEF_HELPER_FLAGS_2(fstox, TCG_CALL_NO_RWG, s64, env, f32) DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_RWG, s64, env, f64) -DEF_HELPER_FLAGS_1(fqtox, TCG_CALL_NO_RWG, s64, env) +DEF_HELPER_FLAGS_2(fqtox, TCG_CALL_NO_RWG, s64, env, i128) =20 DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 657a14575d..9f39b933e8 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -190,9 +190,9 @@ void helper_fstoq(CPUSPARCState *env, float32 src) QT0 =3D float32_to_float128(src, &env->fp_status); } =20 -float64 helper_fqtod(CPUSPARCState *env) +float64 helper_fqtod(CPUSPARCState *env, Int128 src) { - return float128_to_float64(QT1, &env->fp_status); + return float128_to_float64(f128_in(src), &env->fp_status); } =20 void helper_fdtoq(CPUSPARCState *env, float64 src) @@ -227,9 +227,9 @@ int64_t helper_fdtox(CPUSPARCState *env, float64 src) return float64_to_int64_round_to_zero(src, &env->fp_status); } =20 -int64_t helper_fqtox(CPUSPARCState *env) +int64_t helper_fqtox(CPUSPARCState *env, Int128 src) { - return float128_to_int64_round_to_zero(QT1, &env->fp_status); + return float128_to_int64_round_to_zero(f128_in(src), &env->fp_status); } #endif =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 34a774c8ef..ba0b7f32d2 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4717,8 +4717,9 @@ TRANS(FqTOs, ALL, do_env_fq, a, gen_helper_fqtos) TRANS(FqTOi, ALL, do_env_fq, a, gen_helper_fqtoi) =20 static bool do_env_dq(DisasContext *dc, arg_r_r *a, - void (*func)(TCGv_i64, TCGv_env)) + void (*func)(TCGv_i64, TCGv_env, TCGv_i128)) { + TCGv_i128 src; TCGv_i64 dst; =20 if (gen_trap_ifnofpu(dc)) { @@ -4729,9 +4730,9 @@ static bool do_env_dq(DisasContext *dc, arg_r_r *a, } =20 gen_op_clear_ieee_excp_and_FTT(); - gen_op_load_fpr_QT1(QFPREG(a->rs)); + src =3D gen_load_fpr_Q(dc, a->rs); dst =3D gen_dest_fpr_D(dc, a->rd); - func(dst, tcg_env); + func(dst, tcg_env, src); gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_D(dc, a->rd, dst); return advance_pc(dc); --=20 2.34.1 From nobody Wed Nov 27 11:39:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699033388; cv=none; d=zohomail.com; s=zohoarc; b=m9NZVMm+/A5ErLw+4UkrqNTYqjBjCyRkHIYe9qvrvGrBI9kvTp+54L2/mwGgNIYvYNNdXppf2SKtGxqAUDnTf6nxgKEj7ocN37CksenNeM792KTgjnIkJ+lGFnuEe7lSgfqKSVluwS/uTPuOzeLAIoWLM6g8qoQRO6AZIzFwCpc= ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id c10-20020a170902c1ca00b001c0cb2aa2easm1628267plc.121.2023.11.03.10.38.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 10:38:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699033130; x=1699637930; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ER4uvX1BtxDZTzWgZDsDPwgYoxM33bU9YWvNBS9DKAE=; b=MR/YLB6dTErCIOmQTG4u8TGoYkwSlK9fFptaW9rcptO9YZEvmfbHbYkm/9EOtN3VGk d9UGTIUIik8MAlCZpj4UGRdks0w0ctWi12yY8j8hDeyQY4DF6Py96ar6Hz/jngGrs+bf joorw2OQ7h3hKbr3giXqR5lgc7HnhTJD/JOxmqgOwnxSdsa9UE4iwDAjEJStqekM8Axd yZQdv4YV1caKE2DyxDiqqB2BsWJzfY3pIr2jkIzXKMa4FZvhwWzb3ATtWNFB89jeNiX4 XilinfnMvEiiu9NIMMLbpnpm5G0Ko+rBl9hiTSbPrRHi6TYxk0FYZhSUnY+L2fCjD4CU spKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699033130; x=1699637930; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033389039100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 16 ++++++------ target/sparc/fop_helper.c | 23 +++++++++-------- target/sparc/translate.c | 54 +++++++++++++++------------------------ 3 files changed, 41 insertions(+), 52 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 4cb3451878..7caae9a441 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -44,8 +44,8 @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, tl, env, f64, f= 64) DEF_HELPER_FLAGS_3(fcmpes, TCG_CALL_NO_WG, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, tl, env, f64, f64) DEF_HELPER_FLAGS_2(fsqrtq, TCG_CALL_NO_RWG, i128, env, i128) -DEF_HELPER_FLAGS_1(fcmpq, TCG_CALL_NO_WG, tl, env) -DEF_HELPER_FLAGS_1(fcmpeq, TCG_CALL_NO_WG, tl, env) +DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, tl, env, i128, i128) #ifdef TARGET_SPARC64 DEF_HELPER_FLAGS_3(fcmps_fcc1, TCG_CALL_NO_WG, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmps_fcc2, TCG_CALL_NO_WG, tl, env, f32, f32) @@ -59,12 +59,12 @@ DEF_HELPER_FLAGS_3(fcmpes_fcc3, TCG_CALL_NO_WG, tl, env= , f32, f32) DEF_HELPER_FLAGS_3(fcmped_fcc1, TCG_CALL_NO_WG, tl, env, f64, f64) DEF_HELPER_FLAGS_3(fcmped_fcc2, TCG_CALL_NO_WG, tl, env, f64, f64) DEF_HELPER_FLAGS_3(fcmped_fcc3, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_1(fcmpq_fcc1, TCG_CALL_NO_WG, tl, env) -DEF_HELPER_FLAGS_1(fcmpq_fcc2, TCG_CALL_NO_WG, tl, env) -DEF_HELPER_FLAGS_1(fcmpq_fcc3, TCG_CALL_NO_WG, tl, env) -DEF_HELPER_FLAGS_1(fcmpeq_fcc1, TCG_CALL_NO_WG, tl, env) -DEF_HELPER_FLAGS_1(fcmpeq_fcc2, TCG_CALL_NO_WG, tl, env) -DEF_HELPER_FLAGS_1(fcmpeq_fcc3, TCG_CALL_NO_WG, tl, env) +DEF_HELPER_FLAGS_3(fcmpq_fcc1, TCG_CALL_NO_WG, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpq_fcc2, TCG_CALL_NO_WG, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpq_fcc3, TCG_CALL_NO_WG, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq_fcc1, TCG_CALL_NO_WG, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq_fcc2, TCG_CALL_NO_WG, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq_fcc3, TCG_CALL_NO_WG, tl, env, i128, i128) #endif DEF_HELPER_2(raise_exception, noreturn, env, int) =20 diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 9f39b933e8..faf75e651f 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -248,9 +248,12 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) return f128_ret(float128_sqrt(f128_in(src), &env->fp_status)); } =20 -#define GEN_FCMP(name, size, reg1, reg2, FS, E) \ - target_ulong glue(helper_, name) (CPUSPARCState *env) \ +#define GEN_FCMP(name, size, FS, E) \ + target_ulong glue(helper_, name) (CPUSPARCState *env, \ + Int128 src1, Int128 src2) \ { \ + float128 reg1 =3D f128_in(src1); \ + float128 reg2 =3D f128_in(src2); \ FloatRelation ret; \ target_ulong fsr; \ if (E) { \ @@ -316,33 +319,33 @@ GEN_FCMP_T(fcmpd, float64, 0, 0); GEN_FCMP_T(fcmpes, float32, 0, 1); GEN_FCMP_T(fcmped, float64, 0, 1); =20 -GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0); -GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1); +GEN_FCMP(fcmpq, float128, 0, 0); +GEN_FCMP(fcmpeq, float128, 0, 1); =20 #ifdef TARGET_SPARC64 GEN_FCMP_T(fcmps_fcc1, float32, 22, 0); GEN_FCMP_T(fcmpd_fcc1, float64, 22, 0); -GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0); +GEN_FCMP(fcmpq_fcc1, float128, 22, 0); =20 GEN_FCMP_T(fcmps_fcc2, float32, 24, 0); GEN_FCMP_T(fcmpd_fcc2, float64, 24, 0); -GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0); +GEN_FCMP(fcmpq_fcc2, float128, 24, 0); =20 GEN_FCMP_T(fcmps_fcc3, float32, 26, 0); GEN_FCMP_T(fcmpd_fcc3, float64, 26, 0); -GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0); +GEN_FCMP(fcmpq_fcc3, float128, 26, 0); =20 GEN_FCMP_T(fcmpes_fcc1, float32, 22, 1); GEN_FCMP_T(fcmped_fcc1, float64, 22, 1); -GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1); +GEN_FCMP(fcmpeq_fcc1, float128, 22, 1); =20 GEN_FCMP_T(fcmpes_fcc2, float32, 24, 1); GEN_FCMP_T(fcmped_fcc2, float64, 24, 1); -GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1); +GEN_FCMP(fcmpeq_fcc2, float128, 24, 1); =20 GEN_FCMP_T(fcmpes_fcc3, float32, 26, 1); GEN_FCMP_T(fcmped_fcc3, float64, 26, 1); -GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1); +GEN_FCMP(fcmpeq_fcc3, float128, 26, 1); #endif #undef GEN_FCMP_T #undef GEN_FCMP diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ba0b7f32d2..d4eea47c33 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -276,22 +276,6 @@ static void gen_store_fpr_Q(DisasContext *dc, unsigned= int dst, TCGv_i128 v) gen_update_fprs_dirty(dc, dst); } =20 -static void gen_op_load_fpr_QT0(unsigned int src) -{ - tcg_gen_st_i64(cpu_fpr[src / 2], tcg_env, offsetof(CPUSPARCState, qt0)= + - offsetof(CPU_QuadU, ll.upper)); - tcg_gen_st_i64(cpu_fpr[src/2 + 1], tcg_env, offsetof(CPUSPARCState, qt= 0) + - offsetof(CPU_QuadU, ll.lower)); -} - -static void gen_op_load_fpr_QT1(unsigned int src) -{ - tcg_gen_st_i64(cpu_fpr[src / 2], tcg_env, offsetof(CPUSPARCState, qt1)= + - offsetof(CPU_QuadU, ll.upper)); - tcg_gen_st_i64(cpu_fpr[src/2 + 1], tcg_env, offsetof(CPUSPARCState, qt= 1) + - offsetof(CPU_QuadU, ll.lower)); -} - static void gen_op_store_QT0_fpr(unsigned int dst) { tcg_gen_ld_i64(cpu_fpr[dst / 2], tcg_env, offsetof(CPUSPARCState, qt0)= + @@ -1319,20 +1303,20 @@ static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1,= TCGv_i64 r_rs2) } } =20 -static void gen_op_fcmpq(int fccno) +static void gen_op_fcmpq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmpq(cpu_fsr, tcg_env); + gen_helper_fcmpq(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmpq_fcc1(cpu_fsr, tcg_env); + gen_helper_fcmpq_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmpq_fcc2(cpu_fsr, tcg_env); + gen_helper_fcmpq_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmpq_fcc3(cpu_fsr, tcg_env); + gen_helper_fcmpq_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); break; } } @@ -1373,20 +1357,20 @@ static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1= , TCGv_i64 r_rs2) } } =20 -static void gen_op_fcmpeq(int fccno) +static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmpeq(cpu_fsr, tcg_env); + gen_helper_fcmpeq(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmpeq_fcc1(cpu_fsr, tcg_env); + gen_helper_fcmpeq_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmpeq_fcc2(cpu_fsr, tcg_env); + gen_helper_fcmpeq_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmpeq_fcc3(cpu_fsr, tcg_env); + gen_helper_fcmpeq_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); break; } } @@ -1403,9 +1387,9 @@ static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, T= CGv_i64 r_rs2) gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2); } =20 -static void gen_op_fcmpq(int fccno) +static void gen_op_fcmpq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) { - gen_helper_fcmpq(cpu_fsr, tcg_env); + gen_helper_fcmpq(cpu_fsr, tcg_env, r_rs1, r_rs2); } =20 static void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) @@ -1418,9 +1402,9 @@ static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, = TCGv_i64 r_rs2) gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2); } =20 -static void gen_op_fcmpeq(int fccno) +static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) { - gen_helper_fcmpeq(cpu_fsr, tcg_env); + gen_helper_fcmpeq(cpu_fsr, tcg_env, r_rs1, r_rs2); } #endif =20 @@ -5144,6 +5128,8 @@ TRANS(FCMPEd, ALL, do_fcmpd, a, true) =20 static bool do_fcmpq(DisasContext *dc, arg_FCMPq *a, bool e) { + TCGv_i128 src1, src2; + if (avail_32(dc) && a->cc !=3D 0) { return false; } @@ -5155,12 +5141,12 @@ static bool do_fcmpq(DisasContext *dc, arg_FCMPq *a= , bool e) } =20 gen_op_clear_ieee_excp_and_FTT(); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033234496100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 4 ++-- target/sparc/fop_helper.c | 8 ++++---- target/sparc/translate.c | 9 +++++---- 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 7caae9a441..5e93342583 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -87,7 +87,7 @@ DEF_HELPER_FLAGS_3(fsmuld, TCG_CALL_NO_RWG, f64, env, f32= , f32) DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_RWG, void, env, f64, f64) =20 DEF_HELPER_FLAGS_2(fitod, TCG_CALL_NO_RWG_SE, f64, env, s32) -DEF_HELPER_FLAGS_2(fitoq, TCG_CALL_NO_RWG, void, env, s32) +DEF_HELPER_FLAGS_2(fitoq, TCG_CALL_NO_RWG, i128, env, s32) =20 DEF_HELPER_FLAGS_2(fitos, TCG_CALL_NO_RWG, f32, env, s32) =20 @@ -99,7 +99,7 @@ DEF_HELPER_FLAGS_2(fxtoq, TCG_CALL_NO_RWG, void, env, s64) DEF_HELPER_FLAGS_2(fdtos, TCG_CALL_NO_RWG, f32, env, f64) DEF_HELPER_FLAGS_2(fstod, TCG_CALL_NO_RWG, f64, env, f32) DEF_HELPER_FLAGS_2(fqtos, TCG_CALL_NO_RWG, f32, env, i128) -DEF_HELPER_FLAGS_2(fstoq, TCG_CALL_NO_RWG, void, env, f32) +DEF_HELPER_FLAGS_2(fstoq, TCG_CALL_NO_RWG, i128, env, f32) DEF_HELPER_FLAGS_2(fqtod, TCG_CALL_NO_RWG, f64, env, i128) DEF_HELPER_FLAGS_2(fdtoq, TCG_CALL_NO_RWG, void, env, f64) DEF_HELPER_FLAGS_2(fstoi, TCG_CALL_NO_RWG, s32, env, f32) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index faf75e651f..c7dc835d28 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -147,9 +147,9 @@ float64 helper_fitod(CPUSPARCState *env, int32_t src) return int32_to_float64(src, &env->fp_status); } =20 -void helper_fitoq(CPUSPARCState *env, int32_t src) +Int128 helper_fitoq(CPUSPARCState *env, int32_t src) { - QT0 =3D int32_to_float128(src, &env->fp_status); + return f128_ret(int32_to_float128(src, &env->fp_status)); } =20 #ifdef TARGET_SPARC64 @@ -185,9 +185,9 @@ float32 helper_fqtos(CPUSPARCState *env, Int128 src) return float128_to_float32(f128_in(src), &env->fp_status); } =20 -void helper_fstoq(CPUSPARCState *env, float32 src) +Int128 helper_fstoq(CPUSPARCState *env, float32 src) { - QT0 =3D float32_to_float128(src, &env->fp_status); + return f128_ret(float32_to_float128(src, &env->fp_status)); } =20 float64 helper_fqtod(CPUSPARCState *env, Int128 src) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d4eea47c33..1f96990316 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4726,9 +4726,10 @@ TRANS(FqTOd, ALL, do_env_dq, a, gen_helper_fqtod) TRANS(FqTOx, 64, do_env_dq, a, gen_helper_fqtox) =20 static bool do_env_qf(DisasContext *dc, arg_r_r *a, - void (*func)(TCGv_env, TCGv_i32)) + void (*func)(TCGv_i128, TCGv_env, TCGv_i32)) { TCGv_i32 src; + TCGv_i128 dst; =20 if (gen_trap_ifnofpu(dc)) { return true; @@ -4739,9 +4740,9 @@ static bool do_env_qf(DisasContext *dc, arg_r_r *a, =20 gen_op_clear_ieee_excp_and_FTT(); src =3D gen_load_fpr_F(dc, a->rs); - func(tcg_env, src); - gen_op_store_QT0_fpr(QFPREG(a->rd)); - gen_update_fprs_dirty(dc, QFPREG(a->rd)); + dst =3D tcg_temp_new_i128(); + func(dst, tcg_env, src); + gen_store_fpr_Q(dc, a->rd, dst); return advance_pc(dc); } =20 --=20 2.34.1 From nobody Wed Nov 27 11:39:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699033323; cv=none; d=zohomail.com; s=zohoarc; b=LgO+lVStdQLyvT0i40BupaFiplNGqkH20F7DTdf/rX8tVGKVRRrbyIPFDT3OCEGWxGBvIV5LIOzzma6snRCQjYb74tVhXN+SE986anfATKxrY16Y1gyJvESekbzW1a/VBHTzdkyTV+t55Osf6g/kHpKXMZ+ms+NQeTaO1vhcT00= ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id c10-20020a170902c1ca00b001c0cb2aa2easm1628267plc.121.2023.11.03.10.38.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 10:38:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699033132; x=1699637932; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YRZtObwWQaX9TO3lug87cQ176cg0u3ArC+G+NFVft7c=; b=qUWLGIkghipUuswd68B9AHJ78JODQUrYMDKcmKZjsR6G+KVa3bjiVnF/GvEgZsNOSq ijCnkakXeUD2SLVTe8xxr+XxFz5iqdm0KKHSqng75ZACdPzNBP4GQXH6AShj1y70KZRZ Mo1IBSqWT9hxp4jlOeQzKvHZO+UPxx6HW44iBpRmwk5umQQmxazf3Bsors3v/h4zDKdE 2Pjy1jbVowCha+xjQHtyD0MYyMxNtnINvkds27HUkjRpYQu/hmK1uatv1FaexULKCNI7 LChMudIjgbExyZ2xypS3nN7wy7L9boAqohItvP/hlI2OCw180CiEracUrbpIDy8B6yuA u8+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699033132; x=1699637932; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033324791100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 4 ++-- target/sparc/fop_helper.c | 8 ++++---- target/sparc/translate.c | 9 +++++---- 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 5e93342583..20f67f89b0 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -94,14 +94,14 @@ DEF_HELPER_FLAGS_2(fitos, TCG_CALL_NO_RWG, f32, env, s3= 2) #ifdef TARGET_SPARC64 DEF_HELPER_FLAGS_2(fxtos, TCG_CALL_NO_RWG, f32, env, s64) DEF_HELPER_FLAGS_2(fxtod, TCG_CALL_NO_RWG, f64, env, s64) -DEF_HELPER_FLAGS_2(fxtoq, TCG_CALL_NO_RWG, void, env, s64) +DEF_HELPER_FLAGS_2(fxtoq, TCG_CALL_NO_RWG, i128, env, s64) #endif DEF_HELPER_FLAGS_2(fdtos, TCG_CALL_NO_RWG, f32, env, f64) DEF_HELPER_FLAGS_2(fstod, TCG_CALL_NO_RWG, f64, env, f32) DEF_HELPER_FLAGS_2(fqtos, TCG_CALL_NO_RWG, f32, env, i128) DEF_HELPER_FLAGS_2(fstoq, TCG_CALL_NO_RWG, i128, env, f32) DEF_HELPER_FLAGS_2(fqtod, TCG_CALL_NO_RWG, f64, env, i128) -DEF_HELPER_FLAGS_2(fdtoq, TCG_CALL_NO_RWG, void, env, f64) +DEF_HELPER_FLAGS_2(fdtoq, TCG_CALL_NO_RWG, i128, env, f64) DEF_HELPER_FLAGS_2(fstoi, TCG_CALL_NO_RWG, s32, env, f32) DEF_HELPER_FLAGS_2(fdtoi, TCG_CALL_NO_RWG, s32, env, f64) DEF_HELPER_FLAGS_2(fqtoi, TCG_CALL_NO_RWG, s32, env, i128) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index c7dc835d28..9a0110e201 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -163,9 +163,9 @@ float64 helper_fxtod(CPUSPARCState *env, int64_t src) return int64_to_float64(src, &env->fp_status); } =20 -void helper_fxtoq(CPUSPARCState *env, int64_t src) +Int128 helper_fxtoq(CPUSPARCState *env, int64_t src) { - QT0 =3D int64_to_float128(src, &env->fp_status); + return f128_ret(int64_to_float128(src, &env->fp_status)); } #endif =20 @@ -195,9 +195,9 @@ float64 helper_fqtod(CPUSPARCState *env, Int128 src) return float128_to_float64(f128_in(src), &env->fp_status); } =20 -void helper_fdtoq(CPUSPARCState *env, float64 src) +Int128 helper_fdtoq(CPUSPARCState *env, float64 src) { - QT0 =3D float64_to_float128(src, &env->fp_status); + return f128_ret(float64_to_float128(src, &env->fp_status)); } =20 /* Float to integer conversion. */ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 1f96990316..e01cbc5bcb 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4750,9 +4750,10 @@ TRANS(FiTOq, ALL, do_env_qf, a, gen_helper_fitoq) TRANS(FsTOq, ALL, do_env_qf, a, gen_helper_fstoq) =20 static bool do_env_qd(DisasContext *dc, arg_r_r *a, - void (*func)(TCGv_env, TCGv_i64)) + void (*func)(TCGv_i128, TCGv_env, TCGv_i64)) { TCGv_i64 src; + TCGv_i128 dst; =20 if (gen_trap_ifnofpu(dc)) { return true; @@ -4763,9 +4764,9 @@ static bool do_env_qd(DisasContext *dc, arg_r_r *a, =20 gen_op_clear_ieee_excp_and_FTT(); src =3D gen_load_fpr_D(dc, a->rs); - func(tcg_env, src); - gen_op_store_QT0_fpr(QFPREG(a->rd)); - gen_update_fprs_dirty(dc, QFPREG(a->rd)); + dst =3D tcg_temp_new_i128(); + func(dst, tcg_env, src); + gen_store_fpr_Q(dc, a->rd, dst); return advance_pc(dc); } =20 --=20 2.34.1 From nobody Wed Nov 27 11:39:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699033254; cv=none; d=zohomail.com; s=zohoarc; b=kPKCLSAi0pT+ruElAwec7oWbp3moDbmPGsUBN7hQkBxXYxUppF/vONkb7zsUMjnfJxhvuR0poixtiseQy57KbZvf+n4DoxUYzTfS/IUWxivBd8CIGQvyVLOtjsziWvaDA8yzNvfFtZz8i5qH8AppRwfuurdKrKlUKVRP60hrq8U= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033256545100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 2 +- target/sparc/fop_helper.c | 8 ++++---- target/sparc/translate.c | 15 ++++----------- 3 files changed, 9 insertions(+), 16 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 20f67f89b0..f7aeb31169 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -84,7 +84,7 @@ DEF_HELPER_FLAGS_3(fmuls, TCG_CALL_NO_RWG, f32, env, f32,= f32) DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_RWG, f32, env, f32, f32) =20 DEF_HELPER_FLAGS_3(fsmuld, TCG_CALL_NO_RWG, f64, env, f32, f32) -DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_RWG, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_RWG, i128, env, f64, f64) =20 DEF_HELPER_FLAGS_2(fitod, TCG_CALL_NO_RWG_SE, f64, env, s32) DEF_HELPER_FLAGS_2(fitoq, TCG_CALL_NO_RWG, i128, env, s32) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 9a0110e201..cd9b212597 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -129,11 +129,11 @@ float64 helper_fsmuld(CPUSPARCState *env, float32 src= 1, float32 src2) &env->fp_status); } =20 -void helper_fdmulq(CPUSPARCState *env, float64 src1, float64 src2) +Int128 helper_fdmulq(CPUSPARCState *env, float64 src1, float64 src2) { - QT0 =3D float128_mul(float64_to_float128(src1, &env->fp_status), - float64_to_float128(src2, &env->fp_status), - &env->fp_status); + return f128_ret(float128_mul(float64_to_float128(src1, &env->fp_status= ), + float64_to_float128(src2, &env->fp_status= ), + &env->fp_status)); } =20 /* Integer to float conversion. */ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index e01cbc5bcb..99482df256 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -276,14 +276,6 @@ static void gen_store_fpr_Q(DisasContext *dc, unsigned= int dst, TCGv_i128 v) gen_update_fprs_dirty(dc, dst); } =20 -static void gen_op_store_QT0_fpr(unsigned int dst) -{ - tcg_gen_ld_i64(cpu_fpr[dst / 2], tcg_env, offsetof(CPUSPARCState, qt0)= + - offsetof(CPU_QuadU, ll.upper)); - tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], tcg_env, offsetof(CPUSPARCState, qt= 0) + - offsetof(CPU_QuadU, ll.lower)); -} - /* moves */ #ifdef CONFIG_USER_ONLY #define supervisor(dc) 0 @@ -4992,6 +4984,7 @@ TRANS(FDIVq, ALL, do_env_qqq, a, gen_helper_fdivq) static bool trans_FdMULq(DisasContext *dc, arg_r_r_r *a) { TCGv_i64 src1, src2; + TCGv_i128 dst; =20 if (gen_trap_ifnofpu(dc)) { return true; @@ -5003,10 +4996,10 @@ static bool trans_FdMULq(DisasContext *dc, arg_r_r_= r *a) gen_op_clear_ieee_excp_and_FTT(); src1 =3D gen_load_fpr_D(dc, a->rs1); src2 =3D gen_load_fpr_D(dc, a->rs2); - gen_helper_fdmulq(tcg_env, src1, src2); + dst =3D tcg_temp_new_i128(); + gen_helper_fdmulq(dst, tcg_env, src1, src2); gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - gen_op_store_QT0_fpr(QFPREG(a->rd)); - gen_update_fprs_dirty(dc, QFPREG(a->rd)); + gen_store_fpr_Q(dc, a->rd, dst); return advance_pc(dc); } =20 --=20 2.34.1 From nobody Wed Nov 27 11:39:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id c10-20020a170902c1ca00b001c0cb2aa2easm1628267plc.121.2023.11.03.10.38.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 10:38:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699033134; x=1699637934; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hV535+ZsVPNVTyyGsz8sKP3/7RTFgq3VTGjCiMWUEiI=; b=YWpYzp4YZWhqcBay3FXkPYaNgWVZK4/qtp1xqS5btpFn5jCgpGeJOh0QxTUXMLBawS DJpgzR+SU9FK3B+vtvegTFhhnlNMkfDne++0M8RiPKUX4l16+/YaCT7+3vI1qiHx5E70 d2t9tBKHh8alAapYNeEfpclDPE44DsTTn7Q2iXKbQO2gX7c1Y+/cVKUMvezou9SzWLxu /XFefubbEeDuLh8lX9gwaYuaP97PGBpVfkIKkbqFdZf4BpScWws7OoRdCENtBtdPEfCc rQ1ObXdn1rc5tBVeoZE+H+zRTDdPTfVqv5/u3EhXEhjCmTPGm1Zivi/4tw7d9b4uPMXT U/rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699033134; x=1699637934; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hV535+ZsVPNVTyyGsz8sKP3/7RTFgq3VTGjCiMWUEiI=; b=MT8lUwV6cwWDukzaofekKvORhBJ/6xPRTCqDDsll0B+IUypLu0PFMyoeUzB5/6ujSX 4sjgEzIhz8vMlMoOqjQQC8qD9QUpHdXLvm6aI04BeAjBJKMSxfZ8+U019jkxjyJhJTsW iWJLm3km2ToyC6Y/DdqmEkGp/0xlZMkh80OG9T79VMKpIPZYRIK5T9x7SojiBd0HQSUv cIIl23z01WMGHwmkTbF6BKtmg7l87Xi4NZJAdpr1JS7KDcwiu6ykJAWrkHM0iyhuMRe9 U0+fdgu709f0TpA7JYLAGRdlSz6yHwaeSFfgQErFonjd6HYvz5mxNtc7LooN+vLdxtwl fF6w== X-Gm-Message-State: AOJu0YzvYCd3av5rRd5hCtPeqY+M1OIsnM30Eig/JWxmXoWUtPqxTBf/ lKuxw0ElmwYfmFgQ8R1++kg0pxzoEVRTOTkiI0Q= X-Google-Smtp-Source: AGHT+IFBWqcgKGow5C6BCoqmf7ehbH0bm++KYJRCXxuNum5z0ERfy64v30QqtyKOOkQP4kq47kGMCw== X-Received: by 2002:a05:6a20:3d8b:b0:137:514a:984f with SMTP id s11-20020a056a203d8b00b00137514a984fmr23938310pzi.35.1699033133893; Fri, 03 Nov 2023 10:38:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH 14/22] target/sparc: Remove qt0, qt1 temporaries Date: Fri, 3 Nov 2023 10:38:33 -0700 Message-Id: <20231103173841.33651-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103173841.33651-1-richard.henderson@linaro.org> References: <20231103173841.33651-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033364931100001 Content-Type: text/plain; charset="utf-8" These are no longer used for passing data to/from helpers. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland --- target/sparc/cpu.h | 2 -- target/sparc/fop_helper.c | 3 --- target/sparc/ldst_helper.c | 3 --- 3 files changed, 8 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 3e361a5b75..446b38f3df 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -509,8 +509,6 @@ struct CPUArchState { uint64_t mmubpregs[4]; uint64_t prom_addr; #endif - /* temporary float registers */ - float128 qt0, qt1; float_status fp_status; #if defined(TARGET_SPARC64) #define MAXTL_MAX 8 diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index cd9b212597..7353a61237 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -23,9 +23,6 @@ #include "exec/helper-proto.h" #include "fpu/softfloat.h" =20 -#define QT0 (env->qt0) -#define QT1 (env->qt1) - static inline float128 f128_in(Int128 i) { union { diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 09066d5487..fe984d44d7 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -66,9 +66,6 @@ #endif #endif =20 -#define QT0 (env->qt0) -#define QT1 (env->qt1) - #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) /* Calculates TSB pointer value for fault page size * UltraSPARC IIi has fixed sizes (8k or 64k) for the page pointers --=20 2.34.1 From nobody Wed Nov 27 11:39:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699033288; cv=none; d=zohomail.com; s=zohoarc; b=BE5iwiaLZtOLRFtjw/1wDOBPPQv6ZqeDwjau1ljOXdV8kaMfK6O2w7CWJytgiOJ7kkiF2swh9iT+yAY5U/z3f053dThWhsZJSvc3uFWFnfAYiK2NwG9FSF8F6YiuM4ffBjO4E3Ga0yY0ZKEWd4pq88OJQE+kPLEwjcGAW+8U5zA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699033288; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=QRppr0jtETveHLOhJJnBGFSQpLGg4IDz6r7ulJ5/PtI=; b=NYHD7uTbqa1T+y/wK0rQ1/TXdeNozQ0bOaI4+hGb2cRjDytKU4jV6UobL8c+lxXmMDLO0OODzvXT7a0zEji88lJvvbuQ1V27C9JtcuKlYYBSJnFOnkr3Y+EkqyzGYQ68onRFGHEwvHjzKO2Y6JRrfAiSDCVI3dn8fMDGg6vaWOo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699033288401700.1638704706417; Fri, 3 Nov 2023 10:41:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyy8y-0005Ur-Pb; Fri, 03 Nov 2023 13:39:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyy8P-0005FY-6R for qemu-devel@nongnu.org; Fri, 03 Nov 2023 13:39:05 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyy8G-0003WT-44 for qemu-devel@nongnu.org; Fri, 03 Nov 2023 13:38:59 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1cc3bc5df96so19363805ad.2 for ; Fri, 03 Nov 2023 10:38:55 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id c10-20020a170902c1ca00b001c0cb2aa2easm1628267plc.121.2023.11.03.10.38.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 10:38:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699033135; x=1699637935; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QRppr0jtETveHLOhJJnBGFSQpLGg4IDz6r7ulJ5/PtI=; b=SK1d2TE+bxllUmx1kSsJdzSfCWx7LWk3kbO7msBG7d6ijwCrhk9+zCyf0Khxoldc02 Ey+ftPJUIAxK+tOz7Cx1U20M3Og1yX3Or5QrJxqk8KkgHE3JFHSWhWWHigWQrVdqgiar dRytO9CL7bFfaWZYiKocMj8K09fErpISDTiQoeaHMUnGdkAMPzvkCW1JNnj3LzG/rbta 0Ek7PDuom9Sq/K01fWRMXFyNT7NveoqIRB234lksCNv9OCKxEomZbMnKKw5KoEC4i7aR IblcRBQ8BlnC5P/GRWXtjorxCDo0bAc4isjBKHpB7rd4Q9lLqT1zzlvlHcY0BNW2vel1 OKoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699033135; x=1699637935; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033288677100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/sparc/cpu.h | 4 +++- target/sparc/helper.h | 1 + linux-user/sparc/cpu_loop.c | 2 +- linux-user/sparc/signal.c | 14 +++++++++----- target/sparc/cpu.c | 5 +++-- target/sparc/fop_helper.c | 21 ++++++++++++++++++-- target/sparc/gdbstub.c | 8 ++++---- target/sparc/machine.c | 38 +++++++++++++++++++++++++++++++++++-- target/sparc/translate.c | 7 ++++++- 9 files changed, 82 insertions(+), 18 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 446b38f3df..33c7d31fef 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -605,7 +605,9 @@ void sparc_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data); =20 -/* cpu-exec.c */ +/* fop_helper.c */ +target_ulong cpu_get_fsr(CPUSPARCState *); +void cpu_put_fsr(CPUSPARCState *, target_ulong); =20 /* win_helper.c */ target_ulong cpu_get_psr(CPUSPARCState *env1); diff --git a/target/sparc/helper.h b/target/sparc/helper.h index f7aeb31169..cc8db50d75 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -36,6 +36,7 @@ DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, = int, i32) DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32) #endif DEF_HELPER_FLAGS_1(check_ieee_exceptions, TCG_CALL_NO_WG, tl, env) +DEF_HELPER_FLAGS_1(get_fsr, TCG_CALL_NO_WG_SE, tl, env) DEF_HELPER_FLAGS_2(set_fsr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_RWG, f32, env, f32) DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_RWG, f64, env, f64) diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index 3c1bde00dd..50424a54df 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -293,7 +293,7 @@ void cpu_loop (CPUSPARCState *env) case TT_FP_EXCP: { int code =3D TARGET_FPE_FLTUNK; - target_ulong fsr =3D env->fsr; + target_ulong fsr =3D cpu_get_fsr(env); =20 if ((fsr & FSR_FTT_MASK) =3D=3D FSR_FTT_IEEE_EXCP) { if (fsr & FSR_NVC) { diff --git a/linux-user/sparc/signal.c b/linux-user/sparc/signal.c index dfcae707e0..c2dc1000e2 100644 --- a/linux-user/sparc/signal.c +++ b/linux-user/sparc/signal.c @@ -199,20 +199,21 @@ static void save_fpu(struct target_siginfo_fpu *fpu, = CPUSPARCState *env) for (i =3D 0; i < 32; ++i) { __put_user(env->fpr[i].ll, &fpu->si_double_regs[i]); } - __put_user(env->fsr, &fpu->si_fsr); + __put_user(cpu_get_fsr(env), &fpu->si_fsr); __put_user(env->gsr, &fpu->si_gsr); __put_user(env->fprs, &fpu->si_fprs); #else for (i =3D 0; i < 16; ++i) { __put_user(env->fpr[i].ll, &fpu->si_double_regs[i]); } - __put_user(env->fsr, &fpu->si_fsr); + __put_user(cpu_get_fsr(env), &fpu->si_fsr); __put_user(0, &fpu->si_fpqdepth); #endif } =20 static void restore_fpu(struct target_siginfo_fpu *fpu, CPUSPARCState *env) { + target_ulong fsr; int i; =20 #ifdef TARGET_SPARC64 @@ -230,15 +231,16 @@ static void restore_fpu(struct target_siginfo_fpu *fp= u, CPUSPARCState *env) __get_user(env->fpr[i].ll, &fpu->si_double_regs[i]); } } - __get_user(env->fsr, &fpu->si_fsr); __get_user(env->gsr, &fpu->si_gsr); env->fprs |=3D fprs; #else for (i =3D 0; i < 16; ++i) { __get_user(env->fpr[i].ll, &fpu->si_double_regs[i]); } - __get_user(env->fsr, &fpu->si_fsr); #endif + + __get_user(fsr, &fpu->si_fsr); + cpu_put_fsr(env, fsr); } =20 #ifdef TARGET_ARCH_HAS_SETUP_FRAME @@ -662,6 +664,7 @@ void sparc64_set_context(CPUSPARCState *env) __get_user(fenab, &(fpup->mcfpu_enab)); if (fenab) { abi_ulong fprs; + abi_ulong fsr; =20 /* * We use the FPRS from the guest only in deciding whether @@ -690,7 +693,8 @@ void sparc64_set_context(CPUSPARCState *env) __get_user(env->fpr[i].ll, &(fpup->mcfpu_fregs.dregs[i])); } } - __get_user(env->fsr, &(fpup->mcfpu_fsr)); + __get_user(fsr, &(fpup->mcfpu_fsr)); + cpu_put_fsr(env, fsr); __get_user(env->gsr, &(fpup->mcfpu_gsr)); } unlock_user_struct(ucp, ucp_addr, 0); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index befa7fc4eb..69dfa1dd4e 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -670,7 +670,7 @@ static void sparc_cpu_dump_state(CPUState *cs, FILE *f,= int flags) env->cansave, env->canrestore, env->otherwin, env->wstate, env->cleanwin, env->nwindows - 1 - env->cwp); qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: %01= 6x\n", - env->fsr, env->y, env->fprs); + cpu_get_fsr(env), env->y, env->fprs); =20 #else qemu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env)); @@ -679,7 +679,7 @@ static void sparc_cpu_dump_state(CPUState *cs, FILE *f,= int flags) env->psrps ? 'P' : '-', env->psret ? 'E' : '-', env->wim); qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n", - env->fsr, env->y); + cpu_get_fsr(env), env->y); #endif qemu_fprintf(f, "\n"); } @@ -770,6 +770,7 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error= **errp) env->version |=3D env->def.maxtl << 8; env->version |=3D env->def.nwindows - 1; #endif + cpu_put_fsr(env, 0); =20 cpu_exec_realizefn(cs, &local_err); if (local_err !=3D NULL) { diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 7353a61237..70b38011d2 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -347,10 +347,22 @@ GEN_FCMP(fcmpeq_fcc3, float128, 26, 1); #undef GEN_FCMP_T #undef GEN_FCMP =20 -static void set_fsr(CPUSPARCState *env, target_ulong fsr) +target_ulong cpu_get_fsr(CPUSPARCState *env) +{ + return env->fsr; +} + +target_ulong helper_get_fsr(CPUSPARCState *env) +{ + return cpu_get_fsr(env); +} + +static void set_fsr_nonsplit(CPUSPARCState *env, target_ulong fsr) { int rnd_mode; =20 + env->fsr =3D fsr; + switch (fsr & FSR_RD_MASK) { case FSR_RD_NEAREST: rnd_mode =3D float_round_nearest_even; @@ -369,7 +381,12 @@ static void set_fsr(CPUSPARCState *env, target_ulong f= sr) set_float_rounding_mode(rnd_mode, &env->fp_status); } =20 +void cpu_put_fsr(CPUSPARCState *env, target_ulong fsr) +{ + set_fsr_nonsplit(env, fsr); +} + void helper_set_fsr(CPUSPARCState *env, target_ulong fsr) { - set_fsr(env, fsr); + set_fsr_nonsplit(env, fsr); } diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index a1c8fdc4d5..d1586b2392 100644 --- a/target/sparc/gdbstub.c +++ b/target/sparc/gdbstub.c @@ -64,7 +64,7 @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) case 69: return gdb_get_rega(mem_buf, env->npc); case 70: - return gdb_get_rega(mem_buf, env->fsr); + return gdb_get_rega(mem_buf, cpu_get_fsr(env)); case 71: return gdb_get_rega(mem_buf, 0); /* csr */ default: @@ -94,7 +94,7 @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) ((env->pstate & 0xfff) << 8) | cpu_get_cwp64(env)); case 83: - return gdb_get_regl(mem_buf, env->fsr); + return gdb_get_regl(mem_buf, cpu_get_fsr(env)); case 84: return gdb_get_regl(mem_buf, env->fprs); case 85: @@ -156,7 +156,7 @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t = *mem_buf, int n) env->npc =3D tmp; break; case 70: - env->fsr =3D tmp; + cpu_put_fsr(env, tmp); break; default: return 0; @@ -191,7 +191,7 @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t = *mem_buf, int n) cpu_put_cwp64(env, tmp & 0xff); break; case 83: - env->fsr =3D tmp; + cpu_put_fsr(env, tmp); break; case 84: env->fprs =3D tmp; diff --git a/target/sparc/machine.c b/target/sparc/machine.c index 44dfc07014..e46f15adb8 100644 --- a/target/sparc/machine.c +++ b/target/sparc/machine.c @@ -83,6 +83,34 @@ static const VMStateInfo vmstate_psr =3D { .put =3D put_psr, }; =20 +static int get_fsr(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field) +{ + SPARCCPU *cpu =3D opaque; + CPUSPARCState *env =3D &cpu->env; + target_ulong val =3D qemu_get_betl(f); + + cpu_put_fsr(env, val); + return 0; +} + +static int put_fsr(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field, JSONWriter *vmdesc) +{ + SPARCCPU *cpu =3D opaque; + CPUSPARCState *env =3D &cpu->env; + target_ulong val =3D cpu_get_fsr(env); + + qemu_put_betl(f, val); + return 0; +} + +static const VMStateInfo vmstate_fsr =3D { + .name =3D "fsr", + .get =3D get_fsr, + .put =3D put_fsr, +}; + #ifdef TARGET_SPARC64 static int get_xcc(QEMUFile *f, void *opaque, size_t size, const VMStateField *field) @@ -157,7 +185,6 @@ const VMStateDescription vmstate_sparc_cpu =3D { VMSTATE_UINTTL(env.npc, SPARCCPU), VMSTATE_UINTTL(env.y, SPARCCPU), { - .name =3D "psr", .version_id =3D 0, .size =3D sizeof(uint32_t), @@ -165,7 +192,14 @@ const VMStateDescription vmstate_sparc_cpu =3D { .flags =3D VMS_SINGLE, .offset =3D 0, }, - VMSTATE_UINTTL(env.fsr, SPARCCPU), + { + .name =3D "fsr", + .version_id =3D 0, + .size =3D sizeof(target_ulong), + .info =3D &vmstate_fsr, + .flags =3D VMS_SINGLE, + .offset =3D 0, + }, VMSTATE_UINTTL(env.tbr, SPARCCPU), VMSTATE_INT32(env.interrupt_index, SPARCCPU), VMSTATE_UINT32(env.pil_in, SPARCCPU), diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 99482df256..1d5f36dafc 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4417,13 +4417,18 @@ TRANS(LDXFSR, 64, do_ldfsr, a, MO_TEUQ, FSR_LDXFSR_= MASK, FSR_LDXFSR_OLDMASK) static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop) { TCGv addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + TCGv fsr; + if (addr =3D=3D NULL) { return false; } if (gen_trap_ifnofpu(dc)) { return true; } - tcg_gen_qemu_st_tl(cpu_fsr, addr, dc->mem_idx, mop | MO_ALIGN); + + fsr =3D tcg_temp_new(); + gen_helper_get_fsr(fsr, tcg_env); + tcg_gen_qemu_st_tl(fsr, addr, dc->mem_idx, mop | MO_ALIGN); return advance_pc(dc); } =20 --=20 2.34.1 From nobody Wed Nov 27 11:39:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699033260; cv=none; d=zohomail.com; s=zohoarc; b=dTDUqwnWT1tPhMkA05UVf15N0LewKkyClcgrLuWqlHCCMYTg/faFba5aCj76DAk/p3wsiolM2O6SeVSxVrPhy9+mmqfqEh7U5G7KtWLHgPpvXlejmjlPmE/GjiPILrOX09YK1GSFzKFR7TIkD1DGnUxx+tZ6IEp+RhsFdaobwQM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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It is easier to store it separately and merge it only upon read. While we're at it, use FSR_VER_SHIFT to initialize fpu_version. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/sparc/cpu.h | 3 +++ target/sparc/cpu.c | 27 +++++++++++++-------------- target/sparc/fop_helper.c | 9 +++++++-- 3 files changed, 23 insertions(+), 16 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 33c7d31fef..8ff222595e 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -191,6 +191,9 @@ enum { #define FSR_NXC (1ULL << 0) #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) =20 +#define FSR_VER_SHIFT 17 +#define FSR_VER_MASK (7 << FSR_VER_SHIFT) + #define FSR_FTT2 (1ULL << 16) #define FSR_FTT1 (1ULL << 15) #define FSR_FTT0 (1ULL << 14) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 69dfa1dd4e..bebfdbf313 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -368,7 +368,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "Fujitsu MB86904", .iu_version =3D 0x04 << 24, /* Impl 0, ver 4 */ - .fpu_version =3D 4 << 17, /* FPU version 4 (Meiko) */ + .fpu_version =3D 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ .mmu_version =3D 0x04 << 24, /* Impl 0, ver 4 */ .mmu_bm =3D 0x00004000, .mmu_ctpr_mask =3D 0x00ffffc0, @@ -381,7 +381,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "Fujitsu MB86907", .iu_version =3D 0x05 << 24, /* Impl 0, ver 5 */ - .fpu_version =3D 4 << 17, /* FPU version 4 (Meiko) */ + .fpu_version =3D 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ .mmu_version =3D 0x05 << 24, /* Impl 0, ver 5 */ .mmu_bm =3D 0x00004000, .mmu_ctpr_mask =3D 0xffffffc0, @@ -394,7 +394,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "TI MicroSparc I", .iu_version =3D 0x41000000, - .fpu_version =3D 4 << 17, + .fpu_version =3D 4 << FSR_VER_SHIFT, .mmu_version =3D 0x41000000, .mmu_bm =3D 0x00004000, .mmu_ctpr_mask =3D 0x007ffff0, @@ -407,7 +407,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "TI MicroSparc II", .iu_version =3D 0x42000000, - .fpu_version =3D 4 << 17, + .fpu_version =3D 4 << FSR_VER_SHIFT, .mmu_version =3D 0x02000000, .mmu_bm =3D 0x00004000, .mmu_ctpr_mask =3D 0x00ffffc0, @@ -420,7 +420,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "TI MicroSparc IIep", .iu_version =3D 0x42000000, - .fpu_version =3D 4 << 17, + .fpu_version =3D 4 << FSR_VER_SHIFT, .mmu_version =3D 0x04000000, .mmu_bm =3D 0x00004000, .mmu_ctpr_mask =3D 0x00ffffc0, @@ -433,7 +433,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "TI SuperSparc 40", /* STP1020NPGA */ .iu_version =3D 0x41000000, /* SuperSPARC 2.x */ - .fpu_version =3D 0 << 17, + .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x00000800, /* SuperSPARC 2.x, no MXCC */ .mmu_bm =3D 0x00002000, .mmu_ctpr_mask =3D 0xffffffc0, @@ -446,7 +446,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "TI SuperSparc 50", /* STP1020PGA */ .iu_version =3D 0x40000000, /* SuperSPARC 3.x */ - .fpu_version =3D 0 << 17, + .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x01000800, /* SuperSPARC 3.x, no MXCC */ .mmu_bm =3D 0x00002000, .mmu_ctpr_mask =3D 0xffffffc0, @@ -459,7 +459,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "TI SuperSparc 51", .iu_version =3D 0x40000000, /* SuperSPARC 3.x */ - .fpu_version =3D 0 << 17, + .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x01000000, /* SuperSPARC 3.x, MXCC */ .mmu_bm =3D 0x00002000, .mmu_ctpr_mask =3D 0xffffffc0, @@ -473,7 +473,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "TI SuperSparc 60", /* STP1020APGA */ .iu_version =3D 0x40000000, /* SuperSPARC 3.x */ - .fpu_version =3D 0 << 17, + .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x01000800, /* SuperSPARC 3.x, no MXCC */ .mmu_bm =3D 0x00002000, .mmu_ctpr_mask =3D 0xffffffc0, @@ -486,7 +486,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "TI SuperSparc 61", .iu_version =3D 0x44000000, /* SuperSPARC 3.x */ - .fpu_version =3D 0 << 17, + .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x01000000, /* SuperSPARC 3.x, MXCC */ .mmu_bm =3D 0x00002000, .mmu_ctpr_mask =3D 0xffffffc0, @@ -500,7 +500,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "TI SuperSparc II", .iu_version =3D 0x40000000, /* SuperSPARC II 1.x */ - .fpu_version =3D 0 << 17, + .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x08000000, /* SuperSPARC II 1.x, MXCC */ .mmu_bm =3D 0x00002000, .mmu_ctpr_mask =3D 0xffffffc0, @@ -514,7 +514,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "LEON2", .iu_version =3D 0xf2000000, - .fpu_version =3D 4 << 17, /* FPU version 4 (Meiko) */ + .fpu_version =3D 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ .mmu_version =3D 0xf2000000, .mmu_bm =3D 0x00004000, .mmu_ctpr_mask =3D 0x007ffff0, @@ -527,7 +527,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "LEON3", .iu_version =3D 0xf3000000, - .fpu_version =3D 4 << 17, /* FPU version 4 (Meiko) */ + .fpu_version =3D 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ .mmu_version =3D 0xf3000000, .mmu_bm =3D 0x00000000, .mmu_ctpr_mask =3D 0xfffffffc, @@ -758,7 +758,6 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error= **errp) #endif =20 env->version =3D env->def.iu_version; - env->fsr =3D env->def.fpu_version; env->nwindows =3D env->def.nwindows; #if !defined(TARGET_SPARC64) env->mmuregs[0] |=3D env->def.mmu_version; diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 70b38011d2..22b412adb5 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -349,7 +349,12 @@ GEN_FCMP(fcmpeq_fcc3, float128, 26, 1); =20 target_ulong cpu_get_fsr(CPUSPARCState *env) { - return env->fsr; + target_ulong fsr =3D env->fsr; + + /* VER is kept completely separate until re-assembly. */ + fsr |=3D env->def.fpu_version; + + return fsr; } =20 target_ulong helper_get_fsr(CPUSPARCState *env) @@ -361,7 +366,7 @@ static void set_fsr_nonsplit(CPUSPARCState *env, target= _ulong fsr) { int rnd_mode; =20 - env->fsr =3D fsr; + env->fsr =3D fsr & ~FSR_VER_MASK; =20 switch (fsr & FSR_RD_MASK) { case FSR_RD_NEAREST: --=20 2.34.1 From nobody Wed Nov 27 11:39:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699033381; cv=none; d=zohomail.com; s=zohoarc; b=VVMPaG48tFNakaYVj7VgAC7aPz3b4ziEvSID3DifrXOq5Gas22sUcPJq53MgBnKOLQ6+EBoyqe/nGx376lRYPNN2DZZfBe295D+wEQhqpvVsXDiX7QTPLXk35lGr0A53nlOiyIcEE26pbftyc1johJz4UiBb9M0HlgEeqDcr/bA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699033381; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=94raU7rUG4SaFXDKyXSSaATMe2GXL+iedReuLCx526s=; b=mT63DGWPa8bzTdjqmBR07nZlDA82btMANPW78qH1BgN2ETxCRabDswP9WjdmUe2vGhPSUkAw8C7AUwBTu26OJ4H361yKz1Kpk4xttARwCgkdCt9erUksPPcXgNOJDbO5Jjis+maTV79dTnt4liZGQXSBBRfWy0R4sEI7dJTDwao= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16990333809911003.8183662829884; Fri, 3 Nov 2023 10:43:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyy90-0005Xo-Ae; Fri, 03 Nov 2023 13:39:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyy8P-0005Fa-71 for qemu-devel@nongnu.org; Fri, 03 Nov 2023 13:39:05 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyy8I-0003aR-3Z for qemu-devel@nongnu.org; Fri, 03 Nov 2023 13:39:02 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1cc3bb4c307so24607575ad.0 for ; Fri, 03 Nov 2023 10:38:57 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id c10-20020a170902c1ca00b001c0cb2aa2easm1628267plc.121.2023.11.03.10.38.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 10:38:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699033136; x=1699637936; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=94raU7rUG4SaFXDKyXSSaATMe2GXL+iedReuLCx526s=; b=zC2+CMtJtqTHLJNNS8fetXgNw/laLVhIZ2dqqSpPAK7NmLOg35Ov7ZFicnUMZN98Qy ibaMvB1SyxmqIw8V9e4fpYJmL48OKAQ1S8ItKZytsZzGOGseE5ZsJeP1c3OfppXnsJlA zh/5YSF78fJ1ctucKeHomqK54Fe3kfFrB/0bs+OBCngbFOkX6hQSv4oGR/Tp/wEspcC/ 3S+GhoKJj2Fw+ozutrw4+M/p7Z0xWkKSxzyWaJ+X6ULGmkw3GY5JV4m+TNmZOFoqfAln R55mE7htnmN7fLAxA3EesuYK4v3BGp3koBaRAJPDJeCjwXPCTX8J4PFd6G5akH/rsMKc f32w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699033136; x=1699637936; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=94raU7rUG4SaFXDKyXSSaATMe2GXL+iedReuLCx526s=; b=LkbSmOTK6KOmgIohkahpPWspp5JD/7WFUbyNAOij95JpupBaooyUyBZlQsnmr9O2Kf 83q7OilAW01SDNzvjJvU7j14rMgFzmrJQhf5gmFPxtvbNVGG6Dfp1MLx96rbaTrfMTmz zv9W50mRwUsinA06bQFoHitM4a1Jg84+ysA9R+4vjZmfd8CSjXUjW7gIo3Xyeus+MCE6 VvdtQdzxWUbwJj4OwUdFRIra52XHVocouMaGpip8VR0Pue+D0CoX6QfLB6mdRk2k9p1w w6YUEZDa5SyY8HYeZMe5+AXPmiLebEMRF4/RBMLtr/aScsL201iP6VvrgdeDgn8a6d3i 8GVg== X-Gm-Message-State: AOJu0Yyd5SRo4Tn5mzl4mMMzyjuLAYuidn7jFVVWjNu8VvGxJaqWHfik XllZVSK+jYUkQdV44eSa2P94dIH3dZgnAyaioMI= X-Google-Smtp-Source: AGHT+IEXs23dqk2vgcmefCnJxWLIs6CYdBvYGX69hoRot4xsommEjNIAfD4iPZtTlfyR6XGoj4yAVg== X-Received: by 2002:a17:902:db0c:b0:1cc:5833:cf57 with SMTP id m12-20020a170902db0c00b001cc5833cf57mr15358114plx.45.1699033136375; Fri, 03 Nov 2023 10:38:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH 17/22] target/sparc: Clear cexc and ftt in do_check_ieee_exceptions Date: Fri, 3 Nov 2023 10:38:36 -0700 Message-Id: <20231103173841.33651-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103173841.33651-1-richard.henderson@linaro.org> References: <20231103173841.33651-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033383068100003 Content-Type: text/plain; charset="utf-8" Don't do the clearing explicitly before each FPop, rather do it as part of the rest of exception handling. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland --- target/sparc/fop_helper.c | 2 ++ target/sparc/translate.c | 16 ---------------- 2 files changed, 2 insertions(+), 16 deletions(-) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 22b412adb5..64f20e78f1 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -50,6 +50,8 @@ static target_ulong do_check_ieee_exceptions(CPUSPARCStat= e *env, uintptr_t ra) target_ulong status =3D get_float_exception_flags(&env->fp_status); target_ulong fsr =3D env->fsr; =20 + fsr &=3D FSR_FTT_CEXC_NMASK; + if (unlikely(status)) { /* Keep exception flags clear for next time. */ set_float_exception_flags(0, &env->fp_status); diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 1d5f36dafc..11d025f4ea 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4524,7 +4524,6 @@ static bool do_env_ff(DisasContext *dc, arg_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); tmp =3D gen_load_fpr_F(dc, a->rs); func(tmp, tcg_env, tmp); gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); @@ -4546,7 +4545,6 @@ static bool do_env_fd(DisasContext *dc, arg_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); dst =3D tcg_temp_new_i32(); src =3D gen_load_fpr_D(dc, a->rs); func(dst, tcg_env, src); @@ -4590,7 +4588,6 @@ static bool do_env_dd(DisasContext *dc, arg_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); dst =3D gen_dest_fpr_D(dc, a->rd); src =3D gen_load_fpr_D(dc, a->rs); func(dst, tcg_env, src); @@ -4613,7 +4610,6 @@ static bool do_env_df(DisasContext *dc, arg_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); dst =3D gen_dest_fpr_D(dc, a->rd); src =3D gen_load_fpr_F(dc, a->rs); func(dst, tcg_env, src); @@ -4661,8 +4657,6 @@ static bool do_env_qq(DisasContext *dc, arg_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); - t =3D gen_load_fpr_Q(dc, a->rs); func(t, tcg_env, t); gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); @@ -4685,7 +4679,6 @@ static bool do_env_fq(DisasContext *dc, arg_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); src =3D gen_load_fpr_Q(dc, a->rs); dst =3D tcg_temp_new_i32(); func(dst, tcg_env, src); @@ -4710,7 +4703,6 @@ static bool do_env_dq(DisasContext *dc, arg_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); src =3D gen_load_fpr_Q(dc, a->rs); dst =3D gen_dest_fpr_D(dc, a->rd); func(dst, tcg_env, src); @@ -4808,7 +4800,6 @@ static bool do_env_fff(DisasContext *dc, arg_r_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); src1 =3D gen_load_fpr_F(dc, a->rs1); src2 =3D gen_load_fpr_F(dc, a->rs2); func(src1, tcg_env, src1, src2); @@ -4903,7 +4894,6 @@ static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); dst =3D gen_dest_fpr_D(dc, a->rd); src1 =3D gen_load_fpr_D(dc, a->rs1); src2 =3D gen_load_fpr_D(dc, a->rs2); @@ -4930,7 +4920,6 @@ static bool trans_FsMULd(DisasContext *dc, arg_r_r_r = *a) return raise_unimpfpop(dc); } =20 - gen_op_clear_ieee_excp_and_FTT(); dst =3D gen_dest_fpr_D(dc, a->rd); src1 =3D gen_load_fpr_F(dc, a->rs1); src2 =3D gen_load_fpr_F(dc, a->rs2); @@ -4972,7 +4961,6 @@ static bool do_env_qqq(DisasContext *dc, arg_r_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); src1 =3D gen_load_fpr_Q(dc, a->rs1); src2 =3D gen_load_fpr_Q(dc, a->rs2); func(src1, tcg_env, src1, src2); @@ -4998,7 +4986,6 @@ static bool trans_FdMULq(DisasContext *dc, arg_r_r_r = *a) return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); src1 =3D gen_load_fpr_D(dc, a->rs1); src2 =3D gen_load_fpr_D(dc, a->rs2); dst =3D tcg_temp_new_i128(); @@ -5087,7 +5074,6 @@ static bool do_fcmps(DisasContext *dc, arg_FCMPs *a, = bool e) return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); src1 =3D gen_load_fpr_F(dc, a->rs1); src2 =3D gen_load_fpr_F(dc, a->rs2); if (e) { @@ -5112,7 +5098,6 @@ static bool do_fcmpd(DisasContext *dc, arg_FCMPd *a, = bool e) return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); src1 =3D gen_load_fpr_D(dc, a->rs1); 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id c10-20020a170902c1ca00b001c0cb2aa2easm1628267plc.121.2023.11.03.10.38.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 10:38:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699033137; x=1699637937; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iVsbIeWHMF2HBCXqKDb/t306b+v4n8a0ChABNQQ+H1I=; b=P9uUVUNPf41b5DVONc7w7VAB93IVUk9PZS5yGQPFxizu9yUGPjo6tsXoImsT+7VEVV IL/u9ah5Hz7dxKruk0HltoL4AbCb6q9Iwd4ETzTc0BTB4O8HJ88sN7ktiuFe7Lnm9KF0 Xnssav9GkMtL/kc6+dOx8S1bWz0mp5MPNyhGHAx9UU70dxLP1iUW20ONGbUdc4imiLQJ qzyfqumuWOdSXuZ/2f7ZNZYa4qkQPH6y0Dm78DwvALUx/qGYVMYYilRqqoojK0j5IiFz 7A2Nso61zbrYUZXL5TYzl5aP/vM2yRqtZlkVHsUO3ccyVeCpqMF4itI9xSpOh5nb9xLf R7Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699033137; x=1699637937; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iVsbIeWHMF2HBCXqKDb/t306b+v4n8a0ChABNQQ+H1I=; b=CDM7aigk/Y1/jAO3X2gxyXUGynvLNWVzhunGDwpD171L+FnMogVOAzg6521gf7iR/v IaGikAPlsptlI23MeKQ98rk6bTEmknhFUNzG3vftRw5rsK5A4gesbyB+OvgKahIugAJW dEEP6cLm6jcSUvU/VdQzalBYKdk85t4PPdVi3TWCK2XpjgyzXjbFgI0qPFO0Ez97jfg6 Eo8fEht3v6t44Tlk0UTMqPp9UI8KgWUlgJ/1USoSb+41FUXjcCmehyNF0FfHDFadGrp+ gbyj0zwaQ5te9DigVPB5/z47747rBY6uQV80FaAlUvDm2C/bQKY0ROq+3yGqxGaJ/m51 0Pxw== X-Gm-Message-State: AOJu0YzamX7gSZl/R28xAGPbvXB49eMUNDG+YvGiMSIBKn1rxWu8+QYr T7aQLxPBnElmsSKtzZZ1VteDKZK0FJmpf+VTbyU= X-Google-Smtp-Source: AGHT+IHTrhPV7iSWRzryvuFkDlrUtEWUH0Wxt7AT0tadxsgMT13/TnCmJxuo4qax2SdsAidk+fDI8A== X-Received: by 2002:a17:902:f394:b0:1c9:b2c1:139c with SMTP id f20-20020a170902f39400b001c9b2c1139cmr18179316ple.62.1699033137224; Fri, 03 Nov 2023 10:38:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH 18/22] target/sparc: Merge check_ieee_exceptions with FPop helpers Date: Fri, 3 Nov 2023 10:38:37 -0700 Message-Id: <20231103173841.33651-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103173841.33651-1-richard.henderson@linaro.org> References: <20231103173841.33651-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033368960100009 Content-Type: text/plain; charset="utf-8" If an exception is to be raised, the destination fp register should be unmodified. The current implementation is incorrect, in that double results will be written back before calling gen_helper_check_ieee_exceptions, despite the placement of gen_store_fpr_D, since gen_dest_fpr_D returns cpu_fpr[]. We can simplify the entire implementation by having each FPOp helper call check_ieee_exceptions. For the moment this requires that all FPop helpers write to the TCG global cpu_fsr, so remove TCG_CALL_NO_WG from the DEF_HELPER_FLAGS_*. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 119 +++++++++++---------- target/sparc/fop_helper.c | 215 ++++++++++++++++++++++++++++---------- target/sparc/translate.c | 14 --- 3 files changed, 219 insertions(+), 129 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index cc8db50d75..7c688edd62 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -35,81 +35,80 @@ DEF_HELPER_3(tsubcctv, tl, env, tl, tl) DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, int, i32) DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32) #endif -DEF_HELPER_FLAGS_1(check_ieee_exceptions, TCG_CALL_NO_WG, tl, env) DEF_HELPER_FLAGS_1(get_fsr, TCG_CALL_NO_WG_SE, tl, env) DEF_HELPER_FLAGS_2(set_fsr, TCG_CALL_NO_RWG, void, env, tl) -DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_RWG, f32, env, f32) -DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_RWG, f64, env, f64) -DEF_HELPER_FLAGS_3(fcmps, TCG_CALL_NO_WG, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpes, TCG_CALL_NO_WG, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_2(fsqrtq, TCG_CALL_NO_RWG, i128, env, i128) -DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, tl, env, i128, i128) +DEF_HELPER_FLAGS_2(fsqrts, 0, f32, env, f32) +DEF_HELPER_FLAGS_2(fsqrtd, 0, f64, env, f64) +DEF_HELPER_FLAGS_2(fsqrtq, 0, i128, env, i128) +DEF_HELPER_FLAGS_3(fcmps, 0, tl, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpd, 0, tl, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpes, 0, tl, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmped, 0, tl, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpq, 0, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq, 0, tl, env, i128, i128) #ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_3(fcmps_fcc1, TCG_CALL_NO_WG, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmps_fcc2, TCG_CALL_NO_WG, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmps_fcc3, TCG_CALL_NO_WG, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpd_fcc1, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpd_fcc2, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpd_fcc3, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpes_fcc1, TCG_CALL_NO_WG, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpes_fcc2, TCG_CALL_NO_WG, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpes_fcc3, TCG_CALL_NO_WG, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmped_fcc1, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmped_fcc2, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmped_fcc3, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpq_fcc1, TCG_CALL_NO_WG, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpq_fcc2, TCG_CALL_NO_WG, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpq_fcc3, TCG_CALL_NO_WG, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq_fcc1, TCG_CALL_NO_WG, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq_fcc2, TCG_CALL_NO_WG, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq_fcc3, TCG_CALL_NO_WG, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmps_fcc1, 0, tl, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmps_fcc2, 0, tl, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmps_fcc3, 0, tl, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpd_fcc1, 0, tl, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpd_fcc2, 0, tl, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpd_fcc3, 0, tl, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpes_fcc1, 0, tl, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpes_fcc2, 0, tl, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpes_fcc3, 0, tl, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmped_fcc1, 0, tl, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmped_fcc2, 0, tl, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmped_fcc3, 0, tl, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpq_fcc1, 0, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpq_fcc2, 0, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpq_fcc3, 0, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq_fcc1, 0, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq_fcc2, 0, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq_fcc3, 0, tl, env, i128, i128) #endif DEF_HELPER_2(raise_exception, noreturn, env, int) =20 -DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_RWG, f64, env, f64, f64) -DEF_HELPER_FLAGS_3(fsubd, TCG_CALL_NO_RWG, f64, env, f64, f64) -DEF_HELPER_FLAGS_3(fmuld, TCG_CALL_NO_RWG, f64, env, f64, f64) -DEF_HELPER_FLAGS_3(fdivd, TCG_CALL_NO_RWG, f64, env, f64, f64) +DEF_HELPER_FLAGS_3(faddd, 0, f64, env, f64, f64) +DEF_HELPER_FLAGS_3(fsubd, 0, f64, env, f64, f64) +DEF_HELPER_FLAGS_3(fmuld, 0, f64, env, f64, f64) +DEF_HELPER_FLAGS_3(fdivd, 0, f64, env, f64, f64) =20 -DEF_HELPER_FLAGS_3(faddq, TCG_CALL_NO_RWG, i128, env, i128, i128) -DEF_HELPER_FLAGS_3(fsubq, TCG_CALL_NO_RWG, i128, env, i128, i128) -DEF_HELPER_FLAGS_3(fmulq, TCG_CALL_NO_RWG, i128, env, i128, i128) -DEF_HELPER_FLAGS_3(fdivq, TCG_CALL_NO_RWG, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(faddq, 0, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(fsubq, 0, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(fmulq, 0, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(fdivq, 0, i128, env, i128, i128) =20 -DEF_HELPER_FLAGS_3(fadds, TCG_CALL_NO_RWG, f32, env, f32, f32) -DEF_HELPER_FLAGS_3(fsubs, TCG_CALL_NO_RWG, f32, env, f32, f32) -DEF_HELPER_FLAGS_3(fmuls, TCG_CALL_NO_RWG, f32, env, f32, f32) -DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_RWG, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fadds, 0, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fsubs, 0, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fmuls, 0, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fdivs, 0, f32, env, f32, f32) =20 -DEF_HELPER_FLAGS_3(fsmuld, TCG_CALL_NO_RWG, f64, env, f32, f32) -DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_RWG, i128, env, f64, f64) +DEF_HELPER_FLAGS_3(fsmuld, 0, f64, env, f32, f32) +DEF_HELPER_FLAGS_3(fdmulq, 0, i128, env, f64, f64) =20 -DEF_HELPER_FLAGS_2(fitod, TCG_CALL_NO_RWG_SE, f64, env, s32) -DEF_HELPER_FLAGS_2(fitoq, TCG_CALL_NO_RWG, i128, env, s32) +DEF_HELPER_FLAGS_2(fitod, 0, f64, env, s32) +DEF_HELPER_FLAGS_2(fitoq, 0, i128, env, s32) =20 -DEF_HELPER_FLAGS_2(fitos, TCG_CALL_NO_RWG, f32, env, s32) +DEF_HELPER_FLAGS_2(fitos, 0, f32, env, s32) =20 #ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_2(fxtos, TCG_CALL_NO_RWG, f32, env, s64) -DEF_HELPER_FLAGS_2(fxtod, TCG_CALL_NO_RWG, f64, env, s64) -DEF_HELPER_FLAGS_2(fxtoq, TCG_CALL_NO_RWG, i128, env, s64) +DEF_HELPER_FLAGS_2(fxtos, 0, f32, env, s64) +DEF_HELPER_FLAGS_2(fxtod, 0, f64, env, s64) +DEF_HELPER_FLAGS_2(fxtoq, 0, i128, env, s64) #endif -DEF_HELPER_FLAGS_2(fdtos, TCG_CALL_NO_RWG, f32, env, f64) -DEF_HELPER_FLAGS_2(fstod, TCG_CALL_NO_RWG, f64, env, f32) -DEF_HELPER_FLAGS_2(fqtos, TCG_CALL_NO_RWG, f32, env, i128) -DEF_HELPER_FLAGS_2(fstoq, TCG_CALL_NO_RWG, i128, env, f32) -DEF_HELPER_FLAGS_2(fqtod, TCG_CALL_NO_RWG, f64, env, i128) -DEF_HELPER_FLAGS_2(fdtoq, TCG_CALL_NO_RWG, i128, env, f64) -DEF_HELPER_FLAGS_2(fstoi, TCG_CALL_NO_RWG, s32, env, f32) -DEF_HELPER_FLAGS_2(fdtoi, TCG_CALL_NO_RWG, s32, env, f64) -DEF_HELPER_FLAGS_2(fqtoi, TCG_CALL_NO_RWG, s32, env, i128) +DEF_HELPER_FLAGS_2(fdtos, 0, f32, env, f64) +DEF_HELPER_FLAGS_2(fstod, 0, f64, env, f32) +DEF_HELPER_FLAGS_2(fqtos, 0, f32, env, i128) +DEF_HELPER_FLAGS_2(fstoq, 0, i128, env, f32) +DEF_HELPER_FLAGS_2(fqtod, 0, f64, env, i128) +DEF_HELPER_FLAGS_2(fdtoq, 0, i128, env, f64) +DEF_HELPER_FLAGS_2(fstoi, 0, s32, env, f32) +DEF_HELPER_FLAGS_2(fdtoi, 0, s32, env, f64) +DEF_HELPER_FLAGS_2(fqtoi, 0, s32, env, i128) #ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_2(fstox, TCG_CALL_NO_RWG, s64, env, f32) -DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_RWG, s64, env, f64) -DEF_HELPER_FLAGS_2(fqtox, TCG_CALL_NO_RWG, s64, env, i128) +DEF_HELPER_FLAGS_2(fstox, 0, s64, env, f32) +DEF_HELPER_FLAGS_2(fdtox, 0, s64, env, f64) +DEF_HELPER_FLAGS_2(fqtox, 0, s64, env, i128) =20 DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 64f20e78f1..755117ea08 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -45,7 +45,7 @@ static inline Int128 f128_ret(float128 f) return u.i; } =20 -static target_ulong do_check_ieee_exceptions(CPUSPARCState *env, uintptr_t= ra) +static void check_ieee_exceptions(CPUSPARCState *env, uintptr_t ra) { target_ulong status =3D get_float_exception_flags(&env->fp_status); target_ulong fsr =3D env->fsr; @@ -89,162 +89,265 @@ static target_ulong do_check_ieee_exceptions(CPUSPARC= State *env, uintptr_t ra) } } =20 - return fsr; + env->fsr =3D fsr; } =20 -target_ulong helper_check_ieee_exceptions(CPUSPARCState *env) +float32 helper_fadds(CPUSPARCState *env, float32 src1, float32 src2) { - return do_check_ieee_exceptions(env, GETPC()); + float32 ret =3D float32_add(src1, src2, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 -#define F_BINOP(name) \ - float32 helper_f ## name ## s (CPUSPARCState *env, float32 src1, \ - float32 src2) \ - { \ - return float32_ ## name (src1, src2, &env->fp_status); \ - } \ - float64 helper_f ## name ## d (CPUSPARCState * env, float64 src1,\ - float64 src2) \ - { \ - return float64_ ## name (src1, src2, &env->fp_status); \ - } \ - Int128 helper_f ## name ## q(CPUSPARCState * env, Int128 src1, \ - Int128 src2) \ - { \ - return f128_ret(float128_ ## name (f128_in(src1), f128_in(src2), \ - &env->fp_status)); \ - } +float32 helper_fsubs(CPUSPARCState *env, float32 src1, float32 src2) +{ + float32 ret =3D float32_sub(src1, src2, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; +} =20 -F_BINOP(add); -F_BINOP(sub); -F_BINOP(mul); -F_BINOP(div); -#undef F_BINOP +float32 helper_fmuls(CPUSPARCState *env, float32 src1, float32 src2) +{ + float32 ret =3D float32_mul(src1, src2, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; +} + +float32 helper_fdivs(CPUSPARCState *env, float32 src1, float32 src2) +{ + float32 ret =3D float32_div(src1, src2, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; +} + +float64 helper_faddd(CPUSPARCState *env, float64 src1, float64 src2) +{ + float64 ret =3D float64_add(src1, src2, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; +} + +float64 helper_fsubd(CPUSPARCState *env, float64 src1, float64 src2) +{ + float64 ret =3D float64_sub(src1, src2, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; +} + +float64 helper_fmuld(CPUSPARCState *env, float64 src1, float64 src2) +{ + float64 ret =3D float64_mul(src1, src2, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; +} + +float64 helper_fdivd(CPUSPARCState *env, float64 src1, float64 src2) +{ + float64 ret =3D float64_div(src1, src2, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; +} + +Int128 helper_faddq(CPUSPARCState *env, Int128 src1, Int128 src2) +{ + float128 ret =3D float128_add(f128_in(src1), f128_in(src2), &env->fp_s= tatus); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); +} + +Int128 helper_fsubq(CPUSPARCState *env, Int128 src1, Int128 src2) +{ + float128 ret =3D float128_sub(f128_in(src1), f128_in(src2), &env->fp_s= tatus); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); +} + +Int128 helper_fmulq(CPUSPARCState *env, Int128 src1, Int128 src2) +{ + float128 ret =3D float128_mul(f128_in(src1), f128_in(src2), &env->fp_s= tatus); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); +} + +Int128 helper_fdivq(CPUSPARCState *env, Int128 src1, Int128 src2) +{ + float128 ret =3D float128_div(f128_in(src1), f128_in(src2), &env->fp_s= tatus); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); +} =20 float64 helper_fsmuld(CPUSPARCState *env, float32 src1, float32 src2) { - return float64_mul(float32_to_float64(src1, &env->fp_status), - float32_to_float64(src2, &env->fp_status), - &env->fp_status); + float64 ret =3D float64_mul(float32_to_float64(src1, &env->fp_status), + float32_to_float64(src2, &env->fp_status), + &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 Int128 helper_fdmulq(CPUSPARCState *env, float64 src1, float64 src2) { - return f128_ret(float128_mul(float64_to_float128(src1, &env->fp_status= ), - float64_to_float128(src2, &env->fp_status= ), - &env->fp_status)); + float128 ret =3D float128_mul(float64_to_float128(src1, &env->fp_statu= s), + float64_to_float128(src2, &env->fp_status), + &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); } =20 /* Integer to float conversion. */ float32 helper_fitos(CPUSPARCState *env, int32_t src) { - return int32_to_float32(src, &env->fp_status); + float32 ret =3D int32_to_float32(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 float64 helper_fitod(CPUSPARCState *env, int32_t src) { - return int32_to_float64(src, &env->fp_status); + float64 ret =3D int32_to_float64(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 Int128 helper_fitoq(CPUSPARCState *env, int32_t src) { - return f128_ret(int32_to_float128(src, &env->fp_status)); + float128 ret =3D int32_to_float128(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); } =20 #ifdef TARGET_SPARC64 float32 helper_fxtos(CPUSPARCState *env, int64_t src) { - return int64_to_float32(src, &env->fp_status); + float32 ret =3D int64_to_float32(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 float64 helper_fxtod(CPUSPARCState *env, int64_t src) { - return int64_to_float64(src, &env->fp_status); + float64 ret =3D int64_to_float64(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 Int128 helper_fxtoq(CPUSPARCState *env, int64_t src) { - return f128_ret(int64_to_float128(src, &env->fp_status)); + float128 ret =3D int64_to_float128(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); } #endif =20 /* floating point conversion */ float32 helper_fdtos(CPUSPARCState *env, float64 src) { - return float64_to_float32(src, &env->fp_status); + float32 ret =3D float64_to_float32(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 float64 helper_fstod(CPUSPARCState *env, float32 src) { - return float32_to_float64(src, &env->fp_status); + float64 ret =3D float32_to_float64(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 float32 helper_fqtos(CPUSPARCState *env, Int128 src) { - return float128_to_float32(f128_in(src), &env->fp_status); + float32 ret =3D float128_to_float32(f128_in(src), &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 Int128 helper_fstoq(CPUSPARCState *env, float32 src) { - return f128_ret(float32_to_float128(src, &env->fp_status)); + float128 ret =3D float32_to_float128(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); } =20 float64 helper_fqtod(CPUSPARCState *env, Int128 src) { - return float128_to_float64(f128_in(src), &env->fp_status); + float64 ret =3D float128_to_float64(f128_in(src), &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 Int128 helper_fdtoq(CPUSPARCState *env, float64 src) { - return f128_ret(float64_to_float128(src, &env->fp_status)); + float128 ret =3D float64_to_float128(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); } =20 /* Float to integer conversion. */ int32_t helper_fstoi(CPUSPARCState *env, float32 src) { - return float32_to_int32_round_to_zero(src, &env->fp_status); + int32_t ret =3D float32_to_int32_round_to_zero(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 int32_t helper_fdtoi(CPUSPARCState *env, float64 src) { - return float64_to_int32_round_to_zero(src, &env->fp_status); + int32_t ret =3D float64_to_int32_round_to_zero(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 int32_t helper_fqtoi(CPUSPARCState *env, Int128 src) { - return float128_to_int32_round_to_zero(f128_in(src), &env->fp_status); + int32_t ret =3D float128_to_int32_round_to_zero(f128_in(src), + &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 #ifdef TARGET_SPARC64 int64_t helper_fstox(CPUSPARCState *env, float32 src) { - return float32_to_int64_round_to_zero(src, &env->fp_status); + int64_t ret =3D float32_to_int64_round_to_zero(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 int64_t helper_fdtox(CPUSPARCState *env, float64 src) { - return float64_to_int64_round_to_zero(src, &env->fp_status); + int64_t ret =3D float64_to_int64_round_to_zero(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 int64_t helper_fqtox(CPUSPARCState *env, Int128 src) { - return float128_to_int64_round_to_zero(f128_in(src), &env->fp_status); + int64_t ret =3D float128_to_int64_round_to_zero(f128_in(src), + &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } #endif =20 float32 helper_fsqrts(CPUSPARCState *env, float32 src) { - return float32_sqrt(src, &env->fp_status); + float32 ret =3D float32_sqrt(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 float64 helper_fsqrtd(CPUSPARCState *env, float64 src) { - return float64_sqrt(src, &env->fp_status); + float64 ret =3D float64_sqrt(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) { - return f128_ret(float128_sqrt(f128_in(src), &env->fp_status)); + float128 ret =3D float128_sqrt(f128_in(src), &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); } =20 #define GEN_FCMP(name, size, FS, E) \ @@ -261,7 +364,8 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) ret =3D glue(size, _compare_quiet)(reg1, reg2, \ &env->fp_status); \ } \ - fsr =3D do_check_ieee_exceptions(env, GETPC()); \ + check_ieee_exceptions(env, GETPC()); \ + fsr =3D env->fsr; \ switch (ret) { \ case float_relation_unordered: \ fsr |=3D (FSR_FCC1 | FSR_FCC0) << FS; \ @@ -292,7 +396,8 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) ret =3D glue(size, _compare_quiet)(src1, src2, \ &env->fp_status); \ } \ - fsr =3D do_check_ieee_exceptions(env, GETPC()); \ + check_ieee_exceptions(env, GETPC()); \ + fsr =3D env->fsr; \ switch (ret) { \ case float_relation_unordered: \ fsr |=3D (FSR_FCC1 | FSR_FCC0) << FS; \ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 11d025f4ea..8787cb3bfe 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4526,7 +4526,6 @@ static bool do_env_ff(DisasContext *dc, arg_r_r *a, =20 tmp =3D gen_load_fpr_F(dc, a->rs); func(tmp, tcg_env, tmp); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_F(dc, a->rd, tmp); return advance_pc(dc); } @@ -4548,7 +4547,6 @@ static bool do_env_fd(DisasContext *dc, arg_r_r *a, dst =3D tcg_temp_new_i32(); src =3D gen_load_fpr_D(dc, a->rs); func(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_F(dc, a->rd, dst); return advance_pc(dc); } @@ -4591,7 +4589,6 @@ static bool do_env_dd(DisasContext *dc, arg_r_r *a, dst =3D gen_dest_fpr_D(dc, a->rd); src =3D gen_load_fpr_D(dc, a->rs); func(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_D(dc, a->rd, dst); return advance_pc(dc); } @@ -4613,7 +4610,6 @@ static bool do_env_df(DisasContext *dc, arg_r_r *a, dst =3D gen_dest_fpr_D(dc, a->rd); src =3D gen_load_fpr_F(dc, a->rs); func(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_D(dc, a->rd, dst); return advance_pc(dc); } @@ -4659,7 +4655,6 @@ static bool do_env_qq(DisasContext *dc, arg_r_r *a, =20 t =3D gen_load_fpr_Q(dc, a->rs); func(t, tcg_env, t); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_Q(dc, a->rd, t); return advance_pc(dc); } @@ -4682,7 +4677,6 @@ static bool do_env_fq(DisasContext *dc, arg_r_r *a, src =3D gen_load_fpr_Q(dc, a->rs); dst =3D tcg_temp_new_i32(); func(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_F(dc, a->rd, dst); return advance_pc(dc); } @@ -4706,7 +4700,6 @@ static bool do_env_dq(DisasContext *dc, arg_r_r *a, src =3D gen_load_fpr_Q(dc, a->rs); dst =3D gen_dest_fpr_D(dc, a->rd); func(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_D(dc, a->rd, dst); return advance_pc(dc); } @@ -4727,7 +4720,6 @@ static bool do_env_qf(DisasContext *dc, arg_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); src =3D gen_load_fpr_F(dc, a->rs); dst =3D tcg_temp_new_i128(); func(dst, tcg_env, src); @@ -4751,7 +4743,6 @@ static bool do_env_qd(DisasContext *dc, arg_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); src =3D gen_load_fpr_D(dc, a->rs); dst =3D tcg_temp_new_i128(); func(dst, tcg_env, src); @@ -4803,7 +4794,6 @@ static bool do_env_fff(DisasContext *dc, arg_r_r_r *a, src1 =3D gen_load_fpr_F(dc, a->rs1); src2 =3D gen_load_fpr_F(dc, a->rs2); func(src1, tcg_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_F(dc, a->rd, src1); return advance_pc(dc); } @@ -4898,7 +4888,6 @@ static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a, src1 =3D gen_load_fpr_D(dc, a->rs1); src2 =3D gen_load_fpr_D(dc, a->rs2); func(dst, tcg_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_D(dc, a->rd, dst); return advance_pc(dc); } @@ -4924,7 +4913,6 @@ static bool trans_FsMULd(DisasContext *dc, arg_r_r_r = *a) src1 =3D gen_load_fpr_F(dc, a->rs1); src2 =3D gen_load_fpr_F(dc, a->rs2); gen_helper_fsmuld(dst, tcg_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_D(dc, a->rd, dst); return advance_pc(dc); } @@ -4964,7 +4952,6 @@ static bool do_env_qqq(DisasContext *dc, arg_r_r_r *a, src1 =3D gen_load_fpr_Q(dc, a->rs1); src2 =3D gen_load_fpr_Q(dc, a->rs2); func(src1, tcg_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_Q(dc, a->rd, src1); return advance_pc(dc); } @@ -4990,7 +4977,6 @@ static bool trans_FdMULq(DisasContext *dc, arg_r_r_r = *a) src2 =3D gen_load_fpr_D(dc, a->rs2); dst =3D tcg_temp_new_i128(); gen_helper_fdmulq(dst, tcg_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_Q(dc, a->rd, dst); return advance_pc(dc); } --=20 2.34.1 From nobody Wed Nov 27 11:39:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id c10-20020a170902c1ca00b001c0cb2aa2easm1628267plc.121.2023.11.03.10.38.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 10:38:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699033138; x=1699637938; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yWz+ZzAMVjjFRopUVxf0Ass3su6x27zrvmh1JV3hSlI=; b=ft5cXaz9rWFMUokih6eTHEPJE0UIiRF6uvo/CJBuVY4U+vMFVF6dlVpr8/wqSgLHgs 25TKVIDOTIlXofk8cgFiR0BQJai3grdPIXZL7cRWH5iq0rXVeKuVId/NC/lByZhu5lif E98wMjFlzUxuBjo9ioJ9GZ2ZYf9SeIhf6S7Jx46LZSF6e/CwbXVXulZxkDts2M74L52g XWZfasmmhWxv02aqTTwptdsrZmvyauxM7JwfL0E3WRAm7y6Kmh/qcH2JblboZdH9UKV2 XffNFJRc6aafTlp/dxwzKxOHDu6aiV0ieHektxgPRDMRCZfuQDGD66CqTjafHAtNWQNd xKfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699033138; x=1699637938; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yWz+ZzAMVjjFRopUVxf0Ass3su6x27zrvmh1JV3hSlI=; b=SMzzOqcJlJzOzDxunMN1akS1tzRdzskOendT5YSTmmtJGVp+Fk3BHLPetp3pAjn9ms 7YDhf5dlaL5sMUtILPmEbNq95FKWpURWrbsSNXdLgiDZscX+V/UsoLUTcCxHznl8JkjY LumgNZftVCEziLxXaK3Qk710Km7JUPgSAxdSnv5LTYmboQdIS1IyL4WjCaQ0RU4/hAqm yGvcF5UI6BmEvTshrP4Rt/pCEwOyxjEtQZsQuapW9v4gygPUKHuLM/RL+wzEWOnAVs0o YPA+cEY/sv5YHHRhHxj4YWUB1KGx3KTk5pAHp142g2L5w6dX9PeT666Sxo0+fjHuYvoY ctJg== X-Gm-Message-State: AOJu0YxWtLojZ2FFXG1Yj7MMBi6l2qloCTc+tIAgM4+e65/vXXBiCXs9 WKN7pvqLKnEVPETuTeNFph0vdGzIcfuKGfiLg6k= X-Google-Smtp-Source: AGHT+IEqen1ZtAK1+EEliKiPIBnJfUrPnQLycnsAuIV4waH5BPLs4ZWECcMB7kp0Ed8v0DjE71gDzA== X-Received: by 2002:a17:902:e746:b0:1cc:5468:3284 with SMTP id p6-20020a170902e74600b001cc54683284mr4427952plf.23.1699033138053; Fri, 03 Nov 2023 10:38:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH 19/22] target/sparc: Split cexc and ftt from env->fsr Date: Fri, 3 Nov 2023 10:38:38 -0700 Message-Id: <20231103173841.33651-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103173841.33651-1-richard.henderson@linaro.org> References: <20231103173841.33651-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033286684100001 Content-Type: text/plain; charset="utf-8" These two fields are adjusted by all FPop insns. Having them separate makes it easier to set without masking. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland --- target/sparc/cpu.h | 7 +++++- target/sparc/helper.h | 2 +- target/sparc/fop_helper.c | 46 ++++++++++++++++++--------------------- target/sparc/translate.c | 31 ++++++++++++++++---------- 4 files changed, 48 insertions(+), 38 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 8ff222595e..90a7dfb004 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -176,6 +176,7 @@ enum { #define FSR_DZM (1ULL << 24) #define FSR_NXM (1ULL << 23) #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) +#define FSR_TEM_SHIFT 23 =20 #define FSR_NVA (1ULL << 9) #define FSR_OFA (1ULL << 8) @@ -183,6 +184,7 @@ enum { #define FSR_DZA (1ULL << 6) #define FSR_NXA (1ULL << 5) #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) +#define FSR_AEXC_SHIFT 5 =20 #define FSR_NVC (1ULL << 4) #define FSR_OFC (1ULL << 3) @@ -464,7 +466,10 @@ struct CPUArchState { target_ulong cond; /* conditional branch result (XXX: save it in a temporary register when possible) */ =20 - target_ulong fsr; /* FPU state register */ + /* FPU State Register, in parts */ + target_ulong fsr; /* rm, tem, aexc, fcc* */ + uint32_t fsr_cexc_ftt; /* cexc, ftt */ + CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ uint32_t cwp; /* index of current register window (extracted from PSR) */ diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 7c688edd62..7466164468 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -36,7 +36,7 @@ DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, = int, i32) DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32) #endif DEF_HELPER_FLAGS_1(get_fsr, TCG_CALL_NO_WG_SE, tl, env) -DEF_HELPER_FLAGS_2(set_fsr, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_2(set_fsr_noftt, 0, void, env, tl) DEF_HELPER_FLAGS_2(fsqrts, 0, f32, env, f32) DEF_HELPER_FLAGS_2(fsqrtd, 0, f64, env, f64) DEF_HELPER_FLAGS_2(fsqrtq, 0, i128, env, i128) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 755117ea08..ac30f88810 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -48,9 +48,7 @@ static inline Int128 f128_ret(float128 f) static void check_ieee_exceptions(CPUSPARCState *env, uintptr_t ra) { target_ulong status =3D get_float_exception_flags(&env->fp_status); - target_ulong fsr =3D env->fsr; - - fsr &=3D FSR_FTT_CEXC_NMASK; + uint32_t cexc =3D 0; =20 if (unlikely(status)) { /* Keep exception flags clear for next time. */ @@ -58,38 +56,33 @@ static void check_ieee_exceptions(CPUSPARCState *env, u= intptr_t ra) =20 /* Copy IEEE 754 flags into FSR */ if (status & float_flag_invalid) { - fsr |=3D FSR_NVC; + cexc |=3D FSR_NVC; } if (status & float_flag_overflow) { - fsr |=3D FSR_OFC; + cexc |=3D FSR_OFC; } if (status & float_flag_underflow) { - fsr |=3D FSR_UFC; + cexc |=3D FSR_UFC; } if (status & float_flag_divbyzero) { - fsr |=3D FSR_DZC; + cexc |=3D FSR_DZC; } if (status & float_flag_inexact) { - fsr |=3D FSR_NXC; + cexc |=3D FSR_NXC; } =20 - if ((fsr & FSR_CEXC_MASK) & ((fsr & FSR_TEM_MASK) >> 23)) { - CPUState *cs =3D env_cpu(env); - - /* Unmasked exception, generate a trap. Note that while - the helper is marked as NO_WG, we can get away with - writing to cpu state along the exception path, since - TCG generated code will never see the write. */ - env->fsr =3D fsr | FSR_FTT_IEEE_EXCP; - cs->exception_index =3D TT_FP_EXCP; - cpu_loop_exit_restore(cs, ra); - } else { - /* Accumulate exceptions */ - fsr |=3D (fsr & FSR_CEXC_MASK) << 5; + if (cexc & (env->fsr >> FSR_TEM_SHIFT)) { + /* Unmasked exception, generate an IEEE trap. */ + env->fsr_cexc_ftt =3D cexc | FSR_FTT_IEEE_EXCP; + cpu_raise_exception_ra(env, TT_FP_EXCP, ra); } + + /* Accumulate exceptions */ + env->fsr |=3D cexc << FSR_AEXC_SHIFT; } =20 - env->fsr =3D fsr; + /* No trap, so FTT is cleared. */ + env->fsr_cexc_ftt =3D cexc; } =20 float32 helper_fadds(CPUSPARCState *env, float32 src1, float32 src2) @@ -456,7 +449,7 @@ GEN_FCMP(fcmpeq_fcc3, float128, 26, 1); =20 target_ulong cpu_get_fsr(CPUSPARCState *env) { - target_ulong fsr =3D env->fsr; + target_ulong fsr =3D env->fsr | env->fsr_cexc_ftt; =20 /* VER is kept completely separate until re-assembly. */ fsr |=3D env->def.fpu_version; @@ -473,7 +466,7 @@ static void set_fsr_nonsplit(CPUSPARCState *env, target= _ulong fsr) { int rnd_mode; =20 - env->fsr =3D fsr & ~FSR_VER_MASK; + env->fsr =3D fsr & ~(FSR_VER_MASK | FSR_CEXC_MASK | FSR_FTT_MASK); =20 switch (fsr & FSR_RD_MASK) { case FSR_RD_NEAREST: @@ -495,10 +488,13 @@ static void set_fsr_nonsplit(CPUSPARCState *env, targ= et_ulong fsr) =20 void cpu_put_fsr(CPUSPARCState *env, target_ulong fsr) { + env->fsr_cexc_ftt =3D fsr & (FSR_CEXC_MASK | FSR_FTT_MASK); set_fsr_nonsplit(env, fsr); } =20 -void helper_set_fsr(CPUSPARCState *env, target_ulong fsr) +void helper_set_fsr_noftt(CPUSPARCState *env, target_ulong fsr) { + env->fsr_cexc_ftt &=3D FSR_FTT_MASK; + env->fsr_cexc_ftt |=3D fsr & FSR_CEXC_MASK; set_fsr_nonsplit(env, fsr); } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 8787cb3bfe..d2145dcc0b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1199,7 +1199,8 @@ static bool gen_compare_reg(DisasCompare *cmp, int co= nd, TCGv r_src) =20 static void gen_op_clear_ieee_excp_and_FTT(void) { - tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); + tcg_gen_st_i32(tcg_constant_i32(0), tcg_env, + offsetof(CPUSPARCState, fsr_cexc_ftt)); } =20 static void gen_op_fmovs(TCGv_i32 dst, TCGv_i32 src) @@ -1400,10 +1401,15 @@ static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs= 1, TCGv_i128 r_rs2) } #endif =20 -static void gen_op_fpexception_im(DisasContext *dc, int fsr_flags) +static void gen_op_fpexception_im(DisasContext *dc, int ftt) { - tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK); - tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); + /* + * CEXC is only set when succesfully completing an FPop, + * or when raising FSR_FTT_IEEE_EXCP, i.e. check_ieee_exception. + * Thus we can simply store FTT into this field. + */ + tcg_gen_st_i32(tcg_constant_i32(ftt), tcg_env, + offsetof(CPUSPARCState, fsr_cexc_ftt)); gen_exception(dc, TT_FP_EXCP); } =20 @@ -4395,19 +4401,22 @@ static bool trans_STDFQ(DisasContext *dc, arg_STDFQ= *a) static bool do_ldfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop, target_ulong new_mask, target_ulong old_mask) { - TCGv tmp, addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + TCGv addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + TCGv tnew, told; + if (addr =3D=3D NULL) { return false; } if (gen_trap_ifnofpu(dc)) { return true; } - tmp =3D tcg_temp_new(); - tcg_gen_qemu_ld_tl(tmp, addr, dc->mem_idx, mop | MO_ALIGN); - tcg_gen_andi_tl(tmp, tmp, new_mask); - tcg_gen_andi_tl(cpu_fsr, cpu_fsr, old_mask); - tcg_gen_or_tl(cpu_fsr, cpu_fsr, tmp); - gen_helper_set_fsr(tcg_env, cpu_fsr); + tnew =3D tcg_temp_new(); + told =3D tcg_temp_new(); + tcg_gen_qemu_ld_tl(tnew, addr, dc->mem_idx, mop | MO_ALIGN); + tcg_gen_andi_tl(tnew, tnew, new_mask); + tcg_gen_andi_tl(told, cpu_fsr, old_mask); + tcg_gen_or_tl(tnew, tnew, told); + gen_helper_set_fsr_noftt(tcg_env, tnew); return advance_pc(dc); } =20 --=20 2.34.1 From nobody Wed Nov 27 11:39:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id c10-20020a170902c1ca00b001c0cb2aa2easm1628267plc.121.2023.11.03.10.38.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 10:38:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699033139; x=1699637939; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=23apJLMtwFFRbqjYu0yQC8IvOrql8DriMhf5HN175H4=; b=DtZNiBxIC8kJ9DnuwguYTmTjgGMa5ILcUeUmivEijP96R0i6zjXTal2r51Dxzjamt+ 5OZ5fsfedBbxsufBfRLcSO6WmEtMEBeXkvwt4FZ+2INVb5/CvSfqZX1Skm4eFs91k/1X x5NLV1viip5UTAsqVPXUOjnV3WOhjLpW6kJSGzRm+mELPQPEWs+fj8qpUMS0pryVKN5f 9U9N7KfJMYxzDswlXKRfYROLT+k7nQss2DKNa2S45mdeTwN6G3X6pv8m2HZgt/kx6PDV +F9IBHUGfwg0Q+8d2MVet7j9DKsOSEqh34UnM7NOBXHQs+6vGifIjd1Y8a1DjN4DpgKG 5Haw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699033139; x=1699637939; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=23apJLMtwFFRbqjYu0yQC8IvOrql8DriMhf5HN175H4=; b=NO+x9H5z4b/V6mWoJeutC2719s5f3t4w8gJMpXhGwycTcPMskMF9P8YjXpzk4/vUGV Y3E9MitVae9lLamytyc+qEBpv8C9sM309MSqBWU6z29QhBk+6zXMMsgV8D2wxDMcul8z BVI0Zf0s9CYfJZ2bBebOzUXenxufjc8P7DMhjmBdAEtOSlwOdQWaUI4MDV/hRN7v/728 guaUwmtOyKMPcPubR55GuLy0lS9qJv6i0o0/Y/TdiPIamNWXx2jQNRsfyjvOckg+MNO4 C/T2g6g8KUjAer2yO7jS58ALaVFY87MxFtokMhFbtxnR7aPCCZPodpC/NL2epqwYee4A Qk4g== X-Gm-Message-State: AOJu0YwMbgeEk9lHI8lpMsibFCfroefmZWxqAfmdGSr78MaCkLsprsmy 05HNbezJSvfaAWaa6RBnAUY8uao28Xo+mYARbTQ= X-Google-Smtp-Source: AGHT+IH6ze8Q77pmXmIR5aSZqy3MG53aMsjuK0sm0sd1xqGFSCqZdaNxCj8M7pPR4sm78v0O9v1yhA== X-Received: by 2002:a17:903:32cc:b0:1cc:4985:fc04 with SMTP id i12-20020a17090332cc00b001cc4985fc04mr16593187plr.66.1699033138736; Fri, 03 Nov 2023 10:38:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH 20/22] target/sparc: Remove cpu_fsr Date: Fri, 3 Nov 2023 10:38:39 -0700 Message-Id: <20231103173841.33651-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103173841.33651-1-richard.henderson@linaro.org> References: <20231103173841.33651-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033272620100003 Content-Type: text/plain; charset="utf-8" Drop this field as a tcg global, loading it explicitly in the few places required. This means that all FPop helpers may once again be TCG_CALL_NO_WG. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 120 +++++++++++++++++++------------------- target/sparc/fop_helper.c | 9 ++- target/sparc/translate.c | 98 ++++++++++++++++--------------- 3 files changed, 114 insertions(+), 113 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 7466164468..c8e14fe371 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -36,79 +36,79 @@ DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl= , int, i32) DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32) #endif DEF_HELPER_FLAGS_1(get_fsr, TCG_CALL_NO_WG_SE, tl, env) -DEF_HELPER_FLAGS_2(set_fsr_noftt, 0, void, env, tl) -DEF_HELPER_FLAGS_2(fsqrts, 0, f32, env, f32) -DEF_HELPER_FLAGS_2(fsqrtd, 0, f64, env, f64) -DEF_HELPER_FLAGS_2(fsqrtq, 0, i128, env, i128) -DEF_HELPER_FLAGS_3(fcmps, 0, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpd, 0, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpes, 0, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmped, 0, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpq, 0, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq, 0, tl, env, i128, i128) +DEF_HELPER_FLAGS_2(set_fsr_noftt, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_WG, f32, env, f32) +DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_WG, f64, env, f64) +DEF_HELPER_FLAGS_2(fsqrtq, TCG_CALL_NO_WG, i128, env, i128) +DEF_HELPER_FLAGS_3(fcmps, TCG_CALL_NO_WG, void, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpes, TCG_CALL_NO_WG, void, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, void, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, void, env, i128, i128) #ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_3(fcmps_fcc1, 0, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmps_fcc2, 0, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmps_fcc3, 0, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpd_fcc1, 0, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpd_fcc2, 0, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpd_fcc3, 0, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpes_fcc1, 0, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpes_fcc2, 0, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpes_fcc3, 0, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmped_fcc1, 0, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmped_fcc2, 0, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmped_fcc3, 0, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpq_fcc1, 0, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpq_fcc2, 0, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpq_fcc3, 0, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq_fcc1, 0, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq_fcc2, 0, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq_fcc3, 0, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmps_fcc1, TCG_CALL_NO_WG, void, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmps_fcc2, TCG_CALL_NO_WG, void, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmps_fcc3, TCG_CALL_NO_WG, void, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpd_fcc1, TCG_CALL_NO_WG, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpd_fcc2, TCG_CALL_NO_WG, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpd_fcc3, TCG_CALL_NO_WG, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpes_fcc1, TCG_CALL_NO_WG, void, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpes_fcc2, TCG_CALL_NO_WG, void, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpes_fcc3, TCG_CALL_NO_WG, void, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmped_fcc1, TCG_CALL_NO_WG, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmped_fcc2, TCG_CALL_NO_WG, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmped_fcc3, TCG_CALL_NO_WG, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpq_fcc1, TCG_CALL_NO_WG, void, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpq_fcc2, TCG_CALL_NO_WG, void, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpq_fcc3, TCG_CALL_NO_WG, void, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq_fcc1, TCG_CALL_NO_WG, void, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq_fcc2, TCG_CALL_NO_WG, void, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq_fcc3, TCG_CALL_NO_WG, void, env, i128, i128) #endif DEF_HELPER_2(raise_exception, noreturn, env, int) =20 -DEF_HELPER_FLAGS_3(faddd, 0, f64, env, f64, f64) -DEF_HELPER_FLAGS_3(fsubd, 0, f64, env, f64, f64) -DEF_HELPER_FLAGS_3(fmuld, 0, f64, env, f64, f64) -DEF_HELPER_FLAGS_3(fdivd, 0, f64, env, f64, f64) +DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64) +DEF_HELPER_FLAGS_3(fsubd, TCG_CALL_NO_WG, f64, env, f64, f64) +DEF_HELPER_FLAGS_3(fmuld, TCG_CALL_NO_WG, f64, env, f64, f64) +DEF_HELPER_FLAGS_3(fdivd, TCG_CALL_NO_WG, f64, env, f64, f64) =20 -DEF_HELPER_FLAGS_3(faddq, 0, i128, env, i128, i128) -DEF_HELPER_FLAGS_3(fsubq, 0, i128, env, i128, i128) -DEF_HELPER_FLAGS_3(fmulq, 0, i128, env, i128, i128) -DEF_HELPER_FLAGS_3(fdivq, 0, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(faddq, TCG_CALL_NO_WG, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(fsubq, TCG_CALL_NO_WG, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(fmulq, TCG_CALL_NO_WG, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(fdivq, TCG_CALL_NO_WG, i128, env, i128, i128) =20 -DEF_HELPER_FLAGS_3(fadds, 0, f32, env, f32, f32) -DEF_HELPER_FLAGS_3(fsubs, 0, f32, env, f32, f32) -DEF_HELPER_FLAGS_3(fmuls, 0, f32, env, f32, f32) -DEF_HELPER_FLAGS_3(fdivs, 0, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fadds, TCG_CALL_NO_WG, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fsubs, TCG_CALL_NO_WG, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fmuls, TCG_CALL_NO_WG, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_WG, f32, env, f32, f32) =20 -DEF_HELPER_FLAGS_3(fsmuld, 0, f64, env, f32, f32) -DEF_HELPER_FLAGS_3(fdmulq, 0, i128, env, f64, f64) +DEF_HELPER_FLAGS_3(fsmuld, TCG_CALL_NO_WG, f64, env, f32, f32) +DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_WG, i128, env, f64, f64) =20 -DEF_HELPER_FLAGS_2(fitod, 0, f64, env, s32) -DEF_HELPER_FLAGS_2(fitoq, 0, i128, env, s32) +DEF_HELPER_FLAGS_2(fitod, TCG_CALL_NO_WG, f64, env, s32) +DEF_HELPER_FLAGS_2(fitoq, TCG_CALL_NO_WG, i128, env, s32) =20 -DEF_HELPER_FLAGS_2(fitos, 0, f32, env, s32) +DEF_HELPER_FLAGS_2(fitos, TCG_CALL_NO_WG, f32, env, s32) =20 #ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_2(fxtos, 0, f32, env, s64) -DEF_HELPER_FLAGS_2(fxtod, 0, f64, env, s64) -DEF_HELPER_FLAGS_2(fxtoq, 0, i128, env, s64) +DEF_HELPER_FLAGS_2(fxtos, TCG_CALL_NO_WG, f32, env, s64) +DEF_HELPER_FLAGS_2(fxtod, TCG_CALL_NO_WG, f64, env, s64) +DEF_HELPER_FLAGS_2(fxtoq, TCG_CALL_NO_WG, i128, env, s64) #endif -DEF_HELPER_FLAGS_2(fdtos, 0, f32, env, f64) -DEF_HELPER_FLAGS_2(fstod, 0, f64, env, f32) -DEF_HELPER_FLAGS_2(fqtos, 0, f32, env, i128) -DEF_HELPER_FLAGS_2(fstoq, 0, i128, env, f32) -DEF_HELPER_FLAGS_2(fqtod, 0, f64, env, i128) -DEF_HELPER_FLAGS_2(fdtoq, 0, i128, env, f64) -DEF_HELPER_FLAGS_2(fstoi, 0, s32, env, f32) -DEF_HELPER_FLAGS_2(fdtoi, 0, s32, env, f64) -DEF_HELPER_FLAGS_2(fqtoi, 0, s32, env, i128) +DEF_HELPER_FLAGS_2(fdtos, TCG_CALL_NO_WG, f32, env, f64) +DEF_HELPER_FLAGS_2(fstod, TCG_CALL_NO_WG, f64, env, f32) +DEF_HELPER_FLAGS_2(fqtos, TCG_CALL_NO_WG, f32, env, i128) +DEF_HELPER_FLAGS_2(fstoq, TCG_CALL_NO_WG, i128, env, f32) +DEF_HELPER_FLAGS_2(fqtod, TCG_CALL_NO_WG, f64, env, i128) +DEF_HELPER_FLAGS_2(fdtoq, TCG_CALL_NO_WG, i128, env, f64) +DEF_HELPER_FLAGS_2(fstoi, TCG_CALL_NO_WG, s32, env, f32) +DEF_HELPER_FLAGS_2(fdtoi, TCG_CALL_NO_WG, s32, env, f64) +DEF_HELPER_FLAGS_2(fqtoi, TCG_CALL_NO_WG, s32, env, i128) #ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_2(fstox, 0, s64, env, f32) -DEF_HELPER_FLAGS_2(fdtox, 0, s64, env, f64) -DEF_HELPER_FLAGS_2(fqtox, 0, s64, env, i128) +DEF_HELPER_FLAGS_2(fstox, TCG_CALL_NO_WG, s64, env, f32) +DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_WG, s64, env, f64) +DEF_HELPER_FLAGS_2(fqtox, TCG_CALL_NO_WG, s64, env, i128) =20 DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index ac30f88810..796f448bfd 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -344,8 +344,7 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) } =20 #define GEN_FCMP(name, size, FS, E) \ - target_ulong glue(helper_, name) (CPUSPARCState *env, \ - Int128 src1, Int128 src2) \ + void glue(helper_, name)(CPUSPARCState *env, Int128 src1, Int128 src2)= \ { \ float128 reg1 =3D f128_in(src1); \ float128 reg2 =3D f128_in(src2); \ @@ -376,10 +375,10 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) fsr &=3D ~((FSR_FCC1 | FSR_FCC0) << FS); \ break; \ } \ - return fsr; \ + env->fsr =3D fsr; \ } #define GEN_FCMP_T(name, size, FS, E) \ - target_ulong glue(helper_, name)(CPUSPARCState *env, size src1, size s= rc2)\ + void glue(helper_, name)(CPUSPARCState *env, size src1, size src2) \ { \ FloatRelation ret; \ target_ulong fsr; \ @@ -407,7 +406,7 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) fsr &=3D ~((FSR_FCC1 | FSR_FCC0) << FS); \ break; \ } \ - return fsr; \ + env->fsr =3D fsr; \ } =20 GEN_FCMP_T(fcmps, float32, 0, 0); diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d2145dcc0b..4eb6291b81 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -99,7 +99,7 @@ =20 /* global register indexes */ static TCGv_ptr cpu_regwptr; -static TCGv cpu_fsr, cpu_pc, cpu_npc; +static TCGv cpu_pc, cpu_npc; static TCGv cpu_regs[32]; static TCGv cpu_y; static TCGv cpu_tbr; @@ -1097,7 +1097,7 @@ static void gen_compare(DisasCompare *cmp, bool xcc, = unsigned int cond, static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int = cond) { unsigned int offset; - TCGv r_dst; + TCGv r_dst, fsr; =20 /* For now we still generate a straight boolean result. */ cmp->cond =3D TCG_COND_NE; @@ -1120,54 +1120,56 @@ static void gen_fcompare(DisasCompare *cmp, unsigne= d int cc, unsigned int cond) break; } =20 + fsr =3D tcg_temp_new(); + tcg_gen_ld_tl(fsr, tcg_env, offsetof(CPUSPARCState, fsr)); switch (cond) { case 0x0: gen_op_eval_bn(r_dst); break; case 0x1: - gen_op_eval_fbne(r_dst, cpu_fsr, offset); + gen_op_eval_fbne(r_dst, fsr, offset); break; case 0x2: - gen_op_eval_fblg(r_dst, cpu_fsr, offset); + gen_op_eval_fblg(r_dst, fsr, offset); break; case 0x3: - gen_op_eval_fbul(r_dst, cpu_fsr, offset); + gen_op_eval_fbul(r_dst, fsr, offset); break; case 0x4: - gen_op_eval_fbl(r_dst, cpu_fsr, offset); + gen_op_eval_fbl(r_dst, fsr, offset); break; case 0x5: - gen_op_eval_fbug(r_dst, cpu_fsr, offset); + gen_op_eval_fbug(r_dst, fsr, offset); break; case 0x6: - gen_op_eval_fbg(r_dst, cpu_fsr, offset); + gen_op_eval_fbg(r_dst, fsr, offset); break; case 0x7: - gen_op_eval_fbu(r_dst, cpu_fsr, offset); + gen_op_eval_fbu(r_dst, fsr, offset); break; case 0x8: gen_op_eval_ba(r_dst); break; case 0x9: - gen_op_eval_fbe(r_dst, cpu_fsr, offset); + gen_op_eval_fbe(r_dst, fsr, offset); break; case 0xa: - gen_op_eval_fbue(r_dst, cpu_fsr, offset); + gen_op_eval_fbue(r_dst, fsr, offset); break; case 0xb: - gen_op_eval_fbge(r_dst, cpu_fsr, offset); + gen_op_eval_fbge(r_dst, fsr, offset); break; case 0xc: - gen_op_eval_fbuge(r_dst, cpu_fsr, offset); + gen_op_eval_fbuge(r_dst, fsr, offset); break; case 0xd: - gen_op_eval_fble(r_dst, cpu_fsr, offset); + gen_op_eval_fble(r_dst, fsr, offset); break; case 0xe: - gen_op_eval_fbule(r_dst, cpu_fsr, offset); + gen_op_eval_fbule(r_dst, fsr, offset); break; case 0xf: - gen_op_eval_fbo(r_dst, cpu_fsr, offset); + gen_op_eval_fbo(r_dst, fsr, offset); break; } } @@ -1264,16 +1266,16 @@ static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1,= TCGv_i32 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmps(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmps(tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmps_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmps_fcc1(tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmps_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmps_fcc2(tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmps_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmps_fcc3(tcg_env, r_rs1, r_rs2); break; } } @@ -1282,16 +1284,16 @@ static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1,= TCGv_i64 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpd(tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmpd_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpd_fcc1(tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmpd_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpd_fcc2(tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmpd_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpd_fcc3(tcg_env, r_rs1, r_rs2); break; } } @@ -1300,16 +1302,16 @@ static void gen_op_fcmpq(int fccno, TCGv_i128 r_rs1= , TCGv_i128 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmpq(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpq(tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmpq_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpq_fcc1(tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmpq_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpq_fcc2(tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmpq_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpq_fcc3(tcg_env, r_rs1, r_rs2); break; } } @@ -1318,16 +1320,16 @@ static void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1= , TCGv_i32 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmpes(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpes(tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmpes_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpes_fcc1(tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmpes_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpes_fcc2(tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmpes_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpes_fcc3(tcg_env, r_rs1, r_rs2); break; } } @@ -1336,16 +1338,16 @@ static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1= , TCGv_i64 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmped(tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmped_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmped_fcc1(tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmped_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmped_fcc2(tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmped_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmped_fcc3(tcg_env, r_rs1, r_rs2); break; } } @@ -1354,16 +1356,16 @@ static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs= 1, TCGv_i128 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmpeq(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpeq(tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmpeq_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpeq_fcc1(tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmpeq_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpeq_fcc2(tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmpeq_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpeq_fcc3(tcg_env, r_rs1, r_rs2); break; } } @@ -1372,32 +1374,32 @@ static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs= 1, TCGv_i128 r_rs2) =20 static void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) { - gen_helper_fcmps(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmps(tcg_env, r_rs1, r_rs2); } =20 static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) { - gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpd(tcg_env, r_rs1, r_rs2); } =20 static void gen_op_fcmpq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) { - gen_helper_fcmpq(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpq(tcg_env, r_rs1, r_rs2); } =20 static void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) { - gen_helper_fcmpes(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpes(tcg_env, r_rs1, r_rs2); } =20 static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) { - gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmped(tcg_env, r_rs1, r_rs2); } =20 static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) { - gen_helper_fcmpeq(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpeq(tcg_env, r_rs1, r_rs2); } #endif =20 @@ -4413,8 +4415,9 @@ static bool do_ldfsr(DisasContext *dc, arg_r_r_ri *a,= MemOp mop, tnew =3D tcg_temp_new(); told =3D tcg_temp_new(); tcg_gen_qemu_ld_tl(tnew, addr, dc->mem_idx, mop | MO_ALIGN); + tcg_gen_ld_tl(told, tcg_env, offsetof(CPUSPARCState, fsr)); tcg_gen_andi_tl(tnew, tnew, new_mask); - tcg_gen_andi_tl(told, cpu_fsr, old_mask); + tcg_gen_andi_tl(told, told, old_mask); tcg_gen_or_tl(tnew, tnew, told); gen_helper_set_fsr_noftt(tcg_env, tnew); return advance_pc(dc); @@ -5342,7 +5345,6 @@ void sparc_tcg_init(void) { &cpu_icc_Z, offsetof(CPUSPARCState, icc_Z), "icc_Z" }, { &cpu_icc_C, offsetof(CPUSPARCState, icc_C), "icc_C" }, { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" }, - { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" }, { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" }, { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" }, { &cpu_y, offsetof(CPUSPARCState, y), "y" }, --=20 2.34.1 From nobody Wed Nov 27 11:39:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699033296; cv=none; d=zohomail.com; s=zohoarc; b=egV+yDMjikJSAby76cM9uZYWmQ+2EGzVgQsHpYHFXbS6tEGFpVgbItLLd793lpcftS/KZA4hw7WO4bnJ4AE4E1W+vjyfueHdn2k1ZQmaeYf6bitpxfxsSPWEaKnUio1JkvDkW4YX21SmbRNEw8eVBk4F0IivRlPFOTza8qo7a9A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699033296; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id c10-20020a170902c1ca00b001c0cb2aa2easm1628267plc.121.2023.11.03.10.38.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 10:38:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699033139; x=1699637939; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tGowMY5jrj7+UydwFVH5zBuDc0jY2dKtYFqcxIfJu3Y=; b=xtYQqhw14rGeHyjvGUvGkh2vEOuADFKiSg1esfVnMs303T3xtJONg8xxa3w1CPgWBB VJFgLziZHastHgrEeGEyqZpaHJwT9KU7mz6qN7ueMghgtrPgWzZVr6WU/9dV66TWZzkG 2uCdExA+WxsGhX9YpBp2AnyiOEa9raiGmisJDxze2dPZLAPd03Kepl3gykqqu/bEc6z8 JcT2pPD9nbXQ8BytVIEUKKxdkMfEGksN9rBVTfnnyyermUcWyn5jBbIiYjwTHnTvtmVa MuNJ3l/Kg9rgkbfgNekyCzeGck7OXOVaKnSyllnt2dECENb/m121LqOL/LOycWonxRWj iIUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699033139; x=1699637939; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tGowMY5jrj7+UydwFVH5zBuDc0jY2dKtYFqcxIfJu3Y=; b=IEkI4QQ18t8WH3f5ARbAOTS4FqYgQiMqM9ajdKUO870Tbqc2eIct0o3mdtgPhvAu1K j5Y64wTGmYPTd3U3uMSQzju5kFXyNIebBonjy+zWF+yO+JHNAssTVXOdBpCEuvangLvg 9l2z2oRKZRGe0MavJWS2sxJklIneUawFlhltsVqxL/KCVe7zzQ2nAxSkZugMZrz38U5W JUZAsuDIgXWXqPwJmULjSfqLnFTANkhZvwqFilzXMrOlm7kq7qvDVGsXTG2IXBHhyR/e h20EXrVcCRav/IJyY3WvZuDC76JgJHE8qsDi5ZHa4A4zrXcKE/PHz1xbKy+q3I7k3OEU LPXQ== X-Gm-Message-State: AOJu0YxKQpb+wjaPqyRpBui1sg0BrsIc1ONjMR7iTi1PAx+k5qRxhzuf Eknedn8XpaatqamvXhkIFnVgve4ABqunqixPukw= X-Google-Smtp-Source: AGHT+IG0kgbu+SSgz1Jwb8RABfszg5629YNF6eiffORXcjFqn/5eEVRVr+boihBVbwOZrOiRY/W/ag== X-Received: by 2002:a17:903:2346:b0:1cc:5029:e3d4 with SMTP id c6-20020a170903234600b001cc5029e3d4mr4002854plh.23.1699033139522; Fri, 03 Nov 2023 10:38:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH 21/22] target/sparc: Split fcc out of env->fsr Date: Fri, 3 Nov 2023 10:38:40 -0700 Message-Id: <20231103173841.33651-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103173841.33651-1-richard.henderson@linaro.org> References: <20231103173841.33651-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033296750100006 Content-Type: text/plain; charset="utf-8" Represent each fcc field separately from the rest of fsr. This vastly simplifies floating-point comparisons. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland --- target/sparc/cpu.h | 20 +- target/sparc/helper.h | 34 +-- target/sparc/fop_helper.c | 169 ++++++------- target/sparc/translate.c | 503 +++++++++----------------------------- 4 files changed, 201 insertions(+), 525 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 90a7dfb004..30bab9a7b3 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -31,8 +31,10 @@ =20 #if !defined(TARGET_SPARC64) #define TARGET_DPREGS 16 +#define TARGET_FCCREGS 1 #else #define TARGET_DPREGS 32 +#define TARGET_FCCREGS 4 #endif =20 /*#define EXCP_INTERRUPT 0x100*/ @@ -203,24 +205,19 @@ enum { #ifdef TARGET_SPARC64 #define FSR_FTT_NMASK 0xfffffffffffe3fffULL #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL -#define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL -#define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL -#define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL #else #define FSR_FTT_NMASK 0xfffe3fffULL #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL -#define FSR_LDFSR_OLDMASK 0x000fc000ULL #endif -#define FSR_LDFSR_MASK 0xcfc00fffULL #define FSR_FTT_IEEE_EXCP (1ULL << 14) #define FSR_FTT_UNIMPFPOP (3ULL << 14) #define FSR_FTT_SEQ_ERROR (4ULL << 14) #define FSR_FTT_INVAL_FPR (6ULL << 14) =20 -#define FSR_FCC1_SHIFT 11 -#define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT) -#define FSR_FCC0_SHIFT 10 -#define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT) +#define FSR_FCC0_SHIFT 10 +#define FSR_FCC1_SHIFT 32 +#define FSR_FCC2_SHIFT 34 +#define FSR_FCC3_SHIFT 36 =20 /* MMU */ #define MMU_E (1<<0) @@ -467,8 +464,9 @@ struct CPUArchState { temporary register when possible) */ =20 /* FPU State Register, in parts */ - target_ulong fsr; /* rm, tem, aexc, fcc* */ - uint32_t fsr_cexc_ftt; /* cexc, ftt */ + uint32_t fsr; /* rm, tem, aexc */ + uint32_t fsr_cexc_ftt; /* cexc, ftt */ + uint32_t fcc[TARGET_FCCREGS]; /* fcc* */ =20 CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ uint32_t cwp; /* index of current register window (extracted diff --git a/target/sparc/helper.h b/target/sparc/helper.h index c8e14fe371..6a42ba4e9e 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -36,36 +36,16 @@ DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl= , int, i32) DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32) #endif DEF_HELPER_FLAGS_1(get_fsr, TCG_CALL_NO_WG_SE, tl, env) -DEF_HELPER_FLAGS_2(set_fsr_noftt, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_2(set_fsr_nofcc_noftt, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_WG, f32, env, f32) DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_WG, f64, env, f64) DEF_HELPER_FLAGS_2(fsqrtq, TCG_CALL_NO_WG, i128, env, i128) -DEF_HELPER_FLAGS_3(fcmps, TCG_CALL_NO_WG, void, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, void, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpes, TCG_CALL_NO_WG, void, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, void, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, void, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, void, env, i128, i128) -#ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_3(fcmps_fcc1, TCG_CALL_NO_WG, void, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmps_fcc2, TCG_CALL_NO_WG, void, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmps_fcc3, TCG_CALL_NO_WG, void, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpd_fcc1, TCG_CALL_NO_WG, void, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpd_fcc2, TCG_CALL_NO_WG, void, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpd_fcc3, TCG_CALL_NO_WG, void, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpes_fcc1, TCG_CALL_NO_WG, void, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpes_fcc2, TCG_CALL_NO_WG, void, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpes_fcc3, TCG_CALL_NO_WG, void, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmped_fcc1, TCG_CALL_NO_WG, void, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmped_fcc2, TCG_CALL_NO_WG, void, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmped_fcc3, TCG_CALL_NO_WG, void, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpq_fcc1, TCG_CALL_NO_WG, void, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpq_fcc2, TCG_CALL_NO_WG, void, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpq_fcc3, TCG_CALL_NO_WG, void, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq_fcc1, TCG_CALL_NO_WG, void, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq_fcc2, TCG_CALL_NO_WG, void, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq_fcc3, TCG_CALL_NO_WG, void, env, i128, i128) -#endif +DEF_HELPER_FLAGS_3(fcmps, TCG_CALL_NO_WG, i32, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpes, TCG_CALL_NO_WG, i32, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128) DEF_HELPER_2(raise_exception, noreturn, env, int) =20 DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 796f448bfd..1205a599ef 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -343,113 +343,80 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) return f128_ret(ret); } =20 -#define GEN_FCMP(name, size, FS, E) \ - void glue(helper_, name)(CPUSPARCState *env, Int128 src1, Int128 src2)= \ - { \ - float128 reg1 =3D f128_in(src1); \ - float128 reg2 =3D f128_in(src2); \ - FloatRelation ret; \ - target_ulong fsr; \ - if (E) { \ - ret =3D glue(size, _compare)(reg1, reg2, &env->fp_status); \ - } else { \ - ret =3D glue(size, _compare_quiet)(reg1, reg2, \ - &env->fp_status); \ - } \ - check_ieee_exceptions(env, GETPC()); \ - fsr =3D env->fsr; \ - switch (ret) { \ - case float_relation_unordered: \ - fsr |=3D (FSR_FCC1 | FSR_FCC0) << FS; \ - fsr |=3D FSR_NVA; \ - break; \ - case float_relation_less: \ - fsr &=3D ~(FSR_FCC1) << FS; \ - fsr |=3D FSR_FCC0 << FS; \ - break; \ - case float_relation_greater: \ - fsr &=3D ~(FSR_FCC0) << FS; \ - fsr |=3D FSR_FCC1 << FS; \ - break; \ - default: \ - fsr &=3D ~((FSR_FCC1 | FSR_FCC0) << FS); \ - break; \ - } \ - env->fsr =3D fsr; \ - } -#define GEN_FCMP_T(name, size, FS, E) \ - void glue(helper_, name)(CPUSPARCState *env, size src1, size src2) \ - { \ - FloatRelation ret; \ - target_ulong fsr; \ - if (E) { \ - ret =3D glue(size, _compare)(src1, src2, &env->fp_status); \ - } else { \ - ret =3D glue(size, _compare_quiet)(src1, src2, \ - &env->fp_status); \ - } \ - check_ieee_exceptions(env, GETPC()); \ - fsr =3D env->fsr; \ - switch (ret) { \ - case float_relation_unordered: \ - fsr |=3D (FSR_FCC1 | FSR_FCC0) << FS; \ - break; \ - case float_relation_less: \ - fsr &=3D ~(FSR_FCC1 << FS); \ - fsr |=3D FSR_FCC0 << FS; \ - break; \ - case float_relation_greater: \ - fsr &=3D ~(FSR_FCC0 << FS); \ - fsr |=3D FSR_FCC1 << FS; \ - break; \ - default: \ - fsr &=3D ~((FSR_FCC1 | FSR_FCC0) << FS); \ - break; \ - } \ - env->fsr =3D fsr; \ +static uint32_t finish_fcmp(CPUSPARCState *env, FloatRelation r, uintptr_t= ra) +{ + check_ieee_exceptions(env, ra); + + /* + * FCC values: + * 0 =3D + * 1 < + * 2 > + * 3 unordered + */ + switch (r) { + case float_relation_equal: + return 0; + case float_relation_less: + return 1; + case float_relation_greater: + return 2; + case float_relation_unordered: + env->fsr |=3D FSR_NVA; + return 3; } + g_assert_not_reached(); +} =20 -GEN_FCMP_T(fcmps, float32, 0, 0); -GEN_FCMP_T(fcmpd, float64, 0, 0); +uint32_t helper_fcmps(CPUSPARCState *env, float32 src1, float32 src2) +{ + FloatRelation r =3D float32_compare_quiet(src1, src2, &env->fp_status); + return finish_fcmp(env, r, GETPC()); +} =20 -GEN_FCMP_T(fcmpes, float32, 0, 1); -GEN_FCMP_T(fcmped, float64, 0, 1); +uint32_t helper_fcmpes(CPUSPARCState *env, float32 src1, float32 src2) +{ + FloatRelation r =3D float32_compare(src1, src2, &env->fp_status); + return finish_fcmp(env, r, GETPC()); +} =20 -GEN_FCMP(fcmpq, float128, 0, 0); -GEN_FCMP(fcmpeq, float128, 0, 1); +uint32_t helper_fcmpd(CPUSPARCState *env, float64 src1, float64 src2) +{ + FloatRelation r =3D float64_compare_quiet(src1, src2, &env->fp_status); + return finish_fcmp(env, r, GETPC()); +} =20 -#ifdef TARGET_SPARC64 -GEN_FCMP_T(fcmps_fcc1, float32, 22, 0); -GEN_FCMP_T(fcmpd_fcc1, float64, 22, 0); -GEN_FCMP(fcmpq_fcc1, float128, 22, 0); +uint32_t helper_fcmped(CPUSPARCState *env, float64 src1, float64 src2) +{ + FloatRelation r =3D float64_compare(src1, src2, &env->fp_status); + return finish_fcmp(env, r, GETPC()); +} =20 -GEN_FCMP_T(fcmps_fcc2, float32, 24, 0); -GEN_FCMP_T(fcmpd_fcc2, float64, 24, 0); -GEN_FCMP(fcmpq_fcc2, float128, 24, 0); +uint32_t helper_fcmpq(CPUSPARCState *env, Int128 src1, Int128 src2) +{ + FloatRelation r =3D float128_compare_quiet(f128_in(src1), f128_in(src2= ), + &env->fp_status); + return finish_fcmp(env, r, GETPC()); +} =20 -GEN_FCMP_T(fcmps_fcc3, float32, 26, 0); -GEN_FCMP_T(fcmpd_fcc3, float64, 26, 0); -GEN_FCMP(fcmpq_fcc3, float128, 26, 0); - -GEN_FCMP_T(fcmpes_fcc1, float32, 22, 1); -GEN_FCMP_T(fcmped_fcc1, float64, 22, 1); -GEN_FCMP(fcmpeq_fcc1, float128, 22, 1); - -GEN_FCMP_T(fcmpes_fcc2, float32, 24, 1); -GEN_FCMP_T(fcmped_fcc2, float64, 24, 1); -GEN_FCMP(fcmpeq_fcc2, float128, 24, 1); - -GEN_FCMP_T(fcmpes_fcc3, float32, 26, 1); -GEN_FCMP_T(fcmped_fcc3, float64, 26, 1); -GEN_FCMP(fcmpeq_fcc3, float128, 26, 1); -#endif -#undef GEN_FCMP_T -#undef GEN_FCMP +uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2) +{ + FloatRelation r =3D float128_compare(f128_in(src1), f128_in(src2), + &env->fp_status); + return finish_fcmp(env, r, GETPC()); +} =20 target_ulong cpu_get_fsr(CPUSPARCState *env) { target_ulong fsr =3D env->fsr | env->fsr_cexc_ftt; =20 + fsr |=3D env->fcc[0] << FSR_FCC0_SHIFT; +#ifdef TARGET_SPARC64 + fsr |=3D (uint64_t)env->fcc[1] << FSR_FCC1_SHIFT; + fsr |=3D (uint64_t)env->fcc[2] << FSR_FCC2_SHIFT; + fsr |=3D (uint64_t)env->fcc[3] << FSR_FCC3_SHIFT; +#endif + /* VER is kept completely separate until re-assembly. */ fsr |=3D env->def.fpu_version; =20 @@ -465,7 +432,7 @@ static void set_fsr_nonsplit(CPUSPARCState *env, target= _ulong fsr) { int rnd_mode; =20 - env->fsr =3D fsr & ~(FSR_VER_MASK | FSR_CEXC_MASK | FSR_FTT_MASK); + env->fsr =3D fsr & (FSR_RD_MASK | FSR_TEM_MASK | FSR_AEXC_MASK); =20 switch (fsr & FSR_RD_MASK) { case FSR_RD_NEAREST: @@ -488,10 +455,18 @@ static void set_fsr_nonsplit(CPUSPARCState *env, targ= et_ulong fsr) void cpu_put_fsr(CPUSPARCState *env, target_ulong fsr) { env->fsr_cexc_ftt =3D fsr & (FSR_CEXC_MASK | FSR_FTT_MASK); + + env->fcc[0] =3D extract32(fsr, FSR_FCC0_SHIFT, 2); +#ifdef TARGET_SPARC64 + env->fcc[1] =3D extract64(fsr, FSR_FCC1_SHIFT, 2); + env->fcc[2] =3D extract64(fsr, FSR_FCC2_SHIFT, 2); + env->fcc[3] =3D extract64(fsr, FSR_FCC3_SHIFT, 2); +#endif + set_fsr_nonsplit(env, fsr); } =20 -void helper_set_fsr_noftt(CPUSPARCState *env, target_ulong fsr) +void helper_set_fsr_nofcc_noftt(CPUSPARCState *env, uint32_t fsr) { env->fsr_cexc_ftt &=3D FSR_FTT_MASK; env->fsr_cexc_ftt |=3D fsr & FSR_CEXC_MASK; diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 4eb6291b81..b83b4369fd 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -83,8 +83,6 @@ # define gen_helper_fxtoq ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fxtos ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_pdist ({ qemu_build_not_reached(); NULL= ; }) -# define FSR_LDXFSR_MASK 0 -# define FSR_LDXFSR_OLDMASK 0 # define MAXTL_MASK 0 #endif =20 @@ -130,6 +128,7 @@ static TCGv cpu_gsr; =20 /* Floating point registers */ static TCGv_i64 cpu_fpr[TARGET_DPREGS]; +static TCGv_i32 cpu_fcc[TARGET_FCCREGS]; =20 #define env_field_offsetof(X) offsetof(CPUSPARCState, X) #ifdef TARGET_SPARC64 @@ -719,159 +718,6 @@ static void gen_op_bshuffle(TCGv_i64 dst, TCGv_i64 sr= c1, TCGv_i64 src2) #endif } =20 -// 1 -static void gen_op_eval_ba(TCGv dst) -{ - tcg_gen_movi_tl(dst, 1); -} - -// 0 -static void gen_op_eval_bn(TCGv dst) -{ - tcg_gen_movi_tl(dst, 0); -} - -/* - FPSR bit field FCC1 | FCC0: - 0 =3D - 1 < - 2 > - 3 unordered -*/ -static void gen_mov_reg_FCC0(TCGv reg, TCGv src, - unsigned int fcc_offset) -{ - tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset); - tcg_gen_andi_tl(reg, reg, 0x1); -} - -static void gen_mov_reg_FCC1(TCGv reg, TCGv src, unsigned int fcc_offset) -{ - tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset); - tcg_gen_andi_tl(reg, reg, 0x1); -} - -// !0: FCC0 | FCC1 -static void gen_op_eval_fbne(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_or_tl(dst, dst, t0); -} - -// 1 or 2: FCC0 ^ FCC1 -static void gen_op_eval_fblg(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_xor_tl(dst, dst, t0); -} - -// 1 or 3: FCC0 -static void gen_op_eval_fbul(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - gen_mov_reg_FCC0(dst, src, fcc_offset); -} - -// 1: FCC0 & !FCC1 -static void gen_op_eval_fbl(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_andc_tl(dst, dst, t0); -} - -// 2 or 3: FCC1 -static void gen_op_eval_fbug(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - gen_mov_reg_FCC1(dst, src, fcc_offset); -} - -// 2: !FCC0 & FCC1 -static void gen_op_eval_fbg(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_andc_tl(dst, t0, dst); -} - -// 3: FCC0 & FCC1 -static void gen_op_eval_fbu(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_and_tl(dst, dst, t0); -} - -// 0: !(FCC0 | FCC1) -static void gen_op_eval_fbe(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_or_tl(dst, dst, t0); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// 0 or 3: !(FCC0 ^ FCC1) -static void gen_op_eval_fbue(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_xor_tl(dst, dst, t0); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// 0 or 2: !FCC0 -static void gen_op_eval_fbge(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - gen_mov_reg_FCC0(dst, src, fcc_offset); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// !1: !(FCC0 & !FCC1) -static void gen_op_eval_fbuge(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_andc_tl(dst, dst, t0); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// 0 or 1: !FCC1 -static void gen_op_eval_fble(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - gen_mov_reg_FCC1(dst, src, fcc_offset); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// !2: !(!FCC0 & FCC1) -static void gen_op_eval_fbule(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_andc_tl(dst, t0, dst); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// !3: !(FCC0 & FCC1) -static void gen_op_eval_fbo(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_and_tl(dst, dst, t0); - tcg_gen_xori_tl(dst, dst, 0x1); -} - static void finishing_insn(DisasContext *dc) { /* @@ -1096,82 +942,62 @@ static void gen_compare(DisasCompare *cmp, bool xcc,= unsigned int cond, =20 static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int = cond) { - unsigned int offset; - TCGv r_dst, fsr; + TCGv_i32 fcc =3D cpu_fcc[cc]; + TCGv_i32 c1 =3D fcc; + int c2 =3D 0; + TCGCond tcond; =20 - /* For now we still generate a straight boolean result. */ - cmp->cond =3D TCG_COND_NE; - cmp->c1 =3D r_dst =3D tcg_temp_new(); - cmp->c2 =3D 0; - - switch (cc) { - default: - case 0x0: - offset =3D 0; + /* + * FCC values: + * 0 =3D + * 1 < + * 2 > + * 3 unordered + */ + switch (cond & 7) { + case 0x0: /* fbn */ + tcond =3D TCG_COND_NEVER; break; - case 0x1: - offset =3D 32 - 10; + case 0x1: /* fbne : !0 */ + tcond =3D TCG_COND_NE; break; - case 0x2: - offset =3D 34 - 10; + case 0x2: /* fblg : 1 or 2 */ + /* fcc in {1,2} - 1 -> fcc in {0,1} */ + c1 =3D tcg_temp_new_i32(); + tcg_gen_addi_i32(c1, fcc, -1); + c2 =3D 1; + tcond =3D TCG_COND_LEU; break; - case 0x3: - offset =3D 36 - 10; + case 0x3: /* fbul : 1 or 3 */ + c1 =3D tcg_temp_new_i32(); + tcg_gen_andi_i32(c1, fcc, 1); + tcond =3D TCG_COND_NE; + break; + case 0x4: /* fbl : 1 */ + c2 =3D 1; + tcond =3D TCG_COND_EQ; + break; + case 0x5: /* fbug : 2 or 3 */ + c2 =3D 2; + tcond =3D TCG_COND_GEU; + break; + case 0x6: /* fbg : 2 */ + c2 =3D 2; + tcond =3D TCG_COND_EQ; + break; + case 0x7: /* fbu : 3 */ + c2 =3D 3; + tcond =3D TCG_COND_EQ; break; } - - fsr =3D tcg_temp_new(); - tcg_gen_ld_tl(fsr, tcg_env, offsetof(CPUSPARCState, fsr)); - switch (cond) { - case 0x0: - gen_op_eval_bn(r_dst); - break; - case 0x1: - gen_op_eval_fbne(r_dst, fsr, offset); - break; - case 0x2: - gen_op_eval_fblg(r_dst, fsr, offset); - break; - case 0x3: - gen_op_eval_fbul(r_dst, fsr, offset); - break; - case 0x4: - gen_op_eval_fbl(r_dst, fsr, offset); - break; - case 0x5: - gen_op_eval_fbug(r_dst, fsr, offset); - break; - case 0x6: - gen_op_eval_fbg(r_dst, fsr, offset); - break; - case 0x7: - gen_op_eval_fbu(r_dst, fsr, offset); - break; - case 0x8: - gen_op_eval_ba(r_dst); - break; - case 0x9: - gen_op_eval_fbe(r_dst, fsr, offset); - break; - case 0xa: - gen_op_eval_fbue(r_dst, fsr, offset); - break; - case 0xb: - gen_op_eval_fbge(r_dst, fsr, offset); - break; - case 0xc: - gen_op_eval_fbuge(r_dst, fsr, offset); - break; - case 0xd: - gen_op_eval_fble(r_dst, fsr, offset); - break; - case 0xe: - gen_op_eval_fbule(r_dst, fsr, offset); - break; - case 0xf: - gen_op_eval_fbo(r_dst, fsr, offset); - break; + if (cond & 8) { + tcond =3D tcg_invert_cond(tcond); } + + cmp->cond =3D tcond; + cmp->c2 =3D c2; + cmp->c1 =3D tcg_temp_new(); + tcg_gen_extu_i32_tl(cmp->c1, c1); } =20 static bool gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src) @@ -1261,148 +1087,6 @@ static void gen_op_fabsq(TCGv_i128 dst, TCGv_i128 s= rc) tcg_gen_concat_i64_i128(dst, l, h); } =20 -#ifdef TARGET_SPARC64 -static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) -{ - switch (fccno) { - case 0: - gen_helper_fcmps(tcg_env, r_rs1, r_rs2); - break; - case 1: - gen_helper_fcmps_fcc1(tcg_env, r_rs1, r_rs2); - break; - case 2: - gen_helper_fcmps_fcc2(tcg_env, r_rs1, r_rs2); - break; - case 3: - gen_helper_fcmps_fcc3(tcg_env, r_rs1, r_rs2); - break; - } -} - -static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) -{ - switch (fccno) { - case 0: - gen_helper_fcmpd(tcg_env, r_rs1, r_rs2); - break; - case 1: - gen_helper_fcmpd_fcc1(tcg_env, r_rs1, r_rs2); - break; - case 2: - gen_helper_fcmpd_fcc2(tcg_env, r_rs1, r_rs2); - break; - case 3: - gen_helper_fcmpd_fcc3(tcg_env, r_rs1, r_rs2); - break; - } -} - -static void gen_op_fcmpq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) -{ - switch (fccno) { - case 0: - gen_helper_fcmpq(tcg_env, r_rs1, r_rs2); - break; - case 1: - gen_helper_fcmpq_fcc1(tcg_env, r_rs1, r_rs2); - break; - case 2: - gen_helper_fcmpq_fcc2(tcg_env, r_rs1, r_rs2); - break; - case 3: - gen_helper_fcmpq_fcc3(tcg_env, r_rs1, r_rs2); - break; - } -} - -static void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) -{ - switch (fccno) { - case 0: - gen_helper_fcmpes(tcg_env, r_rs1, r_rs2); - break; - case 1: - gen_helper_fcmpes_fcc1(tcg_env, r_rs1, r_rs2); - break; - case 2: - gen_helper_fcmpes_fcc2(tcg_env, r_rs1, r_rs2); - break; - case 3: - gen_helper_fcmpes_fcc3(tcg_env, r_rs1, r_rs2); - break; - } -} - -static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) -{ - switch (fccno) { - case 0: - gen_helper_fcmped(tcg_env, r_rs1, r_rs2); - break; - case 1: - gen_helper_fcmped_fcc1(tcg_env, r_rs1, r_rs2); - break; - case 2: - gen_helper_fcmped_fcc2(tcg_env, r_rs1, r_rs2); - break; - case 3: - gen_helper_fcmped_fcc3(tcg_env, r_rs1, r_rs2); - break; - } -} - -static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) -{ - switch (fccno) { - case 0: - gen_helper_fcmpeq(tcg_env, r_rs1, r_rs2); - break; - case 1: - gen_helper_fcmpeq_fcc1(tcg_env, r_rs1, r_rs2); - break; - case 2: - gen_helper_fcmpeq_fcc2(tcg_env, r_rs1, r_rs2); - break; - case 3: - gen_helper_fcmpeq_fcc3(tcg_env, r_rs1, r_rs2); - break; - } -} - -#else - -static void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) -{ - gen_helper_fcmps(tcg_env, r_rs1, r_rs2); -} - -static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) -{ - gen_helper_fcmpd(tcg_env, r_rs1, r_rs2); -} - -static void gen_op_fcmpq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) -{ - gen_helper_fcmpq(tcg_env, r_rs1, r_rs2); -} - -static void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) -{ - gen_helper_fcmpes(tcg_env, r_rs1, r_rs2); -} - -static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) -{ - gen_helper_fcmped(tcg_env, r_rs1, r_rs2); -} - -static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) -{ - gen_helper_fcmpeq(tcg_env, r_rs1, r_rs2); -} -#endif - static void gen_op_fpexception_im(DisasContext *dc, int ftt) { /* @@ -4400,11 +4084,10 @@ static bool trans_STDFQ(DisasContext *dc, arg_STDFQ= *a) return true; } =20 -static bool do_ldfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop, - target_ulong new_mask, target_ulong old_mask) +static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri *a) { TCGv addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); - TCGv tnew, told; + TCGv_i32 tmp; =20 if (addr =3D=3D NULL) { return false; @@ -4412,19 +4095,48 @@ static bool do_ldfsr(DisasContext *dc, arg_r_r_ri *= a, MemOp mop, if (gen_trap_ifnofpu(dc)) { return true; } - tnew =3D tcg_temp_new(); - told =3D tcg_temp_new(); - tcg_gen_qemu_ld_tl(tnew, addr, dc->mem_idx, mop | MO_ALIGN); - tcg_gen_ld_tl(told, tcg_env, offsetof(CPUSPARCState, fsr)); - tcg_gen_andi_tl(tnew, tnew, new_mask); - tcg_gen_andi_tl(told, told, old_mask); - tcg_gen_or_tl(tnew, tnew, told); - gen_helper_set_fsr_noftt(tcg_env, tnew); + + tmp =3D tcg_temp_new_i32(); + tcg_gen_qemu_ld_i32(tmp, addr, dc->mem_idx, MO_TEUL | MO_ALIGN); + + tcg_gen_extract_i32(cpu_fcc[0], tmp, FSR_FCC0_SHIFT, 2); + /* LDFSR does not change FCC[1-3]. */ + + gen_helper_set_fsr_nofcc_noftt(tcg_env, tmp); return advance_pc(dc); } =20 -TRANS(LDFSR, ALL, do_ldfsr, a, MO_TEUL, FSR_LDFSR_MASK, FSR_LDFSR_OLDMASK) -TRANS(LDXFSR, 64, do_ldfsr, a, MO_TEUQ, FSR_LDXFSR_MASK, FSR_LDXFSR_OLDMAS= K) +static bool trans_LDXFSR(DisasContext *dc, arg_r_r_ri *a) +{ +#ifdef TARGET_SPARC64 + TCGv addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + TCGv_i64 t64; + TCGv_i32 lo, hi; + + if (addr =3D=3D NULL) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + + t64 =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(t64, addr, dc->mem_idx, MO_TEUQ | MO_ALIGN); + + lo =3D tcg_temp_new_i32(); + hi =3D cpu_fcc[3]; + tcg_gen_extr_i64_i32(lo, hi, t64); + tcg_gen_extract_i32(cpu_fcc[0], lo, FSR_FCC0_SHIFT, 2); + tcg_gen_extract_i32(cpu_fcc[1], hi, FSR_FCC1_SHIFT - 32, 2); + tcg_gen_extract_i32(cpu_fcc[2], hi, FSR_FCC2_SHIFT - 32, 2); + tcg_gen_extract_i32(cpu_fcc[3], hi, FSR_FCC3_SHIFT - 32, 2); + + gen_helper_set_fsr_nofcc_noftt(tcg_env, lo); + return advance_pc(dc); +#else + return false; +#endif +} =20 static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop) { @@ -5075,9 +4787,9 @@ static bool do_fcmps(DisasContext *dc, arg_FCMPs *a, = bool e) src1 =3D gen_load_fpr_F(dc, a->rs1); src2 =3D gen_load_fpr_F(dc, a->rs2); if (e) { - gen_op_fcmpes(a->cc, src1, src2); + gen_helper_fcmpes(cpu_fcc[a->cc], tcg_env, src1, src2); } else { - gen_op_fcmps(a->cc, src1, src2); + gen_helper_fcmps(cpu_fcc[a->cc], tcg_env, src1, src2); } return advance_pc(dc); } @@ -5099,9 +4811,9 @@ static bool do_fcmpd(DisasContext *dc, arg_FCMPd *a, = bool e) src1 =3D gen_load_fpr_D(dc, a->rs1); src2 =3D gen_load_fpr_D(dc, a->rs2); if (e) { - gen_op_fcmped(a->cc, src1, src2); + gen_helper_fcmped(cpu_fcc[a->cc], tcg_env, src1, src2); } else { - gen_op_fcmpd(a->cc, src1, src2); + gen_helper_fcmpd(cpu_fcc[a->cc], tcg_env, src1, src2); } return advance_pc(dc); } @@ -5126,9 +4838,9 @@ static bool do_fcmpq(DisasContext *dc, arg_FCMPq *a, = bool e) src1 =3D gen_load_fpr_Q(dc, a->rs1); src2 =3D gen_load_fpr_Q(dc, a->rs2); if (e) { - gen_op_fcmpeq(a->cc, src1, src2); + gen_helper_fcmpeq(cpu_fcc[a->cc], tcg_env, src1, src2); } else { - gen_op_fcmpq(a->cc, src1, src2); + gen_helper_fcmpq(cpu_fcc[a->cc], tcg_env, src1, src2); } return advance_pc(dc); } @@ -5334,6 +5046,18 @@ void sparc_tcg_init(void) "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62", }; =20 + static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[= ] =3D { +#ifdef TARGET_SPARC64 + { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" }, + { &cpu_fcc[0], offsetof(CPUSPARCState, fcc[0]), "fcc0" }, + { &cpu_fcc[1], offsetof(CPUSPARCState, fcc[1]), "fcc1" }, + { &cpu_fcc[2], offsetof(CPUSPARCState, fcc[2]), "fcc2" }, + { &cpu_fcc[3], offsetof(CPUSPARCState, fcc[3]), "fcc3" }, +#else + { &cpu_fcc[0], offsetof(CPUSPARCState, fcc[0]), "fcc" }, +#endif + }; + static const struct { TCGv *ptr; int off; const char *name; } rtl[] = =3D { #ifdef TARGET_SPARC64 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" }, @@ -5357,6 +5081,10 @@ void sparc_tcg_init(void) offsetof(CPUSPARCState, regwptr), "regwptr"); =20 + for (i =3D 0; i < ARRAY_SIZE(r32); ++i) { + *r32[i].ptr =3D tcg_global_mem_new_i32(tcg_env, r32[i].off, r32[i]= .name); + } + for (i =3D 0; i < ARRAY_SIZE(rtl); ++i) { *rtl[i].ptr =3D tcg_global_mem_new(tcg_env, rtl[i].off, rtl[i].nam= e); } @@ -5379,11 +5107,6 @@ void sparc_tcg_init(void) offsetof(CPUSPARCState, fpr[i]= ), fregnames[i]); } - -#ifdef TARGET_SPARC64 - cpu_fprs =3D tcg_global_mem_new_i32(tcg_env, - offsetof(CPUSPARCState, fprs), "fprs= "); -#endif } =20 void sparc_restore_state_to_opc(CPUState *cs, --=20 2.34.1 From nobody Wed Nov 27 11:39:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1699033296; cv=none; d=zohomail.com; s=zohoarc; b=P0mer7NqjkdEPGohLYwhcK7/5dXdbAFoUv7HAMiltJiiOns3iEFpvLJv044Z1scTgsbX7pOy7H1kMDSUpX8hYhaLmT6NElivDqNCtxyYHhagAa5uoHnX81TuqhAGtcbfUrLqgOP7RkoDCrszr8acgvxETy7QhMeLCQo7+7yQ+20= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699033296; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id c10-20020a170902c1ca00b001c0cb2aa2easm1628267plc.121.2023.11.03.10.38.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 10:38:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699033140; x=1699637940; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NhQ6Rz7YzStm0UnlSc7WpS9+YP7leMvfV4vMqg/a6gw=; b=gcG7y38j9DcPedewoZBelol68BtveeXXli+n+SpU7NqbaPzm6s4TmiJp1SNS1Rw48l txfsqcGCo+CXi610Nj16lqmrnnVq8VfjvT2unaxfV49uL5Fd2bPqmt9hpwM+o+nyuQOK bszfAuyLlBS8kxt+gFzt+RihVZCsvu1e4lVs8lJjoiM/UP5ceQULz7y6nRGoTFMTUvs6 dERUvMl4SypE0dO4LWIEhpG1nuwZRLoaYFHIUJodgweGJQAUE0E5i3MB65Lr+CHbAJxy kqhXkpPEH02u/HzNjVmDcyKq5cs+wTDNsAvhg5TGMPhOCLSMYnv7YYP7jd0DHqlyefgR wINQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699033140; x=1699637940; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NhQ6Rz7YzStm0UnlSc7WpS9+YP7leMvfV4vMqg/a6gw=; b=GpDy+09y/rFXue/qgSO0E76aIoHfkbZG9LM2OqT1Cb9oM/TXEnVU7h6XJ+59GFBPC6 Fjz60EaM2IL8asiBc3fOznMsYt0q56wB/tbdl4mNsMKz1iglWOfCoTtB10MBkndify3w Z2l0bgrT7i91t6JZy8U4vJ1lrSXOkLO5OMnvH5Q6K+zCy1dUi8ixcLMeNRTLly+tOaQ5 mPyVLEv5+Fq4PdPUb4qAW2YVI3APOOGnfUJzaGk+ZuHW1vsHe39bDr2imbXAVS7yklFK Sm5HqFmQVGgoaUxaKdW5KxggJ15mGKWHLhvpM2yRkDQWIDUJxBoC9mCfXdSCXEKfIbx2 Bj5A== X-Gm-Message-State: AOJu0YwM69P9mKovTiRLBftwFMmvfpG0NoHLA19WjoVTggS+T0S6Y9vd /1P+GcLTpqNOY3nDo9Al8NRvBqOVZT8bMdX5GYY= X-Google-Smtp-Source: AGHT+IFEI8grCIE4F+NmpGpRZfjnUPmcyrE0ERonGY5kVIiLM7aUvf498Pspy4VVY4TUa4iFHYKRyg== X-Received: by 2002:a17:903:24d:b0:1cc:9781:4782 with SMTP id j13-20020a170903024d00b001cc97814782mr4681845plh.62.1699033140262; Fri, 03 Nov 2023 10:39:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH 22/22] target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASK Date: Fri, 3 Nov 2023 10:38:41 -0700 Message-Id: <20231103173841.33651-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103173841.33651-1-richard.henderson@linaro.org> References: <20231103173841.33651-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699033296709100005 Content-Type: text/plain; charset="utf-8" These macros are no longer used. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Tested-by: Mark Cave-Ayland --- target/sparc/cpu.h | 7 ------- 1 file changed, 7 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 30bab9a7b3..9ca9fb30ff 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -202,13 +202,6 @@ enum { #define FSR_FTT1 (1ULL << 15) #define FSR_FTT0 (1ULL << 14) #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) -#ifdef TARGET_SPARC64 -#define FSR_FTT_NMASK 0xfffffffffffe3fffULL -#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL -#else -#define FSR_FTT_NMASK 0xfffe3fffULL -#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL -#endif #define FSR_FTT_IEEE_EXCP (1ULL << 14) #define FSR_FTT_UNIMPFPOP (3ULL << 14) #define FSR_FTT_SEQ_ERROR (4ULL << 14) --=20 2.34.1