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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=ltaylorsimpson@gmail.com; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1699028660135100006 We divide gen_analyze_funcs.py into 3 phases Declare the operands Analyze the register reads Analyze the register writes We also create special versions of ctx_log_*_read for new operands Check that the operand is written before the read This is a precursor to improving the analysis for short-circuiting the packet semantics in a subsequent commit Signed-off-by: Taylor Simpson --- target/hexagon/translate.h | 24 ++- target/hexagon/README | 7 +- target/hexagon/gen_analyze_funcs.py | 221 +++++++++++----------------- 3 files changed, 111 insertions(+), 141 deletions(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 4dd59c6726..b2fe3a048d 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -75,6 +75,8 @@ typedef struct DisasContext { TCGv dczero_addr; } DisasContext; =20 +bool is_gather_store_insn(DisasContext *ctx); + static inline void ctx_log_pred_write(DisasContext *ctx, int pnum) { if (!test_bit(pnum, ctx->pregs_written)) { @@ -89,6 +91,12 @@ static inline void ctx_log_pred_read(DisasContext *ctx, = int pnum) set_bit(pnum, ctx->pregs_read); } =20 +static inline void ctx_log_pred_read_new(DisasContext *ctx, int pnum) +{ + g_assert(test_bit(pnum, ctx->pregs_written)); + set_bit(pnum, ctx->pregs_read); +} + static inline void ctx_log_reg_write(DisasContext *ctx, int rnum, bool is_predicated) { @@ -120,6 +128,12 @@ static inline void ctx_log_reg_read(DisasContext *ctx,= int rnum) set_bit(rnum, ctx->regs_read); } =20 +static inline void ctx_log_reg_read_new(DisasContext *ctx, int rnum) +{ + g_assert(test_bit(rnum, ctx->regs_written)); + set_bit(rnum, ctx->regs_read); +} + static inline void ctx_log_reg_read_pair(DisasContext *ctx, int rnum) { ctx_log_reg_read(ctx, rnum); @@ -171,6 +185,15 @@ static inline void ctx_log_vreg_read(DisasContext *ctx= , int rnum) set_bit(rnum, ctx->vregs_read); } =20 +static inline void ctx_log_vreg_read_new(DisasContext *ctx, int rnum) +{ + g_assert(is_gather_store_insn(ctx) || + test_bit(rnum, ctx->vregs_updated) || + test_bit(rnum, ctx->vregs_select) || + test_bit(rnum, ctx->vregs_updated_tmp)); + set_bit(rnum, ctx->vregs_read); +} + static inline void ctx_log_vreg_read_pair(DisasContext *ctx, int rnum) { ctx_log_vreg_read(ctx, rnum ^ 0); @@ -205,7 +228,6 @@ extern TCGv hex_vstore_addr[VSTORES_MAX]; extern TCGv hex_vstore_size[VSTORES_MAX]; extern TCGv hex_vstore_pending[VSTORES_MAX]; =20 -bool is_gather_store_insn(DisasContext *ctx); void process_store(DisasContext *ctx, int slot_num); =20 FIELD(PROBE_PKT_SCALAR_STORE_S0, MMU_IDX, 0, 2) diff --git a/target/hexagon/README b/target/hexagon/README index 69b2ffe9bb..7dd74629eb 100644 --- a/target/hexagon/README +++ b/target/hexagon/README @@ -183,10 +183,11 @@ when the override is present. } =20 We also generate an analyze_ function for each instruction. Currentl= y, -these functions record the writes to registers by calling ctx_log_*. Duri= ng +these functions record the reads and writes to registers by calling ctx_lo= g_*. During gen_start_packet, we invoke the analyze_ function for each instructio= n in -the packet, and we mark the implicit writes. After the analysis is perfor= med, -we initialize the result register for each of the predicated assignments. +the packet, and we mark the implicit writes. The analysis determines if t= he packet +semantics can be short-circuited. If not, we initialize the result regist= er for each +of the predicated assignments. =20 In addition to instruction semantics, we use a generator to create the dec= ode tree. This generation is also a two step process. The first step is to r= un diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon/gen_analy= ze_funcs.py index c3b521abef..40b9473c44 100755 --- a/target/hexagon/gen_analyze_funcs.py +++ b/target/hexagon/gen_analyze_funcs.py @@ -22,157 +22,90 @@ import string import hex_common =20 - ## ## Helpers for gen_analyze_func ## def is_predicated(tag): return "A_CONDEXEC" in hex_common.attribdict[tag] =20 +def vreg_write_type(tag): + newv =3D "EXT_DFL" + if hex_common.is_new_result(tag): + newv =3D "EXT_NEW" + elif hex_common.is_tmp_result(tag): + newv =3D "EXT_TMP" + return newv =20 -def analyze_opn_old(f, tag, regtype, regid, regno): +def declare_regn(f, tag, regtype, regid, regno): regN =3D f"{regtype}{regid}N" - predicated =3D "true" if is_predicated(tag) else "false" - if regtype =3D=3D "R": - if regid in {"ss", "tt"}: - f.write(f" const int {regN} =3D insn->regno[{regno}];\n") - f.write(f" ctx_log_reg_read_pair(ctx, {regN});\n") - elif regid in {"dd", "ee", "xx", "yy"}: - f.write(f" const int {regN} =3D insn->regno[{regno}];\n") - f.write(f" ctx_log_reg_write_pair(ctx, {regN}, {predicated}= );\n") - elif regid in {"s", "t", "u", "v"}: - f.write(f" const int {regN} =3D insn->regno[{regno}];\n") - f.write(f" ctx_log_reg_read(ctx, {regN});\n") - elif regid in {"d", "e", "x", "y"}: - f.write(f" const int {regN} =3D insn->regno[{regno}];\n") - f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n") - else: - hex_common.bad_register(regtype, regid) - elif regtype =3D=3D "P": - if regid in {"s", "t", "u", "v"}: - f.write(f" const int {regN} =3D insn->regno[{regno}];\n") - f.write(f" ctx_log_pred_read(ctx, {regN});\n") - elif regid in {"d", "e", "x"}: - f.write(f" const int {regN} =3D insn->regno[{regno}];\n") - f.write(f" ctx_log_pred_write(ctx, {regN});\n") - else: - hex_common.bad_register(regtype, regid) - elif regtype =3D=3D "C": - if regid =3D=3D "ss": - f.write( - f" const int {regN} =3D insn->regno[{regno}] " - "+ HEX_REG_SA0;\n" - ) + if regtype =3D=3D "C": + f.write( + f" const int {regN} =3D insn->regno[{regno}] " + "+ HEX_REG_SA0;\n" + ) + else: + f.write(f" const int {regN} =3D insn->regno[{regno}];\n") + +def analyze_read(f, tag, regtype, regid, regno): + regN =3D f"{regtype}{regid}N" + if hex_common.is_pair(regid): + if regtype in {"R", "C"}: f.write(f" ctx_log_reg_read_pair(ctx, {regN});\n") - elif regid =3D=3D "dd": - f.write(f" const int {regN} =3D insn->regno[{regno}] " "+ H= EX_REG_SA0;\n") - f.write(f" ctx_log_reg_write_pair(ctx, {regN}, {predicated}= );\n") - elif regid =3D=3D "s": - f.write( - f" const int {regN} =3D insn->regno[{regno}] " - "+ HEX_REG_SA0;\n" - ) - f.write(f" ctx_log_reg_read(ctx, {regN});\n") - elif regid =3D=3D "d": - f.write(f" const int {regN} =3D insn->regno[{regno}] " "+ H= EX_REG_SA0;\n") - f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n") - else: - hex_common.bad_register(regtype, regid) - elif regtype =3D=3D "M": - if regid =3D=3D "u": - f.write(f" const int {regN} =3D insn->regno[{regno}];\n") - f.write(f" ctx_log_reg_read(ctx, {regN});\n") - else: - hex_common.bad_register(regtype, regid) - elif regtype =3D=3D "V": - newv =3D "EXT_DFL" - if hex_common.is_new_result(tag): - newv =3D "EXT_NEW" - elif hex_common.is_tmp_result(tag): - newv =3D "EXT_TMP" - if regid in {"dd", "xx"}: - f.write(f" const int {regN} =3D insn->regno[{regno}];\n") - f.write( - f" ctx_log_vreg_write_pair(ctx, {regN}, {newv}, " f"{pr= edicated});\n" - ) - elif regid in {"uu", "vv"}: - f.write(f" const int {regN} =3D insn->regno[{regno}];\n") + elif regtype =3D=3D "V": f.write(f" ctx_log_vreg_read_pair(ctx, {regN});\n") - elif regid in {"s", "u", "v", "w"}: - f.write(f" const int {regN} =3D insn->regno[{regno}];\n") - f.write(f" ctx_log_vreg_read(ctx, {regN});\n") - elif regid in {"d", "x", "y"}: - f.write(f" const int {regN} =3D insn->regno[{regno}];\n") - f.write(f" ctx_log_vreg_write(ctx, {regN}, {newv}, " f"{pre= dicated});\n") else: hex_common.bad_register(regtype, regid) - elif regtype =3D=3D "Q": - if regid in {"d", "e", "x"}: - f.write(f" const int {regN} =3D insn->regno[{regno}];\n") - f.write(f" ctx_log_qreg_write(ctx, {regN});\n") - elif regid in {"s", "t", "u", "v"}: - f.write(f" const int {regN} =3D insn->regno[{regno}];\n") - f.write(f" ctx_log_qreg_read(ctx, {regN});\n") - else: - hex_common.bad_register(regtype, regid) - elif regtype =3D=3D "G": - if regid in {"dd"}: - f.write(f"// const int {regN} =3D insn->regno[{regno}];\n") - elif regid in {"d"}: - f.write(f"// const int {regN} =3D insn->regno[{regno}];\n") - elif regid in {"ss"}: - f.write(f"// const int {regN} =3D insn->regno[{regno}];\n") - elif regid in {"s"}: - f.write(f"// const int {regN} =3D insn->regno[{regno}];\n") - else: - hex_common.bad_register(regtype, regid) - elif regtype =3D=3D "S": - if regid in {"dd"}: - f.write(f"// const int {regN} =3D insn->regno[{regno}];\n") - elif regid in {"d"}: - f.write(f"// const int {regN} =3D insn->regno[{regno}];\n") - elif regid in {"ss"}: - f.write(f"// const int {regN} =3D insn->regno[{regno}];\n") - elif regid in {"s"}: - f.write(f"// const int {regN} =3D insn->regno[{regno}];\n") + elif hex_common.is_single(regid): + if hex_common.is_old_val(regtype, regid, tag): + if regtype in {"R", "C", "M"}: + f.write(f" ctx_log_reg_read(ctx, {regN});\n") + elif regtype =3D=3D "P": + f.write(f" ctx_log_pred_read(ctx, {regN});\n") + elif regtype in {"V", "O"}: + f.write(f" ctx_log_vreg_read(ctx, {regN});\n") + elif regtype =3D=3D "Q": + f.write(f" ctx_log_qreg_read(ctx, {regN});\n") + else: + hex_common.bad_register(regtype, regid) + elif hex_common.is_new_val(regtype, regid, tag): + if regtype =3D=3D "N": + f.write(f" ctx_log_reg_read_new(ctx, {regN});\n") + elif regtype =3D=3D "P": + f.write(f" ctx_log_pred_read_new(ctx, {regN});\n") + elif regtype =3D=3D "O": + f.write(f" ctx_log_vreg_read_new(ctx, {regN});\n") + else: + hex_common.bad_register(regtype, regid) else: hex_common.bad_register(regtype, regid) else: hex_common.bad_register(regtype, regid) =20 - -def analyze_opn_new(f, tag, regtype, regid, regno): +def analyze_write(f, tag, regtype, regid, regno): regN =3D f"{regtype}{regid}N" - if regtype =3D=3D "N": - if regid in {"s", "t"}: - f.write(f" const int {regN} =3D insn->regno[{regno}];\n") - f.write(f" ctx_log_reg_read(ctx, {regN});\n") - else: - hex_common.bad_register(regtype, regid) - elif regtype =3D=3D "P": - if regid in {"t", "u", "v"}: - f.write(f" const int {regN} =3D insn->regno[{regno}];\n") - f.write(f" ctx_log_pred_read(ctx, {regN});\n") - else: - hex_common.bad_register(regtype, regid) - elif regtype =3D=3D "O": - if regid =3D=3D "s": - f.write(f" const int {regN} =3D insn->regno[{regno}];\n") - f.write(f" ctx_log_vreg_read(ctx, {regN});\n") + predicated =3D "true" if is_predicated(tag) else "false" + if hex_common.is_pair(regid): + if regtype in {"R", "C"}: + f.write(f" ctx_log_reg_write_pair(ctx, {regN}, {predicated}= );\n") + elif regtype =3D=3D "V": + f.write( + f" ctx_log_vreg_write_pair(ctx, {regN}, " + f"{vreg_write_type(tag)}, {predicated});\n" + ) else: hex_common.bad_register(regtype, regid) - else: - hex_common.bad_register(regtype, regid) - - -def analyze_opn(f, tag, regtype, regid, i): - if hex_common.is_pair(regid): - analyze_opn_old(f, tag, regtype, regid, i) elif hex_common.is_single(regid): - if hex_common.is_old_val(regtype, regid, tag): - analyze_opn_old(f, tag, regtype, regid, i) - elif hex_common.is_new_val(regtype, regid, tag): - analyze_opn_new(f, tag, regtype, regid, i) + if regtype in {"R", "C"}: + f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n") + elif regtype =3D=3D "P": + f.write(f" ctx_log_pred_write(ctx, {regN});\n") + elif regtype =3D=3D "V": + f.write( + f" ctx_log_vreg_write(ctx, {regN}, " + f"{vreg_write_type(tag)}, {predicated});\n" + ) + elif regtype =3D=3D "Q": + f.write(f" ctx_log_qreg_write(ctx, {regN});\n") else: hex_common.bad_register(regtype, regid) else: @@ -187,11 +120,11 @@ def analyze_opn(f, tag, regtype, regid, i): ## { ## Insn *insn G_GNUC_UNUSED =3D ctx->insn; ## const int RdN =3D insn->regno[0]; -## ctx_log_reg_write(ctx, RdN, false); ## const int RsN =3D insn->regno[1]; -## ctx_log_reg_read(ctx, RsN); ## const int RtN =3D insn->regno[2]; +## ctx_log_reg_read(ctx, RsN); ## ctx_log_reg_read(ctx, RtN); +## ctx_log_reg_write(ctx, RdN, false); ## } ## def gen_analyze_func(f, tag, regs, imms): @@ -200,10 +133,24 @@ def gen_analyze_func(f, tag, regs, imms): =20 f.write(" Insn *insn G_GNUC_UNUSED =3D ctx->insn;\n") =20 + ## Declare the operands + i =3D 0 + for regtype, regid in regs: + declare_regn(f, tag, regtype, regid, i) + i +=3D 1 + + ## Analyze the register reads + i =3D 0 + for regtype, regid in regs: + if hex_common.is_read(regid): + analyze_read(f, tag, regtype, regid, i) + i +=3D 1 + + ## Analyze the register writes i =3D 0 - ## Analyze all the registers for regtype, regid in regs: - analyze_opn(f, tag, regtype, regid, i) + if hex_common.is_written(regid): + analyze_write(f, tag, regtype, regid, i) i +=3D 1 =20 has_generated_helper =3D not hex_common.skip_qemu_helper( @@ -240,13 +187,13 @@ def main(): tagimms =3D hex_common.get_tagimms() =20 with open(sys.argv[-1], "w") as f: - f.write("#ifndef HEXAGON_TCG_FUNCS_H\n") - f.write("#define HEXAGON_TCG_FUNCS_H\n\n") + f.write("#ifndef HEXAGON_ANALYZE_FUNCS_H\n") + f.write("#define HEXAGON_ANALYZE_FUNCS_H\n\n") =20 for tag in hex_common.tags: gen_analyze_func(f, tag, tagregs[tag], tagimms[tag]) =20 - f.write("#endif /* HEXAGON_TCG_FUNCS_H */\n") + f.write("#endif /* HEXAGON_ANALYZE_FUNCS_H */\n") =20 =20 if __name__ =3D=3D "__main__": --=20 2.34.1