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([179.193.10.161]) by smtp.gmail.com with ESMTPSA id j68-20020a0df947000000b00582b239674esm935814ywf.129.2023.11.03.06.46.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 06:46:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1699019213; x=1699624013; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W9vkQpTeB3ayrchqiqPL77Nx2STXCsE/ldIKYWZcyJE=; b=E9L+3SnmMHZexlFnA08dRDnY4Fy+CvKKFFqEd1KvYAtfG6ehNIY1uyuTbRD67AFbd9 NPX0KpIxoDf32ENHUotoaLGyzfkC3kybOoik4qOdFYEAVKF+AwYCPMs38Tk8+vToG8C4 83x1mmWDgECGOkZN0F/4Iv8bTvKmxJnYhSTZZLjQp9DzIWxUWu7gAWxCc8ayOqV5Sdo3 q7Wnp6VRwPRZBMKAiOhzdXieio7s2l2i4dUdwDv2OE8UsdJlI/u/fnyhMRKklmOiLsoN Ts/8DaUGVtvG3p4fIZJ2Qu6FYtxGZA+KcCttB1Usp6nVeizU75kiVxruUGHEPWAdCJvk 1mPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699019213; x=1699624013; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W9vkQpTeB3ayrchqiqPL77Nx2STXCsE/ldIKYWZcyJE=; b=dggVvm3fSnE5TpVvFucwN5IhE1wHN3pFgpj1+xTxIzurpdAAgMClHNoSdkVp31Jnct 1phsA9ZxYkIeiMVWYB0G96tXcflj4Gu8NtkfrsQKg0TUK5t5bYorig+gXHfoMQZS3XZy olcOmdPaRMHlpwNAYysrDbacTr4IaGPKLAZFmGBTXoE3VwVS3QIdDkSOxjJ24QYY/EyI 6fuKsnfwIGyPwL4B2sPpIVjUisUIkauW9ukRV4s3cOIDmpL+HLLWF5pDgxKf4qx43zAo 92o3QKqBLFl7CSUDz3/D+Edke5gz/3c1ognI6ciBQMzXhu6NffjXWSS6H7l+eiNNrkFY MDRA== X-Gm-Message-State: AOJu0YwmHbIz7VyNyHAFRsXMiIeIiEVEwBdyYG36SfZN7JtTB1HHhYTO zkoKhEfpufY8Xde45qz+xvk6TzDQKr4QQYFY31w= X-Google-Smtp-Source: AGHT+IFekF03hJs/NGE0MfTRcIn+oTcETUtfKeiQHJP1Khb23FIpZQtxWgItOMXmmgLeCFKuMU8QeQ== X-Received: by 2002:a05:690c:dc6:b0:5a7:b682:7929 with SMTP id db6-20020a05690c0dc600b005a7b6827929mr3360936ywb.17.1699019213547; Fri, 03 Nov 2023 06:46:53 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v10 07/18] riscv-qmp-cmds.c: expose named features in cpu_model_expansion Date: Fri, 3 Nov 2023 10:46:18 -0300 Message-ID: <20231103134629.561732-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231103134629.561732-1-dbarboza@ventanamicro.com> References: <20231103134629.561732-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1131; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x1131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1699019306414100007 Content-Type: text/plain; charset="utf-8" Named features (zic64b the sole example at this moment) aren't expose to users, thus we need another way to expose them. Go through each named feature, get its boolean value, do the needed conversions (bool to qbool, qbool to QObject) and add it to output dict. Another adjustment is needed: named features are evaluated during finalize(), so riscv_cpu_finalize_features() needs to be mandatory regardless of whether we have an input dict or not. Otherwise zic64b will always return 'false', which is incorrect: the default values of cache blocksizes ([cbom/cbop/cboz]_blocksize) are set to 64, satisfying the conditions for zic64b. Here's an API usage example after this patch: $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp tcp:localhost:1234,server,wait=3Doff $ ./scripts/qmp/qmp-shell localhost:1234 Welcome to the QMP low-level shell! Connected to QEMU 8.1.50 (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"rv64"} {"return": {"model": {"name": "rv64", "props": {... "zic64b": true, ...}}}} zic64b is set to 'true', as expected, since all cache sizes are 64 bytes by default. If we change one of the cache blocksizes, zic64b is returned as 'false': (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"rv64","props"= :{"cbom_blocksize":128}} {"return": {"model": {"name": "rv64", "props": {... "zic64b": false, ...}}}} Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/riscv-qmp-cmds.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index 2f2dbae7c8..5ada279776 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -26,6 +26,7 @@ =20 #include "qapi/error.h" #include "qapi/qapi-commands-machine-target.h" +#include "qapi/qmp/qbool.h" #include "qapi/qmp/qdict.h" #include "qapi/qmp/qerror.h" #include "qapi/qobject-input-visitor.h" @@ -99,6 +100,22 @@ static void riscv_obj_add_multiext_props(Object *obj, Q= Dict *qdict_out, } } =20 +static void riscv_obj_add_named_feats_qdict(Object *obj, QDict *qdict_out) +{ + const RISCVCPUMultiExtConfig *named_cfg; + RISCVCPU *cpu =3D RISCV_CPU(obj); + QObject *value; + bool flag_val; + + for (int i =3D 0; riscv_cpu_named_features[i].name !=3D NULL; i++) { + named_cfg =3D &riscv_cpu_named_features[i]; + flag_val =3D isa_ext_is_enabled(cpu, named_cfg->offset); + value =3D QOBJECT(qbool_from_bool(flag_val)); + + qdict_put_obj(qdict_out, named_cfg->name, value); + } +} + static void riscv_cpuobj_validate_qdict_in(Object *obj, QObject *props, const QDict *qdict_in, Error **errp) @@ -129,11 +146,6 @@ static void riscv_cpuobj_validate_qdict_in(Object *obj= , QObject *props, goto err; } =20 - riscv_cpu_finalize_features(RISCV_CPU(obj), &local_err); - if (local_err) { - goto err; - } - visit_end_struct(visitor, NULL); =20 err: @@ -191,6 +203,13 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(C= puModelExpansionType type, } } =20 + riscv_cpu_finalize_features(RISCV_CPU(obj), &local_err); + if (local_err) { + error_propagate(errp, local_err); + object_unref(obj); + return NULL; + } + expansion_info =3D g_new0(CpuModelExpansionInfo, 1); expansion_info->model =3D g_malloc0(sizeof(*expansion_info->model)); expansion_info->model->name =3D g_strdup(model->name); @@ -200,6 +219,7 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(Cp= uModelExpansionType type, riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_extensions); riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_experimental_ex= ts); riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_vendor_exts); + riscv_obj_add_named_feats_qdict(obj, qdict_out); =20 /* Add our CPU boolean options too */ riscv_obj_add_qdict_prop(obj, qdict_out, "mmu"); --=20 2.41.0