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([179.193.10.161]) by smtp.gmail.com with ESMTPSA id j68-20020a0df947000000b00582b239674esm935814ywf.129.2023.11.03.06.46.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 06:46:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1699019208; x=1699624008; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=712CYVy+EQ0Wv0Iz+priR4rRIhCm9vcc+O/gippj4S4=; b=FYjW2dbxlWigQClOkWIoH4vhfi6m3oSkySaegYgrYBZgDb8Mrc5zX03DlKKF0/Tusu KtPZZjWpc+6ZbFznD0DiNrqcML6Z+ZTmJy5cw1+WXJb8EZH9Fm35kWiADWcJvkRZG0HB JDXHEKnuK/sL6YDSHu7jsbXZbEChZ1ZxkKTr81pIHaFkZQP7LTnZk91q/D4of3eNtbrB CEDQ3rF2Ea+5Wd+RGcnmW+qljC86wzpMse+KAl5M8pb4RozoWeOVDl0vE2ZoskqyzhEX bdQF9qi77YBOwX4C36oh8J4YO8Erxfyaj89i0Qo6el4IAN1jmiLhisepEiduD2qnSZ+I QIDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699019208; x=1699624008; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=712CYVy+EQ0Wv0Iz+priR4rRIhCm9vcc+O/gippj4S4=; b=WuS8BQoV7DHEbhwymNFjDrTCIEaf242eklsZ74XVrqvdXwME6lR96fdMPpK4WfcS9R ZKurUpuiN350L2x1Z0UCWNNGSkhUwDr96D+bJfWHR2xwXC53RLlh0B8PcGEHluDpLX/r /MB6uABlyPr4HxsqTPDLZg+Ns35q9WY83/4ge4/nyrUHpUvLFiI2MsFpWUn5vh1Fmyl+ 5Wg6z4vHAkv6/wx62MCjRj19e+ySUhjhp2GFkTb0TWP9H6H4wygpgb159okHj0mIocNl +ZX5bfcbxzcsbkP2+iHDacBkLFE1k7ckwKGtpKkEZeWAZzMsuklDikME0UXil7hBw3ks TxGQ== X-Gm-Message-State: AOJu0YzlG9TWrQRE6g6aPQ7LzVDQT0FESsQ/U47XlA6SkQxvyEoj1Exc ywLqv57qGDr+H/s15Bp4uAkJc4qk/wd0bnbxYcQ= X-Google-Smtp-Source: AGHT+IGTNMEX5lpdxvJbuw+KljcCgvtPB4KsvAA2zkCCRXPe1SmV80SNUWv4Zge3G9JEzUkPOxKhrw== X-Received: by 2002:a81:8393:0:b0:5a7:b797:d1e4 with SMTP id t141-20020a818393000000b005a7b797d1e4mr2718401ywf.21.1699019208022; Fri, 03 Nov 2023 06:46:48 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v10 05/18] target/riscv: add zicbop extension flag Date: Fri, 3 Nov 2023 10:46:16 -0300 Message-ID: <20231103134629.561732-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231103134629.561732-1-dbarboza@ventanamicro.com> References: <20231103134629.561732-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1135; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x1135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1699019392924100011 Content-Type: text/plain; charset="utf-8" QEMU already implements zicbom (Cache Block Management Operations) and zicboz (Cache Block Zero Operations). Commit 59cb29d6a5 ("target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder") added placeholders for what would be the instructions for zicbop (Cache Block Prefetch Operations), which are now no-ops. The RVA22U64 profile mandates zicbop, which means that applications that run with this profile might expect zicbop to be present in the riscv,isa DT and might behave badly if it's absent. Adding zicbop as an extension will make our future RVA22U64 implementation more in line with what userspace expects and, if/when cache block prefetch operations became relevant to QEMU, we already have the extension flag to turn then on/off as needed. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- hw/riscv/virt.c | 5 +++++ target/riscv/cpu.c | 3 +++ target/riscv/cpu_cfg.h | 2 ++ 3 files changed, 10 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 1732c42915..99c087240f 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -273,6 +273,11 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, = int socket, cpu_ptr->cfg.cboz_blocksize); } =20 + if (cpu_ptr->cfg.ext_zicbop) { + qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-siz= e", + cpu_ptr->cfg.cbop_blocksize); + } + qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 46a5550d72..07c3cb1c23 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -78,6 +78,7 @@ const uint32_t misa_bits[] =3D {RVI, RVE, RVM, RVA, RVF, = RVD, RVV, */ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom), + ISA_EXT_DATA_ENTRY(zicbop, PRIV_VERSION_1_12_0, ext_zicbop), ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr), @@ -1377,6 +1378,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false), =20 MULTI_EXT_CFG_BOOL("zicbom", ext_zicbom, true), + MULTI_EXT_CFG_BOOL("zicbop", ext_zicbop, true), MULTI_EXT_CFG_BOOL("zicboz", ext_zicboz, true), =20 MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false), @@ -1473,6 +1475,7 @@ Property riscv_cpu_options[] =3D { DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), + DEFINE_PROP_UINT16("cbop_blocksize", RISCVCPU, cfg.cbop_blocksize, 64), DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), =20 DEFINE_PROP_END_OF_LIST(), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 634ff673b3..c21e4bcc47 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -65,6 +65,7 @@ struct RISCVCPUConfig { bool ext_zicntr; bool ext_zicsr; bool ext_zicbom; + bool ext_zicbop; bool ext_zicboz; bool ext_zicond; bool ext_zihintntl; @@ -142,6 +143,7 @@ struct RISCVCPUConfig { uint16_t vlen; uint16_t elen; uint16_t cbom_blocksize; + uint16_t cbop_blocksize; uint16_t cboz_blocksize; bool mmu; bool pmp; --=20 2.41.0