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([179.193.10.161]) by smtp.gmail.com with ESMTPSA id j68-20020a0df947000000b00582b239674esm935814ywf.129.2023.11.03.06.46.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 06:46:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1699019200; x=1699624000; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UgRWfBwtayel4L85jalnEfEZ38BIg1pZr2LRgGnFOd0=; b=oOAPAIqDZPn7MnD7/mShT26cOpKy/il1K4iXGnryRi+9O+0hXwXeVVEkYuFHF+Xi90 uJg71EwDtg6xQqn87xvyh1MdTa2uz7Ttuv/sJbYDJk45jkgHLUG6nYnA+3BWmhYC5fCB n77jPcreUgBEAhAk+gphY67i3bGh0i5dwLzv23r4CQUNAJxhHK8+n9Q7vMLT1+VfRbZ2 9PSYGHv1agIEKaFHM7ZOo9Y+a0MOGDO7rSloM8rsGTxcY14j2zbrIJJzDFgfKNHD3mad 9sEYa8YX5IPmJgkxd0MKbPECD2x7P45q8KTcg0NQ0zU/FNv7Dpfk/41Vy/uSVsFuWw1b Gzew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699019200; x=1699624000; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UgRWfBwtayel4L85jalnEfEZ38BIg1pZr2LRgGnFOd0=; b=ldB1f+48ktXTEQg0exVZSNjuYoNTxq6tQ8sUliQq+HTsbFHOKTueH3PV/DnYi1Pc2S m+l6eyaqlHJlAPLBXBWVomTNDMWmJrU5lZJT4VGLNGS2OJNiX4MhAAxvTJgiURxtMBZq 6lGugtv3XTomKETYEVMbDEWNiInARNqQR8gx7Fj71QOjtwSCnnGKOAIrb8h2v9XHDWsq b9WZTyO6VeWcDQRhHo0ueeAumxSRGEM7cEpBwKTINj/T6YROm7lcfDBuYVQB/h9wP7JL opPYzgs7r+fCr2LSNQq1i+V7e3QFsuotx4LHKGaSfPEzeiIlv7jG5v044Xaj3vPecuQ/ ZnKQ== X-Gm-Message-State: AOJu0Yy3kZZMYos5nvz1FH8mq5WB9xFBLKqHKq95MLB6eoHjT0aOd3NK TD1SaOzmGJ/G9Y7VUSVgV3ohMCRxvZozec6CrL0= X-Google-Smtp-Source: AGHT+IFX4BrkVfrQjFrV14rmdv/7kfWQ4BZWjgSyxuK+bcON9JJRrUEiU3hFvxy0iwG+YSNTte3UJA== X-Received: by 2002:a0d:ca8d:0:b0:59b:eab8:7ac6 with SMTP id m135-20020a0dca8d000000b0059beab87ac6mr3032705ywd.42.1699019199988; Fri, 03 Nov 2023 06:46:39 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v10 02/18] target/riscv/tcg: do not use "!generic" CPU checks Date: Fri, 3 Nov 2023 10:46:13 -0300 Message-ID: <20231103134629.561732-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231103134629.561732-1-dbarboza@ventanamicro.com> References: <20231103134629.561732-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1132; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x1132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1699019326577100001 Content-Type: text/plain; charset="utf-8" Our current logic in get/setters of MISA and multi-letter extensions works because we have only 2 CPU types, generic and vendor, and by using "!generic" we're implying that we're talking about vendor CPUs. When adding a third CPU type this logic will break so let's handle it beforehand. In set_misa_ext_cfg() and set_multi_ext_cfg(), check for "vendor" cpu inste= ad of "not generic". The "generic CPU" checks remaining are from riscv_cpu_add_misa_properties() and cpu_add_multi_ext_prop() before applying default values for the extensions. This leaves us with: - vendor CPUs will not allow extension enablement, all other CPUs will; - generic CPUs will inherit default values for extensions, all others won't. And now we can add a new, third CPU type, that will allow extensions to be enabled and will not inherit defaults, without changing the existing logic. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 1a3351b142..08f8dded56 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -654,6 +654,11 @@ static bool riscv_cpu_is_generic(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; } =20 +static bool riscv_cpu_is_vendor(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_VENDOR_CPU) !=3D NULL; +} + /* * We'll get here via the following path: * @@ -716,7 +721,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *= v, const char *name, target_ulong misa_bit =3D misa_ext_cfg->misa_bit; RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - bool generic_cpu =3D riscv_cpu_is_generic(obj); + bool vendor_cpu =3D riscv_cpu_is_vendor(obj); bool prev_val, value; =20 if (!visit_type_bool(v, name, &value, errp)) { @@ -730,7 +735,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *= v, const char *name, } =20 if (value) { - if (!generic_cpu) { + if (vendor_cpu) { g_autofree char *cpuname =3D riscv_cpu_get_name(cpu); error_setg(errp, "'%s' CPU does not allow enabling extensions", cpuname); @@ -835,7 +840,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor = *v, const char *name, { const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; RISCVCPU *cpu =3D RISCV_CPU(obj); - bool generic_cpu =3D riscv_cpu_is_generic(obj); + bool vendor_cpu =3D riscv_cpu_is_vendor(obj); bool prev_val, value; =20 if (!visit_type_bool(v, name, &value, errp)) { @@ -859,7 +864,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor = *v, const char *name, return; } =20 - if (value && !generic_cpu) { + if (value && vendor_cpu) { g_autofree char *cpuname =3D riscv_cpu_get_name(cpu); error_setg(errp, "'%s' CPU does not allow enabling extensions", cpuname); --=20 2.41.0