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([179.193.10.161]) by smtp.gmail.com with ESMTPSA id j68-20020a0df947000000b00582b239674esm935814ywf.129.2023.11.03.06.47.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 06:47:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1699019240; x=1699624040; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eKLA2b+3ni3oHNZSzku3n2BMkvO4OXSmTM950JOFjds=; b=TFPcPOKYchYRfJXpPv0g8OSm8+NqRGBQHUnp/RA2eStZZdC7hc1ZyQZwj6RT6mRNQo lKZNfqzY1IsBMbznGgRI0GDW/hjyNbq0YuheA35x84c3qUO8e/MHcsgyrtp9Ll2MhKl3 dtMAPOq1kC0iM0agqwiPzoXeqCKUQieOdbkk5wCpXbCjrpGKtAC4Trp7ZWtFfqDxawcg NxLpxW6G2tnS4bugBb6zaFcmgv7BmskKAYPHqkLkePshEjYJ+n5Nx3d0AGIijCn1QdAd 3ppEijySEra6vJVxAMZgkz1FrZKdolCLTUktOE5nxO2WCqfy7fYJALWcu55ILtXSWFuM CIxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699019240; x=1699624040; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eKLA2b+3ni3oHNZSzku3n2BMkvO4OXSmTM950JOFjds=; b=qTXqxK8xtPLDjob/todHNUnA1q+uqV42oASVCRHE/cdLL+7LsYYyZMW75l1C+RCWrZ lwbr7l8Jj+2PwI/t/CUulXAhf9fbvZwrd8jEzqfPfibZqOxLmCvgAKuvjCe37CYLXCZ+ z/I0gdfkuGdw31G05/lvIjRVZtCND47buXFPhSzL6poow24jLK9Y/wCDj6zYtB9FETsY lLnBVXyO+wgkaUR+1KcfdUWVlHZHYBGsLyr5rnB09Fn3ONFg59ULKraVXrBHIEApmMH2 1n+LDx3nexoZ77EwTotYn9+ViPDNx1waFer7w8/wdO2nGmn61sMCTh3LGy7iI42ydr4p jhtg== X-Gm-Message-State: AOJu0YxTJE/DUwONhl0mYXE7nmQWw0L5JKAStSh8eDuCfQlHHAju/BTC ukb7B5Aav/8e8NSys3yKddVlLki3McWsgSfMykE= X-Google-Smtp-Source: AGHT+IHOMkn9p4RGHHoRvmKFHUux2lOcrKDRrAr9LMABsY2AWZUZKEoCeDGUKRz4Hc+ySVJemC859g== X-Received: by 2002:a0d:d955:0:b0:5a7:afcc:80fe with SMTP id b82-20020a0dd955000000b005a7afcc80femr2947715ywe.3.1699019238433; Fri, 03 Nov 2023 06:47:18 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v10 16/18] target/riscv/tcg: validate profiles during finalize Date: Fri, 3 Nov 2023 10:46:27 -0300 Message-ID: <20231103134629.561732-17-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231103134629.561732-1-dbarboza@ventanamicro.com> References: <20231103134629.561732-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1133; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x1133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1699019391174100001 Content-Type: text/plain; charset="utf-8" Enabling a profile and then disabling some of its mandatory extensions is a valid use. It can be useful for debugging and testing. But the common expected use of enabling a profile is to enable all its mandatory extensions. Add an user warning when mandatory extensions from an enabled profile are disabled in the command line. We're also going to disable the profile flag in this case since the profile must include all the mandatory extensions. This flag can be exposed by QMP to indicate the actual profile state after the CPU is realized. After this patch, this will throw warnings: -cpu rv64,rva22u64=3Dtrue,zihintpause=3Dfalse,zicbom=3Dfalse,zicboz=3Dfalse qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension = zihintpause qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension = zicbom qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension = zicboz Note that the following will NOT throw warnings because the profile is being enabled last, hence all its mandatory extensions will be enabled: -cpu rv64,zihintpause=3Dfalse,zicbom=3Dfalse,zicboz=3Dfalse,rva22u64=3Dtrue Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 69 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 9c2469412b..50683931e2 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -147,6 +147,26 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_of= fset) g_assert_not_reached(); } =20 +static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) +{ + const RISCVCPUMultiExtConfig *feat; + const RISCVIsaExtData *edata; + + for (edata =3D isa_edata_arr; edata->name !=3D NULL; edata++) { + if (edata->ext_enable_offset =3D=3D ext_offset) { + return edata->name; + } + } + + for (feat =3D riscv_cpu_named_features; feat->name !=3D NULL; feat++) { + if (feat->offset =3D=3D ext_offset) { + return feat->name; + } + } + + g_assert_not_reached(); +} + static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) { const RISCVCPUMultiExtConfig *feat; @@ -710,6 +730,54 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) riscv_cpu_disable_priv_spec_isa_exts(cpu); } =20 +static void riscv_cpu_validate_profile(RISCVCPU *cpu, + RISCVCPUProfile *profile) +{ + const char *warn_msg =3D "Profile %s mandates disabled extension %s"; + bool send_warn =3D profile->user_set && profile->enabled; + bool profile_impl =3D true; + int i; + + for (i =3D 0; misa_bits[i] !=3D 0; i++) { + uint32_t bit =3D misa_bits[i]; + + if (!(profile->misa_ext & bit)) { + continue; + } + + if (!riscv_has_ext(&cpu->env, bit)) { + profile_impl =3D false; + + if (send_warn) { + warn_report(warn_msg, profile->name, + riscv_get_misa_ext_name(bit)); + } + } + } + + for (i =3D 0; profile->ext_offsets[i] !=3D RISCV_PROFILE_EXT_LIST_END;= i++) { + int ext_offset =3D profile->ext_offsets[i]; + + if (!isa_ext_is_enabled(cpu, ext_offset)) { + profile_impl =3D false; + + if (send_warn) { + warn_report(warn_msg, profile->name, + cpu_cfg_ext_get_name(ext_offset)); + } + } + } + + profile->enabled =3D profile_impl; +} + +static void riscv_cpu_validate_profiles(RISCVCPU *cpu) +{ + for (int i =3D 0; riscv_profiles[i] !=3D NULL; i++) { + riscv_cpu_validate_profile(cpu, riscv_profiles[i]); + } +} + void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; @@ -728,6 +796,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Err= or **errp) } =20 riscv_cpu_validate_named_features(cpu); + riscv_cpu_validate_profiles(cpu); =20 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { /* --=20 2.41.0