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([179.193.10.161]) by smtp.gmail.com with ESMTPSA id j68-20020a0df947000000b00582b239674esm935814ywf.129.2023.11.03.06.47.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 06:47:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1699019233; x=1699624033; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Xy+PLu3dn1jAXbmRaqjBWNLGWZ1413jdcQdUSFdHc8M=; b=m9SiJfLHJG1zVyrTno9CCZ/u9h+xHB6khwS+DF1mqjnZWMw1z4HdtRG0/atKEhmMO2 Jmgg/0p3JOdOJAMsUbtucJWhs98w3B3V1Nvf3pwaAuXcssf/3DtrAbwBDGMjn+g2w/r2 febnz28H9mKW5YZdhYQldTDXUWq3CHNZ7kFlv7mvpb+G7WLBu/Rcfx6o5vrAV50SlR4s d2wXEdSODsdQF1yfYlNivXd5RKvkU6dLQRgUDf/Fz+0OIyCXOqhi4Mw4HvyCvftJAQn2 Z5yTH2TCad2WewpvnUylmL7SBUs6WqAK1PeEddIHBPad1aQPz+6l6CQ/ME1n9DhpPRvs QW1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699019233; x=1699624033; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Xy+PLu3dn1jAXbmRaqjBWNLGWZ1413jdcQdUSFdHc8M=; b=UlhUIMwe9dpyKVk8U2plx98Ijuit6YAMU7xjtSiZ5VIFAN0VOmw55XFWeMR7HbfrJa AQ9IJIZOaoJc+r04UChX9FPfB5u8loiepreQCYjYtklwl42CKYfc+TPBxXPRcAt5kf0k dE162AxPsLjMYTQcMLyq1w2W2Xig7sqqqd2A+dnDUhWRu+q/SMoEtk2/HOfJE834AlgL osYb2p3DsrOS0GAqyBx561/7Or94+d0eEXVhdZTYwfVFzNf5rYEmbMfuX+reQrCgnop5 C1R1ZbFcalxpQyoQ2CSDAP1dSWnv2YailAY+IJreE4vZq+GceO6CX0IsF1rc6dH7HGwu Gwsg== X-Gm-Message-State: AOJu0YzQqz+srcephj7yvhi/+ReJ96KCfeUx8pNWkPf1iSRTyPx/4tgl V0BCxvN354u1YbbOiEavG1O+alwxku4ZjEtVUIw= X-Google-Smtp-Source: AGHT+IGCveAGVTTavWmCgJ3pykXD0r4PtSrs9twyY3HMaDPHqBRLTTwjH6KkLXkA+t13rs7KkmKMKg== X-Received: by 2002:a0d:d696:0:b0:5ac:fe2d:5edf with SMTP id y144-20020a0dd696000000b005acfe2d5edfmr2739588ywd.44.1699019233088; Fri, 03 Nov 2023 06:47:13 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v10 14/18] target/riscv/tcg: add hash table insert helpers Date: Fri, 3 Nov 2023 10:46:25 -0300 Message-ID: <20231103134629.561732-15-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231103134629.561732-1-dbarboza@ventanamicro.com> References: <20231103134629.561732-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::112c; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x112c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1699019384915100008 Content-Type: text/plain; charset="utf-8" Previous patches added several g_hash_table_insert() patterns. Add two helpers, one for each user hash, to make the code cleaner. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 7ecd95c2e1..dd9026c675 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -42,6 +42,18 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) GUINT_TO_POINTER(ext_offset)); } =20 +static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) +{ + g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), + (gpointer)value); +} + +static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) +{ + g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), + (gpointer)value); +} + static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, bool enabled) { @@ -794,9 +806,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *= v, const char *name, return; } =20 - g_hash_table_insert(misa_ext_user_opts, - GUINT_TO_POINTER(misa_bit), - (gpointer)value); + cpu_misa_ext_add_user_opt(misa_bit, value); =20 prev_val =3D env->misa_ext & misa_bit; =20 @@ -933,9 +943,7 @@ static void cpu_set_profile(Object *obj, Visitor *v, co= nst char *name, continue; } =20 - g_hash_table_insert(misa_ext_user_opts, - GUINT_TO_POINTER(bit), - (gpointer)value); + cpu_misa_ext_add_user_opt(bit, profile->enabled); riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); } =20 @@ -946,9 +954,7 @@ static void cpu_set_profile(Object *obj, Visitor *v, co= nst char *name, cpu_validate_multi_ext_priv_ver(&cpu->env, ext_offset); } =20 - g_hash_table_insert(multi_ext_user_opts, - GUINT_TO_POINTER(ext_offset), - (gpointer)profile->enabled); + cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); isa_ext_update_enabled(cpu, ext_offset, profile->enabled); } } @@ -1011,9 +1017,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visito= r *v, const char *name, multi_ext_cfg->name, lower); } =20 - g_hash_table_insert(multi_ext_user_opts, - GUINT_TO_POINTER(multi_ext_cfg->offset), - (gpointer)value); + cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value); =20 prev_val =3D isa_ext_is_enabled(cpu, multi_ext_cfg->offset); =20 --=20 2.41.0