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([179.193.10.161]) by smtp.gmail.com with ESMTPSA id j68-20020a0df947000000b00582b239674esm935814ywf.129.2023.11.03.06.47.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 06:47:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1699019230; x=1699624030; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+C6CHYh24kH7MoMh0oWp4kFRb4ZW2UxlCtbQUQeF5xE=; b=Tleikze2V9FMhfENuZsApPf2PKA7Oq0hZiAY+qbEtoe2vZ01e2WVeaqdymwMdnDPHS D/Hbi85LujzqSccY9gbqTjX8B5XKDgkxoCmxoEcDn9l6GKcWnYNRO6j4mV9K8E3HDImA bOvP78/m4OIT7tHLlhNpjxqg5VbD6qVwK6+pvXf7zbiLwejWlHzXR1aGad5fHLYJGulR 0aKxpHLYOmjXw1HRWjVp3eCH4uCRjCbbZ0NhDaBrzEExTm9ATzXsqosiwM4rzTLgv03T cGRYb/1bOgsjcR5u0eiIm2PTByU0po5OtL0Npi0DuWL3H9OHOeREy+4+FTliMZOj1dMe XtYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699019230; x=1699624030; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+C6CHYh24kH7MoMh0oWp4kFRb4ZW2UxlCtbQUQeF5xE=; b=Pd1nYW1fFMxX4TVjug9i84cbufUrFvg4uLom509UdZqVeE7/Tr6yFW2spRhQFbkLDF MPAuJLe+1erk3KtPnioSniF59vOt7hZABbPhN5cYWq+XNAK5cUDDfPDp3Th0l4Rac6ja /E7y5Ct5+K299NU4CMU1JeDDfU50oRzfcbxZ/rljUYp/beSDu9Gyfr27fV2IU/Ph2sOO kjpJj9TPOulS6jskhB/0C9OoKHo7kUEdsTU8Z4t9ctCdycU+JA/zustB/VENs/BaVXID Y9R+YMpLRrg9Me4qaKCqfNESBHJf6QEI5rck2GXWsK/TPukHUxXneOG1s/BX2eZ61JHl NcPw== X-Gm-Message-State: AOJu0Yym2OOu54dWIQghjxjC73ByPAa4uN9NPHDxVSAIAhIBzyAazz0C dryeIyPR7ou9C9t13DrmSAB7wm7d00QzaYSI62Q= X-Google-Smtp-Source: AGHT+IGVL5rTqrwLBiLYJuhG95EYpQ2yFdWxT+NqZyl7J/LjTD1hdKGvAFAvGs5hCJvRR1nOFcD4NQ== X-Received: by 2002:a81:6043:0:b0:598:5bb5:1801 with SMTP id u64-20020a816043000000b005985bb51801mr2352945ywb.50.1699019230449; Fri, 03 Nov 2023 06:47:10 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v10 13/18] target/riscv/tcg: handle profile MISA bits Date: Fri, 3 Nov 2023 10:46:24 -0300 Message-ID: <20231103134629.561732-14-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231103134629.561732-1-dbarboza@ventanamicro.com> References: <20231103134629.561732-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1134; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x1134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1699019384873100005 Content-Type: text/plain; charset="utf-8" The profile support is handling multi-letter extensions only. Let's add support for MISA bits as well. We'll go through every known MISA bit. If the profile doesn't declare the bit as mandatory, ignore it. Otherwise, set the bit in env->misa_ext and env->misa_ext_mask. Now that we're setting profile MISA bits, one can use the rv64i CPU to boot Linux using the following options: -cpu rv64i,rva22u64=3Dtrue,rv39=3Dtrue,s=3Dtrue,zifencei=3Dtrue In the near future, when rva22s64 (where, 's', 'zifencei' and sv39 are mandatory), is implemented, rv64i will be able to boot Linux loading rva22s64 and no additional flags. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 87e39f7d19..7ecd95c2e1 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -918,6 +918,27 @@ static void cpu_set_profile(Object *obj, Visitor *v, c= onst char *name, profile->user_set =3D true; profile->enabled =3D value; =20 + for (i =3D 0; misa_bits[i] !=3D 0; i++) { + uint32_t bit =3D misa_bits[i]; + + if (!(profile->misa_ext & bit)) { + continue; + } + + if (bit =3D=3D RVI && !profile->enabled) { + /* + * Disabling profiles will not disable the base + * ISA RV64I. + */ + continue; + } + + g_hash_table_insert(misa_ext_user_opts, + GUINT_TO_POINTER(bit), + (gpointer)value); + riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); + } + for (i =3D 0; profile->ext_offsets[i] !=3D RISCV_PROFILE_EXT_LIST_END;= i++) { ext_offset =3D profile->ext_offsets[i]; =20 --=20 2.41.0