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([179.193.10.161]) by smtp.gmail.com with ESMTPSA id j68-20020a0df947000000b00582b239674esm935814ywf.129.2023.11.03.06.47.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 06:47:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1699019224; x=1699624024; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IW8tZpX8+WPhvoMhvan4F5qvVJ8OewiS17Az1wv5CnA=; b=JSQPUe8TEJXuXepkFLkgIL9kCuFh0rpA9pjEu5zm2f67r1Q5vKU/hVeUDTKF+C01+9 zXOxCmbQ/uVUkcCkt31r84ZlnzlV26Ge3aZdeNUA/dePHGPErXEyj+z9gM9A4CmWVU3/ K4ijdMDHDw4yRYzfKDhgtk5dtWzoi/SiZPosCLdkS9Im2L3Ou75w48T8WHCzn8V0oZCe q0cAwj/JQAfDPV6lnGomcrjznekuFguTooAfRp6IFYSi8Gebt/cLyQBUxZSj1LZo+Vu/ eaZaC+xVxiEwTqzBtoXBprK1o0gyVK+BwR+hCtXqoi4BWKKvOaOxlTipAgc5PbpkqaVV rLxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699019224; x=1699624024; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IW8tZpX8+WPhvoMhvan4F5qvVJ8OewiS17Az1wv5CnA=; b=B3r6FaLnRzp+5vtZ28DN0SeIVQ/4Orqvz7m+MrOO+6reN6quB8SjZZuWlumu64bwhR Y5rAMiLwsullp80GDgXPMluVw3nuMDCwQe4de8AP5frz8m+k88E1Qil+s6MjPftJBAtw cokJUtFY0BZnkIxYVjtCNMfnV8FxD2XbvIz0iPURLcY4aPKOT7NDs/tuIfAT68p5oHL1 j3NiFEeF1K//xUDkKoT2cRCU0NfqGrgq0zg8+fJAe2pCfM4q2vKEwpdCY8M4R4l/mALx d+kr7On3o6xC/w64xIa3HnZxLxH1J/8tV+JoPjV+AURtYNS70mPMOUvYNtpH+AC8BNnX diSA== X-Gm-Message-State: AOJu0YztFkfuai8VbRXNrslHRNlIP4XuwppbJe2yCOZyWoh30sILn/vH mzTSEBqR2GWPvR0GGEd5a273Wa7CgZhHVoheNMk= X-Google-Smtp-Source: AGHT+IGaMra8M/jDDvWjANcEU/SsuVyJveMRZnAd9RXAgfmjZGeJZWn1y5HWjEUJJKeAY+YiI4GJig== X-Received: by 2002:a81:4904:0:b0:5b3:2acd:8d83 with SMTP id w4-20020a814904000000b005b32acd8d83mr2831374ywa.22.1699019224619; Fri, 03 Nov 2023 06:47:04 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v10 11/18] target/riscv/tcg: add MISA user options hash Date: Fri, 3 Nov 2023 10:46:22 -0300 Message-ID: <20231103134629.561732-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231103134629.561732-1-dbarboza@ventanamicro.com> References: <20231103134629.561732-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1133; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x1133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1699019483587100001 Content-Type: text/plain; charset="utf-8" We already track user choice for multi-letter extensions because we needed to honor user choice when enabling/disabling extensions during realize(). We refrained from adding the same mechanism for MISA extensions since we didn't need it. Profile support requires tne need to check for user choice for MISA extensions, so let's add the corresponding hash now. It works like the existing multi-letter hash (multi_ext_user_opts) but tracking MISA bits options in the cpu_set_misa_ext_cfg() callback. Note that we can't re-use the same hash from multi-letter extensions because that hash uses cpu->cfg offsets as keys, while for MISA extensions we're using MISA bits as keys. After adding the user hash in cpu_set_misa_ext_cfg(), setting default values with object_property_set_bool() in add_misa_properties() will end up marking the user choice hash with them. Set the default value manually to avoid it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 336faf8c3c..2fd395db1c 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -34,6 +34,7 @@ =20 /* Hash that stores user set extensions */ static GHashTable *multi_ext_user_opts; +static GHashTable *misa_ext_user_opts; =20 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) { @@ -779,6 +780,10 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor = *v, const char *name, return; } =20 + g_hash_table_insert(misa_ext_user_opts, + GUINT_TO_POINTER(misa_bit), + (gpointer)value); + prev_val =3D env->misa_ext & misa_bit; =20 if (value =3D=3D prev_val) { @@ -850,6 +855,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { */ static void riscv_cpu_add_misa_properties(Object *cpu_obj) { + CPURISCVState *env =3D &RISCV_CPU(cpu_obj)->env; bool use_def_vals =3D riscv_cpu_is_generic(cpu_obj); int i; =20 @@ -870,7 +876,13 @@ static void riscv_cpu_add_misa_properties(Object *cpu_= obj) NULL, (void *)misa_cfg); object_property_set_description(cpu_obj, name, desc); if (use_def_vals) { - object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NUL= L); + if (misa_cfg->enabled) { + env->misa_ext |=3D bit; + env->misa_ext_mask |=3D bit; + } else { + env->misa_ext &=3D ~bit; + env->misa_ext_mask &=3D ~bit; + } } } } @@ -1115,6 +1127,7 @@ static void tcg_cpu_instance_init(CPUState *cs) RISCVCPU *cpu =3D RISCV_CPU(cs); Object *obj =3D OBJECT(cpu); =20 + misa_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); riscv_cpu_add_user_properties(obj); =20 --=20 2.41.0