From nobody Wed Nov 27 13:52:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1699019530; cv=none; d=zohomail.com; s=zohoarc; b=GanH61HktlS26kwrsaH1YW81puLw3POR1jVgNhW8a8TevkGEQKSaNaACnY+Eil3KtBEA0V7MIFn8Ls5blfyNZWOk9tz9Xbp2AF9uE8W0P1Vf+6OLKKiL/yyaRh1G/BOBMI2q+WbcOvglfjF3iLQrevh5t77xlQqP0T8oG0IRm00= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699019530; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=PlP+Iyr9KpDJ+G112oT1/imB+3zxpn9UeTPe5BqWiPs=; b=CGnXUWPuqLwvIb3Qufe00/QheCAsnhLzpeHIT2QByWm6ieBmZ1tKQ/i1f6dIjtxT2lceCyqHDAwYGC7xKYB1RfCyEyRGybXMr9Aj+cs4dkImXz8TBEfjhUOj8Cva0S5/mhkPzupVulHJFGB7oVFX1tVuBAAOVSOoU3Mpfn3MsHw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699019530249393.19506972164777; Fri, 3 Nov 2023 06:52:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyuWA-0002Dq-NL; Fri, 03 Nov 2023 09:47:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyuW4-00029o-9z for qemu-devel@nongnu.org; Fri, 03 Nov 2023 09:47:16 -0400 Received: from mail-yw1-x1134.google.com ([2607:f8b0:4864:20::1134]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyuVu-0000wM-52 for qemu-devel@nongnu.org; Fri, 03 Nov 2023 09:47:16 -0400 Received: by mail-yw1-x1134.google.com with SMTP id 00721157ae682-5b499b18b28so25219367b3.0 for ; Fri, 03 Nov 2023 06:47:04 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id j68-20020a0df947000000b00582b239674esm935814ywf.129.2023.11.03.06.46.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 06:47:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1699019223; x=1699624023; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PlP+Iyr9KpDJ+G112oT1/imB+3zxpn9UeTPe5BqWiPs=; b=TnormbN/5O1nNLh06+fJXYbaZ2QndPc1jD9vMWYvd00Xy736BJPhlCxyRAeqePwCPy Gq/Ii6K++wOWLD2y6if5lb78asSw4PbzNR90CC9NVGvF7KdqyrDHoyK/B3hrsj3a9ETO U559cuQyCFUvVsmiAjDuIe1lAFyDnsziIHEdp1Si0lksp/lrBs7+u/32zWQIG5s9MV/G OcJDAO16ApOkBW9Ox4AMxebSabRwomuvMzD2h00KD9eFJRbKCNBYmY9Li/bjjnMi3q61 HHB09soLUYDyK1ZazLOC5InuViZFRmPWdmnQw77/co3vGS6wkwX80PYqwmX8TQirDhg0 HxKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699019223; x=1699624023; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PlP+Iyr9KpDJ+G112oT1/imB+3zxpn9UeTPe5BqWiPs=; b=rMw5IznnsrA6AqYn3evCTy+zSIUsqM5mDupKE090tTcbBaE3bj7cPyCYXUllHZebUb i7wlxcyRMdv4hkYVv+RV8HiJTsTi4f1AzxUxBSUBInyuFJqZucAGGEWEebw/qpkrBvkM tlW7pC3ej+0Kom60YzlxFU7uhIjoGnmUkoNMZ5ZRsuV1wS3WHQfggA7Fv8KDqbOBMdnw r04UTJGwPTpZ17QhIIGLElLJMPASYoBO+O8xsiYhRWA0VbdtPnQVSmdqKBJxu0Scie5Z cSMxzlhQFppUkmewFtXbt0cnwLBmWBteqEmsUyjd2IM9fsjfEDQ3SQVmkVR4Ce9OsRHL w8kw== X-Gm-Message-State: AOJu0YxRbiCDLtYcyr0/Q7Zm+KMTjXgFDxLstpuNRxykZ/fWoHCLeZSK 3LS6zWTEuqCULUZ03wDNrdorWcf5M5Xwed9gz2s= X-Google-Smtp-Source: AGHT+IEaTbkD+bwzHWU4NVjSlGMC/gjRiv0uOLYYRbI414kwFyNTREdJ7hpOGBJVL9K55gC7187Axw== X-Received: by 2002:a05:690c:388:b0:59b:cfe1:bcf1 with SMTP id bh8-20020a05690c038800b0059bcfe1bcf1mr2519790ywb.44.1699019221874; Fri, 03 Nov 2023 06:47:01 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v10 10/18] target/riscv/tcg: add user flag for profile support Date: Fri, 3 Nov 2023 10:46:21 -0300 Message-ID: <20231103134629.561732-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231103134629.561732-1-dbarboza@ventanamicro.com> References: <20231103134629.561732-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1134; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x1134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1699019531867100003 Content-Type: text/plain; charset="utf-8" The TCG emulation implements all the extensions described in the RVA22U64 profile, both mandatory and optional. The mandatory extensions will be enabled via the profile flag. We'll leave the optional extensions to be enabled by hand. Given that this is the first profile we're implementing in TCG we'll need some ground work first: - all profiles declared in riscv_profiles[] will be exposed to users. TCG is the main accelerator we're considering when adding profile support in QEMU, so for now it's safe to assume that all profiles in riscv_profiles[] will be relevant to TCG; - we'll not support user profile settings for vendor CPUs. The flags will still be exposed but users won't be able to change them; - profile support, albeit available for all non-vendor CPUs, will be based on top of the new 'rv64i' CPU. Setting a profile to 'true' means enable all mandatory extensions of this profile, setting it to 'false' will disable all mandatory profile extensions of the CPU, which will obliterate preset defaults. This is not a problem for a bare CPU like rv64i but it can allow for silly scenarios when using other CPUs. E.g. an user can do "-cpu rv64,rva22u64=3Dfalse" and have a bunch of default rv64 extensions disabled. The recommended way of using profiles is the rv64i CPU, but users are free to experiment. For now we'll handle multi-letter extensions only. MISA extensions need additional steps that we'll take care later. At this point we can boot a Linux buildroot using rva22u64 using the following options: -cpu rv64i,rva22u64=3Dtrue,sv39=3Dtrue,g=3Dtrue,c=3Dtrue,s=3Dtrue Note that being an usermode/application profile we still need to explicitly set 's=3Dtrue' to enable Supervisor mode to boot Linux. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 63 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c33a355583..336faf8c3c 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -875,6 +875,67 @@ static void riscv_cpu_add_misa_properties(Object *cpu_= obj) } } =20 +static void cpu_set_profile(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPUProfile *profile =3D opaque; + RISCVCPU *cpu =3D RISCV_CPU(obj); + bool value; + int i, ext_offset; + + if (riscv_cpu_is_vendor(obj)) { + error_setg(errp, "Profile %s is not available for vendor CPUs", + profile->name); + return; + } + + if (cpu->env.misa_mxl !=3D MXL_RV64) { + error_setg(errp, "Profile %s only available for 64 bit CPUs", + profile->name); + return; + } + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + profile->user_set =3D true; + profile->enabled =3D value; + + for (i =3D 0; profile->ext_offsets[i] !=3D RISCV_PROFILE_EXT_LIST_END;= i++) { + ext_offset =3D profile->ext_offsets[i]; + + if (profile->enabled) { + cpu_validate_multi_ext_priv_ver(&cpu->env, ext_offset); + } + + g_hash_table_insert(multi_ext_user_opts, + GUINT_TO_POINTER(ext_offset), + (gpointer)profile->enabled); + isa_ext_update_enabled(cpu, ext_offset, profile->enabled); + } +} + +static void cpu_get_profile(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPUProfile *profile =3D opaque; + bool value =3D profile->enabled; + + visit_type_bool(v, name, &value, errp); +} + +static void riscv_cpu_add_profiles(Object *cpu_obj) +{ + for (int i =3D 0; riscv_profiles[i] !=3D NULL; i++) { + const RISCVCPUProfile *profile =3D riscv_profiles[i]; + + object_property_add(cpu_obj, profile->name, "bool", + cpu_get_profile, cpu_set_profile, + NULL, (void *)profile); + } +} + static bool cpu_ext_is_deprecated(const char *ext_name) { return isupper(ext_name[0]); @@ -1002,6 +1063,8 @@ static void riscv_cpu_add_user_properties(Object *obj) =20 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); =20 + riscv_cpu_add_profiles(obj); + for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { qdev_property_add_static(DEVICE(obj), prop); } --=20 2.41.0