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([179.193.10.161]) by smtp.gmail.com with ESMTPSA id ce10-20020a05690c098a00b0059b24bd4f2asm259523ywb.57.2023.11.02.15.45.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Nov 2023 15:45:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698965121; x=1699569921; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WeIpVV+xwLYJejpYC6ocOxy0ApoeLk6Pw/Epuw/aRd4=; b=LtLsUBIUGJ6pKSlRHnNaeCgwIR6Mo870UEvTOHxruRN9w/DCh8oDzWHddeVEBCzajq AUweaJl3FjLPB9jhVCLBnuK/j/ow3VhBDNgS22twRwwDBCuR9pdkxLn7JahtUvFf/2qd zr4wcAE6HJ6/9WSQ9wxHPvHxbS428TsTL+yWKaxSg9KiyyEUwwqUdkCbFMesn6aL4XmQ sGYo+av8kxQJhu2FvOpInuOL1FTDKIFZrgm5i1EyfhqgIhBeqbqKx+2W3kb3KsQfDMRj lVBFXyAEn2OzFm27JVbT/km0HSsZz9LHiKy0M15Aq7Iqqs5+ssuF88QQVFaEu+engfLd UXYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698965121; x=1699569921; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WeIpVV+xwLYJejpYC6ocOxy0ApoeLk6Pw/Epuw/aRd4=; b=K7Q5cC2dT7OqCQGcoVxScsj6MIR+6p0sFjYRyID3XRly0gQGGGMRkcuzbmCNdWBf5+ sNrXnfqpRFTlJdx3E4Askv6UNk0tgnqaZf5tpapqKAleV3Od3V2+EcmCg+6Aq6kKOSnG gXtUTBuZHUrKABG68va1X1NIGZ4xWyFuy3kkKluT1o+ztz2miEUq8/9hCq10XnDmPRNI qlmvEtFnFlVBJg0mLKumZ4xQrJcFum77xl2KnpWUWc4hMDd0iKa/7YXZEZBNwQKFHfmP tjfR6ex8yEpR6DGJyRNdbqX/iYtaBE6TttFNlkYDIA8ArqszBWHzV9lPhcQzdsc2jMN+ swUA== X-Gm-Message-State: AOJu0YzSDWzqRBNT2Akazplu7KBzgbxinwvsy7WMDin5IQJHUNLnJ9ec d1ozSK1pCm/RlTnCE1ZlEMh8i9lFwcTAFaw5xq8= X-Google-Smtp-Source: AGHT+IHqhHkPIs2zxLPQjXn9aqig/RUNM8jcX9EOH/qxINduy57tr7QMJFNRS6Ey2HMkVpNhhDOJWQ== X-Received: by 2002:a0d:d48a:0:b0:5ad:4975:c860 with SMTP id w132-20020a0dd48a000000b005ad4975c860mr1217016ywd.39.1698965121414; Thu, 02 Nov 2023 15:45:21 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v9 12/19] target/riscv/tcg: add riscv_cpu_write_misa_bit() Date: Thu, 2 Nov 2023 19:44:38 -0300 Message-ID: <20231102224445.527355-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231102224445.527355-1-dbarboza@ventanamicro.com> References: <20231102224445.527355-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::112e; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x112e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1698965361118100001 Content-Type: text/plain; charset="utf-8" We have two instances of the setting/clearing a MISA bit from env->misa_ext and env->misa_ext_mask pattern. And the next patch will end up adding one more. Create a helper to avoid code repetition. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c1f203bf34..d80f72a9da 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -42,6 +42,20 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) GUINT_TO_POINTER(ext_offset)); } =20 +static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, + bool enabled) +{ + CPURISCVState *env =3D &cpu->env; + + if (enabled) { + env->misa_ext |=3D bit; + env->misa_ext_mask |=3D bit; + } else { + env->misa_ext &=3D ~bit; + env->misa_ext_mask &=3D ~bit; + } +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -801,13 +815,9 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor = *v, const char *name, */ env->priv_ver =3D PRIV_VERSION_1_12_0; } - - env->misa_ext |=3D misa_bit; - env->misa_ext_mask |=3D misa_bit; - } else { - env->misa_ext &=3D ~misa_bit; - env->misa_ext_mask &=3D ~misa_bit; } + + riscv_cpu_write_misa_bit(cpu, misa_bit, value); } =20 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, @@ -851,7 +861,6 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { */ static void riscv_cpu_add_misa_properties(Object *cpu_obj) { - CPURISCVState *env =3D &RISCV_CPU(cpu_obj)->env; bool use_def_vals =3D riscv_cpu_is_generic(cpu_obj); int i; =20 @@ -872,13 +881,8 @@ static void riscv_cpu_add_misa_properties(Object *cpu_= obj) NULL, (void *)misa_cfg); object_property_set_description(cpu_obj, name, desc); if (use_def_vals) { - if (misa_cfg->enabled) { - env->misa_ext |=3D bit; - env->misa_ext_mask |=3D bit; - } else { - env->misa_ext &=3D ~bit; - env->misa_ext_mask &=3D ~bit; - } + riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, + misa_cfg->enabled); } } } --=20 2.41.0