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([179.193.10.161]) by smtp.gmail.com with ESMTPSA id ce10-20020a05690c098a00b0059b24bd4f2asm259523ywb.57.2023.11.02.15.45.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Nov 2023 15:45:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698965119; x=1699569919; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q95WrFKjJ3lEB45kZzBEwCGqF8+mMghcVkJ4xXnrYEo=; b=RL4J4BLKI2OqWhfwwnjEXzDhlIsQWQ3sqsknn6Ym6QZ//wovb8pS1G96WuIfp1/LTV Ejf9bR9Y92H0DuUBY/k0zH1HcR8AERIXhi0AXbD40c4GmTVSCXuF55hW2zfKkXzZv9YA ctPGNC7PzhtqkH4jNugqa4G99KCLJPTxaE4wSemE0yhw4fbGSf2kQxV5ekiIxKRRu7pe 61Yz4r+aoxZWlrKqtSjgaeP90KfJWqQXQqOsC0/4qmryVs6JyYbenA1x+K8nwNVJnFh5 wt59kw693thTs03aKEqeQsiSB8cUm0giXoVWCErXoMLA6THXUAX362df1+Aa4MUwI4Hv hrqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698965119; x=1699569919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q95WrFKjJ3lEB45kZzBEwCGqF8+mMghcVkJ4xXnrYEo=; b=LOIW5UMSk5E/U+K4vWI6kWuIXJQ2MurNtzcTbfzHZrQU8TIp3ExI2t3ZQ8lKGN+vpp vnMyaRw+xSAW+uPUsDeYe1RMuTKF5FUYEXRZqAjTlmrnCz/VRdieEvW6RM0k6oXojPrb l7JYQPNSlCDyeDkPsc5eILIbab15kPEcLHpZXoRzGtp9IKWJnTPZ5gwlxsqn9dxW1tLQ 9bkEHZhmTih+1E/plzM3dKSyownUCRLstXXzAsxiTlYgnnl3+H8BtYxWWIxp8UavPYa3 /YpihNnBQGRiGcd4VyDEral5SAXKZkUzgZFZ79JZVw/7CLVPOJJbTZezMWBZJMEEmtKi ZF4A== X-Gm-Message-State: AOJu0YwIe+XQVcdSdalzdaEX2510jz2OJ3z/zmiY62OJR2b5GAiVDUMO BfIknBfxlwKaooknm5grBi3PmUtpbWsRcy5UiDE= X-Google-Smtp-Source: AGHT+IHP25JJLV6iPQMYzHBMBVfgqC0Xss+l5Em3PHKimCGiFWIZVmfapgajweVqwvvD+UxIxK27EA== X-Received: by 2002:a05:690c:6:b0:5a1:d352:9fe1 with SMTP id bc6-20020a05690c000600b005a1d3529fe1mr1218979ywb.42.1698965118814; Thu, 02 Nov 2023 15:45:18 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v9 11/19] target/riscv/tcg: add MISA user options hash Date: Thu, 2 Nov 2023 19:44:37 -0300 Message-ID: <20231102224445.527355-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231102224445.527355-1-dbarboza@ventanamicro.com> References: <20231102224445.527355-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::112c; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x112c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1698965268829100011 Content-Type: text/plain; charset="utf-8" We already track user choice for multi-letter extensions because we needed to honor user choice when enabling/disabling extensions during realize(). We refrained from adding the same mechanism for MISA extensions since we didn't need it. Profile support requires tne need to check for user choice for MISA extensions, so let's add the corresponding hash now. It works like the existing multi-letter hash (multi_ext_user_opts) but tracking MISA bits options in the cpu_set_misa_ext_cfg() callback. Note that we can't re-use the same hash from multi-letter extensions because that hash uses cpu->cfg offsets as keys, while for MISA extensions we're using MISA bits as keys. After adding the user hash in cpu_set_misa_ext_cfg(), setting default values with object_property_set_bool() in add_misa_properties() will end up marking the user choice hash with them. Set the default value manually to avoid it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index b52910850f..c1f203bf34 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -34,6 +34,7 @@ =20 /* Hash that stores user set extensions */ static GHashTable *multi_ext_user_opts; +static GHashTable *misa_ext_user_opts; =20 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) { @@ -775,6 +776,10 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor = *v, const char *name, return; } =20 + g_hash_table_insert(misa_ext_user_opts, + GUINT_TO_POINTER(misa_bit), + (gpointer)value); + prev_val =3D env->misa_ext & misa_bit; =20 if (value =3D=3D prev_val) { @@ -846,6 +851,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { */ static void riscv_cpu_add_misa_properties(Object *cpu_obj) { + CPURISCVState *env =3D &RISCV_CPU(cpu_obj)->env; bool use_def_vals =3D riscv_cpu_is_generic(cpu_obj); int i; =20 @@ -866,7 +872,13 @@ static void riscv_cpu_add_misa_properties(Object *cpu_= obj) NULL, (void *)misa_cfg); object_property_set_description(cpu_obj, name, desc); if (use_def_vals) { - object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NUL= L); + if (misa_cfg->enabled) { + env->misa_ext |=3D bit; + env->misa_ext_mask |=3D bit; + } else { + env->misa_ext &=3D ~bit; + env->misa_ext_mask &=3D ~bit; + } } } } @@ -1119,6 +1131,7 @@ static void tcg_cpu_instance_init(CPUState *cs) RISCVCPU *cpu =3D RISCV_CPU(cs); Object *obj =3D OBJECT(cpu); =20 + misa_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); riscv_cpu_add_user_properties(obj); =20 --=20 2.41.0