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([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698871350; x=1699476150; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NT0jvyKzdtzF9zQdRLgFLjwKag0HYamRR1hXbSBg0xk=; b=XRr8wz2pkuuEqhfS0PnBZ/5UziZLP05GuwppteAG38lb0mbhL6D9NBJQlceiOIQnaN uz60n0XsxhcIOPwb2B0G/q2y0WxdQ5T6Uu2F3u+cooguW7ClCmH5J0FYyADk4euaB43r kz6iDAld2CRtNJyP6UeSjvvpNER79AtqDpAGaYTEzFANL25CCcy745UdvvsNRIZVi0qL i39n/FOBN7CY1DtHvcr4EHDgfoCa8KpXywvvSNUMCFintQZJW9EVnzdc4FufTpcNL0Xl 0wAp2TxsUCnzak2HYlhV9J0s4F50rOqTZhOiOVpCfQLUlhxgJEU85Q5dhXo6i6y0JgAh 1LLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698871350; x=1699476150; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NT0jvyKzdtzF9zQdRLgFLjwKag0HYamRR1hXbSBg0xk=; b=AlAK7h1erk/L2EZS2YpvHpQWoOw/nFXLZJIw0aKmIMp8bxyvQbLqRbRkCGZPSttlXY A5+0YI/q38pVzEwzVY10gTh1eiTjip6ErNbNqqbyPmjbu2bVULw9Sl3aaOpXfR5aaxXh pV5DsnT27GtyX/fq9Piy/Q86/n2x3/Oxln+m8kclfczpJa7N5+23glVFLDtblP0cVrIL H0hng3X3+McTHOLgvvjxYIpEThFtfyxn+7WwLuaL54riNWBUJd8xcwskibdMnT0Oup/i 0fNYkeG8nDHXzG0SO4GoZzrGW2uCtf/cNaIWJGvgfFAuJcw9ILVY6aPAbd7ZQJrAj9De xidw== X-Gm-Message-State: AOJu0Yz/31pAaHPacG+217n8FfihEbDDdg63G8jbZd+kARTs2/cAMAc9 CPe589Ik8hCXmJzqFvevSzWNYyDb3eUegwEIdoQ= X-Google-Smtp-Source: AGHT+IGWGcMrKuISnXoWKNcUhrKLPFqdZ/neMYhsvWnay7aSYaajAw695Ea3UzYq4W3dx1peAcJcBA== X-Received: by 2002:a25:7806:0:b0:da0:d0be:ef06 with SMTP id t6-20020a257806000000b00da0d0beef06mr11206622ybc.51.1698871349865; Wed, 01 Nov 2023 13:42:29 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 07/19] target/riscv: add zicbop extension flag Date: Wed, 1 Nov 2023 17:41:52 -0300 Message-ID: <20231101204204.345470-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::b32; envelope-from=dbarboza@ventanamicro.com; helo=mail-yb1-xb32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1698871433619100001 Content-Type: text/plain; charset="utf-8" QEMU already implements zicbom (Cache Block Management Operations) and zicboz (Cache Block Zero Operations). Commit 59cb29d6a5 ("target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder") added placeholders for what would be the instructions for zicbop (Cache Block Prefetch Operations), which are now no-ops. The RVA22U64 profile mandates zicbop, which means that applications that run with this profile might expect zicbop to be present in the riscv,isa DT and might behave badly if it's absent. Adding zicbop as an extension will make our future RVA22U64 implementation more in line with what userspace expects and, if/when cache block prefetch operations became relevant to QEMU, we already have the extension flag to turn then on/off as needed. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- hw/riscv/virt.c | 5 +++++ target/riscv/cpu.c | 3 +++ target/riscv/cpu_cfg.h | 2 ++ 3 files changed, 10 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 1732c42915..99c087240f 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -273,6 +273,11 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, = int socket, cpu_ptr->cfg.cboz_blocksize); } =20 + if (cpu_ptr->cfg.ext_zicbop) { + qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-siz= e", + cpu_ptr->cfg.cbop_blocksize); + } + qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4a6e544eaf..92807f5324 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -78,6 +78,7 @@ const uint32_t misa_bits[] =3D {RVI, RVE, RVM, RVA, RVF, = RVD, RVV, */ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom), + ISA_EXT_DATA_ENTRY(zicbop, PRIV_VERSION_1_12_0, ext_zicbop), ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr), @@ -1367,6 +1368,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false), =20 MULTI_EXT_CFG_BOOL("zicbom", ext_zicbom, true), + MULTI_EXT_CFG_BOOL("zicbop", ext_zicbop, true), MULTI_EXT_CFG_BOOL("zicboz", ext_zicboz, true), =20 MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false), @@ -1455,6 +1457,7 @@ Property riscv_cpu_options[] =3D { DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), + DEFINE_PROP_UINT16("cbop_blocksize", RISCVCPU, cfg.cbop_blocksize, 64), DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), =20 DEFINE_PROP_END_OF_LIST(), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 6eef4a51ea..2203b4c45b 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -65,6 +65,7 @@ struct RISCVCPUConfig { bool ext_zicntr; bool ext_zicsr; bool ext_zicbom; + bool ext_zicbop; bool ext_zicboz; bool ext_zicond; bool ext_zihintntl; @@ -134,6 +135,7 @@ struct RISCVCPUConfig { uint16_t vlen; uint16_t elen; uint16_t cbom_blocksize; + uint16_t cbop_blocksize; uint16_t cboz_blocksize; bool mmu; bool pmp; --=20 2.41.0