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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id h9-20020a170902f7c900b001b8a3e2c241sm3600096plw.14.2023.10.28.12.45.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Oct 2023 12:45:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698522332; x=1699127132; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h+gt0CjYg4HfuULsURoNWzr2njchZ3xEe5eZdBzd0U4=; b=SKojQMpetIQroFyANyAose+wX9fYIlrUvheJ5gxZs18GdUky9al8JSUF8KijCtar41 jmRdiWSYDUwK0tH/0xbrfuaYu2g8Ss8O4xubcesPWQgjaM9XqCirgBIlPgeU219a8UNz Bqh2HGCq0P4Y6TEnZbWpq+X0CTye+6Vcdqvmo5KgVQjgxPXYC3G3PIoP6BHXKvTom/DD QorBPmOhTC6Dk9xdEg1lgwJe1A2r06xIsIpsQNt02Hs/0782dN6sLiRngAGADYzXo00X ouL26TZ4WjevjUSTgJQd+Z1nkE1PqdF4WFarIVxF7Dj/s7Z5Y3opssVJwmu5GGVioyNY drWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698522332; x=1699127132; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h+gt0CjYg4HfuULsURoNWzr2njchZ3xEe5eZdBzd0U4=; b=TzG1eMR/r+Imy9sm/Vzc0gNJ8UrvgkJnFTUYxY7uCcJyFBilvNmaXy/DMgD4mFEp7z 9fKy+ukmUUJ2TaJv+yoymca7lV3N1vcfKlf6YZXsIiU1BYkTPKBJpiJUKZykPfUdfrXQ 1T3EQtDn7IB72JIsg58J/pYZ5BfJsb6dRRpnZ5Zgi6moMmbIb5I2vzoYJu/Id5vxxOZj ohjF95rYRmZTCX1S0ef7O9/wtNGpZmFgdMD8HeA8iF/svxJVNbuCCOsjZ88IPBerFmUS OJ2VudYzjilLmqGu5fCbC044yAaGERFmfFEaidj5F+FVsOgeSrTGB5LYMxC64qokVUy5 j4Xw== X-Gm-Message-State: AOJu0YxHThB+mL8YjRkHAkkmpMp0epV66kA3SGMeZ5VS8aipMhAfwiAz i60nd+d1OLSkjdhqsZaOQ+9p4uEHofYhmHSYP3s= X-Google-Smtp-Source: AGHT+IHs+vXLlm48V53MSv21N1wltJ9jdZu0Ea5C4spLoPj/uNOtAUte03Eugpf3Lov4e6XJU7+LFA== X-Received: by 2002:a17:902:d401:b0:1cc:2f90:6291 with SMTP id b1-20020a170902d40100b001cc2f906291mr2818017ple.54.1698522332518; Sat, 28 Oct 2023 12:45:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, pbonzini@redhat.com Subject: [PATCH v2 09/35] tcg/aarch64: Generate TBZ, TBNZ Date: Sat, 28 Oct 2023 12:44:56 -0700 Message-Id: <20231028194522.245170-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231028194522.245170-1-richard.henderson@linaro.org> References: <20231028194522.245170-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698522510067100003 Content-Type: text/plain; charset="utf-8" Test the sign bit for LT/GE vs 0, and TSTNE/EQ vs a power of 2. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 100 ++++++++++++++++++++++++++++------- 1 file changed, 81 insertions(+), 19 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 70df250c04..55225313ad 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -105,6 +105,18 @@ static bool reloc_pc19(tcg_insn_unit *src_rw, const tc= g_insn_unit *target) return false; } =20 +static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target) +{ + const tcg_insn_unit *src_rx =3D tcg_splitwx_to_rx(src_rw); + ptrdiff_t offset =3D target - src_rx; + + if (offset =3D=3D sextract64(offset, 0, 14)) { + *src_rw =3D deposit32(*src_rw, 5, 14, offset); + return true; + } + return false; +} + static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { @@ -115,6 +127,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int ty= pe, return reloc_pc26(code_ptr, (const tcg_insn_unit *)value); case R_AARCH64_CONDBR19: return reloc_pc19(code_ptr, (const tcg_insn_unit *)value); + case R_AARCH64_TSTBR14: + return reloc_pc14(code_ptr, (const tcg_insn_unit *)value); default: g_assert_not_reached(); } @@ -380,6 +394,10 @@ typedef enum { /* Conditional branch (immediate). */ I3202_B_C =3D 0x54000000, =20 + /* Test and branch (immediate). */ + I3205_TBZ =3D 0x36000000, + I3205_TBNZ =3D 0x37000000, + /* Unconditional branch (immediate). */ I3206_B =3D 0x14000000, I3206_BL =3D 0x94000000, @@ -660,6 +678,14 @@ static void tcg_out_insn_3202(TCGContext *s, AArch64In= sn insn, tcg_out32(s, insn | tcg_cond_to_aarch64[c] | (imm19 & 0x7ffff) << 5); } =20 +static void tcg_out_insn_3205(TCGContext *s, AArch64Insn insn, + TCGReg rt, int imm6, int imm14) +{ + insn |=3D (imm6 & 0x20) << (31 - 5); + insn |=3D (imm6 & 0x1f) << 19; + tcg_out32(s, insn | (imm14 & 0x3fff) << 5 | rt); +} + static void tcg_out_insn_3206(TCGContext *s, AArch64Insn insn, int imm26) { tcg_out32(s, insn | (imm26 & 0x03ffffff)); @@ -1415,30 +1441,66 @@ static inline void tcg_out_goto_label(TCGContext *s= , TCGLabel *l) static void tcg_out_brcond(TCGContext *s, TCGType ext, TCGCond c, TCGArg a, TCGArg b, bool b_const, TCGLabel *l) { - intptr_t offset; - bool need_cmp; + int tbit =3D -1; + bool need_cmp =3D true; =20 - if (b_const && b =3D=3D 0 && (c =3D=3D TCG_COND_EQ || c =3D=3D TCG_CON= D_NE)) { - need_cmp =3D false; - } else { - need_cmp =3D true; - tcg_out_cmp(s, ext, c, a, b, b_const); - } - - if (!l->has_value) { - tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0); - offset =3D tcg_in32(s) >> 5; - } else { - offset =3D tcg_pcrel_diff(s, l->u.value_ptr) >> 2; - tcg_debug_assert(offset =3D=3D sextract64(offset, 0, 19)); + switch (c) { + case TCG_COND_EQ: + case TCG_COND_NE: + if (b_const && b =3D=3D 0) { + need_cmp =3D false; + } + break; + case TCG_COND_LT: + case TCG_COND_GE: + if (b_const && b =3D=3D 0) { + c =3D (c =3D=3D TCG_COND_LT ? TCG_COND_TSTNE : TCG_COND_TSTEQ); + tbit =3D ext ? 63 : 31; + need_cmp =3D false; + } + break; + case TCG_COND_TSTEQ: + case TCG_COND_TSTNE: + if (b_const && is_power_of_2(b)) { + tbit =3D ctz64(b); + need_cmp =3D false; + } + break; + default: + break; } =20 if (need_cmp) { - tcg_out_insn(s, 3202, B_C, c, offset); - } else if (c =3D=3D TCG_COND_EQ) { - tcg_out_insn(s, 3201, CBZ, ext, a, offset); + tcg_out_cmp(s, ext, c, a, b, b_const); + tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0); + tcg_out_insn(s, 3202, B_C, c, 0); + return; + } + + if (tbit >=3D 0) { + tcg_out_reloc(s, s->code_ptr, R_AARCH64_TSTBR14, l, 0); + switch (c) { + case TCG_COND_TSTEQ: + tcg_out_insn(s, 3205, TBZ, a, tbit, 0); + break; + case TCG_COND_TSTNE: + tcg_out_insn(s, 3205, TBNZ, a, tbit, 0); + break; + default: + g_assert_not_reached(); + } } else { - tcg_out_insn(s, 3201, CBNZ, ext, a, offset); + tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0); + switch (c) { + case TCG_COND_EQ: + tcg_out_insn(s, 3201, CBZ, ext, a, 0); + break; + case TCG_COND_NE: + tcg_out_insn(s, 3201, CBNZ, ext, a, 0); + break; + default: + g_assert_not_reached(); + } } } =20 --=20 2.34.1