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b=IdfF1vwMKRdryBo/PicW9MuewRYM4e4IQZd9fkwBP4FCytgSkcl/ZvVGABV6AO63r80c xiFCretqIoiqNyDroDkGWso2ZXKceanjbN8zfQC3YdjGSLHSIMbcm6LIl9pcwlJxB2TI Ln9ZkPCidZWp8qDiUfQw4ljW87ox2iYVDyJ4YNGCWnQadTONV7/x5/4icPIPgrmP0V3T SazwZ5/JigQcsK/KeRCjRR/0QtAoRFhyrYdkMdRVfZDCvScUalhgKAf4Crs2gpQnEoBh ewhrW6WQ7UMrVQ/RegXUoQ1vpSdADoP0Eo5AHtExgEogdZ8Am5dv3nf7Atr71O8yQ2Td lw== From: Chalapathi V To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com, clg@kaod.org, calebs@us.ibm.com, chalapathi.v@ibm.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH v3 2/3] hw/ppc: Add nest1 chiplet model Date: Sat, 28 Oct 2023 06:30:25 -0500 Message-Id: <20231028113026.23510-3-chalapathi.v@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20231028113026.23510-1-chalapathi.v@linux.ibm.com> References: <20231028113026.23510-1-chalapathi.v@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: sAlG8c-IfExLkfjq48PXTWG57bWz9-3Z X-Proofpoint-ORIG-GUID: h2CIsw9cvyNUxU3WafEQip2hdfQ9fCz5 Content-Transfer-Encoding: quoted-printable X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-28_09,2023-10-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 impostorscore=0 mlxscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 clxscore=1015 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310280088 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=chalapathi.v@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1698492735244100003 Content-Type: text/plain; charset="utf-8" The nest1 chiplet handle the high speed i/o traffic over PCIe and others. The nest1 chiplet consists of PowerBus Fabric controller, nest Memory Management Unit, chiplet control unit and more. This commit creates a nest1 chiplet model and initialize and realize the pervasive chiplet model where chiplet control registers are implemented. Signed-off-by: Chalapathi V --- hw/ppc/meson.build | 1 + hw/ppc/pnv_nest1_chiplet.c | 104 ++++++++++++++++++++++++++++++ include/hw/ppc/pnv_nest_chiplet.h | 39 +++++++++++ 3 files changed, 144 insertions(+) create mode 100644 hw/ppc/pnv_nest1_chiplet.c create mode 100644 include/hw/ppc/pnv_nest_chiplet.h diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build index c80d2f6cfb..4e45e5c1a7 100644 --- a/hw/ppc/meson.build +++ b/hw/ppc/meson.build @@ -51,6 +51,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files( 'pnv_homer.c', 'pnv_pnor.c', 'pnv_pervasive.c', + 'pnv_nest1_chiplet.c', )) # PowerPC 4xx boards ppc_ss.add(when: 'CONFIG_PPC405', if_true: files( diff --git a/hw/ppc/pnv_nest1_chiplet.c b/hw/ppc/pnv_nest1_chiplet.c new file mode 100644 index 0000000000..160e2ba4cb --- /dev/null +++ b/hw/ppc/pnv_nest1_chiplet.c @@ -0,0 +1,104 @@ +/* + * QEMU PowerPC nest1 chiplet model + * + * Copyright (c) 2023, IBM Corporation. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/qdev-properties.h" +#include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_xscom.h" +#include "hw/ppc/pnv_nest_chiplet.h" +#include "hw/ppc/pnv_pervasive.h" +#include "hw/ppc/fdt.h" +#include + +/* + * The nest1 chiplet contains chiplet control unit, + * PowerBus/RaceTrack/Bridge logic, nest Memory Management Unit(nMMU) + * and more. + */ + +static void pnv_nest1_chiplet_realize(DeviceState *dev, Error **errp) +{ + PnvNest1Chiplet *nest1_chiplet =3D PNV_NEST1CHIPLET(dev); + + assert(nest1_chiplet->chip); + + object_initialize_child(OBJECT(nest1_chiplet), "perv_chiplet", + &nest1_chiplet->perv_chiplet, + TYPE_PNV_PERV_CHIPLET); + + if (!qdev_realize(DEVICE(&nest1_chiplet->perv_chiplet), NULL, errp)) { + return; + } +} + +static int pnv_nest1_chiplet_dt_xscom(PnvXScomInterface *dev, void *fdt, + int offset) +{ + char *name; + int nest1_chiplet_offset; + const char compat[] =3D "ibm,power10-nest1-chiplet"; + + name =3D g_strdup_printf("nest1_chiplet@%x", + PNV10_XSCOM_NEST1_CTRL_CHIPLET_BASE); + nest1_chiplet_offset =3D fdt_add_subnode(fdt, offset, name); + _FDT(nest1_chiplet_offset); + g_free(name); + + _FDT(fdt_setprop(fdt, nest1_chiplet_offset, "compatible", + compat, sizeof(compat))); + return 0; +} + +static Property pnv_nest1_chiplet_properties[] =3D { + DEFINE_PROP_LINK("chip", PnvNest1Chiplet, chip, TYPE_PNV_CHIP, PnvChip= *), + DEFINE_PROP_END_OF_LIST(), +}; + +static void pnv_nest1_chiplet_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PnvXScomInterfaceClass *xscomc =3D PNV_XSCOM_INTERFACE_CLASS(klass); + + xscomc->dt_xscom =3D pnv_nest1_chiplet_dt_xscom; + + dc->desc =3D "PowerNV nest1 chiplet"; + dc->realize =3D pnv_nest1_chiplet_realize; + device_class_set_props(dc, pnv_nest1_chiplet_properties); +} + +static const TypeInfo pnv_nest1_chiplet_info =3D { + .name =3D TYPE_PNV_NEST1_CHIPLET, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(PnvNest1Chiplet), + .class_init =3D pnv_nest1_chiplet_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_PNV_XSCOM_INTERFACE }, + { } + } +}; + +static void pnv_nest1_chiplet_register_types(void) +{ + type_register_static(&pnv_nest1_chiplet_info); +} + +type_init(pnv_nest1_chiplet_register_types); diff --git a/include/hw/ppc/pnv_nest_chiplet.h b/include/hw/ppc/pnv_nest_ch= iplet.h new file mode 100644 index 0000000000..b2ffe128bd --- /dev/null +++ b/include/hw/ppc/pnv_nest_chiplet.h @@ -0,0 +1,39 @@ +/* + * QEMU PowerPC nest chiplet model + * + * Copyright (c) 2023, IBM Corporation. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef PPC_PNV_NEST1_CHIPLET_H +#define PPC_PNV_NEST1_CHIPLET_H + +#include "hw/ppc/pnv_pervasive.h" + +#define TYPE_PNV_NEST1_CHIPLET "pnv-nest1-chiplet" +#define PNV_NEST1CHIPLET(obj) OBJECT_CHECK(PnvNest1Chiplet, (obj), TYPE_PN= V_NEST1_CHIPLET) + +typedef struct PnvNest1Chiplet { + DeviceState parent; + + struct PnvChip *chip; + + /* common pervasive chiplet unit */ + PnvPervChiplet perv_chiplet; +} PnvNest1Chiplet; + +#endif /*PPC_PNV_NEST1_CHIPLET_H */ --=20 2.31.1