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b=YnYqy/WXXYvmWLwjC5i2B7SPC01oq4AiVdO2OV143yEE2GtggnqCV1b+HRmeBherTslC 0cv4Zu1o8hdWA6k+lPyPcqhEf5xOtUzL/C2tnCSrw8egEG9wMdt83M33ZNFoi0GS9TjS dardGZnSE8G7zNg0D3NI+H71cmvRsFuADKFPbh10lry0dru7wKKIA7d8BJHxhuNeSTX3 wYFibADs/n5cvCWyLyBK/Ym4TQT5pRCVlNHMgwuG/Rj5zJmA0hPzH3EopnmWDevzz/2s p8rjK9UlxNvhA2EzAyHndXtV/w3zMDBmrdqEGGHXcS68+d+ywmyVh4Wf3yc4fi3f20Bu Eg== From: Ninad Palsule To: qemu-devel@nongnu.org, clg@kaod.org, peter.maydell@linaro.org, andrew@codeconstruct.com.au, joel@jms.id.au, pbonzini@redhat.com, marcandre.lureau@redhat.com, berrange@redhat.com, thuth@redhat.com, philmd@linaro.org, lvivier@redhat.com Cc: Ninad Palsule , qemu-arm@nongnu.org Subject: [PATCH v7 09/10] hw/fsi: Added FSI documentation Date: Thu, 26 Oct 2023 11:47:40 -0500 Message-Id: <20231026164741.1184058-10-ninad@linux.ibm.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231026164741.1184058-1-ninad@linux.ibm.com> References: <20231026164741.1184058-1-ninad@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: R_eFr-7EkGSsoNX_Dl6vjbTgC_Qqapbk X-Proofpoint-ORIG-GUID: Qgn_KX8oJMrx1RwaJXthqqEEzQzqLoLI Content-Transfer-Encoding: quoted-printable X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-26_15,2023-10-26_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 impostorscore=0 malwarescore=0 mlxlogscore=700 clxscore=1015 bulkscore=0 adultscore=0 spamscore=0 suspectscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310170001 definitions=main-2310260145 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=ninad@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1698339015503100004 Content-Type: text/plain; charset="utf-8" Documentation for IBM FSI model. Signed-off-by: Ninad Palsule --- v4: - Added separate commit for documentation v7: - Incorporated review comments by Cedric. --- docs/specs/fsi.rst | 138 +++++++++++++++++++++++++++++++++++++++++++ docs/specs/index.rst | 1 + 2 files changed, 139 insertions(+) create mode 100644 docs/specs/fsi.rst diff --git a/docs/specs/fsi.rst b/docs/specs/fsi.rst new file mode 100644 index 0000000000..05a6b6347a --- /dev/null +++ b/docs/specs/fsi.rst @@ -0,0 +1,138 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +IBM's Flexible Service Interface (FSI) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The QEMU FSI emulation implements hardware interfaces between ASPEED SOC, = FSI +master/slave and the end engine. + +FSI is a point-to-point two wire interface which is capable of supporting +distances of up to 4 meters. FSI interfaces have been used successfully for +many years in IBM servers to attach IBM Flexible Support Processors(FSP) to +CPUs and IBM ASICs. + +FSI allows a service processor access to the internal buses of a host POWER +processor to perform configuration or debugging. FSI has long existed in P= OWER +processes and so comes with some baggage, including how it has been integr= ated +into the ASPEED SoC. + +Working backwards from the POWER processor, the fundamental pieces of inte= rest +for the implementation are: (see the `FSI specification`_ for more details) + +1. The Common FRU Access Macro (CFAM), an address space containing various + "engines" that drive accesses on buses internal and external to the POW= ER + chip. Examples include the SBEFIFO and I2C masters. The engines hang of= f of + an internal Local Bus (LBUS) which is described by the CFAM configurati= on + block. + +2. The FSI slave: The slave is the terminal point of the FSI bus for FSI + symbols addressed to it. Slaves can be cascaded off of one another. The + slave's configuration registers appear in address space of the CFAM to + which it is attached. + +3. The FSI master: A controller in the platform service processor (e.g. BM= C) + driving CFAM engine accesses into the POWER chip. At the hardware level + FSI is a bit-based protocol supporting synchronous and DMA-driven acces= ses + of engines in a CFAM. + +4. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in PO= WER + processors. This now makes an appearance in the ASPEED SoC due to tight + integration of the FSI master IP with the OPB, mainly the existence of = an + MMIO-mapping of the CFAM address straight onto a sub-region of the OPB + address space. + +5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the + AST2600. Hardware limitations prevent the OPB from being directly mapped + into APB, so all accesses are indirect through the bridge. + +The LBUS is modelled to maintain the qdev bus hierarchy and to take advant= ages +of the object model to automatically generate the CFAM configuration block. +The configuration block presents engines in the order they are attached to= the +CFAM's LBUS. Engine implementations should subclass the LBusDevice and set= the +'config' member of LBusDeviceClass to match the engine's type. + +CFAM designs offer a lot of flexibility, for instance it is possible for a +CFAM to be simultaneously driven from multiple FSI links. The modeling is = not +so complete; it's assumed that each CFAM is attached to a single FSI slave= (as +a consequence the CFAM subclasses the FSI slave). + +As for FSI, its symbols and wire-protocol are not modelled at all. This is= not +necessary to get FSI off the ground thanks to the mapping of the CFAM addr= ess +space onto the OPB address space - the models follow this directly and map= the +CFAM memory region into the OPB's memory region. + +QEMU files related to FSI interface: + - ``hw/fsi/aspeed-apb2opb.c`` + - ``include/hw/fsi/aspeed-apb2opb.h`` + - ``hw/fsi/opb.c`` + - ``include/hw/fsi/opb.h`` + - ``hw/fsi/fsi.c`` + - ``include/hw/fsi/fsi.h`` + - ``hw/fsi/fsi-master.c`` + - ``include/hw/fsi/fsi-master.h`` + - ``hw/fsi/fsi-slave.c`` + - ``include/hw/fsi/fsi-slave.h`` + - ``hw/fsi/cfam.c`` + - ``include/hw/fsi/cfam.h`` + - ``hw/fsi/engine-scratchpad.c`` + - ``include/hw/fsi/engine-scratchpad.h`` + - ``include/hw/fsi/lbus.h`` + +The following commands start the rainier machine with built-in FSI model. +There are no model specific arguments. + +.. code-block:: console + + qemu-system-arm -M rainier-bmc -nographic \ + -kernel fitImage-linux.bin \ + -dtb aspeed-bmc-ibm-rainier.dtb \ + -initrd obmc-phosphor-initramfs.rootfs.cpio.xz \ + -drive file=3Dobmc-phosphor-image.rootfs.wic.qcow2,if=3Dsd,index=3D2 \ + -append "rootwait console=3DttyS4,115200n8 root=3DPARTLABEL=3Drofs-a" + +The implementation appears as following in the qemu device tree: + +.. code-block:: console + + (qemu) info qtree + bus: main-system-bus + type System + ... + dev: aspeed.apb2opb, id "" + gpio-out "sysbus-irq" 1 + mmio 000000001e79b000/0000000000001000 + bus: opb.1 + type opb + dev: fsi.master, id "" + bus: fsi.bus.1 + type fsi.bus + dev: cfam.config, id "" + dev: cfam, id "" + bus: lbus.1 + type lbus + dev: scratchpad, id "" + address =3D 0 (0x0) + bus: opb.0 + type opb + dev: fsi.master, id "" + bus: fsi.bus.0 + type fsi.bus + dev: cfam.config, id "" + dev: cfam, id "" + bus: lbus.0 + type lbus + dev: scratchpad, id "" + address =3D 0 (0x0) + +pdbg is a simple application to allow debugging of the host POWER processo= rs +from the BMC. (see the `pdbg source repository`_ for more details) + +.. code-block:: console + + root@p10bmc:~# pdbg -a getcfam 0x0 + p0: 0x0 =3D 0xc0022d15 + +.. _FSI specification: + https://openpowerfoundation.org/specifications/fsi/ + +.. _pdbg source repository: + https://github.com/open-power/pdbg diff --git a/docs/specs/index.rst b/docs/specs/index.rst index e58be38c41..255a1c6536 100644 --- a/docs/specs/index.rst +++ b/docs/specs/index.rst @@ -24,3 +24,4 @@ guest hardware that is specific to QEMU. acpi_erst sev-guest-firmware fw_cfg + fsi --=20 2.39.2