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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id y6-20020a170902864600b001c0c86a5415sm9817032plt.154.2023.10.25.18.39.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 18:39:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698284389; x=1698889189; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FoKclLNER0V8XEHrKIXGl1qWfltrfJBKVAYf+F60a9E=; b=Jm8ziepP689N0M/Uwee1IybdKnGvVAepVoevyZa9nBWWNZMSvJjVNNV0HWY+6Q5iT7 zqMzcWuhJnzHhHQBDBB3YLh9AO8HlOJ22Xj5hwWKOTjrLHwro4qV8mX9k4uVanwa7PZg aM/WqHrsOAWOeoJ+EIwCIW65v8bhxmyah7fyM89w5IDf3g5NmJ6+rY56n5m8Lz6T5Kpv MhYf3TNiCdt5mCDLJAL7FspiQ1tGErGAcxdWPygR7P+z1oqvKo8yAqsFN63CyrsibZ14 KKkaaWXGhkbbQC+ckYm3HW6XNCly/xhwEUeC7GQOOnfUWEWXUdjJ6hmjIDPXz+eT1Ln3 C1Iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698284389; x=1698889189; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FoKclLNER0V8XEHrKIXGl1qWfltrfJBKVAYf+F60a9E=; b=DSCR/quWBBuBCrszoFgJ7AGLGbnmf3I1XqvhHnGgiXFxTf/S2Y3rYkdrdDDEp3AK9G Cs90M3BjpcKRu4joIi8P0cyoDaWmeliXeADyGDu4x0Rio5NxpNGBR3jvYff7TuHXqlVD L4TDjat1nu+RvRdNlB5Ri4g3LzW5xL8yA1IuTXsfkU9TLfGRhJYDbE6gS6NrLuKnbExR wpWsiY8pRzjlofY6aBUkQxmWSLrViCSJmfkRGD20NicgnDa/F1X7mOBhHjCNzV7EJ7s/ +5691TP7NuOGEWyCOCU4iTxWojri4S9/U7M1PWVlj/A7JU26/rRdwGSMA2Kp9Q8V5wL1 iHrQ== X-Gm-Message-State: AOJu0YzIR7zwP549qZszvkyu7EZD3bj9iDKD71AYX3IT5cFouHoxUicE woAwZDH48+4DKV+xT75Ev3DNCPlUIlNN5KIgdvU= X-Google-Smtp-Source: AGHT+IG8uN4yYSgNoWUitVKdaeAwkToyh+oFl0WphejWPLFeQJbDYkz1S/UopSvPBy1/KjsanJjPvw== X-Received: by 2002:a17:902:edc2:b0:1c6:2d13:5b77 with SMTP id q2-20020a170902edc200b001c62d135b77mr16245109plk.39.1698284389657; Wed, 25 Oct 2023 18:39:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH 4/4] NOTFORMERGE tcg/i386: Assert sub of immediate has been folded Date: Wed, 25 Oct 2023 18:39:45 -0700 Message-Id: <20231026013945.1152174-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026013945.1152174-1-richard.henderson@linaro.org> References: <20231026013945.1152174-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698284433193100003 Content-Type: text/plain; charset="utf-8" A release build should simply accept and emit the subtract. I'm not even sure if this is reasonable to keep for debug. Not-Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg.c | 49 ++++++++++++++++++++++++++------------- tcg/i386/tcg-target.c.inc | 13 ++++++++--- 2 files changed, 43 insertions(+), 19 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index a507c111cf..408647af7e 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3618,23 +3618,40 @@ liveness_pass_1(TCGContext *s) do_addsub2: nb_iargs =3D 4; nb_oargs =3D 2; - /* Test if the high part of the operation is dead, but not - the low part. The result can be optimized to a simple - add or sub. This happens often for x86_64 guest when the - cpu mode is set to 32 bit. */ - if (arg_temp(op->args[1])->state =3D=3D TS_DEAD) { - if (arg_temp(op->args[0])->state =3D=3D TS_DEAD) { - goto do_remove; - } - /* Replace the opcode and adjust the args in place, - leaving 3 unused args at the end. */ - op->opc =3D opc =3D opc_new; - op->args[1] =3D op->args[2]; - op->args[2] =3D op->args[4]; - /* Fall through and mark the single-word operation live. = */ - nb_iargs =3D 2; - nb_oargs =3D 1; + /* + * Test if the high part of the operation is dead, but the low + * part is still live. The result can be optimized to a simple + * add or sub. + */ + if (arg_temp(op->args[1])->state !=3D TS_DEAD) { + goto do_not_remove; } + if (arg_temp(op->args[0])->state =3D=3D TS_DEAD) { + goto do_remove; + } + /* + * Replace the opcode and adjust the args in place, leaving 3 + * unused args at the end. Canonicalize subi to andi. + */ + op->args[1] =3D op->args[2]; + { + TCGTemp *src2 =3D arg_temp(op->args[4]); + if (src2->kind =3D=3D TEMP_CONST) { + if (opc_new =3D=3D INDEX_op_sub_i32) { + src2 =3D tcg_constant_internal(TCG_TYPE_I32, + (int32_t)-src2->val); + opc_new =3D INDEX_op_add_i32; + } else if (opc_new =3D=3D INDEX_op_sub_i64) { + src2 =3D tcg_constant_internal(TCG_TYPE_I64, -src2= ->val); + opc_new =3D INDEX_op_add_i64; + } + } + op->args[2] =3D temp_arg(src2); + } + op->opc =3D opc =3D opc_new; + /* Mark the single-word operation live. */ + nb_iargs =3D 2; + nb_oargs =3D 1; goto do_not_remove; =20 case INDEX_op_mulu2_i32: diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 0d97864174..39d03fa698 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2544,8 +2544,14 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, c =3D ARITH_ADD; goto gen_arith; OP_32_64(sub): - c =3D ARITH_SUB; - goto gen_arith; + /* + * Should have canonicalized all constants to add. + * Keep the constraint allowing any constant so that we catch this + * case without register allocation loading the constant first. + */ + tcg_debug_assert(!const_a2); + tgen_arithr(s, ARITH_SUB + rexw, a0, a2); + break; OP_32_64(and): c =3D ARITH_AND; goto gen_arith; @@ -3325,7 +3331,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) return C_O1_I2(r, r, re); =20 case INDEX_op_sub_i32: - case INDEX_op_sub_i64: case INDEX_op_mul_i32: case INDEX_op_mul_i64: case INDEX_op_or_i32: @@ -3333,6 +3338,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_xor_i32: case INDEX_op_xor_i64: return C_O1_I2(r, 0, re); + case INDEX_op_sub_i64: + return C_O1_I2(r, 0, ri); =20 case INDEX_op_and_i32: case INDEX_op_and_i64: --=20 2.34.1