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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:22:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279776; x=1698884576; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MS8CtSutyWAJAksCJoGHPpSo/oeGceEkhH07ubL3sMY=; b=BygX+Jj9NP+IVqkgQagfv+J67MDHAtp6KEeb+RNQfDj0OXEKauQtg/QaFHkIPh6f7M rgM4f1mT+c37T3gEduVYzLuu0xlB1RaXFLvjPY87mlhHLlUsmz7ozt79KvXVf2uWVNFk /zTnOCtIDU5EMKhP1VD0Wr1yk0PQzFlLNBM05UIg6xfQI2XOvHQoYr6HxCdKVG1HJOfw uA45yGmZK+pDLpukjqOoMiuLSBDdUPg7HkaBlAwGdNYlDVmfM0BGDhGY9qmbFHUmDG29 QLpYIyDGmJV+uJxdwQ4JUfjEuFDTjCeLOkOeTJpYyUBfoQWRdZGS5fHejq1Ld6ERYjyr 58nA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279776; x=1698884576; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MS8CtSutyWAJAksCJoGHPpSo/oeGceEkhH07ubL3sMY=; b=htAxAL9rnWA/LSQplEvByUnlz3RMdsuXHNapksK+sFFlhTusssobbV75shmh9hTDW6 +RfoMrVII+92dRp7U/IHYmO9jx8iNWuEgZzD+SG9r9Ash+m8MqIIffc/lCDX0vzvAw/I uliekMx5+l/EvyiIUH8GG/ZeXsPm3wL1Wot9At9limPR1g+iUTRcG6pnjuVOvTWaeOC1 rQq8qiyvtNOqvEw8z71w2fCo/PFYwkm8tArKYvRmvF2VyytzLl8Rm4tCXX9ymDQj81zu LyP+F5uAD525lcDhhV+ouMwsA+ajMoGY8+zxl9JhJ8LBen5l7S5nXuw5n2VZXv1rnsAQ pnZg== X-Gm-Message-State: AOJu0YxRiKrP6hAxumU//O0lvtXRGeiZDlgeun2wMD/emgTAZelJTwSu rPss/opH3Y+iBDrzbgCHqcxplFxRtvvKSmxEnbE= X-Google-Smtp-Source: AGHT+IFDacrXp5DWghQ2gKumDQebG2jRrcGn2iZGQMydEZAYRgTZo08L0COJaIOkuc4ZLg17rhnVGg== X-Received: by 2002:a17:90b:1093:b0:27d:2c3c:7e25 with SMTP id gj19-20020a17090b109300b0027d2c3c7e25mr14823515pjb.46.1698279776085; Wed, 25 Oct 2023 17:22:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 58/94] target/sparc: Split out fp ldst functions with asi precomputed Date: Wed, 25 Oct 2023 17:15:06 -0700 Message-Id: <20231026001542.1141412-88-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280279935100001 Content-Type: text/plain; charset="utf-8" Take the operation size from the MemOp instead of a separate parameter. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 138 +++++++++++++++++++++++---------------- 1 file changed, 80 insertions(+), 58 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 363d8b7fc8..55d6f83736 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2320,35 +2320,41 @@ static void gen_ldstub_asi(DisasContext *dc, DisasA= SI *da, TCGv dst, TCGv addr) } } =20 -static void __attribute__((unused)) -gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) +static void gen_ldf_asi0(DisasContext *dc, DisasASI *da, MemOp orig_size, + TCGv addr, int rd) { - DisasASI da =3D get_asi(dc, insn, (size =3D=3D 4 ? MO_TEUL : MO_TEUQ)); + MemOp memop =3D da->memop; + MemOp size =3D memop & MO_SIZE; TCGv_i32 d32; TCGv_i64 d64; =20 - switch (da.type) { + /* TODO: Use 128-bit load/store below. */ + if (size =3D=3D MO_128) { + memop =3D (memop & ~MO_SIZE) | MO_64; + } + + switch (da->type) { case GET_ASI_EXCP: break; =20 case GET_ASI_DIRECT: - gen_address_mask(dc, addr); + memop |=3D MO_ALIGN_4; switch (size) { - case 4: + case MO_32: d32 =3D gen_dest_fpr_F(dc); - tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN= ); + tcg_gen_qemu_ld_i32(d32, addr, da->mem_idx, memop); gen_store_fpr_F(dc, rd, d32); break; - case 8: - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, - da.memop | MO_ALIGN_4); + + case MO_64: + tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da->mem_idx, memop); break; - case 16: + + case MO_128: d64 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(d64, addr, da.mem_idx, da.memop | MO_ALIGN= _4); + tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, - da.memop | MO_ALIGN_4); + tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + 1], addr, da->mem_idx, me= mop); tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); break; default: @@ -2358,24 +2364,19 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, = int size, int rd) =20 case GET_ASI_BLOCK: /* Valid for lddfa on aligned registers only. */ - if (size =3D=3D 8 && (rd & 7) =3D=3D 0) { - MemOp memop; + if (orig_size =3D=3D MO_64 && (rd & 7) =3D=3D 0) { TCGv eight; int i; =20 - gen_address_mask(dc, addr); - /* The first operation checks required alignment. */ - memop =3D da.memop | MO_ALIGN_64; eight =3D tcg_constant_tl(8); for (i =3D 0; ; ++i) { - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, - da.mem_idx, memop); + tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx, + memop | (i =3D=3D 0 ? MO_ALIGN_64 : 0)= ); if (i =3D=3D 7) { break; } tcg_gen_add_tl(addr, addr, eight); - memop =3D da.memop; } } else { gen_exception(dc, TT_ILL_INSN); @@ -2384,10 +2385,9 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, i= nt size, int rd) =20 case GET_ASI_SHORT: /* Valid for lddfa only. */ - if (size =3D=3D 8) { - gen_address_mask(dc, addr); - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, - da.memop | MO_ALIGN); + if (orig_size =3D=3D MO_64) { + tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da->mem_idx, + memop | MO_ALIGN); } else { gen_exception(dc, TT_ILL_INSN); } @@ -2395,8 +2395,8 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, in= t size, int rd) =20 default: { - TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); - TCGv_i32 r_mop =3D tcg_constant_i32(da.memop | MO_ALIGN); + TCGv_i32 r_asi =3D tcg_constant_i32(da->asi); + TCGv_i32 r_mop =3D tcg_constant_i32(memop | MO_ALIGN); =20 save_state(dc); /* According to the table in the UA2011 manual, the only @@ -2404,21 +2404,23 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, = int size, int rd) the NO_FAULT asis. We still need a helper for these, but we can just use the integer asi helper for them. */ switch (size) { - case 4: + case MO_32: d64 =3D tcg_temp_new_i64(); gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop); d32 =3D gen_dest_fpr_F(dc); tcg_gen_extrl_i64_i32(d32, d64); gen_store_fpr_F(dc, rd, d32); break; - case 8: - gen_helper_ld_asi(cpu_fpr[rd / 2], tcg_env, addr, r_asi, r= _mop); + case MO_64: + gen_helper_ld_asi(cpu_fpr[rd / 2], tcg_env, addr, + r_asi, r_mop); break; - case 16: + case MO_128: d64 =3D tcg_temp_new_i64(); gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop); tcg_gen_addi_tl(addr, addr, 8); - gen_helper_ld_asi(cpu_fpr[rd/2+1], tcg_env, addr, r_asi, r= _mop); + gen_helper_ld_asi(cpu_fpr[rd / 2 + 1], tcg_env, addr, + r_asi, r_mop); tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); break; default: @@ -2430,36 +2432,52 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, = int size, int rd) } =20 static void __attribute__((unused)) -gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) +gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) { - DisasASI da =3D get_asi(dc, insn, (size =3D=3D 4 ? MO_TEUL : MO_TEUQ)); + MemOp sz =3D ctz32(size); + DisasASI da =3D get_asi(dc, insn, MO_TE | sz); + + gen_address_mask(dc, addr); + gen_ldf_asi0(dc, &da, sz, addr, rd); +} + +static void gen_stf_asi0(DisasContext *dc, DisasASI *da, MemOp orig_size, + TCGv addr, int rd) +{ + MemOp memop =3D da->memop; + MemOp size =3D memop & MO_SIZE; TCGv_i32 d32; =20 - switch (da.type) { + /* TODO: Use 128-bit load/store below. */ + if (size =3D=3D MO_128) { + memop =3D (memop & ~MO_SIZE) | MO_64; + } + + switch (da->type) { case GET_ASI_EXCP: break; =20 case GET_ASI_DIRECT: - gen_address_mask(dc, addr); + memop |=3D MO_ALIGN_4; switch (size) { - case 4: + case MO_32: d32 =3D gen_load_fpr_F(dc, rd); - tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN= ); + tcg_gen_qemu_st_i32(d32, addr, da->mem_idx, memop | MO_ALIGN); break; - case 8: - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, - da.memop | MO_ALIGN_4); + case MO_64: + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx, + memop | MO_ALIGN_4); break; - case 16: + case MO_128: /* Only 4-byte alignment required. However, it is legal for t= he cpu to signal the alignment fault, and the OS trap handler = is required to fix it up. Requiring 16-byte alignment here av= oids having to probe the second page before performing the first write. */ - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, - da.memop | MO_ALIGN_16); + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx, + memop | MO_ALIGN_16); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_st_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, da.memo= p); + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + 1], addr, da->mem_idx, me= mop); break; default: g_assert_not_reached(); @@ -2468,24 +2486,19 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, = int size, int rd) =20 case GET_ASI_BLOCK: /* Valid for stdfa on aligned registers only. */ - if (size =3D=3D 8 && (rd & 7) =3D=3D 0) { - MemOp memop; + if (orig_size =3D=3D MO_64 && (rd & 7) =3D=3D 0) { TCGv eight; int i; =20 - gen_address_mask(dc, addr); - /* The first operation checks required alignment. */ - memop =3D da.memop | MO_ALIGN_64; eight =3D tcg_constant_tl(8); for (i =3D 0; ; ++i) { - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, - da.mem_idx, memop); + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx, + memop | (i =3D=3D 0 ? MO_ALIGN_64 : 0)= ); if (i =3D=3D 7) { break; } tcg_gen_add_tl(addr, addr, eight); - memop =3D da.memop; } } else { gen_exception(dc, TT_ILL_INSN); @@ -2494,10 +2507,9 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, i= nt size, int rd) =20 case GET_ASI_SHORT: /* Valid for stdfa only. */ - if (size =3D=3D 8) { - gen_address_mask(dc, addr); - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, - da.memop | MO_ALIGN); + if (orig_size =3D=3D MO_64) { + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx, + memop | MO_ALIGN); } else { gen_exception(dc, TT_ILL_INSN); } @@ -2512,6 +2524,16 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, i= nt size, int rd) } } =20 +static void __attribute__((unused)) +gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) +{ + MemOp sz =3D ctz32(size); + DisasASI da =3D get_asi(dc, insn, MO_TE | sz); + + gen_address_mask(dc, addr); + gen_stf_asi0(dc, &da, sz, addr, rd); +} + static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) { TCGv hi =3D gen_dest_gpr(dc, rd); --=20 2.34.1