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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280175717100008 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 8 ++++++-- target/sparc/translate.c | 23 ++++++++--------------- 2 files changed, 14 insertions(+), 17 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 82c484fbc7..aa452f1d00 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -231,6 +231,9 @@ RESTORE 10 ..... 111101 ..... . ............. = @r_r_ri DONE 10 00000 111110 00000 0 0000000000000 RETRY 10 00001 111110 00000 0 0000000000000 =20 +NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 +NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 + ## ## Major Opcode 11 -- load and store instructions ## @@ -299,8 +302,9 @@ CASA 11 ..... 111100 ..... . ............. = @casa_imm CASXA 11 ..... 111110 ..... . ............. @r_r_r_asi CASXA 11 ..... 111110 ..... . ............. @casa_imm =20 -NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 -NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 +NOP_v9 11 ----- 101101 ----- 0 00000000 ----- # PREFETCH +NOP_v9 11 ----- 101101 ----- 1 ------------- # PREFETCH +NOP_v9 11 ----- 111101 ----- - ------------- # PREFETCHA =20 NCP 11 ----- 110000 ----- --------- ----- # v8 LDC NCP 11 ----- 110001 ----- --------- ----- # v8 LDCSR diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 2175c00ded..363d8b7fc8 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4031,17 +4031,12 @@ static bool trans_NOP(DisasContext *dc, arg_NOP *a) return advance_pc(dc); } =20 -static bool trans_NOP_v7(DisasContext *dc, arg_NOP_v7 *a) -{ - /* - * TODO: Need a feature bit for sparcv8. - * In the meantime, treat all 32-bit cpus like sparcv7. - */ - if (avail_32(dc)) { - return advance_pc(dc); - } - return false; -} +/* + * TODO: Need a feature bit for sparcv8. + * In the meantime, treat all 32-bit cpus like sparcv7. + */ +TRANS(NOP_v7, 32, trans_NOP, a) +TRANS(NOP_v9, 64, trans_NOP, a) =20 static bool do_arith_int(DisasContext *dc, arg_r_r_ri_cc *a, int cc_op, void (*func)(TCGv, TCGv, TCGv), @@ -5457,10 +5452,10 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 0x0b: /* V9 ldx */ case 0x18: /* V9 ldswa */ case 0x1b: /* V9 ldxa */ + case 0x2d: /* V9 prefetch */ + case 0x3d: /* V9 prefetcha */ goto illegal_insn; /* in decodetree */ #ifdef TARGET_SPARC64 - case 0x2d: /* V9 prefetch, no effect */ - goto skip_move; case 0x30: /* V9 ldfa */ if (gen_trap_ifnofpu(dc)) { goto jmp_insn; @@ -5475,8 +5470,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd)); gen_update_fprs_dirty(dc, DFPREG(rd)); goto skip_move; - case 0x3d: /* V9 prefetcha, no effect */ - goto skip_move; case 0x32: /* V9 ldqfa */ CHECK_FPU_FEATURE(dc, FLOAT128); if (gen_trap_ifnofpu(dc)) { --=20 2.34.1