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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.22.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:22:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279772; x=1698884572; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jZBbjchxW1tHrNN5v0YkGnZIiPMEUx8oDtYFBFTOGuQ=; b=n1AyPk7kp2Cdh3G1FlMsXyqbcRDtsarjxZs5iZqI43FGzj0JWCUq+0Ky6ewqNxVeD6 eWU7koCtwUnw6VqjDixNmvDp9ajf233i6YLtfPNRFc9pxxDjYH1ptOAoT0MyxtH08I0s +z2d/IQ4I2ittE7o6Zqv9jGbVCyOzIxQXyzcUFF/aiMOivPL8RMuQiIiNSG9hT1+L+oM sy+GQSvyeifq/pKO/AeoqY8VOriPpcUE79rPdqD6nXkx+v2ZZKRAfvQn9hVPsMSrYamB ekno/ax8IhBjBUW3medjr9MDl72ERu0zEYrl1pJgIL7yXBmq4pyV4cMgy078Lycz0iCe bkVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279772; x=1698884572; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jZBbjchxW1tHrNN5v0YkGnZIiPMEUx8oDtYFBFTOGuQ=; b=mmkBn3JOhBoGSvymbzi6OHjaR+xu68/nT6EvOWitbN+2UyEzql4KiGvJGb/RzPnzLZ kql/segrvxAI1lfGE1kEXeaVIfJPIcwtsVg4zNCGu4ficWoWLhUqjEMQdr6fB40PCx06 daG1VRM8TUpKTBr3JzngeZQfH4LHySoB0r0jebTAooy6IBPJpomypw9QdEnMCxIcZW+8 J1NxFwV1bnJb2wUJ2T0o8yx4dmfSwBTLJNvrThxjQGwfu/XGRZii4fPbLqHHo9msoKdG 8W+nbkRlqzLGYJjRDV3mnvoCnOlLcTuwLClnlrPTIvX6g+zRr7fdlnEpTIVEAfgpU8Al ntTg== X-Gm-Message-State: AOJu0YyCOeUU7MG2+n6pXOvur0+caezvM8Kny1bgrgiQnKo/2Hq90Q96 PprjANr0+acCOSoz2KBnW1yF/R/bF9NhQ4VUByc= X-Google-Smtp-Source: AGHT+IHfI9yJruwdJdeJynHVEAieaX/vzZhRkk4e8IEe8ix0EILLXnnEj2bZl/RtW4KrsUYH1u3cnQ== X-Received: by 2002:a17:90a:7442:b0:27d:9b67:7fa6 with SMTP id o2-20020a17090a744200b0027d9b677fa6mr14984972pjk.3.1698279771997; Wed, 25 Oct 2023 17:22:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 53/94] target/sparc: Move asi integer load/store to decodetree Date: Wed, 25 Oct 2023 17:15:01 -0700 Message-Id: <20231026001542.1141412-83-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280360972100003 Content-Type: text/plain; charset="utf-8" Move LDDA, LDSBA, LDSHA, LDSWA, LDUBA, LDUHA, LDUWA, LDXA, STBA, STDA, STHA, STWA, STXA. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 31 +++++++++ target/sparc/translate.c | 128 +++++--------------------------------- 2 files changed, 48 insertions(+), 111 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 6197fbdb03..280b19f033 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -237,6 +237,9 @@ RETRY 10 00001 111110 00000 0 0000000000000 =20 &r_r_ri_asi rd rs1 rs2_or_imm asi imm:bool @r_r_ri_na .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_asi asi= =3D-1 +@r_r_r_asi .. rd:5 ...... rs1:5 0 asi:8 rs2_or_imm:5 &r_r_ri_asi imm= =3D0 +@r_r_i_asi .. rd:5 ...... rs1:5 1 rs2_or_imm:s13 \ + &r_r_ri_asi imm=3D1 asi=3D-2 =20 LDUW 11 ..... 000000 ..... . ............. @r_r_ri_na LDUB 11 ..... 000001 ..... . ............. @r_r_ri_na @@ -253,6 +256,34 @@ STH 11 ..... 000110 ..... . ............. = @r_r_ri_na STD 11 ..... 000111 ..... . ............. @r_r_ri_na STX 11 ..... 001110 ..... . ............. @r_r_ri_na =20 +LDUW 11 ..... 010000 ..... . ............. @r_r_r_asi # LD= UWA +LDUW 11 ..... 010000 ..... . ............. @r_r_i_asi # LD= UWA +LDUB 11 ..... 010001 ..... . ............. @r_r_r_asi # LD= UBA +LDUB 11 ..... 010001 ..... . ............. @r_r_i_asi # LD= UBA +LDUH 11 ..... 010010 ..... . ............. @r_r_r_asi # LD= UHA +LDUH 11 ..... 010010 ..... . ............. @r_r_i_asi # LD= UHA +LDD 11 ..... 010011 ..... . ............. @r_r_r_asi # LD= DA +LDD 11 ..... 010011 ..... . ............. @r_r_i_asi # LD= DA +LDX 11 ..... 011011 ..... . ............. @r_r_r_asi # LD= XA +LDX 11 ..... 011011 ..... . ............. @r_r_i_asi # LD= XA +LDSB 11 ..... 011001 ..... . ............. @r_r_r_asi # LD= SBA +LDSB 11 ..... 011001 ..... . ............. @r_r_i_asi # LD= SBA +LDSH 11 ..... 011010 ..... . ............. @r_r_r_asi # LD= SHA +LDSH 11 ..... 011010 ..... . ............. @r_r_i_asi # LD= SHA +LDSW 11 ..... 011000 ..... . ............. @r_r_r_asi # LD= SWA +LDSW 11 ..... 011000 ..... . ............. @r_r_i_asi # LD= SWA + +STW 11 ..... 010100 ..... . ............. @r_r_r_asi # ST= WA +STW 11 ..... 010100 ..... . ............. @r_r_i_asi # ST= WA +STB 11 ..... 010101 ..... . ............. @r_r_r_asi # ST= BA +STB 11 ..... 010101 ..... . ............. @r_r_i_asi # ST= BA +STH 11 ..... 010110 ..... . ............. @r_r_r_asi # ST= HA +STH 11 ..... 010110 ..... . ............. @r_r_i_asi # ST= HA +STD 11 ..... 010111 ..... . ............. @r_r_r_asi # ST= DA +STD 11 ..... 010111 ..... . ............. @r_r_i_asi # ST= DA +STX 11 ..... 011110 ..... . ............. @r_r_r_asi # ST= XA +STX 11 ..... 011110 ..... . ............. @r_r_i_asi # ST= XA + NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index db09255854..74cf3105f0 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2162,7 +2162,7 @@ static void gen_helper_st_asi(TCGv_env e, TCGv a, TCG= v_i64 r, } #endif =20 -static void gen_ld_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv add= r) +static void gen_ld_asi(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr) { switch (da->type) { case GET_ASI_EXCP: @@ -2193,16 +2193,7 @@ static void gen_ld_asi0(DisasContext *dc, DisasASI *= da, TCGv dst, TCGv addr) } } =20 -static void __attribute__((unused)) -gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop) -{ - DisasASI da =3D get_asi(dc, insn, memop); - - gen_address_mask(dc, addr); - gen_ld_asi0(dc, &da, dst, addr); -} - -static void gen_st_asi0(DisasContext *dc, DisasASI *da, TCGv src, TCGv add= r) +static void gen_st_asi(DisasContext *dc, DisasASI *da, TCGv src, TCGv addr) { switch (da->type) { case GET_ASI_EXCP: @@ -2274,15 +2265,6 @@ static void gen_st_asi0(DisasContext *dc, DisasASI *= da, TCGv src, TCGv addr) } } =20 -static void __attribute__((unused)) -gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop) -{ - DisasASI da =3D get_asi(dc, insn, memop); - - gen_address_mask(dc, addr); - gen_st_asi0(dc, &da, src, addr); -} - static void gen_swap_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv src, TCGv addr) { @@ -2584,7 +2566,7 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, in= t size, int rd) } } =20 -static void gen_ldda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int r= d) +static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) { TCGv hi =3D gen_dest_gpr(dc, rd); TCGv lo =3D gen_dest_gpr(dc, rd + 1); @@ -2660,16 +2642,7 @@ static void gen_ldda_asi0(DisasContext *dc, DisasASI= *da, TCGv addr, int rd) gen_store_gpr(dc, rd + 1, lo); } =20 -static void __attribute__((unused)) -gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) -{ - DisasASI da =3D get_asi(dc, insn, MO_TEUQ); - - gen_address_mask(dc, addr); - gen_ldda_asi0(dc, &da, addr, rd); -} - -static void gen_stda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int r= d) +static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) { TCGv hi =3D gen_load_gpr(dc, rd); TCGv lo =3D gen_load_gpr(dc, rd + 1); @@ -2761,15 +2734,6 @@ static void gen_stda_asi0(DisasContext *dc, DisasASI= *da, TCGv addr, int rd) } } =20 -static void __attribute__((unused)) -gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd) -{ - DisasASI da =3D get_asi(dc, insn, MO_TEUQ); - - gen_address_mask(dc, addr); - gen_stda_asi0(dc, &da, addr, rd); -} - static TCGv get_src1(DisasContext *dc, unsigned int insn) { unsigned int rs1 =3D GET_FIELD(insn, 13, 17); @@ -4580,7 +4544,7 @@ static bool do_ld_gpr(DisasContext *dc, arg_r_r_ri_as= i *a, MemOp mop) da =3D resolve_asi(dc, a->asi, mop); =20 reg =3D gen_dest_gpr(dc, a->rd); - gen_ld_asi0(dc, &da, reg, addr); + gen_ld_asi(dc, &da, reg, addr); gen_store_gpr(dc, a->rd, reg); return advance_pc(dc); } @@ -4604,7 +4568,7 @@ static bool do_st_gpr(DisasContext *dc, arg_r_r_ri_as= i *a, MemOp mop) da =3D resolve_asi(dc, a->asi, mop); =20 reg =3D gen_load_gpr(dc, a->rd); - gen_st_asi0(dc, &da, reg, addr); + gen_st_asi(dc, &da, reg, addr); return advance_pc(dc); } =20 @@ -4626,7 +4590,7 @@ static bool trans_LDD(DisasContext *dc, arg_r_r_ri_as= i *a) return false; } da =3D resolve_asi(dc, a->asi, MO_TEUQ); - gen_ldda_asi0(dc, &da, addr, a->rd); + gen_ldda_asi(dc, &da, addr, a->rd); return advance_pc(dc); } =20 @@ -4643,7 +4607,7 @@ static bool trans_STD(DisasContext *dc, arg_r_r_ri_as= i *a) return false; } da =3D resolve_asi(dc, a->asi, MO_TEUQ); - gen_stda_asi0(dc, &da, addr, a->rd); + gen_stda_asi(dc, &da, addr, a->rd); return advance_pc(dc); } =20 @@ -5475,9 +5439,17 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) case 0x3: /* ldd, load double word */ case 0x9: /* ldsb, load signed byte */ case 0xa: /* ldsh, load signed halfword */ + case 0x10: /* lda, V9 lduwa, load word alternate */ + case 0x11: /* lduba, load unsigned byte alternate */ + case 0x12: /* lduha, load unsigned halfword alternate= */ + case 0x13: /* ldda, load double word alternate */ + case 0x19: /* ldsba, load signed byte alternate */ + case 0x1a: /* ldsha, load signed halfword alternate */ g_assert_not_reached(); /* in decodetree */ case 0x08: /* V9 ldsw */ case 0x0b: /* V9 ldx */ + case 0x18: /* V9 ldswa */ + case 0x1b: /* V9 ldxa */ goto illegal_insn; /* in decodetree */ case 0xd: /* ldstub */ gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx); @@ -5489,27 +5461,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) dc->mem_idx, MO_TEUL); break; #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) - case 0x10: /* lda, V9 lduwa, load word alternate */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL); - break; - case 0x11: /* lduba, load unsigned byte alternate */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_UB); - break; - case 0x12: /* lduha, load unsigned halfword alternate= */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW); - break; - case 0x13: /* ldda, load double word alternate */ - if (rd & 1) { - goto illegal_insn; - } - gen_ldda_asi(dc, cpu_addr, insn, rd); - goto skip_move; - case 0x19: /* ldsba, load signed byte alternate */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_SB); - break; - case 0x1a: /* ldsha, load signed halfword alternate */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESW); - break; case 0x1d: /* ldstuba -- XXX: should be atomically */ gen_ldstub_asi(dc, cpu_val, cpu_addr, insn); break; @@ -5520,12 +5471,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) break; #endif #ifdef TARGET_SPARC64 - case 0x18: /* V9 ldswa */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL); - break; - case 0x1b: /* V9 ldxa */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ); - break; case 0x2d: /* V9 prefetch, no effect */ goto skip_move; case 0x30: /* V9 ldfa */ @@ -5557,7 +5502,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) goto illegal_insn; } gen_store_gpr(dc, rd, cpu_val); -#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) +#if defined(TARGET_SPARC64) skip_move: ; #endif } else if (xop >=3D 0x20 && xop < 0x24) { @@ -5610,45 +5555,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) default: goto illegal_insn; } - } else if (xop < 8 || (xop >=3D 0x14 && xop < 0x18) || - xop =3D=3D 0xe || xop =3D=3D 0x1e) { -#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) - TCGv cpu_val =3D gen_load_gpr(dc, rd); -#endif - - switch (xop) { - case 0x4: /* st, store word */ - case 0x5: /* stb, store byte */ - case 0x6: /* sth, store halfword */ - case 0x7: /* std, store double word */ - g_assert_not_reached(); /* in decodetree */ - case 0x0e: /* V9 stx */ - goto illegal_insn; /* in decodetree */ -#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) - case 0x14: /* sta, V9 stwa, store word alternate */ - gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL); - break; - case 0x15: /* stba, store byte alternate */ - gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_UB); - break; - case 0x16: /* stha, store halfword alternate */ - gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW); - break; - case 0x17: /* stda, store double word alternate */ - if (rd & 1) { - goto illegal_insn; - } - gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd); - break; -#endif -#ifdef TARGET_SPARC64 - case 0x1e: /* V9 stxa */ - gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ); - break; -#endif - default: - goto illegal_insn; - } } else if (xop > 0x23 && xop < 0x28) { if (gen_trap_ifnofpu(dc)) { goto jmp_insn; --=20 2.34.1