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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:22:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279771; x=1698884571; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=10ZlbZnfTg8LnI0vemtKsGjnuIMVwA7h5DHDNssZclo=; b=OxwTXMYl3k5hd4lHcZu8RhKI5xcXN2bT+XBgjIIVaGsqvLoaJXmFPywRJ4kciIe3fT zwgPJZpU2BdZvT+Q7bv6Xeu/gnyPCpIeN+NDUQ4QAgcFENHE0AfhGkvuhPK7tQZGfwhL Y5q26ZCFKw0XUHQ35AuFroWbbwns98Q7IXVmEviff1uZffoHLvcyKBKaDWw33yEHlVyg gT5I+icpoLMUujk3w5xP8j7yLCiMxa7rZGkoQiqzU370w05NhtIaerJzc5J4MfRwq65t jbu3pIUJezdnTgZDPZhgjsYh/uIeU1DteJjsXD6CVZzWMPsYfqiK272QzpeFjEGufSFp xMVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279771; x=1698884571; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=10ZlbZnfTg8LnI0vemtKsGjnuIMVwA7h5DHDNssZclo=; b=LSzd51usgBZYTv84I/3rlovmr03753qUJf8H4uVVTwt9gzDRyuSuEdp5lYYhIlkUGV CRFdFVXQ/Vf8mPbxueOxg7FSHAumHusq06BEb5o7eTi3YGIGKKLIZdHc9s6ReyBvoYFT hHOuQ376d5blj6BIkdqIUos9kHCrMiNm0hpIVP+I2qpleofzBXhaL5mSFHa3CsECqlUs iWuaMEoPwa7zIV9drWiGhzlg7diAOjCPl15llIRDUNZkT6a6PloGDF6r/UFZqCqws+OA SsrpBnB/pAl3eG71+StUVyqt0rHFqCvQtlpI6KVmuD2bD4QkzvNZslxRrwQcSXbaNzsk fx5Q== X-Gm-Message-State: AOJu0YzRvCNS8AnsmCcfhBiPJfwU3FKw5O57PjOvMC5eB6U7hWYUZLHz RwOrtoy3QigQpmoCOn4w39hDo4WJFMdC8vEJMcU= X-Google-Smtp-Source: AGHT+IEL6RJ1Q2eLwKS6nu5jr0UrCTy3J/LgQ0HSt3USenk7fHYEpQpPMqnnaPMUc/SexOuLxyC3PA== X-Received: by 2002:a17:90a:fa8f:b0:268:2658:3b01 with SMTP id cu15-20020a17090afa8f00b0026826583b01mr13163836pjb.39.1698279771277; Wed, 25 Oct 2023 17:22:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 52/94] target/sparc: Move simple integer load/store to decodetree Date: Wed, 25 Oct 2023 17:15:00 -0700 Message-Id: <20231026001542.1141412-82-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279884842100003 Content-Type: text/plain; charset="utf-8" Move LDUW, LDUB, LDUH, LDD, LDSW, LDSB, LDSH, LDX, STW, STB, STH, STD, STX. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 22 +++++ target/sparc/translate.c | 196 +++++++++++++++++++++++--------------- 2 files changed, 142 insertions(+), 76 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 137b7eb3c6..6197fbdb03 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -231,6 +231,28 @@ RESTORE 10 ..... 111101 ..... . ............. = @r_r_ri DONE 10 00000 111110 00000 0 0000000000000 RETRY 10 00001 111110 00000 0 0000000000000 =20 +## +## Major Opcode 11 -- load and store instructions +## + +&r_r_ri_asi rd rs1 rs2_or_imm asi imm:bool +@r_r_ri_na .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_asi asi= =3D-1 + +LDUW 11 ..... 000000 ..... . ............. @r_r_ri_na +LDUB 11 ..... 000001 ..... . ............. @r_r_ri_na +LDUH 11 ..... 000010 ..... . ............. @r_r_ri_na +LDD 11 ..... 000011 ..... . ............. @r_r_ri_na +LDSW 11 ..... 001000 ..... . ............. @r_r_ri_na +LDSB 11 ..... 001001 ..... . ............. @r_r_ri_na +LDSH 11 ..... 001010 ..... . ............. @r_r_ri_na +LDX 11 ..... 001011 ..... . ............. @r_r_ri_na + +STW 11 ..... 000100 ..... . ............. @r_r_ri_na +STB 11 ..... 000101 ..... . ............. @r_r_ri_na +STH 11 ..... 000110 ..... . ............. @r_r_ri_na +STD 11 ..... 000111 ..... . ............. @r_r_ri_na +STX 11 ..... 001110 ..... . ............. @r_r_ri_na + NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 7ce9ab66c6..db09255854 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4536,6 +4536,117 @@ static bool do_done_retry(DisasContext *dc, bool do= ne) TRANS(DONE, 64, do_done_retry, true) TRANS(RETRY, 64, do_done_retry, false) =20 +/* + * Major opcode 11 -- load and store instructions + */ + +static TCGv gen_ldst_addr(DisasContext *dc, int rs1, bool imm, int rs2_or_= imm) +{ + TCGv addr, tmp =3D NULL; + + /* For simplicity, we under-decoded the rs2 form. */ + if (!imm && rs2_or_imm & ~0x1f) { + return NULL; + } + + addr =3D gen_load_gpr(dc, rs1); + if (rs2_or_imm) { + tmp =3D tcg_temp_new(); + if (imm) { + tcg_gen_addi_tl(tmp, addr, rs2_or_imm); + } else { + tcg_gen_add_tl(tmp, addr, cpu_regs[rs2_or_imm]); + } + addr =3D tmp; + } + if (AM_CHECK(dc)) { + if (!tmp) { + tmp =3D tcg_temp_new(); + } + tcg_gen_ext32u_tl(tmp, addr); + addr =3D tmp; + } + return addr; +} + +static bool do_ld_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) +{ + TCGv reg, addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + DisasASI da; + + if (addr =3D=3D NULL) { + return false; + } + da =3D resolve_asi(dc, a->asi, mop); + + reg =3D gen_dest_gpr(dc, a->rd); + gen_ld_asi0(dc, &da, reg, addr); + gen_store_gpr(dc, a->rd, reg); + return advance_pc(dc); +} + +TRANS(LDUW, ALL, do_ld_gpr, a, MO_TEUL) +TRANS(LDUB, ALL, do_ld_gpr, a, MO_UB) +TRANS(LDUH, ALL, do_ld_gpr, a, MO_TEUW) +TRANS(LDSB, ALL, do_ld_gpr, a, MO_SB) +TRANS(LDSH, ALL, do_ld_gpr, a, MO_TESW) +TRANS(LDSW, 64, do_ld_gpr, a, MO_TESL) +TRANS(LDX, 64, do_ld_gpr, a, MO_TEUQ) + +static bool do_st_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) +{ + TCGv reg, addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + DisasASI da; + + if (addr =3D=3D NULL) { + return false; + } + da =3D resolve_asi(dc, a->asi, mop); + + reg =3D gen_load_gpr(dc, a->rd); + gen_st_asi0(dc, &da, reg, addr); + return advance_pc(dc); +} + +TRANS(STW, ALL, do_st_gpr, a, MO_TEUL) +TRANS(STB, ALL, do_st_gpr, a, MO_UB) +TRANS(STH, ALL, do_st_gpr, a, MO_TEUW) +TRANS(STX, 64, do_st_gpr, a, MO_TEUQ) + +static bool trans_LDD(DisasContext *dc, arg_r_r_ri_asi *a) +{ + TCGv addr; + DisasASI da; + + if (a->rd & 1) { + return false; + } + addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + if (addr =3D=3D NULL) { + return false; + } + da =3D resolve_asi(dc, a->asi, MO_TEUQ); + gen_ldda_asi0(dc, &da, addr, a->rd); + return advance_pc(dc); +} + +static bool trans_STD(DisasContext *dc, arg_r_r_ri_asi *a) +{ + TCGv addr; + DisasASI da; + + if (a->rd & 1) { + return false; + } + addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + if (addr =3D=3D NULL) { + return false; + } + da =3D resolve_asi(dc, a->asi, MO_TEUQ); + gen_stda_asi0(dc, &da, addr, a->rd); + return advance_pc(dc); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5359,47 +5470,15 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) =20 switch (xop) { case 0x0: /* ld, V9 lduw, load unsigned word */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUL | MO_ALIGN); - break; case 0x1: /* ldub, load unsigned byte */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_UB); - break; case 0x2: /* lduh, load unsigned halfword */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUW | MO_ALIGN); - break; case 0x3: /* ldd, load double word */ - if (rd & 1) - goto illegal_insn; - else { - TCGv_i64 t64; - - gen_address_mask(dc, cpu_addr); - t64 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t64, cpu_addr, - dc->mem_idx, MO_TEUQ | MO_ALIG= N); - tcg_gen_trunc_i64_tl(cpu_val, t64); - tcg_gen_ext32u_tl(cpu_val, cpu_val); - gen_store_gpr(dc, rd + 1, cpu_val); - tcg_gen_shri_i64(t64, t64, 32); - tcg_gen_trunc_i64_tl(cpu_val, t64); - tcg_gen_ext32u_tl(cpu_val, cpu_val); - } - break; case 0x9: /* ldsb, load signed byte */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, dc->mem_idx, MO_= SB); - break; case 0xa: /* ldsh, load signed halfword */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TESW | MO_ALIGN); - break; + g_assert_not_reached(); /* in decodetree */ + case 0x08: /* V9 ldsw */ + case 0x0b: /* V9 ldx */ + goto illegal_insn; /* in decodetree */ case 0xd: /* ldstub */ gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx); break; @@ -5441,16 +5520,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) break; #endif #ifdef TARGET_SPARC64 - case 0x08: /* V9 ldsw */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TESL | MO_ALIGN); - break; - case 0x0b: /* V9 ldx */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUQ | MO_ALIGN); - break; case 0x18: /* V9 ldswa */ gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL); break; @@ -5543,38 +5612,18 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) } } else if (xop < 8 || (xop >=3D 0x14 && xop < 0x18) || xop =3D=3D 0xe || xop =3D=3D 0x1e) { +#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) TCGv cpu_val =3D gen_load_gpr(dc, rd); +#endif =20 switch (xop) { case 0x4: /* st, store word */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_st_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUL | MO_ALIGN); - break; case 0x5: /* stb, store byte */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_st_tl(cpu_val, cpu_addr, dc->mem_idx, MO_= UB); - break; case 0x6: /* sth, store halfword */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_st_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUW | MO_ALIGN); - break; case 0x7: /* std, store double word */ - if (rd & 1) - goto illegal_insn; - else { - TCGv_i64 t64; - TCGv lo; - - gen_address_mask(dc, cpu_addr); - lo =3D gen_load_gpr(dc, rd + 1); - t64 =3D tcg_temp_new_i64(); - tcg_gen_concat_tl_i64(t64, lo, cpu_val); - tcg_gen_qemu_st_i64(t64, cpu_addr, - dc->mem_idx, MO_TEUQ | MO_ALIG= N); - } - break; + g_assert_not_reached(); /* in decodetree */ + case 0x0e: /* V9 stx */ + goto illegal_insn; /* in decodetree */ #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x14: /* sta, V9 stwa, store word alternate */ gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL); @@ -5593,11 +5642,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) break; #endif #ifdef TARGET_SPARC64 - case 0x0e: /* V9 stx */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_st_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUQ | MO_ALIGN); - break; case 0x1e: /* V9 stxa */ gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ); break; --=20 2.34.1