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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279589; x=1698884389; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FJWQTSXIVaWpvvHhP9KgF/nTwAogXnm2BnoIdB4YZKA=; b=mRrGtxEwAzlyy8tbSip8Xx/kwvpMClMXkEPMvrQGydmdu5nqBryAn2Uk7qr0zLeni3 OVTjeFMigz/odrBWLo07+FSSZc29vroXayt1BA/pXxOZb2Y/PXn86KRq03cWCIvkeHVV vl5WAiKVetnh/fx/R1O8/NpR3werMLvIqQlbK3LsDF9QCIf3IuVz9aunS3mtaydV/8mh l2kuVvC8dWRELZSUiuPmDnWheazWv/rhBBoxGLnn3P0XMdzxfS6eph14Br6Luitj2Upc VGT7MeJeO+uGQt80zK/NvOCVf9D807ORpoHdUv9GvqOraXwFkV0qWR50DTz80VHY9JWy YfSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279589; x=1698884389; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FJWQTSXIVaWpvvHhP9KgF/nTwAogXnm2BnoIdB4YZKA=; b=ulp2USFaHuTLXeRn0YKPlO3UvbCarpThsgpSzBuq9PxvGN0yVpbZ1MbCYnHbL27PCm wjLzvBFV1wJv7/83oqkI4oNbXYvyP9+qnaFpNp+AMwTdvgpHZtpfoUXrckBZTLf1RIQP bbxkYhTgxVjjM0Z13Nk4sydoKZnPfsjJHzZmZiA+00EmPlIbMgDIgKHlsJSwUluQAQ4t nte9WSLFhGtVy36tzA5Aczg2MpjwQSwyA29rU+OkfF2shPyQjLU73MM5PX2HtRiZewju 6Hv2kM9QweLsqqQqmwiCFpZAhhO1IUgG3Qru8pjWUJnTceJnfxT7uXsPKO77ZHxuFidE BBkg== X-Gm-Message-State: AOJu0Yxq4+p9MsxLEKnUEFR3eYhiCRd1uj+IgRrBz6JJdWMr96AShr0U W/QwbYDm3cr1hmk5c4aoapXMcS9gbMMJ2uXKPSE= X-Google-Smtp-Source: AGHT+IGCQbT+dqODAOLe8ctv34rQdYgKp8FqD7QcNRkzTr95gTpbHFIddBdq7hpmH55QDGgh+m6U8A== X-Received: by 2002:a17:902:ce88:b0:1ca:92a:df0 with SMTP id f8-20020a170902ce8800b001ca092a0df0mr18705046plg.59.1698279589218; Wed, 25 Oct 2023 17:19:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 50/94] target/sparc: Split out ldst functions with asi pre-computed Date: Wed, 25 Oct 2023 17:14:58 -0700 Message-Id: <20231026001542.1141412-80-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279828673100003 Content-Type: text/plain; charset="utf-8" As an intermediate step in decodetree conversion, create new functions passing in DisasASI and not insn. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 215 ++++++++++++++++++++++----------------- 1 file changed, 123 insertions(+), 92 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 09b01ccf77..e24945e50e 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2162,25 +2162,21 @@ static void gen_helper_st_asi(TCGv_env e, TCGv a, T= CGv_i64 r, } #endif =20 -static void __attribute__((unused)) -gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop) +static void gen_ld_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv add= r) { - DisasASI da =3D get_asi(dc, insn, memop); - - switch (da.type) { + switch (da->type) { case GET_ASI_EXCP: break; case GET_ASI_DTWINX: /* Reserved for ldda. */ gen_exception(dc, TT_ILL_INSN); break; case GET_ASI_DIRECT: - gen_address_mask(dc, addr); - tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop | MO_ALIGN); + tcg_gen_qemu_ld_tl(dst, addr, da->mem_idx, da->memop | MO_ALIGN); break; default: { - TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); - TCGv_i32 r_mop =3D tcg_constant_i32(memop | MO_ALIGN); + TCGv_i32 r_asi =3D tcg_constant_i32(da->asi); + TCGv_i32 r_mop =3D tcg_constant_i32(da->memop | MO_ALIGN); =20 save_state(dc); #ifdef TARGET_SPARC64 @@ -2198,33 +2194,38 @@ gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, i= nt insn, MemOp memop) } =20 static void __attribute__((unused)) -gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop) +gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop) { DisasASI da =3D get_asi(dc, insn, memop); =20 - switch (da.type) { + gen_address_mask(dc, addr); + gen_ld_asi0(dc, &da, dst, addr); +} + +static void gen_st_asi0(DisasContext *dc, DisasASI *da, TCGv src, TCGv add= r) +{ + switch (da->type) { case GET_ASI_EXCP: break; + case GET_ASI_DTWINX: /* Reserved for stda. */ -#ifndef TARGET_SPARC64 - gen_exception(dc, TT_ILL_INSN); - break; -#else - if (!(dc->def->features & CPU_FEATURE_HYPV)) { + if (TARGET_LONG_BITS =3D=3D 32) { + gen_exception(dc, TT_ILL_INSN); + break; + } else if (!(dc->def->features & CPU_FEATURE_HYPV)) { /* Pre OpenSPARC CPUs don't have these */ gen_exception(dc, TT_ILL_INSN); - return; + break; } - /* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions - * are ST_BLKINIT_ ASIs */ -#endif + /* In OpenSPARC T1+ CPUs TWINX ASIs in store are ST_BLKINIT_ ASIs = */ /* fall through */ + case GET_ASI_DIRECT: - gen_address_mask(dc, addr); - tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop | MO_ALIGN); + tcg_gen_qemu_st_tl(src, addr, da->mem_idx, da->memop | MO_ALIGN); break; -#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) + case GET_ASI_BCOPY: + assert(TARGET_LONG_BITS =3D=3D 32); /* Copy 32 bytes from the address in SRC to ADDR. */ /* ??? The original qemu code suggests 4-byte alignment, dropping the low bits, but the only place I can see this used is in the @@ -2242,18 +2243,18 @@ gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, i= nt insn, MemOp memop) for (i =3D 0; i < 32; i +=3D 4) { /* Since the loads and stores are paired, allow the copy to happen in the host endianness. */ - tcg_gen_qemu_ld_i32(tmp, saddr, da.mem_idx, MO_UL); - tcg_gen_qemu_st_i32(tmp, daddr, da.mem_idx, MO_UL); + tcg_gen_qemu_ld_i32(tmp, saddr, da->mem_idx, MO_UL); + tcg_gen_qemu_st_i32(tmp, daddr, da->mem_idx, MO_UL); tcg_gen_add_tl(saddr, saddr, four); tcg_gen_add_tl(daddr, daddr, four); } } break; -#endif + default: { - TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); - TCGv_i32 r_mop =3D tcg_constant_i32(memop | MO_ALIGN); + TCGv_i32 r_asi =3D tcg_constant_i32(da->asi); + TCGv_i32 r_mop =3D tcg_constant_i32(da->memop | MO_ALIGN); =20 save_state(dc); #ifdef TARGET_SPARC64 @@ -2273,16 +2274,49 @@ gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, i= nt insn, MemOp memop) } } =20 +static void __attribute__((unused)) +gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop) +{ + DisasASI da =3D get_asi(dc, insn, memop); + + gen_address_mask(dc, addr); + gen_st_asi0(dc, &da, src, addr); +} + +static void gen_swap_asi0(DisasContext *dc, DisasASI *da, + TCGv dst, TCGv src, TCGv addr) +{ + switch (da->type) { + case GET_ASI_EXCP: + break; + case GET_ASI_DIRECT: + gen_swap(dc, dst, src, addr, da->mem_idx, da->memop); + break; + default: + /* ??? Should be DAE_invalid_asi. */ + gen_exception(dc, TT_DATA_ACCESS); + break; + } +} + static void __attribute__((unused)) gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, TCGv addr, int insn) { DisasASI da =3D get_asi(dc, insn, MO_TEUL); =20 - switch (da.type) { + gen_address_mask(dc, addr); + gen_swap_asi0(dc, &da, dst, src, addr); +} + +static void gen_cas_asi0(DisasContext *dc, DisasASI *da, + TCGv oldv, TCGv newv, TCGv cmpv, TCGv addr) +{ + switch (da->type) { case GET_ASI_EXCP: - break; + return; case GET_ASI_DIRECT: - gen_swap(dc, dst, src, addr, da.mem_idx, da.memop); + tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, newv, + da->mem_idx, da->memop | MO_ALIGN); break; default: /* ??? Should be DAE_invalid_asi. */ @@ -2295,34 +2329,33 @@ static void __attribute__((unused)) gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) { DisasASI da =3D get_asi(dc, insn, MO_TEUL); - TCGv oldv; + TCGv oldv =3D gen_dest_gpr(dc, rd); + TCGv newv =3D gen_load_gpr(dc, rd); =20 - switch (da.type) { - case GET_ASI_EXCP: - return; - case GET_ASI_DIRECT: - oldv =3D tcg_temp_new(); - tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd), - da.mem_idx, da.memop | MO_ALIGN); - gen_store_gpr(dc, rd, oldv); - break; - default: - /* ??? Should be DAE_invalid_asi. */ - gen_exception(dc, TT_DATA_ACCESS); - break; - } + gen_address_mask(dc, addr); + gen_cas_asi0(dc, &da, oldv, newv, cmpv, addr); + gen_store_gpr(dc, rd, oldv); } =20 static void __attribute__((unused)) -gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) +gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) { - DisasASI da =3D get_asi(dc, insn, MO_UB); + DisasASI da =3D get_asi(dc, insn, MO_TEUQ); + TCGv oldv =3D gen_dest_gpr(dc, rd); + TCGv newv =3D gen_load_gpr(dc, rd); =20 - switch (da.type) { + gen_address_mask(dc, addr); + gen_cas_asi0(dc, &da, oldv, newv, cmpv, addr); + gen_store_gpr(dc, rd, oldv); +} + +static void gen_ldstub_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv= addr) +{ + switch (da->type) { case GET_ASI_EXCP: break; case GET_ASI_DIRECT: - gen_ldstub(dc, dst, addr, da.mem_idx); + gen_ldstub(dc, dst, addr, da->mem_idx); break; default: /* ??? In theory, this should be raise DAE_invalid_asi. @@ -2330,7 +2363,7 @@ gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr,= int insn) if (tb_cflags(dc->base.tb) & CF_PARALLEL) { gen_helper_exit_atomic(tcg_env); } else { - TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); + TCGv_i32 r_asi =3D tcg_constant_i32(da->asi); TCGv_i32 r_mop =3D tcg_constant_i32(MO_UB); TCGv_i64 s64, t64; =20 @@ -2350,6 +2383,15 @@ gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr= , int insn) } } =20 +static void __attribute__((unused)) +gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) +{ + DisasASI da =3D get_asi(dc, insn, MO_UB); + + gen_address_mask(dc, addr); + gen_ldstub_asi0(dc, &da, dst, addr); +} + static void __attribute__((unused)) gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) { @@ -2542,36 +2584,32 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, = int size, int rd) } } =20 -static void __attribute__((unused)) -gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) +static void gen_ldda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int r= d) { - DisasASI da =3D get_asi(dc, insn, MO_TEUQ); TCGv hi =3D gen_dest_gpr(dc, rd); TCGv lo =3D gen_dest_gpr(dc, rd + 1); =20 - switch (da.type) { + switch (da->type) { case GET_ASI_EXCP: return; =20 case GET_ASI_DTWINX: assert(TARGET_LONG_BITS =3D=3D 64); - gen_address_mask(dc, addr); - tcg_gen_qemu_ld_tl(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); + tcg_gen_qemu_ld_tl(hi, addr, da->mem_idx, da->memop | MO_ALIGN_16); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_ld_tl(lo, addr, da.mem_idx, da.memop); + tcg_gen_qemu_ld_tl(lo, addr, da->mem_idx, da->memop); break; =20 case GET_ASI_DIRECT: { TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 - gen_address_mask(dc, addr); - tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop | MO_ALIGN= ); + tcg_gen_qemu_ld_i64(tmp, addr, da->mem_idx, da->memop | MO_ALI= GN); =20 /* Note that LE ldda acts as if each 32-bit register result is byte swapped. Having just performed one 64-bit bswap, we need now to swap the writebacks. */ - if ((da.memop & MO_BSWAP) =3D=3D MO_TE) { + if ((da->memop & MO_BSWAP) =3D=3D MO_TE) { tcg_gen_extr_i64_tl(lo, hi, tmp); } else { tcg_gen_extr_i64_tl(hi, lo, tmp); @@ -2585,15 +2623,15 @@ gen_ldda_asi(DisasContext *dc, TCGv addr, int insn,= int rd) real hardware allows others. This can be seen with e.g. FreeBSD 10.3 wrt ASI_IC_TAG. */ { - TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); - TCGv_i32 r_mop =3D tcg_constant_i32(da.memop); + TCGv_i32 r_asi =3D tcg_constant_i32(da->asi); + TCGv_i32 r_mop =3D tcg_constant_i32(da->memop); TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 save_state(dc); gen_helper_ld_asi(tmp, tcg_env, addr, r_asi, r_mop); =20 /* See above. */ - if ((da.memop & MO_BSWAP) =3D=3D MO_TE) { + if ((da->memop & MO_BSWAP) =3D=3D MO_TE) { tcg_gen_extr_i64_tl(lo, hi, tmp); } else { tcg_gen_extr_i64_tl(hi, lo, tmp); @@ -2607,21 +2645,28 @@ gen_ldda_asi(DisasContext *dc, TCGv addr, int insn,= int rd) } =20 static void __attribute__((unused)) -gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd) +gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) { DisasASI da =3D get_asi(dc, insn, MO_TEUQ); + + gen_address_mask(dc, addr); + gen_ldda_asi0(dc, &da, addr, rd); +} + +static void gen_stda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int r= d) +{ + TCGv hi =3D gen_load_gpr(dc, rd); TCGv lo =3D gen_load_gpr(dc, rd + 1); =20 - switch (da.type) { + switch (da->type) { case GET_ASI_EXCP: break; =20 case GET_ASI_DTWINX: assert(TARGET_LONG_BITS =3D=3D 64); - gen_address_mask(dc, addr); - tcg_gen_qemu_st_tl(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); + tcg_gen_qemu_st_tl(hi, addr, da->mem_idx, da->memop | MO_ALIGN_16); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_st_tl(lo, addr, da.mem_idx, da.memop); + tcg_gen_qemu_st_tl(lo, addr, da->mem_idx, da->memop); break; =20 case GET_ASI_DIRECT: @@ -2631,13 +2676,12 @@ gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, = int insn, int rd) /* Note that LE stda acts as if each 32-bit register result is byte swapped. We will perform one 64-bit LE store, so now we must swap the order of the construction. */ - if ((da.memop & MO_BSWAP) =3D=3D MO_TE) { + if ((da->memop & MO_BSWAP) =3D=3D MO_TE) { tcg_gen_concat_tl_i64(t64, lo, hi); } else { tcg_gen_concat_tl_i64(t64, hi, lo); } - gen_address_mask(dc, addr); - tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN= ); + tcg_gen_qemu_st_i64(t64, addr, da->mem_idx, da->memop | MO_ALI= GN); } break; =20 @@ -2657,7 +2701,7 @@ gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, in= t insn, int rd) tcg_gen_concat_tl_i64(t64, lo, hi); tcg_gen_andi_tl(d_addr, addr, -8); for (i =3D 0; i < 32; i +=3D 8) { - tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop); + tcg_gen_qemu_st_i64(t64, d_addr, da->mem_idx, da->memop); tcg_gen_add_tl(d_addr, d_addr, eight); } } @@ -2667,12 +2711,12 @@ gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, = int insn, int rd) /* ??? In theory we've handled all of the ASIs that are valid for stda, and this should raise DAE_invalid_asi. */ { - TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); - TCGv_i32 r_mop =3D tcg_constant_i32(da.memop); + TCGv_i32 r_asi =3D tcg_constant_i32(da->asi); + TCGv_i32 r_mop =3D tcg_constant_i32(da->memop); TCGv_i64 t64 =3D tcg_temp_new_i64(); =20 /* See above. */ - if ((da.memop & MO_BSWAP) =3D=3D MO_TE) { + if ((da->memop & MO_BSWAP) =3D=3D MO_TE) { tcg_gen_concat_tl_i64(t64, lo, hi); } else { tcg_gen_concat_tl_i64(t64, hi, lo); @@ -2686,25 +2730,12 @@ gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, = int insn, int rd) } =20 static void __attribute__((unused)) -gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) +gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd) { DisasASI da =3D get_asi(dc, insn, MO_TEUQ); - TCGv oldv; =20 - switch (da.type) { - case GET_ASI_EXCP: - return; - case GET_ASI_DIRECT: - oldv =3D tcg_temp_new(); - tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd), - da.mem_idx, da.memop | MO_ALIGN); - gen_store_gpr(dc, rd, oldv); - break; - default: - /* ??? Should be DAE_invalid_asi. */ - gen_exception(dc, TT_DATA_ACCESS); - break; - } + gen_address_mask(dc, addr); + gen_stda_asi0(dc, &da, addr, rd); } =20 static TCGv get_src1(DisasContext *dc, unsigned int insn) --=20 2.34.1