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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279579; x=1698884379; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hha0FUqXQ6TXOMfH2RRgnruE6/BvIlYzO4Xx1oTtT4o=; b=KslmL5a11SbbeH1AQmNHkQOZOoOC7r8sCHrMapvNNxQ3yC3E/nauII9xz2NtY3pRxM 4vGOdIv2OT1lu/v6jbYcBzOG9tRKpwRRis7KPXo1fwFZbBmKwef9Yt8sDdaROhdyBCHG PoosUfMxyy5FPdwpXwFMe1MuVLcIZMakP51vzoHn3TIM7GLq+YEX44rDSQFzoB5luwgm NEsWjvyx9htoEMfjA1Ijy6WxTWzat/TSka6n6iY+tKkWKP48wuEp0BWdNLm1FphdcAdr MwHV6/2GDTffi8ejUXlJ5y4drdAheQ17TeXpYnvBqDor9bhJbatxyJB5/LAJcqfYY1yt 3gFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279579; x=1698884379; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hha0FUqXQ6TXOMfH2RRgnruE6/BvIlYzO4Xx1oTtT4o=; b=LSeXwRpxc9jT1yvoIBmXqwftbRceSya6mrB7y8kfCSXBm8J2dRK5kj6lunqArW+EaJ D3N3CS8P/yF+PQ7OqxlKWQk90zjIWlKkf0BKtCVolR50RI5kRN2n9/Mmb1wirsWhkA/O 7VbLa62US8NNIvPZdMXG5/P8S3fBawzTDsjXEkE9Gr1EvhHimhXwtTrflcfNLQiFKgP2 mJgl1SQlxPVHWAHAr5aeZRz333DBig8orvUAJWxMV3CWHzZqSh/t1FckrOU60DRaXS9X /45yDb7kiLQl7kNc9s2d9q5NjtBTnGNa+X07aZl82sdpPNMvYpNGeXNUqY7rhTjFMpBA PuuQ== X-Gm-Message-State: AOJu0Ywaingqvu+DOvlXO9Im5bno5tF6BrzpqAjiX1XEL8jQzHxWMoN/ XRG4GaIA2QXtsZJxhHT8u5VtJiYknGzjSQMw/UY= X-Google-Smtp-Source: AGHT+IGsaMrYcmWdQDyHlzdIAN7ywXmowIbrceEUWHZtWvnMi90nCqNzTo3bWKowMSYzYO05MjIsAw== X-Received: by 2002:a17:902:e545:b0:1c9:ddd8:9950 with SMTP id n5-20020a170902e54500b001c9ddd89950mr1584571plf.21.1698279578755; Wed, 25 Oct 2023 17:19:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 37/94] target/sparc: Move SUBC to decodetree Date: Wed, 25 Oct 2023 17:14:45 -0700 Message-Id: <20231026001542.1141412-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280399280100008 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 139 ++++++++++++++++++++++++-------------- 2 files changed, 90 insertions(+), 50 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index d6a7256e71..a188452d2e 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -165,6 +165,7 @@ ANDN 10 ..... 0.0101 ..... . ............. = @r_r_ri_cc ORN 10 ..... 0.0110 ..... . ............. @r_r_ri_cc XORN 10 ..... 0.0111 ..... . ............. @r_r_ri_cc ADDC 10 ..... 0.1000 ..... . ............. @r_r_ri_cc +SUBC 10 ..... 0.1100 ..... . ............. @r_r_ri_cc =20 MULX 10 ..... 001001 ..... . ............. @r_r_ri_cc0 UMUL 10 ..... 0.1010 ..... . ............. @r_r_ri_cc diff --git a/target/sparc/translate.c b/target/sparc/translate.c index e7c3c68402..b8fbd18a4c 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -538,51 +538,11 @@ static void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv s= rc2) tcg_gen_mov_tl(dst, cpu_cc_dst); } =20 -static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1, - TCGv src2, int update_cc) +static void gen_op_subc_int(TCGv dst, TCGv src1, TCGv src2, + TCGv_i32 carry_32, bool update_cc) { - TCGv_i32 carry_32; TCGv carry; =20 - switch (dc->cc_op) { - case CC_OP_DIV: - case CC_OP_LOGIC: - /* Carry is known to be zero. Fall back to plain SUB. */ - if (update_cc) { - gen_op_sub_cc(dst, src1, src2); - } else { - tcg_gen_sub_tl(dst, src1, src2); - } - return; - - case CC_OP_ADD: - case CC_OP_TADD: - case CC_OP_TADDTV: - carry_32 =3D gen_add32_carry32(); - break; - - case CC_OP_SUB: - case CC_OP_TSUB: - case CC_OP_TSUBTV: - if (TARGET_LONG_BITS =3D=3D 32) { - /* We can re-use the host's hardware carry generation by using - a SUB2 opcode. We discard the low part of the output. - Ideally we'd combine this operation with the add that - generated the carry in the first place. */ - carry =3D tcg_temp_new(); - tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src= 2); - goto sub_done; - } - carry_32 =3D gen_sub32_carry32(); - break; - - default: - /* We need external help to produce the carry. */ - carry_32 =3D tcg_temp_new_i32(); - gen_helper_compute_C_icc(carry_32, tcg_env); - break; - } - #if TARGET_LONG_BITS =3D=3D 64 carry =3D tcg_temp_new(); tcg_gen_extu_i32_i64(carry, carry_32); @@ -593,16 +553,75 @@ static void gen_op_subx_int(DisasContext *dc, TCGv ds= t, TCGv src1, tcg_gen_sub_tl(dst, src1, src2); tcg_gen_sub_tl(dst, dst, carry); =20 - sub_done: if (update_cc) { + tcg_debug_assert(dst =3D=3D cpu_cc_dst); tcg_gen_mov_tl(cpu_cc_src, src1); tcg_gen_mov_tl(cpu_cc_src2, src2); - tcg_gen_mov_tl(cpu_cc_dst, dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX); - dc->cc_op =3D CC_OP_SUBX; } } =20 +static void gen_op_subc_add(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_subc_int(dst, src1, src2, gen_add32_carry32(), false); +} + +static void gen_op_subccc_add(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_subc_int(dst, src1, src2, gen_add32_carry32(), true); +} + +static void gen_op_subc_int_sub(TCGv dst, TCGv src1, TCGv src2, bool updat= e_cc) +{ + TCGv discard; + + if (TARGET_LONG_BITS =3D=3D 64) { + gen_op_subc_int(dst, src1, src2, gen_sub32_carry32(), update_cc); + return; + } + + /* + * We can re-use the host's hardware carry generation by using + * a SUB2 opcode. We discard the low part of the output. + */ + discard =3D tcg_temp_new(); + tcg_gen_sub2_tl(discard, dst, cpu_cc_src, src1, cpu_cc_src2, src2); + + if (update_cc) { + tcg_debug_assert(dst =3D=3D cpu_cc_dst); + tcg_gen_mov_tl(cpu_cc_src, src1); + tcg_gen_mov_tl(cpu_cc_src2, src2); + } +} + +static void gen_op_subc_sub(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_subc_int_sub(dst, src1, src2, false); +} + +static void gen_op_subccc_sub(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_subc_int_sub(dst, src1, src2, true); +} + +static void gen_op_subc_int_generic(TCGv dst, TCGv src1, TCGv src2, + bool update_cc) +{ + TCGv_i32 carry_32 =3D tcg_temp_new_i32(); + + gen_helper_compute_C_icc(carry_32, tcg_env); + gen_op_subc_int(dst, src1, src2, carry_32, update_cc); +} + +static void gen_op_subc_generic(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_subc_int_generic(dst, src1, src2, false); +} + +static void gen_op_subccc_generic(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_subc_int_generic(dst, src1, src2, true); +} + static void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) { TCGv r_temp, zero, t0; @@ -4144,6 +4163,30 @@ static bool trans_ADDC(DisasContext *dc, arg_r_r_ri_= cc *a) } } =20 +static bool trans_SUBC(DisasContext *dc, arg_r_r_ri_cc *a) +{ + switch (dc->cc_op) { + case CC_OP_DIV: + case CC_OP_LOGIC: + /* Carry is known to be zero. Fall back to plain SUB. */ + return do_arith(dc, a, CC_OP_SUB, + tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_sub_cc); + case CC_OP_ADD: + case CC_OP_TADD: + case CC_OP_TADDTV: + return do_arith(dc, a, CC_OP_SUBX, + gen_op_subc_add, NULL, gen_op_subccc_add); + case CC_OP_SUB: + case CC_OP_TSUB: + case CC_OP_TSUBTV: + return do_arith(dc, a, CC_OP_SUBX, + gen_op_subc_sub, NULL, gen_op_subccc_sub); + default: + return do_arith(dc, a, CC_OP_SUBX, + gen_op_subc_generic, NULL, gen_op_subccc_generic); + } +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4568,10 +4611,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) cpu_src1 =3D get_src1(dc, insn); cpu_src2 =3D get_src2(dc, insn); switch (xop & ~0x10) { - case 0xc: /* subx, V9 subc */ - gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2, - (xop & 0x10)); - break; #ifdef TARGET_SPARC64 case 0xd: /* V9 udivx */ gen_helper_udivx(cpu_dst, tcg_env, cpu_src1, cpu_s= rc2); --=20 2.34.1