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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279574; x=1698884374; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=70Ansy+qoBySZPBjDOmIfy2SuZzlDjYJIwvEAx7FQ7k=; b=UxdnknKc2UdpsNtVa/eZj4gSW5imARaL6UR9CkddUZq15cpAoqwqEtnbZfTT4PKf7A kQxIJ2g88OU046/tw2M/NYH+yfatxOQpme5BuwNyJhGZegSFyDAV79aup6wRsCXNAbt/ Wq7YxvaiC4dG0TCmJB9gFW6orNS4u2s+x7h61+FzYKv/kQuieaUtaHlomx/KLENpga73 Hg7eQNgdqNHIfNkKWbK74zeNtv5BFtD5YZNpvZXuVjwoMF6cHO7XolDkQUKk9H9Lu4Du 0PKJvB9xUqZmbk6bYF5IdnR89BMYtD8sBTktVFe+KYOZNTTHWOkPPn6nscgwUOX62rMH N7Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279574; x=1698884374; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=70Ansy+qoBySZPBjDOmIfy2SuZzlDjYJIwvEAx7FQ7k=; b=R4GzoD79Jq8BwVLiGUKEijYMApDMBt+bCVZc2cEgl0jKjfB62mYElzQCdELVsRygAJ NrKjpjCRqd+vz5rxHT20IsTrPaOHNFfvbhbo6ssa/iUYtRwugdseevbpCFbuVAzkDcZu ZcMIuxoaGQd8nm3o2bpssBBjuK07a/KbX9/2tGNwaszSn2VvJNn4cGIwf4DUb/nbERQU 0yYlVEhWgKawqVbeOdAwrhbIZeUXTJEQUX1fzxsQM9LMFldDYYA9o7qVzLRN3OVQ7T1I +BlW6sUapfZ2EvqJ64E0LHtxSqMa0n+DXD0rt78Yp0Bd68E8BtZnhfX2nePqi+W39jzj rk0A== X-Gm-Message-State: AOJu0YzfvSAdTqp8HSPJp/QzWWUqcdY0c2UkiGwaYEWHiX/57QdceFtR RfB6+BttpPkzQ2W3InB65veB6B6cs1H3oTPCkYU= X-Google-Smtp-Source: AGHT+IGw/vl4AnYVG4huI6OuxKvwYpTDjAu9reWI6xUxr1PtBZkoNb5USAKXb5Q7JprHxAtAndPU9w== X-Received: by 2002:a05:6a21:4984:b0:179:fbe5:f535 with SMTP id ax4-20020a056a21498400b00179fbe5f535mr6310504pzc.58.1698279573841; Wed, 25 Oct 2023 17:19:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 31/94] target/sparc: Remove cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr Date: Wed, 25 Oct 2023 17:14:39 -0700 Message-Id: <20231026001542.1141412-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280531764100003 Content-Type: text/plain; charset="utf-8" Use direct loads and stores to env instead. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 41 ++++++++++++++-------------------------- 1 file changed, 14 insertions(+), 27 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 096cbb869f..65b71dd931 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -82,18 +82,14 @@ static TCGv cpu_cond; #ifdef TARGET_SPARC64 static TCGv_i32 cpu_xcc, cpu_fprs; static TCGv cpu_gsr; -static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr; static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver; #else # define cpu_fprs ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_gsr ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_hintp ({ qemu_build_not_reached(); (TCGv)NULL; }) -# define cpu_hstick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_htba ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_hver ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_ssr ({ qemu_build_not_reached(); (TCGv)NULL; }) -# define cpu_stick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; }) -# define cpu_tick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_ver ({ qemu_build_not_reached(); (TCGv)NULL; }) #endif /* Floating point registers */ @@ -3307,7 +3303,8 @@ TRANS(RDSOFTINT, 64, do_rd_special, supervisor(dc), a= ->rd, do_rdsoftint) =20 static TCGv do_rdtick_cmpr(DisasContext *dc, TCGv dst) { - return cpu_tick_cmpr; + tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(tick_cmpr)); + return dst; } =20 /* TODO: non-priv access only allowed when enabled. */ @@ -3331,7 +3328,8 @@ TRANS(RDSTICK, 64, do_rd_special, true, a->rd, do_rds= tick) =20 static TCGv do_rdstick_cmpr(DisasContext *dc, TCGv dst) { - return cpu_stick_cmpr; + tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(stick_cmpr)); + return dst; } =20 /* TODO: supervisor access only allowed when enabled by hypervisor. */ @@ -3406,7 +3404,8 @@ TRANS(RDHPR_hver, HYPV, do_rd_special, hypervisor(dc)= , a->rd, do_rdhver) =20 static TCGv do_rdhstick_cmpr(DisasContext *dc, TCGv dst) { - return cpu_hstick_cmpr; + tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(hstick_cmpr)); + return dst; } =20 TRANS(RDHPR_hstick_cmpr, HYPV, do_rd_special, hypervisor(dc), a->rd, @@ -3696,18 +3695,14 @@ TRANS(WRSOFTINT, 64, do_wr_special, a, supervisor(d= c), do_wrsoftint) =20 static void do_wrtick_cmpr(DisasContext *dc, TCGv src) { -#ifdef TARGET_SPARC64 TCGv_ptr r_tickptr =3D tcg_temp_new_ptr(); =20 - tcg_gen_mov_tl(cpu_tick_cmpr, src); - tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, tick)); + tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(tick_cmpr)); + tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(tick)); translator_io_start(&dc->base); - gen_helper_tick_set_limit(r_tickptr, cpu_tick_cmpr); + gen_helper_tick_set_limit(r_tickptr, src); /* End TB to handle timer interrupt */ dc->base.is_jmp =3D DISAS_EXIT; -#else - qemu_build_not_reached(); -#endif } =20 TRANS(WRTICK_CMPR, 64, do_wr_special, a, supervisor(dc), do_wrtick_cmpr) @@ -3731,18 +3726,14 @@ TRANS(WRSTICK, 64, do_wr_special, a, supervisor(dc)= , do_wrstick) =20 static void do_wrstick_cmpr(DisasContext *dc, TCGv src) { -#ifdef TARGET_SPARC64 TCGv_ptr r_tickptr =3D tcg_temp_new_ptr(); =20 - tcg_gen_mov_tl(cpu_stick_cmpr, src); - tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, stick)); + tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(stick_cmpr)); + tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(stick)); translator_io_start(&dc->base); - gen_helper_tick_set_limit(r_tickptr, cpu_stick_cmpr); + gen_helper_tick_set_limit(r_tickptr, src); /* End TB to handle timer interrupt */ dc->base.is_jmp =3D DISAS_EXIT; -#else - qemu_build_not_reached(); -#endif } =20 TRANS(WRSTICK_CMPR, 64, do_wr_special, a, supervisor(dc), do_wrstick_cmpr) @@ -3984,10 +3975,10 @@ static void do_wrhstick_cmpr(DisasContext *dc, TCGv= src) { TCGv_ptr r_tickptr =3D tcg_temp_new_ptr(); =20 - tcg_gen_mov_tl(cpu_hstick_cmpr, src); + tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(hstick_cmpr)); tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(hstick)); translator_io_start(&dc->base); - gen_helper_tick_set_limit(r_tickptr, cpu_hstick_cmpr); + gen_helper_tick_set_limit(r_tickptr, src); /* End TB to handle timer interrupt */ dc->base.is_jmp =3D DISAS_EXIT; } @@ -5951,10 +5942,6 @@ void sparc_tcg_init(void) static const struct { TCGv *ptr; int off; const char *name; } rtl[] = =3D { #ifdef TARGET_SPARC64 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" }, - { &cpu_tick_cmpr, offsetof(CPUSPARCState, tick_cmpr), "tick_cmpr" = }, - { &cpu_stick_cmpr, offsetof(CPUSPARCState, stick_cmpr), "stick_cmp= r" }, - { &cpu_hstick_cmpr, offsetof(CPUSPARCState, hstick_cmpr), - "hstick_cmpr" }, { &cpu_hintp, offsetof(CPUSPARCState, hintp), "hintp" }, { &cpu_htba, offsetof(CPUSPARCState, htba), "htba" }, { &cpu_hver, offsetof(CPUSPARCState, hver), "hver" }, --=20 2.34.1