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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279820655100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++ target/sparc/translate.c | 117 +++++++++++++++++++------------------- 2 files changed, 61 insertions(+), 60 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a5f5d2681e..15cd975f4e 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -3,4 +3,8 @@ # Sparc instruction decode definitions. # Copyright (c) 2023 Richard Henderson =20 +&bcc i a cond cc +BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc +Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=3D0 + CALL 01 i:s30 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 7ef4c6d4f7..92ea6bab6b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1367,44 +1367,6 @@ static void gen_cond_reg(TCGv r_dst, int cond, TCGv = r_src) } #endif =20 -static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int= cc) -{ - unsigned int cond =3D GET_FIELD(insn, 3, 6), a =3D (insn & (1 << 29)); - target_ulong target =3D dc->pc + offset; - - if (unlikely(AM_CHECK(dc))) { - target &=3D 0xffffffffULL; - } - if (cond =3D=3D 0x0) { - /* unconditional not taken */ - if (a) { - dc->pc =3D dc->npc + 4; - dc->npc =3D dc->pc + 4; - } else { - dc->pc =3D dc->npc; - dc->npc =3D dc->pc + 4; - } - } else if (cond =3D=3D 0x8) { - /* unconditional taken */ - if (a) { - dc->pc =3D target; - dc->npc =3D dc->pc + 4; - } else { - dc->pc =3D dc->npc; - dc->npc =3D target; - tcg_gen_mov_tl(cpu_pc, cpu_npc); - } - } else { - flush_cond(dc); - gen_cond(cpu_cond, cc, cond, dc); - if (a) { - gen_branch_a(dc, target); - } else { - gen_branch_n(dc, target); - } - } -} - static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, in= t cc) { unsigned int cond =3D GET_FIELD(insn, 3, 6), a =3D (insn & (1 << 29)); @@ -3046,6 +3008,61 @@ static bool advance_pc(DisasContext *dc) return true; } =20 +static bool advance_jump_uncond_never(DisasContext *dc, bool annul) +{ + if (annul) { + dc->pc =3D dc->npc + 4; + dc->npc =3D dc->pc + 4; + } else { + dc->pc =3D dc->npc; + dc->npc =3D dc->pc + 4; + } + return true; +} + +static bool advance_jump_uncond_always(DisasContext *dc, bool annul, + target_ulong dest) +{ + if (annul) { + dc->pc =3D dest; + dc->npc =3D dest + 4; + } else { + dc->pc =3D dc->npc; + dc->npc =3D dest; + tcg_gen_mov_tl(cpu_pc, cpu_npc); + } + return true; +} + +static bool advance_jump_cond(DisasContext *dc, bool annul, target_ulong d= est) +{ + if (annul) { + gen_branch_a(dc, dest); + } else { + gen_branch_n(dc, dest); + } + return true; +} + +static bool do_bpcc(DisasContext *dc, arg_bcc *a) +{ + target_long target =3D address_mask_i(dc, dc->pc + a->i * 4); + + switch (a->cond) { + case 0x0: + return advance_jump_uncond_never(dc, a->a); + case 0x8: + return advance_jump_uncond_always(dc, a->a, target); + default: + flush_cond(dc); + gen_cond(cpu_cond, a->cc, a->cond, dc); + return advance_jump_cond(dc, a->a, target); + } +} + +TRANS(Bicc, ALL, do_bpcc, a) +TRANS(BPcc, 64, do_bpcc, a) + static bool trans_CALL(DisasContext *dc, arg_CALL *a) { target_long target =3D address_mask_i(dc, dc->pc + a->i * 4); @@ -3083,21 +3100,7 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) switch (xop) { #ifdef TARGET_SPARC64 case 0x1: /* V9 BPcc */ - { - int cc; - - target =3D GET_FIELD_SP(insn, 0, 18); - target =3D sign_extend(target, 19); - target <<=3D 2; - cc =3D GET_FIELD_SP(insn, 20, 21); - if (cc =3D=3D 0) - do_branch(dc, target, insn, 0); - else if (cc =3D=3D 2) - do_branch(dc, target, insn, 1); - else - goto illegal_insn; - goto jmp_insn; - } + g_assert_not_reached(); /* in decodetree */ case 0x3: /* V9 BPr */ { target =3D GET_FIELD_SP(insn, 0, 13) | @@ -3127,13 +3130,7 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) } #endif case 0x2: /* BN+x */ - { - target =3D GET_FIELD(insn, 10, 31); - target =3D sign_extend(target, 22); - target <<=3D 2; - do_branch(dc, target, insn, 0); - goto jmp_insn; - } + g_assert_not_reached(); /* in decodetree */ case 0x6: /* FBN+x */ { if (gen_trap_ifnofpu(dc)) { --=20 2.34.1