From nobody Wed Nov 27 14:40:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279518; cv=none; d=zohomail.com; s=zohoarc; b=AyhsDy+TCHZ8I79n77FTXBCNiVM3dU22gjkpBNQE7SDfihXjGNqroOMSvU9ptjcQlyCp8a25uy5MuYYhACvLVGlNp17fTyvfySlkpLsUTp2t3lpppmKJt4kpvUXAEz8403rF1jVgJsuDGcOwrV384GWp0IzjV0DbrB7REPRt6RU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279518; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=imDgEUum8PsXbQ/+Z4HhrVdRHwLKWjtXZ1f2ZH8WSQs=; b=IWCHcBg7zHX5J0miv7OlstZXf2udLnhTOhTezz4lzEyOxZOMHyuDUCQzpz8SNigbBtrzia/hp+vOoi53jL60wWfyqEOZZ0zFDo69HnMPBRm4kvf5fI/6obWjw9UviJlFNs9GTWzGxZiioSPkVxyNS0o/kw0CZnoCoz8LTSM5/Kc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698279518858211.24570486464245; Wed, 25 Oct 2023 17:18:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo3B-0007QF-Qb; Wed, 25 Oct 2023 20:16:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo2w-0007HJ-BB for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:22 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo2h-0004r1-LK for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:22 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1ca3a54d2c4so2278555ad.3 for ; Wed, 25 Oct 2023 17:15:57 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.15.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:15:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279357; x=1698884157; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=imDgEUum8PsXbQ/+Z4HhrVdRHwLKWjtXZ1f2ZH8WSQs=; b=Egqdm0bh4dL6SOd/hGqa0G5CSoXKcOibxWz3AAwEsvYBop9dig3Xj7obDkrM0UezXV t57TGEOZmuvI54YJGthF6CUKB8GydZtkjVxiKEsRO8ANrMG/dy6qQy691ib9RxF+R23l 69vf+AJzYG+OzUYWqNGYBv8Py8zvNoSttyNmqfBdsEXP52VxvVdo6EhN3asi01bX2Idh MejvYiEMZOrU5xw9zbm1MSBC0rR6qjUq6IPVoM73xaLzOVNkCgDXTx/zI7u0PB0Fib5T LEmdlKPa9rN+eyNHb8xuUvi8Tyi4ox4g4z3aVTCWbSX5sOgpuB54GToa0tGjMsCAusSy ljDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279357; x=1698884157; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=imDgEUum8PsXbQ/+Z4HhrVdRHwLKWjtXZ1f2ZH8WSQs=; b=MRu+0vVacmSa4vox4oL7U1/fAXTWif0dKTxNrIv6uueVWXnG/bMP5h5th6TpwGH21s EsDFVd+6p8FCMOYJ6yoryKTmykjdlX169jkz9BMNIsSuu0z4AlYSRVev5OkIfvA7O0Oh DAdZ6G3JHXqlbHgsv/7deOCLqPvG31y3FR59xpst0cFlL1lHHmQ8vMN8bEAXC/wPDS5e kPMgLLjeRBD+JsuUbVGOrf0CCcQTAFPUM9Yaw7GNcJPMu/wpM7b2SG92+lQaYjMh1EUk CWn2YWrG1x7XtsWNNQ2VBt6D1QMeWVrIPZVipMoLSp5sWNjbR/FTlmXbElaz5kp6pAi3 HhIQ== X-Gm-Message-State: AOJu0YxgaxtbHwtA3U9wcVnIEygitlaWQgqKexVDTS1MsptbPhHFtZxM M66OW6ttMnEb6XcYxHsEIknUU/I4+ZUDXT1AQ70= X-Google-Smtp-Source: AGHT+IEJPYD1A8tHzIDEQ487Mrm1qYMnSKiiSDgt+9TEXniTeCdgKupuKdYrO133CNTR6lgyV8Q+LQ== X-Received: by 2002:a17:902:ea0e:b0:1c3:6d97:e89e with SMTP id s14-20020a170902ea0e00b001c36d97e89emr17428302plg.58.1698279356782; Wed, 25 Oct 2023 17:15:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 08/94] target/sparc: Remove sparcv7 cpu features Date: Wed, 25 Oct 2023 17:13:54 -0700 Message-Id: <20231026001542.1141412-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279519648100005 Content-Type: text/plain; charset="utf-8" The oldest supported cpu is the microsparc 1; all other cpus use CPU_DEFAULT_FEATURES. Remove the features that must always be present for sparcv7: FLOAT, SWAP, FLUSH, FSQRT, FMUL. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- linux-user/sparc/target_syscall.h | 6 +----- target/sparc/cpu.h | 21 +++++++-------------- target/sparc/cpu-feature.h.inc | 5 ----- target/sparc/cpu.c | 24 +++--------------------- target/sparc/translate.c | 12 ------------ 5 files changed, 11 insertions(+), 57 deletions(-) diff --git a/linux-user/sparc/target_syscall.h b/linux-user/sparc/target_sy= scall.h index be77e44eb8..e421165357 100644 --- a/linux-user/sparc/target_syscall.h +++ b/linux-user/sparc/target_syscall.h @@ -50,11 +50,7 @@ static inline abi_ulong target_shmlba(CPUSPARCState *env) #ifdef TARGET_SPARC64 return MAX(TARGET_PAGE_SIZE, 16 * 1024); #else - if (!(env->def.features & CPU_FEATURE_FLUSH)) { - return 64 * 1024; - } else { - return 256 * 1024; - } + return 256 * 1024; #endif } =20 diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index aaecbf0876..758a4e8aaa 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -306,17 +306,12 @@ enum { #undef FEATURE =20 #ifndef TARGET_SPARC64 -#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ - CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ - CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ - CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD) +#define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ + CPU_FEATURE_FSMULD) #else -#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ - CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ - CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ - CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \ - CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \ - CPU_FEATURE_CASA) +#define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ + CPU_FEATURE_FSMULD | CPU_FEATURE_CASA | \ + CPU_FEATURE_VIS1 | CPU_FEATURE_VIS2) enum { mmu_us_12, // Ultrasparc < III (64 entry TLB) mmu_us_3, // Ultrasparc III (512 entry TLB) @@ -799,14 +794,12 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState= *env, vaddr *pc, if (env->pstate & PS_AM) { flags |=3D TB_FLAG_AM_ENABLED; } - if ((env->def.features & CPU_FEATURE_FLOAT) - && (env->pstate & PS_PEF) - && (env->fprs & FPRS_FEF)) { + if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { flags |=3D TB_FLAG_FPU_ENABLED; } flags |=3D env->asi << TB_FLAG_ASI_SHIFT; #else - if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) { + if (env->psref) { flags |=3D TB_FLAG_FPU_ENABLED; } #endif diff --git a/target/sparc/cpu-feature.h.inc b/target/sparc/cpu-feature.h.inc index d35fe90c92..d800f18c4e 100644 --- a/target/sparc/cpu-feature.h.inc +++ b/target/sparc/cpu-feature.h.inc @@ -1,11 +1,6 @@ -FEATURE(FLOAT) FEATURE(FLOAT128) -FEATURE(SWAP) FEATURE(MUL) FEATURE(DIV) -FEATURE(FLUSH) -FEATURE(FSQRT) -FEATURE(FMUL) FEATURE(VIS1) FEATURE(VIS2) FEATURE(FSMULD) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 330b7bead3..f527244aa4 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -403,9 +403,7 @@ static const sparc_def_t sparc_defs[] =3D { .mmu_sfsr_mask =3D 0x00016fff, .mmu_trcr_mask =3D 0x0000003f, .nwindows =3D 7, - .features =3D CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_M= UL | - CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | - CPU_FEATURE_FMUL, + .features =3D CPU_FEATURE_MUL | CPU_FEATURE_DIV, }, { .name =3D "TI MicroSparc II", @@ -547,14 +545,9 @@ static const sparc_def_t sparc_defs[] =3D { =20 /* This must match sparc_cpu_properties[]. */ static const char * const feature_name[] =3D { - [CPU_FEATURE_BIT_FLOAT] =3D "float", [CPU_FEATURE_BIT_FLOAT128] =3D "float128", - [CPU_FEATURE_BIT_SWAP] =3D "swap", [CPU_FEATURE_BIT_MUL] =3D "mul", [CPU_FEATURE_BIT_DIV] =3D "div", - [CPU_FEATURE_BIT_FLUSH] =3D "flush", - [CPU_FEATURE_BIT_FSQRT] =3D "fsqrt", - [CPU_FEATURE_BIT_FMUL] =3D "fmul", [CPU_FEATURE_BIT_VIS1] =3D "vis1", [CPU_FEATURE_BIT_VIS2] =3D "vis2", [CPU_FEATURE_BIT_FSMULD] =3D "fsmuld", @@ -758,9 +751,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error= **errp) CPUSPARCState *env =3D &cpu->env; =20 #if defined(CONFIG_USER_ONLY) - if ((env->def.features & CPU_FEATURE_FLOAT)) { - env->def.features |=3D CPU_FEATURE_FLOAT128; - } + /* We are emulating the kernel, which will trap and emulate float128. = */ + env->def.features |=3D CPU_FEATURE_FLOAT128; #endif =20 env->version =3D env->def.iu_version; @@ -838,22 +830,12 @@ static PropertyInfo qdev_prop_nwindows =3D { =20 /* This must match feature_name[]. */ static Property sparc_cpu_properties[] =3D { - DEFINE_PROP_BIT("float", SPARCCPU, env.def.features, - CPU_FEATURE_BIT_FLOAT, false), DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features, CPU_FEATURE_BIT_FLOAT128, false), - DEFINE_PROP_BIT("swap", SPARCCPU, env.def.features, - CPU_FEATURE_BIT_SWAP, false), DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, CPU_FEATURE_BIT_MUL, false), DEFINE_PROP_BIT("div", SPARCCPU, env.def.features, CPU_FEATURE_BIT_DIV, false), - DEFINE_PROP_BIT("flush", SPARCCPU, env.def.features, - CPU_FEATURE_BIT_FLUSH, false), - DEFINE_PROP_BIT("fsqrt", SPARCCPU, env.def.features, - CPU_FEATURE_BIT_FSQRT, false), - DEFINE_PROP_BIT("fmul", SPARCCPU, env.def.features, - CPU_FEATURE_BIT_FMUL, false), DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features, CPU_FEATURE_BIT_VIS1, false), DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features, diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 8f6fd453e7..cab9f13421 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -3527,11 +3527,9 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss); break; case 0x29: /* fsqrts */ - CHECK_FPU_FEATURE(dc, FSQRT); gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts); break; case 0x2a: /* fsqrtd */ - CHECK_FPU_FEATURE(dc, FSQRT); gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd); break; case 0x2b: /* fsqrtq */ @@ -3559,16 +3557,13 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq); break; case 0x49: /* fmuls */ - CHECK_FPU_FEATURE(dc, FMUL); gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls); break; case 0x4a: /* fmuld */ - CHECK_FPU_FEATURE(dc, FMUL); gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld); break; case 0x4b: /* fmulq */ CHECK_FPU_FEATURE(dc, FLOAT128); - CHECK_FPU_FEATURE(dc, FMUL); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq); break; case 0x4d: /* fdivs */ @@ -5105,8 +5100,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) goto jmp_insn; #endif case 0x3b: /* flush */ - if (!((dc)->def->features & CPU_FEATURE_FLUSH)) - goto unimp_flush; /* nop */ break; case 0x3c: /* save */ @@ -5224,7 +5217,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) break; case 0x0f: /* swap, swap register with memory. Also atomically */ - CHECK_IU_FEATURE(dc, SWAP); cpu_src1 =3D gen_load_gpr(dc, rd); gen_swap(dc, cpu_val, cpu_src1, cpu_addr, dc->mem_idx, MO_TEUL); @@ -5256,7 +5248,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) break; case 0x1f: /* swapa, swap reg with alt. memory. Also atomically */ - CHECK_IU_FEATURE(dc, SWAP); cpu_src1 =3D gen_load_gpr(dc, rd); gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn); break; @@ -5578,9 +5569,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) illegal_insn: gen_exception(dc, TT_ILL_INSN); return; - unimp_flush: - gen_exception(dc, TT_UNIMP_FLUSH); - return; #if !defined(CONFIG_USER_ONLY) priv_insn: gen_exception(dc, TT_PRIV_INSN); --=20 2.34.1