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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.23.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:23:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279792; x=1698884592; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mjRWjnlqByQklHOKc+9sawwOVbp/u1JMPPydsIJPquk=; b=nGusn1v0FsFwyC6/xWst6bTMtxRZG3RcP7DKHxeMHCR5yevQihbdm199YRAZHsYzNU Cm2UPyj/819TIs/ls0RBVg+XjgWSTbXQxKuexzkOZJPTR2Lsjsns4tQv6ii0U6uZw4Tv OIeEKVfKl4p24S/enzbju9AMsD7Kl82ozQbYBnDDqzaFexyyZECJdarwevyKFMfWVdwa 66xuZjsaWPJHpJvo3yl05EnfryjIhTlaAscaXpJUdq+eGOtP0XSXQznh1gm2dFHoKc5+ UiSzsUs8dHVig2TnWgz2bAs8wlx7eGmn0oyto2Z6WLn62GqZNLkuvSNKQC7aN0YiMbVq MjNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279792; x=1698884592; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mjRWjnlqByQklHOKc+9sawwOVbp/u1JMPPydsIJPquk=; b=ppovui9uEf554G/ZJrV6FbW7naBpNOYKB75tnwHDe7BSFCRtv5ueGNJsU+tdENwMA5 56TKJoIHD1jYL7riP1a0IrMqIqf4imqV/Et67juh3y5BT13Q/G0A+Wynxt8yfGfPUjPC 4n2AaQe5e33YGKmSYWKSq/QK9Ph31YhqsOcFDeFaGaWpT6RsqnsIn05NVa/S4b/fdXSw sqwvURPGDmylNOsptZzeSDhUfpaSFh4sH2LS48SysyuoNtzxSzg+DRko6z37RLszhu0K rPo0PEBrPBNwWdI9TGWR+aey71BBge5/13vNJkLiRyDH6fWiwuQbloNwxb6DAs6KDNqF PpvQ== X-Gm-Message-State: AOJu0Yw0A9VMBEllrQkVhSpqU67zhfvUhyfzFKeSKPDzTLlzHwSIckK7 OUzzlA2MuiOcYQghZuNKWDGoMX+3K9O2tq5ZriE= X-Google-Smtp-Source: AGHT+IF+5XFwOwTYY0TSIOGFjXwY0Vbm9iGV2AwPH8Dis5Vq5+1lE5n3ZiFsUcIFMgmNF5baQicRwg== X-Received: by 2002:a17:90b:3c0d:b0:27d:29f6:79e0 with SMTP id pb13-20020a17090b3c0d00b0027d29f679e0mr17840829pjb.17.1698279792039; Wed, 25 Oct 2023 17:23:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 79/94] target/sparc: Move gen_fop_QQQ insns to decodetree Date: Wed, 25 Oct 2023 17:15:27 -0700 Message-Id: <20231026001542.1141412-109-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280963100100001 Content-Type: text/plain; charset="utf-8" Move FADDq, FSUBq, FMULq, FDIVq. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 52 +++++++++++++++++++-------------------- 2 files changed, 30 insertions(+), 26 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a429c04980..f18fd99476 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -250,12 +250,16 @@ FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... = @r_r2 FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2 FADDs 10 ..... 110100 ..... 0 0100 0001 ..... @r_r_r FADDd 10 ..... 110100 ..... 0 0100 0010 ..... @r_r_r +FADDq 10 ..... 110100 ..... 0 0100 0011 ..... @r_r_r FSUBs 10 ..... 110100 ..... 0 0100 0101 ..... @r_r_r FSUBd 10 ..... 110100 ..... 0 0100 0110 ..... @r_r_r +FSUBq 10 ..... 110100 ..... 0 0100 0111 ..... @r_r_r FMULs 10 ..... 110100 ..... 0 0100 1001 ..... @r_r_r FMULd 10 ..... 110100 ..... 0 0100 1010 ..... @r_r_r +FMULq 10 ..... 110100 ..... 0 0100 1011 ..... @r_r_r FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @r_r_r +FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @r_r_r FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index e2bcb3c7b1..94ad75b897 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1669,19 +1669,6 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, = int rs, } #endif =20 -static void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_ptr)) -{ - gen_op_load_fpr_QT0(QFPREG(rs1)); - gen_op_load_fpr_QT1(QFPREG(rs2)); - - gen(tcg_env); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(dc, QFPREG(rd)); -} - static void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32= )) { @@ -4964,6 +4951,31 @@ static bool do_dddd(DisasContext *dc, arg_r_r_r *a, =20 TRANS(PDIST, VIS1, do_dddd, a, gen_helper_pdist) =20 +static bool do_env_qqq(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_env)) +{ + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + gen_op_load_fpr_QT0(QFPREG(a->rs1)); + gen_op_load_fpr_QT1(QFPREG(a->rs2)); + func(tcg_env); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_op_store_QT0_fpr(QFPREG(a->rd)); + gen_update_fprs_dirty(dc, QFPREG(a->rd)); + return advance_pc(dc); +} + +TRANS(FADDq, ALL, do_env_qqq, a, gen_helper_faddq) +TRANS(FSUBq, ALL, do_env_qqq, a, gen_helper_fsubq) +TRANS(FMULq, ALL, do_env_qqq, a, gen_helper_fmulq) +TRANS(FDIVq, ALL, do_env_qqq, a, gen_helper_fdivq) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5025,23 +5037,11 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 0x46: /* fsubd */ case 0x4a: /* fmuld */ case 0x4e: /* fdivd */ - g_assert_not_reached(); /* in decodetree */ case 0x43: /* faddq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq); - break; case 0x47: /* fsubq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq); - break; case 0x4b: /* fmulq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq); - break; case 0x4f: /* fdivq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq); - break; + g_assert_not_reached(); /* in decodetree */ case 0x69: /* fsmuld */ CHECK_FPU_FEATURE(dc, FSMULD); gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld); --=20 2.34.1