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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.23.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:23:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279790; x=1698884590; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2Vu8uE4u91cXAtlNEMc67KwdFgVsES8vkFmIj+yngHw=; b=iFbAkQmYiTlvqNfnQCGrSTy8wkXUqpb/oPDad81H8CTUs/2mbT1vAnkuoCNfjZwzdZ 4ZTFFJVJ8gU6hPoj5IfyZ3hq1DjHw7nRUMR/hnMwfNmpYEwXMVm+dre/fpovFqta0jCi 5FcN4wd8dSpchBNXYVyQ55jyPQJ4HDfpHQHg5Ugxg+x0PdbOXUJ0JUwI2O10nbVoefrO yX1lm3k7ntWo8OmvSEK647tFuoJV6kOuKIT+LYHRSdSN2vAYgzzLHg2LdJuYocdocWo/ 2fiME/CSn5l6MeC6kcqKHLC/iJlZl03qjuLFEl6jPayziJe0R4yMPAsKGsF7ONZqaOnC +SXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279790; x=1698884590; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2Vu8uE4u91cXAtlNEMc67KwdFgVsES8vkFmIj+yngHw=; b=o2xzNJrflODygXigyY85Qe0D5mZ+CSHqyBgr+XcgjKq6Yb5JiIUp5wfegSgAN3DLJa HKUbHKH2cauqz+VzVLwq7pOG8FMxVnwPPWSPJ9kmNlsDs9di51NPiQWQEaCds0nXgvST dY44KpKZin9gjSQXitFaVZlF6slANqlqw/R98VA3ZLdfQbez+kbvjByYEJf4JiN9HBjO 9zz2Tx6tJpl3bDU4Ebolo24YN8USvDWUoqxes8sTTorn7z2IxFdtoRCVdnxtIuHOL2ds Cvll/U/SS7qbYqDgNEplBIYbJPJBa0IuMNgLWWlxIo92usle3vGXKg+pwU9xmWF5D0rY ZHkg== X-Gm-Message-State: AOJu0YwRIIUbRe2zNWLFmeUg8O+FO2eVT1lXOPMnjJi2LKtVHD6B6qUP JzpYlVlwvD5JzgcrzF4fuJfLUlMhB5+BynWDOr0= X-Google-Smtp-Source: AGHT+IFDiz/Z8fv3mNGqD7hqziXcayVBA6p1CAu4AYVSky66jsv5ICbBl+OjhA6IMqTqKHrE24nJKQ== X-Received: by 2002:a17:90a:194b:b0:27d:1ea0:bc84 with SMTP id 11-20020a17090a194b00b0027d1ea0bc84mr13636473pjh.34.1698279790409; Wed, 25 Oct 2023 17:23:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 77/94] target/sparc: Move gen_fop_FFF insns to decodetree Date: Wed, 25 Oct 2023 17:15:25 -0700 Message-Id: <20231026001542.1141412-107-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280724346100005 Content-Type: text/plain; charset="utf-8" Move FADDs, FSUBs, FMULs, FDIVs. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 54 +++++++++++++++++++-------------------- 2 files changed, 31 insertions(+), 27 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 4cb250265d..09444e313f 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -248,6 +248,10 @@ FABSd 10 ..... 110100 00000 0 0000 1010 ..... = @r_r2 FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2 FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2 FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2 +FADDs 10 ..... 110100 ..... 0 0100 0001 ..... @r_r_r +FSUBs 10 ..... 110100 ..... 0 0100 0101 ..... @r_r_r +FMULs 10 ..... 110100 ..... 0 0100 1001 ..... @r_r_r +FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 93efdf3383..d2205f7e7d 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1656,21 +1656,6 @@ static int gen_trap_ifnofpu(DisasContext *dc) return 0; } =20 -static void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32= )) -{ - TCGv_i32 dst, src1, src2; - - src1 =3D gen_load_fpr_F(dc, rs1); - src2 =3D gen_load_fpr_F(dc, rs2); - dst =3D gen_dest_fpr_F(dc); - - gen(dst, tcg_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_F(dc, rd, dst); -} - static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64= )) { @@ -4883,6 +4868,29 @@ TRANS(FXNORs, VIS1, do_fff, a, tcg_gen_eqv_i32) TRANS(FORNOTs, VIS1, do_fff, a, tcg_gen_orc_i32) TRANS(FORs, VIS1, do_fff, a, tcg_gen_or_i32) =20 +static bool do_env_fff(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32= )) +{ + TCGv_i32 src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + src1 =3D gen_load_fpr_F(dc, a->rs1); + src2 =3D gen_load_fpr_F(dc, a->rs2); + func(src1, tcg_env, src1, src2); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_F(dc, a->rd, src1); + return advance_pc(dc); +} + +TRANS(FADDs, ALL, do_env_fff, a, gen_helper_fadds) +TRANS(FSUBs, ALL, do_env_fff, a, gen_helper_fsubs) +TRANS(FMULs, ALL, do_env_fff, a, gen_helper_fmuls) +TRANS(FDIVs, ALL, do_env_fff, a, gen_helper_fdivs) + static bool do_ddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i64, TCGv_i64)) { @@ -5000,10 +5008,11 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 0x82: /* V9 fdtox */ case 0x88: /* V9 fxtod */ case 0x2b: /* fsqrtq */ - g_assert_not_reached(); /* in decodetree */ case 0x41: /* fadds */ - gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds); - break; + case 0x45: /* fsubs */ + case 0x49: /* fmuls */ + case 0x4d: /* fdivs */ + g_assert_not_reached(); /* in decodetree */ case 0x42: /* faddd */ gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd); break; @@ -5011,9 +5020,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq); break; - case 0x45: /* fsubs */ - gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs); - break; case 0x46: /* fsubd */ gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd); break; @@ -5021,9 +5027,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq); break; - case 0x49: /* fmuls */ - gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls); - break; case 0x4a: /* fmuld */ gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld); break; @@ -5031,9 +5034,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq); break; - case 0x4d: /* fdivs */ - gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs); - break; case 0x4e: /* fdivd */ gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd); break; --=20 2.34.1