From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279921; cv=none; d=zohomail.com; s=zohoarc; b=HEu785xjTQ+htem/Qs0E6hB1epGwkZO1IU8COJxhO40A67Q5/g3u/woAaAGZqjDCluG/IqkxzWxS51oxrL0Ba2XXOnHbWpWSZd16kM2+ZZEfp3bOe3+50/REgPWMaAOWemSRvL5dSRZy0ONQ1cLEOfk4jLzDwi1fHF1YkUaKO+g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279921; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Dcov+EvgUKOcstVsIicTu1476ZKJilrV5KBfm5f0U0k=; b=TGSRbo8gDn/+KLktrGqNaNSjxDl3PiRIL47f6XAZ9mc0rpda2Nc1CoilHZ7/oUIiMduWHERHKMNVIycNi+N43Q88wqSecT1U5RDOOORiZ7cGgyzCsTnsCbh+tXdmUO5Z2ElfqxvEYk75lTj9UdkgNMuDi8fqwGHSIXMxRfKSrww= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698279921591866.685429368685; Wed, 25 Oct 2023 17:25:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo2n-000723-6H; Wed, 25 Oct 2023 20:16:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo2S-0006y2-As for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:06 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo2N-0004pH-J2 for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:15:49 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1ca215cc713so2016735ad.3 for ; Wed, 25 Oct 2023 17:15:46 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.15.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:15:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279345; x=1698884145; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Dcov+EvgUKOcstVsIicTu1476ZKJilrV5KBfm5f0U0k=; b=WPKowjfQJWVwFKPYucglTywmHO+jpyGzh+BvfOrShZZ93jzZ2D03wfNOMs83uMlfir GwZxnM5Vku2giu1Dzck/qpsMFT6UJcopOfFmE7huTIExzwwNHy+nVOePc5ZfAtx30/V8 ljCrQkQsq0W2iMjnkfjkpfvU5Zoh+Lf1EIb68GLg8biOyzYCv630vsMdpusjfr2rtwwV JBII6O3WPS/i2s1pUTqlB3IR+0zHQCRuIY2C1kfp1OPyQdaHwSpEjrHSkDVFj7Q2+Wb5 SuzAS9/lYQia4euvT/ixeeMsNJL02+QUtP0Z/feQR4uTnligjrFlzW99TvQtSlduuqHV DuQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279345; x=1698884145; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Dcov+EvgUKOcstVsIicTu1476ZKJilrV5KBfm5f0U0k=; b=Ot+AbY4+S5Xsn/3r+H/RXok+WD752UDLzHZAp2NE4WXLuNLSgmydK5M9jYK8l7fHS+ aqgGFFt/ev6cbq1HFZcjrALCfBUIeGmbvI2EEA5iwoqNy4o5kkMM8KII0yzQbFbYaQ3u YFZ20co5eaZ0SPbQB0yMmmDj9murqxqQlLoK7tXIezC++CuzcTvI5ROrmfl+mbyL0ktC 3mOAgloiFGjoxpuNYnJLDbaA55XxQy+FmShuUPmFg5K5Rz/dFXnmL08Dm6V3GmSTe9dp JxNxWEEHe4bEHxEuE3Q8nE7UtgVQLaQyHinQlfK6qABS0By0pxzoz4se5h0c0ufrrKNh C1wQ== X-Gm-Message-State: AOJu0YzNzAARkrceEY51C6Q+/+BzyVlbhGCwdhRK43XGVHYLLvMz/jln Sw6HWSZDPG4fmzlirhUVPuW3AMPKBlxaRKH7f6I= X-Google-Smtp-Source: AGHT+IH6eA5Blzb8w9nLZvQNNdBr488p2pnsdRzjIk3TXJiLVNNFsk9v/mBwWaGTu5VfX4pWKHkeXg== X-Received: by 2002:a17:903:2450:b0:1ca:2ec4:7f3f with SMTP id l16-20020a170903245000b001ca2ec47f3fmr16268257pls.45.1698279345552; Wed, 25 Oct 2023 17:15:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 01/29] tcg: Introduce TCG_COND_TST{EQ,NE} Date: Wed, 25 Oct 2023 17:13:41 -0700 Message-Id: <20231026001542.1141412-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279922960100003 Content-Type: text/plain; charset="utf-8" Add the enumerators, adjust the helpers to match, and dump. Not supported anywhere else just yet. Signed-off-by: Richard Henderson --- include/tcg/tcg-cond.h | 49 ++++++++++++++++++++++++++++++++---------- tcg/tcg.c | 4 +++- docs/devel/tcg-ops.rst | 2 ++ 3 files changed, 43 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg-cond.h b/include/tcg/tcg-cond.h index 2a38a386d4..bf3fcf5968 100644 --- a/include/tcg/tcg-cond.h +++ b/include/tcg/tcg-cond.h @@ -49,6 +49,9 @@ typedef enum { TCG_COND_GEU =3D 0 | 4 | 0 | 1, TCG_COND_LEU =3D 8 | 4 | 0 | 0, TCG_COND_GTU =3D 8 | 4 | 0 | 1, + /* "test" i.e. and then compare vs 0 */ + TCG_COND_TSTEQ =3D 8 | 4 | 2 | 0, + TCG_COND_TSTNE =3D 8 | 4 | 2 | 1, } TCGCond; =20 /* Invert the sense of the comparison. */ @@ -60,25 +63,49 @@ static inline TCGCond tcg_invert_cond(TCGCond c) /* Swap the operands in a comparison. */ static inline TCGCond tcg_swap_cond(TCGCond c) { - return c & 6 ? (TCGCond)(c ^ 9) : c; + return (c + 2) & 4 ? (TCGCond)(c ^ 9) : c; } =20 -/* Create an "unsigned" version of a "signed" comparison. */ -static inline TCGCond tcg_unsigned_cond(TCGCond c) +/* Must a comparison be considered signed? */ +static inline bool is_signed_cond(TCGCond c) { - return c & 2 ? (TCGCond)(c ^ 6) : c; -} - -/* Create a "signed" version of an "unsigned" comparison. */ -static inline TCGCond tcg_signed_cond(TCGCond c) -{ - return c & 4 ? (TCGCond)(c ^ 6) : c; + return (c & 6) =3D=3D 2; } =20 /* Must a comparison be considered unsigned? */ static inline bool is_unsigned_cond(TCGCond c) { - return (c & 4) !=3D 0; + return (c & 6) =3D=3D 4; +} + +/* Must a comparison be considered a test? */ +static inline bool is_tst_cond(TCGCond c) +{ + return (c | 1) =3D=3D 0xf; +} + +/* Create an "unsigned" version of a "signed" comparison. */ +static inline TCGCond tcg_unsigned_cond(TCGCond c) +{ + return is_signed_cond(c) ? (TCGCond)(c ^ 6) : c; +} + +/* Create a "signed" version of an "unsigned" comparison. */ +static inline TCGCond tcg_signed_cond(TCGCond c) +{ + return is_unsigned_cond(c) ? (TCGCond)(c ^ 6) : c; +} + +/* Create the eq/ne version of a tsteq/tstne comparison. */ +static inline TCGCond tcg_tst_eqne_cond(TCGCond c) +{ + return is_tst_cond(c) ? (TCGCond)(c ^ 6) : c; +} + +/* Create the lt/ge version of a tstne/tsteq comparison of the sign. */ +static inline TCGCond tcg_tst_ltge_cond(TCGCond c) +{ + return is_tst_cond(c) ? (TCGCond)(c ^ (8 | 4 | 1)) : c; } =20 /* diff --git a/tcg/tcg.c b/tcg/tcg.c index 35158a0846..57d0583fe7 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2378,7 +2378,9 @@ static const char * const cond_name[] =3D [TCG_COND_LTU] =3D "ltu", [TCG_COND_GEU] =3D "geu", [TCG_COND_LEU] =3D "leu", - [TCG_COND_GTU] =3D "gtu" + [TCG_COND_GTU] =3D "gtu", + [TCG_COND_TSTEQ] =3D "tsteq", + [TCG_COND_TSTNE] =3D "tstne", }; =20 static const char * const ldst_name[(MO_BSWAP | MO_SSIZE) + 1] =3D diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst index 8ae59ea02b..d46b625e0e 100644 --- a/docs/devel/tcg-ops.rst +++ b/docs/devel/tcg-ops.rst @@ -253,6 +253,8 @@ Jumps/Labels | ``TCG_COND_GEU /* unsigned */`` | ``TCG_COND_LEU /* unsigned */`` | ``TCG_COND_GTU /* unsigned */`` + | ``TCG_COND_TSTEQ /* t1 & t2 =3D=3D 0 */`` + | ``TCG_COND_TSTNE /* t1 & t2 !=3D 0 */`` =20 Arithmetic ---------- --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279485; cv=none; d=zohomail.com; s=zohoarc; b=ia6H0kDuSHaEQrBOAzFQ7B55QNoCmqDP58oMmewWA/VDY9Sr3jptvfAkdqa4tnApOvbbr6ADR+wGdSP0jbB0T5C1yAwneOaIYtVTQTIb8VLK83GhKtMfrX50BvnpYz0XiZEHXx8i+RoU/o21SVKX/WOUtfdUNha9xWOXZcYpOdg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279485; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=XJ6RCYZtqS9hM9/RkJUGxHsAy/nMvqiERtpBq5MiRjQ=; b=CNPerO+cVLWI2XqQuq3x+UEQAJB+KG30WIje1XaEsJyBgpCr0dWn2lZQu4DeHrBFOpU1jqCMhwYYO9V1apuGVqZqi+eoUuQbBQ1ENERvDweONnzUbDqG3RUc9FAtKUqpPOQAxp5Dwf7LfQQTGtRPAytOdM9QfFewZiffBNunO8I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698279485279969.9037478067676; Wed, 25 Oct 2023 17:18:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo2i-00070L-QQ; Wed, 25 Oct 2023 20:16:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo2Q-0006wt-7T for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:15:50 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo2M-0004pB-Ag for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:15:48 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1caa7597af9so2153385ad.1 for ; Wed, 25 Oct 2023 17:15:45 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.15.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:15:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279345; x=1698884145; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XJ6RCYZtqS9hM9/RkJUGxHsAy/nMvqiERtpBq5MiRjQ=; b=PWvk4i4bdEw3gTHNM5sVe4vj2PzzZiQZLACV0iiAzSLAWZ9/NHzmQ3AgWl6c+Qy8vU bZ/jL0a5jKeq/Mslm+Yym3RDpfCzoA35QNItEYSfcyabFewdNX/71SiVXVZdg7UROads rA+9tRQpJcHRPUyQSKrNb9vmdTttej+HX95oIQuQ5EHKuQ34h5sqGOjlDVs54pQ6pFx0 m51wLhHCoG+PwlCgqRPT28T4MWOPlgUgc+lIvZcKeWzj708EDFwcle5irLQLxfdemb2c SPd57f75DSgVkYZJyDfjYTP0gVByaRoKnE0ngPz5J8sj3u9OnLCRI1Pf3upT9S8Ed75z Bw6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279345; x=1698884145; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XJ6RCYZtqS9hM9/RkJUGxHsAy/nMvqiERtpBq5MiRjQ=; b=CczMlr7usE6IA/4KDDnfzuMTJtGuePbzz2sMOzRhLXoZbxXJjYBJzscARIP3wur2cu N/nn7mfSPVnG9dj3R9MEZeuE6VDAZOyDJ4JKeVvn+ofDpvrGuyeSudLejlxv+nubOkQV Jdw/C8R47Yh4O/G969o7IOOQjgnrMTNAEAkpN6N0RealHAz+JHX0j9Hv1tFdLqWczXXN XE0phicZoId7469QXf8MeI/Kp6IoZ/V/5N8O+EftFEez2oQqchxuRmITyi9IYbfbTyD/ uN6rLBMXewmZbKYNhHzixB3QmpCmbypihK+jXwVVZLCOI2C4FYkHKLGu9Op9iQw/76kr cdJA== X-Gm-Message-State: AOJu0YybhAqaffHrtEN5AE00Gpi9EW42ox7wukZXikBMe9EPx77WtxJ9 ugtnE5hNqDp2rT0jjFhO4517zBVY5vkuHOstNig= X-Google-Smtp-Source: AGHT+IFs7Gz9HpSNg5U5PHN0/mW+UI2BYTkCqvvwNzqAgC8efbqk/7hV+qzPc2iol62LERnIc8MvAw== X-Received: by 2002:a17:902:f904:b0:1ca:1c89:9adb with SMTP id kw4-20020a170902f90400b001ca1c899adbmr12484141plb.51.1698279344769; Wed, 25 Oct 2023 17:15:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Mark Cave-Ayland Subject: [PULL 01/94] target/sparc: Clear may_lookup for npc == DYNAMIC_PC Date: Wed, 25 Oct 2023 17:13:40 -0700 Message-Id: <20231026001542.1141412-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279485598100005 Content-Type: text/plain; charset="utf-8" With pairs of jmp+rett, pc =3D=3D DYNAMIC_PC_LOOKUP and npc =3D=3D DYNAMIC_PC. Make sure that we exit for interrupts. Cc: qemu-stable@nongnu.org Fixes: 633c42834c7 ("target/sparc: Introduce DYNAMIC_PC_LOOKUP") Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index f92ff80ac8..8fabed28fd 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5654,10 +5654,10 @@ static void sparc_tr_tb_stop(DisasContextBase *dcba= se, CPUState *cs) break; } =20 + may_lookup =3D true; if (dc->pc & 3) { switch (dc->pc) { case DYNAMIC_PC_LOOKUP: - may_lookup =3D true; break; case DYNAMIC_PC: may_lookup =3D false; @@ -5667,10 +5667,24 @@ static void sparc_tr_tb_stop(DisasContextBase *dcba= se, CPUState *cs) } } else { tcg_gen_movi_tl(cpu_pc, dc->pc); - may_lookup =3D true; } =20 - save_npc(dc); + if (dc->npc & 3) { + switch (dc->npc) { + case JUMP_PC: + gen_generic_branch(dc); + break; + case DYNAMIC_PC: + may_lookup =3D false; + break; + case DYNAMIC_PC_LOOKUP: + break; + default: + g_assert_not_reached(); + } + } else { + tcg_gen_movi_tl(cpu_npc, dc->npc); + } if (may_lookup) { tcg_gen_lookup_and_goto_ptr(); } else { --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279482; cv=none; d=zohomail.com; s=zohoarc; b=nETHPcA0/KD5ub19XpzukUVa3bM7Qku5SucorNu40ULMAIDw28AwjdL0/GAEIi0VktRY3qbkLzVrNz3DhE3lvzN43PG1LhdREpwDdhvB28uuauAf8cjHmcvEENj/ZOygUvqOkYr/UPpBrK/zfblinL25Tr+CSX9bqwQgBIPRKdY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279482; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Zh61DK1PDe6VrwXTSbb5OfrsTdylybfZGSWnmMjbkM0=; b=lVvAphJnKSH59G8hShanC5eVkfzgXxyer1UtzWhYQ9TEeQ5VeggtJrF3egLf1n3kvH1+ftcrOc6I92w4Pn00L8lPI2ctwKEquFFKLnFn9hbpaLoBqet/63l+HKFonIWChb8V5QEsR7z9r/J9vl1irfIzOUn0QUbbJBrbEns9TpU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698279482109954.3626727911693; Wed, 25 Oct 2023 17:18:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo2p-00073o-6P; Wed, 25 Oct 2023 20:16:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo2g-0006za-Ut for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:07 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo2P-0004pT-Ua for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:04 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1c9d3a21f7aso2172795ad.2 for ; Wed, 25 Oct 2023 17:15:48 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279483564100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/optimize.c | 38 +++++++++++++++++++++++--------------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 2db5177c32..e8a13fedb5 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -112,11 +112,22 @@ static inline bool ts_is_const(TCGTemp *ts) return ts_info(ts)->is_const; } =20 +static inline bool ts_is_const_val(TCGTemp *ts, uint64_t val) +{ + TempOptInfo *ti =3D ts_info(ts); + return ti->is_const && ti->val =3D=3D val; +} + static inline bool arg_is_const(TCGArg arg) { return ts_is_const(arg_temp(arg)); } =20 +static inline bool arg_is_const_val(TCGArg arg, uint64_t val) +{ + return ts_is_const_val(arg_temp(arg), val); +} + static inline bool ts_is_copy(TCGTemp *ts) { return ts_info(ts)->next_copy !=3D ts; @@ -565,7 +576,7 @@ static int do_constant_folding_cond(TCGType type, TCGAr= g x, } } else if (args_are_copies(x, y)) { return do_constant_folding_cond_eq(c); - } else if (arg_is_const(y) && arg_info(y)->val =3D=3D 0) { + } else if (arg_is_const_val(y, 0)) { switch (c) { case TCG_COND_LTU: return 0; @@ -831,7 +842,7 @@ static bool fold_to_not(OptContext *ctx, TCGOp *op, int= idx) /* If the binary operation has first argument @i, fold to @i. */ static bool fold_ix_to_i(OptContext *ctx, TCGOp *op, uint64_t i) { - if (arg_is_const(op->args[1]) && arg_info(op->args[1])->val =3D=3D i) { + if (arg_is_const_val(op->args[1], i)) { return tcg_opt_gen_movi(ctx, op, op->args[0], i); } return false; @@ -840,7 +851,7 @@ static bool fold_ix_to_i(OptContext *ctx, TCGOp *op, ui= nt64_t i) /* If the binary operation has first argument @i, fold to NOT. */ static bool fold_ix_to_not(OptContext *ctx, TCGOp *op, uint64_t i) { - if (arg_is_const(op->args[1]) && arg_info(op->args[1])->val =3D=3D i) { + if (arg_is_const_val(op->args[1], i)) { return fold_to_not(ctx, op, 2); } return false; @@ -849,7 +860,7 @@ static bool fold_ix_to_not(OptContext *ctx, TCGOp *op, = uint64_t i) /* If the binary operation has second argument @i, fold to @i. */ static bool fold_xi_to_i(OptContext *ctx, TCGOp *op, uint64_t i) { - if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val =3D=3D i) { + if (arg_is_const_val(op->args[2], i)) { return tcg_opt_gen_movi(ctx, op, op->args[0], i); } return false; @@ -858,7 +869,7 @@ static bool fold_xi_to_i(OptContext *ctx, TCGOp *op, ui= nt64_t i) /* If the binary operation has second argument @i, fold to identity. */ static bool fold_xi_to_x(OptContext *ctx, TCGOp *op, uint64_t i) { - if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val =3D=3D i) { + if (arg_is_const_val(op->args[2], i)) { return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]); } return false; @@ -867,7 +878,7 @@ static bool fold_xi_to_x(OptContext *ctx, TCGOp *op, ui= nt64_t i) /* If the binary operation has second argument @i, fold to NOT. */ static bool fold_xi_to_not(OptContext *ctx, TCGOp *op, uint64_t i) { - if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val =3D=3D i) { + if (arg_is_const_val(op->args[2], i)) { return fold_to_not(ctx, op, 1); } return false; @@ -1083,8 +1094,8 @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op) * Simplify LT/GE comparisons vs zero to a single compare * vs the high word of the input. */ - if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val =3D=3D= 0 && - arg_is_const(op->args[3]) && arg_info(op->args[3])->val =3D=3D= 0) { + if (arg_is_const_val(op->args[2], 0) && + arg_is_const_val(op->args[3], 0)) { goto do_brcond_high; } break; @@ -1303,9 +1314,7 @@ static bool fold_deposit(OptContext *ctx, TCGOp *op) } =20 /* Inserting a value into zero at offset 0. */ - if (arg_is_const(op->args[1]) - && arg_info(op->args[1])->val =3D=3D 0 - && op->args[3] =3D=3D 0) { + if (arg_is_const_val(op->args[1], 0) && op->args[3] =3D=3D 0) { uint64_t mask =3D MAKE_64BIT_MASK(0, op->args[4]); =20 op->opc =3D and_opc; @@ -1316,8 +1325,7 @@ static bool fold_deposit(OptContext *ctx, TCGOp *op) } =20 /* Inserting zero into a value. */ - if (arg_is_const(op->args[2]) - && arg_info(op->args[2])->val =3D=3D 0) { + if (arg_is_const_val(op->args[2], 0)) { uint64_t mask =3D deposit64(-1, op->args[3], op->args[4], 0); =20 op->opc =3D and_opc; @@ -1855,8 +1863,8 @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op) * Simplify LT/GE comparisons vs zero to a single compare * vs the high word of the input. */ - if (arg_is_const(op->args[3]) && arg_info(op->args[3])->val =3D=3D= 0 && - arg_is_const(op->args[4]) && arg_info(op->args[4])->val =3D=3D= 0) { + if (arg_is_const_val(op->args[3], 0) && + arg_is_const_val(op->args[4], 0)) { goto do_setcond_high; } break; --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.15.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:15:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279346; x=1698884146; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gYhvKxqYq5JV9In/R2ATIQpLZ14hQa9hieJVJfsIFqc=; b=c27mi1B5pvgTHcLemzGBuoJG9gf0taDvwrhe1Xj7FEoQ36hKnHP+EdbhJOlYVHbY8L F8kSipKrMaXihxM4B+3SQLB9B8/5sFAcT/c5JZSjyaRfEb96LAh19+vrnSG9f2eWfMtU /Tw23MAkLh2JeeIJAXnwEcLRbWbXTrbvgHWbbL+ehXo56eBddA0KzkV/jBlT8sR0zzYx e1CQ/U9EGtoFpKylxVr/pNM6kwo7gwfl56wr8BBv1bMfOlOmVpsS15iC9GRevfbVihvK 6sHJlB5NwGTL1Fetxi+QdQjzhnrZcx/0vGvfryh6WAUf87arhH+6a9t70JxatHy6iVaQ E0MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279346; x=1698884146; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gYhvKxqYq5JV9In/R2ATIQpLZ14hQa9hieJVJfsIFqc=; b=tiAARDDXpFNALCrCxBaWXCOi1EOvH+pR+sHDKQiBPoT5BlZsR+yyWhwWEgePlKxp2J YEdTL0cybhlWVFyl3NdC/+UlhVka+7jJXYPE+5SjTD0q1f6TBYGEa0h0XdwbN0OH5pqE FETUmPeflBC1uOA0QraMBSAgs6zbgFP15xroVpfa862iddciCGOShyQOAtnjPB2rWcId EkQOvI0sXxCBFac6DKGS5hLQqvNsGE/ocj83w6NkSUOCl9BZen77brxY9ezWiULqv+E6 vlIgj6uB4Tdx5sy+GXM0wBgUoOy+WZmmUyK06DXFi+hfCOnoSlJNmWfGrrH+mQ8zItOJ XN5w== X-Gm-Message-State: AOJu0YwcaK1y3Zx8fcrMw40tJ6Gw2Unj536keFk5IpaoKEQZLHiY/mGa s++mLImTZXLfPJQV5aInuH3jF9+5SFdB3NKAtT0= X-Google-Smtp-Source: AGHT+IFLcvsIy9JMlHjvnoYK9/x4PuzI3sjNddQ8Bm9QKUheqPq345IyQeJr6iIqSlT9r/JJr81pew== X-Received: by 2002:a17:902:ce8d:b0:1c7:4ab6:b3cc with SMTP id f13-20020a170902ce8d00b001c74ab6b3ccmr20340206plg.54.1698279346537; Wed, 25 Oct 2023 17:15:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 02/94] target/sparc: Implement check_align inline Date: Wed, 25 Oct 2023 17:13:42 -0700 Message-Id: <20231026001542.1141412-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279469699100007 Content-Type: text/plain; charset="utf-8" Emit the exception at the end of the translation block, so that the non-exception case can fall through. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/helper.h | 1 - target/sparc/ldst_helper.c | 7 ++-- target/sparc/translate.c | 68 +++++++++++++++++++++++++++++++++----- 3 files changed, 61 insertions(+), 15 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index b8f1e78c75..b116ddcb29 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -24,7 +24,6 @@ DEF_HELPER_FLAGS_2(tick_set_count, TCG_CALL_NO_RWG, void,= ptr, i64) DEF_HELPER_FLAGS_3(tick_get_count, TCG_CALL_NO_WG, i64, env, ptr, int) DEF_HELPER_FLAGS_2(tick_set_limit, TCG_CALL_NO_RWG, void, ptr, i64) #endif -DEF_HELPER_FLAGS_3(check_align, TCG_CALL_NO_WG, void, env, tl, i32) DEF_HELPER_1(debug, void, env) DEF_HELPER_1(save, void, env) DEF_HELPER_1(restore, void, env) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 78b03308ae..246de86c98 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -360,6 +360,7 @@ static inline void do_check_asi(CPUSPARCState *env, int= asi, uintptr_t ra) #endif /* !CONFIG_USER_ONLY */ #endif =20 +#if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY) static void do_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align, uintptr_t ra) { @@ -367,11 +368,7 @@ static void do_check_align(CPUSPARCState *env, target_= ulong addr, cpu_raise_exception_ra(env, TT_UNALIGNED, ra); } } - -void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t al= ign) -{ - do_check_align(env, addr, align, GETPC()); -} +#endif =20 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \ defined(DEBUG_MXCC) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 8fabed28fd..8f6fd453e7 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -68,6 +68,15 @@ static TCGv cpu_wim; /* Floating point registers */ static TCGv_i64 cpu_fpr[TARGET_DPREGS]; =20 +typedef struct DisasDelayException { + struct DisasDelayException *next; + TCGLabel *lab; + TCGv_i32 excp; + /* Saved state at parent insn. */ + target_ulong pc; + target_ulong npc; +} DisasDelayException; + typedef struct DisasContext { DisasContextBase base; target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC = */ @@ -89,6 +98,7 @@ typedef struct DisasContext { int fprs_dirty; int asi; #endif + DisasDelayException *delay_excp_list; } DisasContext; =20 typedef struct { @@ -984,9 +994,38 @@ static void gen_exception(DisasContext *dc, int which) dc->base.is_jmp =3D DISAS_NORETURN; } =20 -static void gen_check_align(TCGv addr, int mask) +static TCGLabel *delay_exceptionv(DisasContext *dc, TCGv_i32 excp) { - gen_helper_check_align(tcg_env, addr, tcg_constant_i32(mask)); + DisasDelayException *e =3D g_new0(DisasDelayException, 1); + + e->next =3D dc->delay_excp_list; + dc->delay_excp_list =3D e; + + e->lab =3D gen_new_label(); + e->excp =3D excp; + e->pc =3D dc->pc; + /* Caller must have used flush_cond before branch. */ + assert(e->npc !=3D JUMP_PC); + e->npc =3D dc->npc; + + return e->lab; +} + +static TCGLabel *delay_exception(DisasContext *dc, int excp) +{ + return delay_exceptionv(dc, tcg_constant_i32(excp)); +} + +static void gen_check_align(DisasContext *dc, TCGv addr, int mask) +{ + TCGv t =3D tcg_temp_new(); + TCGLabel *lab; + + tcg_gen_andi_tl(t, addr, mask); + + flush_cond(dc); + lab =3D delay_exception(dc, TT_UNALIGNED); + tcg_gen_brcondi_tl(TCG_COND_NE, t, 0, lab); } =20 static void gen_mov_pc_npc(DisasContext *dc) @@ -5019,9 +5058,9 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) tcg_gen_mov_tl(cpu_tmp0, cpu_src1); } } + gen_check_align(dc, cpu_tmp0, 3); gen_helper_restore(tcg_env); gen_mov_pc_npc(dc); - gen_check_align(cpu_tmp0, 3); tcg_gen_mov_tl(cpu_npc, cpu_tmp0); dc->npc =3D DYNAMIC_PC_LOOKUP; goto jmp_insn; @@ -5044,12 +5083,9 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) switch (xop) { case 0x38: /* jmpl */ { - TCGv t =3D gen_dest_gpr(dc, rd); - tcg_gen_movi_tl(t, dc->pc); - gen_store_gpr(dc, rd, t); - + gen_check_align(dc, cpu_tmp0, 3); + gen_store_gpr(dc, rd, tcg_constant_tl(dc->pc)); gen_mov_pc_npc(dc); - gen_check_align(cpu_tmp0, 3); gen_address_mask(dc, cpu_tmp0); tcg_gen_mov_tl(cpu_npc, cpu_tmp0); dc->npc =3D DYNAMIC_PC_LOOKUP; @@ -5060,8 +5096,8 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) { if (!supervisor(dc)) goto priv_insn; + gen_check_align(dc, cpu_tmp0, 3); gen_mov_pc_npc(dc); - gen_check_align(cpu_tmp0, 3); tcg_gen_mov_tl(cpu_npc, cpu_tmp0); dc->npc =3D DYNAMIC_PC; gen_helper_rett(tcg_env); @@ -5643,6 +5679,7 @@ static void sparc_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cs) static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); + DisasDelayException *e, *e_next; bool may_lookup; =20 switch (dc->base.is_jmp) { @@ -5704,6 +5741,19 @@ static void sparc_tr_tb_stop(DisasContextBase *dcbas= e, CPUState *cs) default: g_assert_not_reached(); } + + for (e =3D dc->delay_excp_list; e ; e =3D e_next) { + gen_set_label(e->lab); + + tcg_gen_movi_tl(cpu_pc, e->pc); + if (e->npc % 4 =3D=3D 0) { + tcg_gen_movi_tl(cpu_npc, e->npc); + } + gen_helper_raise_exception(tcg_env, e->excp); + + e_next =3D e->next; + g_free(e); + } } =20 static void sparc_tr_disas_log(const DisasContextBase *dcbase, --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279456; cv=none; d=zohomail.com; s=zohoarc; b=jR/qFbCzMsrCR/Fue6mEWSVdPOhWiEsauF2H4aNMcZ34fsuDnNum1paLpuoOoDOUuqaHcF0kpQYvWk3gL6iIxpLShsiGNFLHaRfz65ZA4Sz2cRJv5An51ousYRDYbtqhy9lh/FACe6LN7gn0ENMuEiJwjx+za7WzdRGsLadnlyA= ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.15.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:15:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279349; x=1698884149; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=9eXocbu34bghBLrSPFKvIsugn7thygfTREC245booiE=; b=ViFPoTpYbs8TzCeDyeQsbyRwCeKZfUkn+Wue5Tzr/LderAgydYhYiw1BdYQu1qYS6n hBFbb6M/lqMQGPyNWDHgIYr/cfz9mJbQwRWs3+JcvQfZ7f6oOjootgdvAfpIQ4CoMDgJ 2hMRglDA+515UftG6PPJU4iIyPIJHxruCQxhdC1U58uDaRn3prcZM1nLQ6SECx6LtvTe JAz7jkMEhtIBiOJ4/LK/sPMRPr0RXm4H7feROP6/ZEq2KXNc+LjdvOorGRG8Sw+A1oOs mY1N2FF3u4/jUwQYzZ2VcDFBRlWivVHP9XQ48cUKq0GLCrYv/WTE4jgi5lKQEWs2Cxhn gDIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279349; x=1698884149; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9eXocbu34bghBLrSPFKvIsugn7thygfTREC245booiE=; b=LBa4OLcaE5BFFV/xGVVkwOyrh+LoToGFiEtN/ZIEMwY3GeF+6Z4UMJzWdKISC+gz9F F228i2e//MwjJNX2tkK+m2jPrvnsv0VvN8BbTpBtgYuJB8IslKf77WoVERHM6NCogZDe ZDKMaNBg/kqTt7WhivOl8RdC7AgxmomuI39wueTBM73KP14zXSiMe5kcbfuJBs+jJfnO YwEgdcAaviPM7LvKQQVMA8oC7Cygr7zBo4UjIYp/61mCIl0RVmd9dSqJmdKJ94N1Is6s ioJercjAy2iDXBjiKSieHpnoDzFnMmD6/ZGGpl9++ndpch8f81DzEu6e9Tm1rGMMKJ69 40ZQ== X-Gm-Message-State: AOJu0YwcQLDzCHX5J9donQ7bLwmw7sawuIvvmz3RfFg09q6OHKHFH5xJ N2PiOMAzyWKR4KJLSGh0kic50xN2MU3WA5jz9c8= X-Google-Smtp-Source: AGHT+IHESTepAuQmaqFWTCm2M5XkN9zsZ/Zo6rdbIkG9DvJ3kShBCRIg/K6fD8N4ms6/ztlHzLahvQ== X-Received: by 2002:a17:903:268c:b0:1c9:b207:d40b with SMTP id jf12-20020a170903268c00b001c9b207d40bmr13726537plb.38.1698279349169; Wed, 25 Oct 2023 17:15:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 03/29] tcg/optimize: Split out do_constant_folding_cond1 Date: Wed, 25 Oct 2023 17:13:45 -0700 Message-Id: <20231026001542.1141412-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279457522100003 Content-Type: text/plain; charset="utf-8" Handle modifications to the arguments and condition in a single place. Signed-off-by: Richard Henderson --- tcg/optimize.c | 57 ++++++++++++++++++++++++-------------------------- 1 file changed, 27 insertions(+), 30 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index e8a13fedb5..89cc794d24 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -672,6 +672,23 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2) return false; } =20 +static int do_constant_folding_cond1(OptContext *ctx, TCGArg dest, + TCGArg *p1, TCGArg *p2, TCGArg *pcond) +{ + TCGCond cond; + bool swap; + int r; + + swap =3D swap_commutative(dest, p1, p2); + cond =3D *pcond; + if (swap) { + *pcond =3D cond =3D tcg_swap_cond(cond); + } + + r =3D do_constant_folding_cond(ctx->type, *p1, *p2, cond); + return r; +} + static void init_arguments(OptContext *ctx, TCGOp *op, int nb_args) { for (int i =3D 0; i < nb_args; i++) { @@ -1053,14 +1070,8 @@ static bool fold_andc(OptContext *ctx, TCGOp *op) =20 static bool fold_brcond(OptContext *ctx, TCGOp *op) { - TCGCond cond =3D op->args[2]; - int i; - - if (swap_commutative(NO_DEST, &op->args[0], &op->args[1])) { - op->args[2] =3D cond =3D tcg_swap_cond(cond); - } - - i =3D do_constant_folding_cond(ctx->type, op->args[0], op->args[1], co= nd); + int i =3D do_constant_folding_cond1(ctx, NO_DEST, &op->args[0], + &op->args[1], &op->args[2]); if (i =3D=3D 0) { tcg_op_remove(ctx->tcg, op); return true; @@ -1550,21 +1561,18 @@ static bool fold_mov(OptContext *ctx, TCGOp *op) =20 static bool fold_movcond(OptContext *ctx, TCGOp *op) { - TCGCond cond =3D op->args[5]; int i; =20 - if (swap_commutative(NO_DEST, &op->args[1], &op->args[2])) { - op->args[5] =3D cond =3D tcg_swap_cond(cond); - } /* * Canonicalize the "false" input reg to match the destination reg so * that the tcg backend can implement a "move if true" operation. */ if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) { - op->args[5] =3D cond =3D tcg_invert_cond(cond); + op->args[5] =3D tcg_invert_cond(op->args[5]); } =20 - i =3D do_constant_folding_cond(ctx->type, op->args[1], op->args[2], co= nd); + i =3D do_constant_folding_cond1(ctx, NO_DEST, &op->args[1], + &op->args[2], &op->args[5]); if (i >=3D 0) { return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[4 - i]); } @@ -1578,6 +1586,7 @@ static bool fold_movcond(OptContext *ctx, TCGOp *op) uint64_t tv =3D arg_info(op->args[3])->val; uint64_t fv =3D arg_info(op->args[4])->val; TCGOpcode opc, negopc =3D 0; + TCGCond cond =3D op->args[5]; =20 switch (ctx->type) { case TCG_TYPE_I32: @@ -1805,14 +1814,8 @@ static bool fold_remainder(OptContext *ctx, TCGOp *o= p) =20 static bool fold_setcond(OptContext *ctx, TCGOp *op) { - TCGCond cond =3D op->args[3]; - int i; - - if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) { - op->args[3] =3D cond =3D tcg_swap_cond(cond); - } - - i =3D do_constant_folding_cond(ctx->type, op->args[1], op->args[2], co= nd); + int i =3D do_constant_folding_cond1(ctx, op->args[0], &op->args[1], + &op->args[2], &op->args[3]); if (i >=3D 0) { return tcg_opt_gen_movi(ctx, op, op->args[0], i); } @@ -1824,14 +1827,8 @@ static bool fold_setcond(OptContext *ctx, TCGOp *op) =20 static bool fold_negsetcond(OptContext *ctx, TCGOp *op) { - TCGCond cond =3D op->args[3]; - int i; - - if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) { - op->args[3] =3D cond =3D tcg_swap_cond(cond); - } - - i =3D do_constant_folding_cond(ctx->type, op->args[1], op->args[2], co= nd); + int i =3D do_constant_folding_cond1(ctx, op->args[0], &op->args[1], + &op->args[2], &op->args[3]); if (i >=3D 0) { return tcg_opt_gen_movi(ctx, op, op->args[0], -i); } --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279562; cv=none; d=zohomail.com; s=zohoarc; b=PKUsMw+c44wy6iHl+DbCPtP3Iwm4xlwxVQnskemDamMheudDsP09wH8gxg2amgFsybH2KstVJPYE4bGerUhH+O82jt7jR36YFeC/0TnyhP5CkzMWNiB6cLBx3bn6wBPDuzjihpH592tpUbk8isTXy3UzE6EsiaGuTp/Yrw0EXq8= ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.15.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:15:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279348; x=1698884148; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a6T/c3A96Bz3wE+bsJljf0ySAcIsMHNjnW78siXjVBI=; b=yCAN3Aw4444XqOT64d85qGq5ufleB0tXDzpiplpEiLDAF9V2CdX16bBumSvm7EfKpo U6Hc8t/jucAFW5AfxwIFaErPB9XO3xQlGB4a3SF9jnqPZQ3MvFKcVTPw56CkB+XEP1pz JRfdero6Ud6Po+fKY0fSgzxc1fKFZAfQOnkZCeEWIn/VPtX5vRldDILbFknyoaiUhvkI Lrs8CIShWTQYctvwBdj4s8ScuwWkOTpfxGKDB/UhvbRIy1Pmktna7AKUukU5GFEOxG17 kRMcpMACI+KJpywxm0TDUtoaSBxqegznfzFdCG0K8rnZdqPJ7Y2crh3vwltAUP5W/fjj VEbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279348; x=1698884148; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a6T/c3A96Bz3wE+bsJljf0ySAcIsMHNjnW78siXjVBI=; b=qZaZ+BkmU0POHBp3trLdA7gaYHj0UoSKw/o7yi/T3EJzq7YLUDUQXF1i/m4VHM96ou PsKaEg2UmiaubdcGIcGDQJg8bYiM1JhmAOSoILvE+k/dd0MgYHT9v8ooze/NoqcOvJ04 Q1K0KYl+hFhA3Prrgd90TqvlfVQM4ybEuwdbMUq+nD0sHYZou8gqvvPOLXe6fHnjUkW+ y+6IvkYGSPrFLSeayCMELF1LibhNgfYc3DGtptX2wa+rQkRV72PRdUI+leRFkTnlDaaW JVG16yGaHMkKAuiOEpHazlhAK9678tk41P0RTtmUhQQ/oa7Fd9CFCuwPEKtxv5Cut8Oz 6HTA== X-Gm-Message-State: AOJu0YwonhOT5zMg3Os4rM5Mq8JMs6PTWkFqldHbT4V/1CZ1h/0ukkGM 0pPJP8z1yb2osFjCRo+AfxHtTaLn6F1HycQmTz0= X-Google-Smtp-Source: AGHT+IGSED9kxEI5GOLUvQcbo9shOVqJ3gEAw8/TxeLZoDYuQRhsR1k779EDhb0U7EDfmslWrvBMCw== X-Received: by 2002:a17:902:c404:b0:1c7:8345:f377 with SMTP id k4-20020a170902c40400b001c78345f377mr18274565plk.29.1698279348361; Wed, 25 Oct 2023 17:15:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 03/94] target/sparc: Avoid helper_raise_exception in helper_st_asi Date: Wed, 25 Oct 2023 17:13:44 -0700 Message-Id: <20231026001542.1141412-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279563740100001 Content-Type: text/plain; charset="utf-8" Always use cpu_raise_exception_ra with GETPC for unwind. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 246de86c98..09066d5487 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1650,7 +1650,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong a= ddr, target_ulong val, int idx =3D ((asi & 2) >> 1) | ((asi & 8) >> 2); env->dmmu.sun4v_tsb_pointers[idx] =3D val; } else { - helper_raise_exception(env, TT_ILL_INSN); + goto illegal_insn; } break; case 0x33: @@ -1662,7 +1662,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong a= ddr, target_ulong val, */ env->dmmu.sun4v_ctx_config[(asi & 8) >> 3] =3D val; } else { - helper_raise_exception(env, TT_ILL_INSN); + goto illegal_insn; } break; case 0x35: @@ -1679,7 +1679,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong a= ddr, target_ulong val, int idx =3D ((asi & 2) >> 1) | ((asi & 8) >> 2); env->immu.sun4v_tsb_pointers[idx] =3D val; } else { - helper_raise_exception(env, TT_ILL_INSN); + goto illegal_insn; } break; case 0x37: @@ -1691,7 +1691,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong a= ddr, target_ulong val, */ env->immu.sun4v_ctx_config[(asi & 8) >> 3] =3D val; } else { - helper_raise_exception(env, TT_ILL_INSN); + goto illegal_insn; } break; case ASI_UPA_CONFIG: /* UPA config */ @@ -1920,6 +1920,8 @@ void helper_st_asi(CPUSPARCState *env, target_ulong a= ddr, target_ulong val, default: sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); return; + illegal_insn: + cpu_raise_exception_ra(env, TT_ILL_INSN, GETPC()); } } #endif /* CONFIG_USER_ONLY */ --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279522; cv=none; d=zohomail.com; s=zohoarc; b=L35bNBDZC9D/lDfsWOAlz1x79W1Xl7vJtVKyL2yPS9bg52UyoIPeZ/Kne4N9HjKKuU39F8l18CW12nxc7s36OyrUWrYszEzZ8a3KJ9mvsMUuS8rnZDNprG9Q4oayCR7EIdEyLOFRIFFvf8Dko558UzLja4Ds8wfkjKpR8lwentI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279522; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+FzEYXMiYUmAnzQhyJLC08QhIql51EYsnrwBv94uD9o=; b=fGnh5AxNDhQUetkSdYjVO+wlLm0qPpBU1dzj/swk6Ke1QGRVv/xPNihIZHm3JvMRHAggJwfXgVgXtA63pHOQV/gtOrvMsN3INUV7j7PEJXEmYSuEsx9wcGPHNeKaxh9ZC77QkVPFwBDrYlmW0ncd91upJ7O5XjlVqoosk4gqlbU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698279522510170.11625058222978; Wed, 25 Oct 2023 17:18:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo2n-00072I-DZ; Wed, 25 Oct 2023 20:16:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo2g-0006zc-Vx for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:07 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo2S-0004py-2v for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:06 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1ca215cc713so2017035ad.3 for ; Wed, 25 Oct 2023 17:15:51 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.15.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:15:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279350; x=1698884150; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+FzEYXMiYUmAnzQhyJLC08QhIql51EYsnrwBv94uD9o=; b=TwyApiMWjqElD1rNs7/DY+fIZlwvakBGmNFSqrv5XY4LuKyYcs+vWuNiT+Ksx19kk1 0/YVUb4FdkZzGj6Gl17xU5Phv9V3eB8QUZ9NeQ7vOTo0OqLeuI5Q38YLG4BjIG7rF3YG TFaIhs4Jiko3vEK88e88inTR+iYEIJWmjQyFfR0AlAGReSbWSq2MAJxK1sopP/xNXuME 5nru8x7r4QH8bzlC5yWX2tfBT0uUHMO/0Bp67DIDcxOiD+VFS4H15hNTl3gTZtcEKNTc odkbeIScK9abROCb8H9V23WRXTGyCup7299jKq38knqywPyjEHBk24S2JcJrpdOugdPz fkGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279350; x=1698884150; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+FzEYXMiYUmAnzQhyJLC08QhIql51EYsnrwBv94uD9o=; b=dQHdaqDrmxxo9DwB+4/eBDET+s7WW4sGY3sowQy1oELVAMtNK191E5Js5h/nIbsrMi 4M43SPHj/xszcKIYthGyGMcE4NnpUAPNRRG50nSrd6dTl7GXqhoXqKYkH8EFdLnKaTxg ALvxQIXdapB2I52vA3HtHYrTtFlaniEmDymARZ+IxyuiBkAPMD+HGJzT/lwC8DRl3ige DPuESiJgP6zVmfQHroK7vfLsmOZXw2XakeQbgvq+NS6xHa7eX9bFon/+9WGkXEObP7yC rBb92AG9o/tPTApoU/CQ+rsHeDCK56Yorgo5xXwZV5dOgDyoF7G+58F1VHvdTkOaMm2f p2gg== X-Gm-Message-State: AOJu0YzY7S+rllE6RCwTfDwN8gKCVc8UltA3ORuwGnQJMQUuh+e6B31x a9lRkZ/5Ea1uOHBGg+9sPZcGETkLjIWlm8sKp+c= X-Google-Smtp-Source: AGHT+IEx3c8walI5+UFnhn5ZAaTBPiltDwl1eQiQ5j7HNcUeazHczOs+q380AymLSYxF36W/9/Uo5g== X-Received: by 2002:a17:902:f0c4:b0:1c8:a132:a00f with SMTP id v4-20020a170902f0c400b001c8a132a00fmr12817707pla.12.1698279349998; Wed, 25 Oct 2023 17:15:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 04/94] target/sparc: Set TCG_GUEST_DEFAULT_MO Date: Wed, 25 Oct 2023 17:13:46 -0700 Message-Id: <20231026001542.1141412-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279523698100013 Always use TSO, per the Oracle 2015 manual. This is slightly less restrictive than the TCG_MO_ALL default, and happens to match the i386 model, which will eliminate a few extra barriers on that host. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index b3a98f1d74..9fc5c401d2 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -6,6 +6,29 @@ #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" =20 +/* + * From Oracle SPARC Architecture 2015: + * + * Compatibility notes: The PSO memory model described in SPARC V8 and + * SPARC V9 compatibility architecture specifications was never implemen= ted + * in a SPARC V9 implementation and is not included in the Oracle SPARC + * Architecture specification. + * + * The RMO memory model described in the SPARC V9 specification was + * implemented in some non-Sun SPARC V9 implementations, but is not + * directly supported in Oracle SPARC Architecture 2015 implementations. + * + * Therefore always use TSO in QEMU. + * + * D.5 Specification of Partial Store Order (PSO) + * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. + * + * D.6 Specification of Total Store Order (TSO) + * ... PSO with the additional requirement that all [stores] are followed + * by an implied MEMBAR #StoreStore. + */ +#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) + #if !defined(TARGET_SPARC64) #define TARGET_DPREGS 16 #else --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279808; cv=none; d=zohomail.com; s=zohoarc; b=Bhzd04ANjljBkGMPAHZgLUit3M7ZC+ocL3+XdOW1Pc2o6EwFi/mRCId2IQqAbu5z63xRZ05JcZx83P0KipvKrrWfWdRtqCGukw3LgmTq6XxUQyQYVnSv9ie/O8JYuZwAi+P2lkBgdHzjNE/A5pQiSmbPs9uhc7CT0AsPY8A0R+k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279808; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=xFOV1ZTpKlHV2EkIZjqhQOIe3ZbiCQ+tGnrYqmSw9YI=; b=VVdRWf58L3lZ+U5xHNE20T8UX6l5XBCS8LzPszWu19rC0eNsBg/WokgGWQjmkR+w4nFBS35ah4EfRFEb9YlfbqEDHwEb7PUz8Wzdp6O54KcMGzmMBCVm3Sf24wFm0c8tRirhinbLUnuIoaqA2aQzCwMZkAN0mXwoPwNMdpWlevw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698279808844654.373211838991; Wed, 25 Oct 2023 17:23:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo2p-00073n-4K; Wed, 25 Oct 2023 20:16:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo2g-0006zZ-Ua for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:06 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo2X-0004q2-ET for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:06 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1cac925732fso2239485ad.1 for ; Wed, 25 Oct 2023 17:15:51 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.15.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:15:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279351; x=1698884151; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=xFOV1ZTpKlHV2EkIZjqhQOIe3ZbiCQ+tGnrYqmSw9YI=; b=p7sHZTYH5eS2Q/EBI8/XUAWycHrOI8dHk2GvMoBZ12UKgQcXv8Fi3CGc7zL41An5mG LZyfL7pkO669t+cD+s+20GGy5buDcqGBJYmxgS+gZn/j+NBoZIfvFUTkfLBc4dwyh08p kNSBT6RMk6ooHlht1WjNA+58G54xhaJigmGt3XHcZuisE2obBPhalk+7jX8EFNybWg9G 3qycPbmmFxwP756EBx7vwlEpTeWzyMG2QYSnwmWHremDKzuIjBElrsunIgMj06uIr9kj bImhk/EoSV/qD+w8yQu2n+DOI/BIl88iqOUkNDPKf9TEgmpW8Veef9066R55S7f37YIL sIrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279351; x=1698884151; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xFOV1ZTpKlHV2EkIZjqhQOIe3ZbiCQ+tGnrYqmSw9YI=; b=MCgDT/wsX75q/dHrriKPY3qDnPVi81Ppc2w595CNi97aSYBcz/lgy3nj0SasHujexZ +6EKZ1NFzSKxtNiamds6R478kbjGbWt4MPKbTLufYfrcZTdy3CuVDiDXr1hWQE+hkeke fUdcFJ0Blt2B/0DhSo7k+ACpRsrfOIPF9OYtn681jpKNFq1C5Ypx0Um0/niB7vG7rrsp s5clrp5Ch2Df04XCoMbVcE05h6tErENGgOcfwALaOeWRlogLe7ccOJivYV0R/qGhDFUB +ajp0CAyXabIcE7SPRSHcEiVg5oGltzEuBGTmxxm1ogUD+bn4aw/WPWXMNBpsZ+E9+m1 IFaQ== X-Gm-Message-State: AOJu0YwLglAQqWcw35d7SBFER+fM1cthyhRf4Z355RKCo/clC1DBsbYL bKuRgPmWOURF/W8/f3wxwLxaM3v1dDb/EId+EOA= X-Google-Smtp-Source: AGHT+IHTofsyucuKU6KnRLzB9OBX9uAgEPTeXQluwYQXUj2tmqyhcomn3UVVYZEsoTX5PDVTvBSZkQ== X-Received: by 2002:a17:903:3208:b0:1ca:8e43:765d with SMTP id s8-20020a170903320800b001ca8e43765dmr12437887plh.64.1698279350813; Wed, 25 Oct 2023 17:15:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 04/29] tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2 Date: Wed, 25 Oct 2023 17:13:47 -0700 Message-Id: <20231026001542.1141412-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279810595100003 Content-Type: text/plain; charset="utf-8" Mirror the new do_constant_folding_cond1 by doing all argument and condition adjustment within one helper. Signed-off-by: Richard Henderson --- tcg/optimize.c | 107 ++++++++++++++++++++++++++----------------------- 1 file changed, 57 insertions(+), 50 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 89cc794d24..76be0fc337 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -589,43 +589,6 @@ static int do_constant_folding_cond(TCGType type, TCGA= rg x, return -1; } =20 -/* - * Return -1 if the condition can't be simplified, - * and the result of the condition (0 or 1) if it can. - */ -static int do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c) -{ - TCGArg al =3D p1[0], ah =3D p1[1]; - TCGArg bl =3D p2[0], bh =3D p2[1]; - - if (arg_is_const(bl) && arg_is_const(bh)) { - tcg_target_ulong blv =3D arg_info(bl)->val; - tcg_target_ulong bhv =3D arg_info(bh)->val; - uint64_t b =3D deposit64(blv, 32, 32, bhv); - - if (arg_is_const(al) && arg_is_const(ah)) { - tcg_target_ulong alv =3D arg_info(al)->val; - tcg_target_ulong ahv =3D arg_info(ah)->val; - uint64_t a =3D deposit64(alv, 32, 32, ahv); - return do_constant_folding_cond_64(a, b, c); - } - if (b =3D=3D 0) { - switch (c) { - case TCG_COND_LTU: - return 0; - case TCG_COND_GEU: - return 1; - default: - break; - } - } - } - if (args_are_copies(al, bl) && args_are_copies(ah, bh)) { - return do_constant_folding_cond_eq(c); - } - return -1; -} - /** * swap_commutative: * @dest: TCGArg of the destination argument, or NO_DEST. @@ -672,6 +635,10 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2) return false; } =20 +/* + * Return -1 if the condition can't be simplified, + * and the result of the condition (0 or 1) if it can. + */ static int do_constant_folding_cond1(OptContext *ctx, TCGArg dest, TCGArg *p1, TCGArg *p2, TCGArg *pcond) { @@ -689,6 +656,51 @@ static int do_constant_folding_cond1(OptContext *ctx, = TCGArg dest, return r; } =20 +static int do_constant_folding_cond2(OptContext *ctx, TCGArg *args) +{ + TCGArg al, ah, bl, bh; + TCGCond c; + bool swap; + + swap =3D swap_commutative2(args, args + 2); + c =3D args[4]; + if (swap) { + args[4] =3D c =3D tcg_swap_cond(c); + } + + al =3D args[0]; + ah =3D args[1]; + bl =3D args[2]; + bh =3D args[3]; + + if (arg_is_const(bl) && arg_is_const(bh)) { + tcg_target_ulong blv =3D arg_info(bl)->val; + tcg_target_ulong bhv =3D arg_info(bh)->val; + uint64_t b =3D deposit64(blv, 32, 32, bhv); + + if (arg_is_const(al) && arg_is_const(ah)) { + tcg_target_ulong alv =3D arg_info(al)->val; + tcg_target_ulong ahv =3D arg_info(ah)->val; + uint64_t a =3D deposit64(alv, 32, 32, ahv); + return do_constant_folding_cond_64(a, b, c); + } + if (b =3D=3D 0) { + switch (c) { + case TCG_COND_LTU: + return 0; + case TCG_COND_GEU: + return 1; + default: + break; + } + } + } + if (args_are_copies(al, bl) && args_are_copies(ah, bh)) { + return do_constant_folding_cond_eq(c); + } + return -1; +} + static void init_arguments(OptContext *ctx, TCGOp *op, int nb_args) { for (int i =3D 0; i < nb_args; i++) { @@ -1085,15 +1097,13 @@ static bool fold_brcond(OptContext *ctx, TCGOp *op) =20 static bool fold_brcond2(OptContext *ctx, TCGOp *op) { - TCGCond cond =3D op->args[4]; - TCGArg label =3D op->args[5]; + TCGCond cond; + TCGArg label; int i, inv =3D 0; =20 - if (swap_commutative2(&op->args[0], &op->args[2])) { - op->args[4] =3D cond =3D tcg_swap_cond(cond); - } - - i =3D do_constant_folding_cond2(&op->args[0], &op->args[2], cond); + i =3D do_constant_folding_cond2(ctx, &op->args[0]); + cond =3D op->args[4]; + label =3D op->args[5]; if (i >=3D 0) { goto do_brcond_const; } @@ -1841,14 +1851,11 @@ static bool fold_negsetcond(OptContext *ctx, TCGOp = *op) =20 static bool fold_setcond2(OptContext *ctx, TCGOp *op) { - TCGCond cond =3D op->args[5]; + TCGCond cond; int i, inv =3D 0; =20 - if (swap_commutative2(&op->args[1], &op->args[3])) { - op->args[5] =3D cond =3D tcg_swap_cond(cond); - } - - i =3D do_constant_folding_cond2(&op->args[1], &op->args[3], cond); + i =3D do_constant_folding_cond2(ctx, &op->args[1]); + cond =3D op->args[5]; if (i >=3D 0) { goto do_setcond_const; } --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.15.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:15:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279352; x=1698884152; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=D1jMbpp1weXZkSHBUh0Jn0kijypmzVFb4f/5Y0tU+kg=; b=WmYjuOPQnWYowCgVOigqJACvsa2g/1OEDSIhZ9omh8JP1QpCmBSltEC1+Yf8gs73Sj e8raS8ecIu1+Z2Tzw2GQD5tMi6SMS3GauyVVk+5HajgOiXNo0clpo+a0pktGPggFhw7e Y8pmIjZLF0pXSmeIQ2xoqz7RK5CzSmALzP7S0zSDrEWGWHyGyHNb8SiJssTUf0j0EfUE OZsEcyD4DnhQ4NY23sIs3mskm937qPFYQWCoHvjYabh7rZG05KiOvECkGnMF1aKM8n21 tFeJUr9Xw+Ui/iFOU4wKuSJ2pJCy7IZOexgEL1U7XQXlhGcEzzhwy/DIQsDHMBCb8xtM aurw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279352; x=1698884152; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D1jMbpp1weXZkSHBUh0Jn0kijypmzVFb4f/5Y0tU+kg=; b=MKheI31gDT4f8GjaQ8oSjfzMvwMIjqrR4DgRkoik5B8FVEOOtM2CTo0est0H6Vq5OQ xndK/6q3YOTlUOvjbyo2WXL3vLgoIKZEi9DVh5iXAMIOKCbE3EhqqynT7gE+lDzI8ZCD 0Gx78WOpN8TCoC3lskU7KhfNuEzgJ4X5DcAU4JdFmHlFSzwcUVEua7VVhP5iwEgy1+to NmZ5/e1gaffB8bHyXquM/x77OwPQkWVyuUX+NWAirAVDleNlW8+Nn9Uv/mn+lo6NrZL+ hN6Du2cpYNSuVLA3VvrYDyjjJsKWpCFMJW1d65PVc9N1eUzIgjY74k4g0LnqnE7iOb+3 WsoQ== X-Gm-Message-State: AOJu0YySiAY3XwotLMPkfv4xBLGPUuJD8LzwbtNRWYpeklAyrW5JXbqn vo8ybcF6RgU1SU1cjM++Vkx5DfmFBr1GCusCjvM= X-Google-Smtp-Source: AGHT+IFwoTIEC/Tr7pl7KEvOj401ibO/S1DIfGRHC3W/c7vcTwruYJ4YUvPHgX+BB8fIB7hA4meI8A== X-Received: by 2002:a17:902:e747:b0:1c9:fb76:42fe with SMTP id p7-20020a170902e74700b001c9fb7642femr19636917plf.45.1698279352351; Wed, 25 Oct 2023 17:15:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 05/29] tcg/optimize: Split out arg_new_constant Date: Wed, 25 Oct 2023 17:13:49 -0700 Message-Id: <20231026001542.1141412-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279521683100009 Content-Type: text/plain; charset="utf-8" Fixes a bug wherein raw uses of tcg_constant_internal do not have their TempOptInfo initialized. Signed-off-by: Richard Henderson --- tcg/optimize.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 76be0fc337..2f2d1c3001 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -237,6 +237,21 @@ static bool args_are_copies(TCGArg arg1, TCGArg arg2) return ts_are_copies(arg_temp(arg1), arg_temp(arg2)); } =20 +static TCGArg arg_new_constant(OptContext *ctx, uint64_t val) +{ + TCGType type =3D ctx->type; + TCGTemp *ts; + + if (type =3D=3D TCG_TYPE_I32) { + val =3D (int32_t)val; + } + + ts =3D tcg_constant_internal(type, val); + init_ts_info(ctx, ts); + + return temp_arg(ts); +} + static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg= src) { TCGTemp *dst_ts =3D arg_temp(dst); @@ -293,16 +308,8 @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op= , TCGArg dst, TCGArg src) static bool tcg_opt_gen_movi(OptContext *ctx, TCGOp *op, TCGArg dst, uint64_t val) { - TCGTemp *tv; - - if (ctx->type =3D=3D TCG_TYPE_I32) { - val =3D (int32_t)val; - } - /* Convert movi to mov with constant temp. */ - tv =3D tcg_constant_internal(ctx->type, val); - init_ts_info(ctx, tv); - return tcg_opt_gen_mov(ctx, op, dst, temp_arg(tv)); + return tcg_opt_gen_mov(ctx, op, dst, arg_new_constant(ctx, val)); } =20 static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y) @@ -1340,7 +1347,7 @@ static bool fold_deposit(OptContext *ctx, TCGOp *op) =20 op->opc =3D and_opc; op->args[1] =3D op->args[2]; - op->args[2] =3D temp_arg(tcg_constant_internal(ctx->type, mask)); + op->args[2] =3D arg_new_constant(ctx, mask); ctx->z_mask =3D mask & arg_info(op->args[1])->z_mask; return false; } @@ -1350,7 +1357,7 @@ static bool fold_deposit(OptContext *ctx, TCGOp *op) uint64_t mask =3D deposit64(-1, op->args[3], op->args[4], 0); =20 op->opc =3D and_opc; - op->args[2] =3D temp_arg(tcg_constant_internal(ctx->type, mask)); + op->args[2] =3D arg_new_constant(ctx, mask); ctx->z_mask =3D mask & arg_info(op->args[1])->z_mask; return false; } --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279418; cv=none; d=zohomail.com; s=zohoarc; b=eRf3vvjIk8hh3mfdMFp+guuqZG/cOKgno8e8xC7pXrjLfvjFnMVhIHjI/2LvEH64K79HOATfSGUsN6f67cRPD+e+ELdqmwPQfpjfxI2Eu324k6EZ3+8A2KgBXbLwP8i/aDjGugOkxi/wwmJskkmZXk/xh2GhnOMxmnFiHys4ihI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279418; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=yydutm4GC4YL//fMbFA0uGJAc/KbeYkkAz+lArCCg2s=; b=MKo89yelHOqL60SLYUtHcRcg3fQi9YLQ9OVrHClxOA9RnvpyW2WYU4AIHa+SrvHw4wejI/1zHIWbQisSj21e5bV2wuTJrmYyLHtyJaboXt838GwYthG4yL5FkDrxjsIsii3yqqKT+bTD+uPig9ydoTGxoxz5TXOqbfnDnTh7s5M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169827941886098.68295014491332; Wed, 25 Oct 2023 17:16:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo2o-00073d-Qp; Wed, 25 Oct 2023 20:16:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo2l-00070v-GE for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:12 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo2e-0004q9-Ur for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:11 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1cac925732fso2239585ad.1 for ; Wed, 25 Oct 2023 17:15:52 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.15.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:15:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279351; x=1698884151; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yydutm4GC4YL//fMbFA0uGJAc/KbeYkkAz+lArCCg2s=; b=OLg3jWhCXXwFU7UCxL9P47+pazgnuoxU71LfZg3C90HE5gRLV6FmAzYImSLdokK+wj mAb/k7W67B+g9kby74HQwhUg/1u5tHjJXfA9VRifEG3mKVu9DZ6WFQrh3jDJEdjt/PnX KBpyYCWhYM2yPeQL2eFIoaZ9lqXiooFCnmCX6CC9ylvojglEnWkrR3ScmwswRh01aWiW X/dCUdoikgwB/o++1uKFUEm/5DqEILz+3eD/6k5R4EZWtd+75oRJmUFbiS0uDdVDjLnn 37E14xEtdza6UDgGIqjIg/K31E886vmml3VMeZXZy9l3/3k0HtuiahN6VmooN1gu/ud+ nr2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279351; x=1698884151; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yydutm4GC4YL//fMbFA0uGJAc/KbeYkkAz+lArCCg2s=; b=pYLFN/ubecOq/9GykwC11W+TaLwd+CttkiXn1D68ncCLOuZoHEqK1kwjcW5XCpCGoD iQiO2mRr6mX+QcUq1WcMchWXwg7KJzSZRiJ0Bay0JHQpG67+G6jSuQOr0z3M+DTIUF78 +FwojKQWZFOLcpiAeeHgegeO4QXxgrPR8iIC+DGxjtJdJtEpHt2BRSB+j4Ck5DuMbhlm Sqh90RcDEj3s9vjaGq/1JnOwCY88hpM8os6VTeJ2w6/SEBzPq3QImI1Gm3jMdcOTdewb A4LdRongjmAdW1vM8ictUGlG+IBIPcOJUd1O2v+DifeB+0LqirqW4TYDgkB3E9cyFkHa E3Cw== X-Gm-Message-State: AOJu0Yzb82kwf2cCwaFphJcFxQtbZTitwJKzsmyZQSBfTaNZxI59w1n/ IyFLs3ND0n5gMk9SlrvRqFyJgCBEJhPGU9pJiGw= X-Google-Smtp-Source: AGHT+IFI8jKJRIH3V2MXC3tpYWbfuB4oMi3nFl7mXnTOX/fq6DqEBQyu9sPkNgHD8N/H0rOZ7BR2wg== X-Received: by 2002:a17:903:246:b0:1c5:bc83:557b with SMTP id j6-20020a170903024600b001c5bc83557bmr16248766plh.51.1698279351643; Wed, 25 Oct 2023 17:15:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 05/94] configs: Enable MTTCG for sparc, sparc64 Date: Wed, 25 Oct 2023 17:13:48 -0700 Message-Id: <20231026001542.1141412-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279419326100001 Content-Type: text/plain; charset="utf-8" This will be of small comfort to sparc64, because both sun4u and sun4v board models force max_cpus =3D 1. But it does enable actual smp for sparc32 sun4m. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- configs/targets/sparc-softmmu.mak | 1 + configs/targets/sparc64-softmmu.mak | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-soft= mmu.mak index 454eb35499..a5d9200382 100644 --- a/configs/targets/sparc-softmmu.mak +++ b/configs/targets/sparc-softmmu.mak @@ -1,2 +1,3 @@ TARGET_ARCH=3Dsparc TARGET_BIG_ENDIAN=3Dy +TARGET_SUPPORTS_MTTCG=3Dy diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-= softmmu.mak index d3f8a3b710..36ca64ec41 100644 --- a/configs/targets/sparc64-softmmu.mak +++ b/configs/targets/sparc64-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=3Dsparc64 TARGET_BASE_ARCH=3Dsparc TARGET_BIG_ENDIAN=3Dy +TARGET_SUPPORTS_MTTCG=3Dy --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279693; cv=none; d=zohomail.com; s=zohoarc; b=e9bDrHCMOaBfdu2HFmgyTuzjVaOVFNFy3FuZNHRENz9Xku9nJasmqtSlfoaEgIoshg9WIOODjFtAWpCWuiSYrQyfba9GpBKgXiDL22Z5DtiQZhK47JQYHm6JDUjhTu2YlfK0R9DjzEG9emUc4vkRCuuVVDhPmTIUJ5Oij+0hxRE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279693; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=/3tyPErdBidq6AacxwJD8cDdKu9xx4iNX0WzEVUzfVw=; b=E1hAer+071dLmm6WBFyR+p0LgC4fJeaLsxVkXHdcgkyYWwuCNmsxXyFVvOZsEITC6JvbEsasNLQu9865gGgslIldT00opsz+AQ4y59gLbBUgF9SSMTbPM+kgbtCfNYMCI00co7hOypowEp41cMQKlGVN5SD2t8rVehCucM9wDP0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698279693555653.5098076519806; Wed, 25 Oct 2023 17:21:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo2w-0007IG-Qp; Wed, 25 Oct 2023 20:16:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo2m-00071Q-Oq for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:12 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo2h-0004qp-MC for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:12 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1cbf47fa563so2273145ad.2 for ; Wed, 25 Oct 2023 17:15:55 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.15.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:15:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279354; x=1698884154; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=/3tyPErdBidq6AacxwJD8cDdKu9xx4iNX0WzEVUzfVw=; b=J/067aruZyZvE70TK3ULa+HzCEgXHUXIDP9t7r1Hk11grFDVYkUMT61W/P2yKRmMMG C7D+39SdPz+VoUQ5+Rz+Ubg4/P6c4UiHQ+QjAJji4lGsTyOi0aijQEr7bLUDuvOYLPIl 347IzrJaRkA1hGACsnLsr509sObYiSyckC2yTSl7kJ/babrjo18svpwaPibv+WR30DTn 3c8ruly7GABPlCeFip8H1qIenCIZzuKjZVcA2IpYrTL+hzk3TL5wYpi3y9Qqlg8Pxo5X PVW4a4m+QtRl7UP0xFSBTX39FMnUctuKiCJLh343+tnTk1b2Oy5w3L3AAvp6iGLVZcs3 KRLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279354; x=1698884154; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/3tyPErdBidq6AacxwJD8cDdKu9xx4iNX0WzEVUzfVw=; b=eTE7k5JzKOEZ9BdC+wB75h9ma8/ELVCK3cH+YM1rWUekXVA/HNtACocYXJ1tnsC2kZ QgHmo02VJppQU/uHPxwyWqNcFKCCRsqgEGihDmO1KwBadepgNqHutGefJByIBR+Iwv9w lyNhWgl+OpuKj4sLGyhIukZxswPdIUGdq+KRVDEH/2LjA+hi1tifAp6R9Zgrp7i0rKYn ccp0FagwSKR+3Era9aQDAGOM3Dv8VmYTM6BzTPB+GgpPY7N0hkGF4ucismwfYwmtkbDE U8PdDQ0gvmoVzFNTIgKouIQKDlQKLRJd5FJ4avJI1f6a9k8RUBPYe68FFTkqqzPNkCtu Mkjw== X-Gm-Message-State: AOJu0YwoWdtsCo+5fn6c/UEhr4dYD2Vw2s3IatcLjG6uYBHiot6BfV3n QFk3gzRzUkZufJl1Yu/z7dD2LDdJZWAH/qg/w7M= X-Google-Smtp-Source: AGHT+IH73VacN0HKtOd5jyyWinWoVMO8NThyjnQyzHpSnA+FU/g09XUq7dxsBfDdBpTdY/wYvwdemA== X-Received: by 2002:a17:903:1210:b0:1c5:d8a3:8789 with SMTP id l16-20020a170903121000b001c5d8a38789mr17803639plh.4.1698279354218; Wed, 25 Oct 2023 17:15:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 06/29] tcg/optimize: Handle TCG_COND_TST{EQ,NE} Date: Wed, 25 Oct 2023 17:13:51 -0700 Message-Id: <20231026001542.1141412-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279694155100003 Content-Type: text/plain; charset="utf-8" Fold constant comparisons. Canonicalize "tst x,x" to equality vs zero. Canonicalize "tst x,sign" to sign test vs zero. Fold double-word comparisons with zero parts. Fold setcond of "tst x,pow2" to a bit extract. Signed-off-by: Richard Henderson --- tcg/optimize.c | 225 ++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 205 insertions(+), 20 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 2f2d1c3001..27b1eaaa8d 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -508,9 +508,15 @@ static bool do_constant_folding_cond_32(uint32_t x, ui= nt32_t y, TCGCond c) return x <=3D y; case TCG_COND_GTU: return x > y; - default: - g_assert_not_reached(); + case TCG_COND_TSTEQ: + return (x & y) =3D=3D 0; + case TCG_COND_TSTNE: + return (x & y) !=3D 0; + case TCG_COND_ALWAYS: + case TCG_COND_NEVER: + break; } + g_assert_not_reached(); } =20 static bool do_constant_folding_cond_64(uint64_t x, uint64_t y, TCGCond c) @@ -536,12 +542,18 @@ static bool do_constant_folding_cond_64(uint64_t x, u= int64_t y, TCGCond c) return x <=3D y; case TCG_COND_GTU: return x > y; - default: - g_assert_not_reached(); + case TCG_COND_TSTEQ: + return (x & y) =3D=3D 0; + case TCG_COND_TSTNE: + return (x & y) !=3D 0; + case TCG_COND_ALWAYS: + case TCG_COND_NEVER: + break; } + g_assert_not_reached(); } =20 -static bool do_constant_folding_cond_eq(TCGCond c) +static int do_constant_folding_cond_eq(TCGCond c) { switch (c) { case TCG_COND_GT: @@ -556,9 +568,14 @@ static bool do_constant_folding_cond_eq(TCGCond c) case TCG_COND_LEU: case TCG_COND_EQ: return 1; - default: - g_assert_not_reached(); + case TCG_COND_TSTEQ: + case TCG_COND_TSTNE: + return -1; + case TCG_COND_ALWAYS: + case TCG_COND_NEVER: + break; } + g_assert_not_reached(); } =20 /* @@ -660,7 +677,27 @@ static int do_constant_folding_cond1(OptContext *ctx, = TCGArg dest, } =20 r =3D do_constant_folding_cond(ctx->type, *p1, *p2, cond); - return r; + if (r >=3D 0) { + return r; + } + if (!is_tst_cond(cond)) { + return -1; + } + + /* TSTNE x,x -> NE x,0 */ + if (args_are_copies(*p1, *p2)) { + *p2 =3D arg_new_constant(ctx, 0); + *pcond =3D tcg_tst_eqne_cond(cond); + return -1; + } + + /* TSTNE x,sign -> LT x,0 */ + if (arg_is_const_val(*p2, (ctx->type =3D=3D TCG_TYPE_I32 + ? INT32_MIN : INT64_MIN))) { + *p2 =3D arg_new_constant(ctx, 0); + *pcond =3D tcg_tst_ltge_cond(cond); + } + return -1; } =20 static int do_constant_folding_cond2(OptContext *ctx, TCGArg *args) @@ -668,6 +705,7 @@ static int do_constant_folding_cond2(OptContext *ctx, T= CGArg *args) TCGArg al, ah, bl, bh; TCGCond c; bool swap; + int r; =20 swap =3D swap_commutative2(args, args + 2); c =3D args[4]; @@ -689,8 +727,13 @@ static int do_constant_folding_cond2(OptContext *ctx, = TCGArg *args) tcg_target_ulong alv =3D arg_info(al)->val; tcg_target_ulong ahv =3D arg_info(ah)->val; uint64_t a =3D deposit64(alv, 32, 32, ahv); - return do_constant_folding_cond_64(a, b, c); + + r =3D do_constant_folding_cond_64(a, b, c); + if (r >=3D 0) { + return r; + } } + if (b =3D=3D 0) { switch (c) { case TCG_COND_LTU: @@ -701,9 +744,28 @@ static int do_constant_folding_cond2(OptContext *ctx, = TCGArg *args) break; } } + + /* TSTNE x,sign -> LT x,0 */ + if (b =3D=3D INT64_MIN && is_tst_cond(c)) { + /* bl must be 0, so copy that to bh */ + args[3] =3D bl; + args[4] =3D tcg_tst_ltge_cond(c); + return -1; + } } + if (args_are_copies(al, bl) && args_are_copies(ah, bh)) { - return do_constant_folding_cond_eq(c); + r =3D do_constant_folding_cond_eq(c); + if (r >=3D 0) { + return r; + } + + /* TSTNE x,x -> NE x,0 */ + if (is_tst_cond(c)) { + args[3] =3D args[2] =3D arg_new_constant(ctx, 0); + args[4] =3D tcg_tst_eqne_cond(c); + return -1; + } } return -1; } @@ -1151,17 +1213,30 @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op) case 0: goto do_brcond_const; case 1: - op->opc =3D INDEX_op_brcond_i32; - op->args[1] =3D op->args[2]; - op->args[2] =3D cond; - op->args[3] =3D label; - break; + goto do_brcond_low; + } + break; + + case TCG_COND_TSTEQ: + case TCG_COND_TSTNE: + if (arg_is_const_val(op->args[2], 0)) { + goto do_brcond_high; + } + if (arg_is_const_val(op->args[3], 0)) { + goto do_brcond_low; } break; =20 default: break; =20 + do_brcond_low: + op->opc =3D INDEX_op_brcond_i32; + op->args[1] =3D op->args[2]; + op->args[2] =3D cond; + op->args[3] =3D label; + break; + do_brcond_high: op->opc =3D INDEX_op_brcond_i32; op->args[0] =3D op->args[1]; @@ -1829,6 +1904,100 @@ static bool fold_remainder(OptContext *ctx, TCGOp *= op) return false; } =20 +static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg) +{ + TCGOpcode and_opc, sub_opc, xor_opc, neg_opc, shr_opc, uext_opc, sext_= opc; + TCGCond cond =3D op->args[3]; + TCGArg ret, src1, src2; + TCGOp *op2; + uint64_t val; + int sh; + bool inv; + + if (!is_tst_cond(cond) || !arg_is_const(op->args[2])) { + return; + } + + src2 =3D op->args[2]; + val =3D arg_info(src2)->val; + if (!is_power_of_2(val)) { + return; + } + + switch (ctx->type) { + case TCG_TYPE_I32: + and_opc =3D INDEX_op_and_i32; + sub_opc =3D INDEX_op_sub_i32; + xor_opc =3D INDEX_op_xor_i32; + shr_opc =3D INDEX_op_shr_i32; + neg_opc =3D TCG_TARGET_HAS_neg_i32 ? INDEX_op_neg_i32 : 0; + uext_opc =3D TCG_TARGET_HAS_extract_i32 ? INDEX_op_extract_i32 : 0; + sext_opc =3D TCG_TARGET_HAS_sextract_i32 ? INDEX_op_sextract_i32 := 0; + break; + case TCG_TYPE_I64: + and_opc =3D INDEX_op_and_i64; + sub_opc =3D INDEX_op_sub_i64; + xor_opc =3D INDEX_op_xor_i64; + shr_opc =3D INDEX_op_shr_i64; + neg_opc =3D TCG_TARGET_HAS_neg_i64 ? INDEX_op_neg_i64 : 0; + uext_opc =3D TCG_TARGET_HAS_extract_i64 ? INDEX_op_extract_i64 : 0; + sext_opc =3D TCG_TARGET_HAS_sextract_i64 ? INDEX_op_sextract_i64 := 0; + break; + default: + g_assert_not_reached(); + } + + sh =3D ctz64(val); + ret =3D op->args[0]; + src1 =3D op->args[1]; + inv =3D cond =3D=3D TCG_COND_TSTEQ; + + if (neg && !inv && sext_opc) { + op->opc =3D sext_opc; + op->args[1] =3D src1; + op->args[2] =3D sh; + op->args[3] =3D 1; + neg =3D false; + } else if (uext_opc) { + op->opc =3D uext_opc; + op->args[1] =3D src1; + op->args[2] =3D sh; + op->args[3] =3D 1; + } else { + if (sh) { + op2 =3D tcg_op_insert_before(ctx->tcg, op, shr_opc, 3); + op2->args[0] =3D ret; + op2->args[1] =3D src1; + op2->args[2] =3D arg_new_constant(ctx, sh); + src1 =3D ret; + } + op->opc =3D and_opc; + op->args[1] =3D src1; + op->args[2] =3D arg_new_constant(ctx, 1); + } + + if (neg && inv) { + op2 =3D tcg_op_insert_after(ctx->tcg, op, sub_opc, 3); + op2->args[0] =3D ret; + op2->args[1] =3D ret; + op2->args[2] =3D arg_new_constant(ctx, 1); + } else if (inv) { + op2 =3D tcg_op_insert_after(ctx->tcg, op, xor_opc, 3); + op2->args[0] =3D ret; + op2->args[1] =3D ret; + op2->args[2] =3D arg_new_constant(ctx, 1); + } else if (neg && neg_opc) { + op2 =3D tcg_op_insert_after(ctx->tcg, op, neg_opc, 2); + op2->args[0] =3D ret; + op2->args[1] =3D ret; + } else if (neg) { + op2 =3D tcg_op_insert_after(ctx->tcg, op, sub_opc, 3); + op2->args[0] =3D ret; + op2->args[1] =3D arg_new_constant(ctx, 0); + op2->args[2] =3D ret; + } +} + static bool fold_setcond(OptContext *ctx, TCGOp *op) { int i =3D do_constant_folding_cond1(ctx, op->args[0], &op->args[1], @@ -1836,6 +2005,7 @@ static bool fold_setcond(OptContext *ctx, TCGOp *op) if (i >=3D 0) { return tcg_opt_gen_movi(ctx, op, op->args[0], i); } + fold_setcond_tst_pow2(ctx, op, false); =20 ctx->z_mask =3D 1; ctx->s_mask =3D smask_from_zmask(1); @@ -1849,13 +2019,13 @@ static bool fold_negsetcond(OptContext *ctx, TCGOp = *op) if (i >=3D 0) { return tcg_opt_gen_movi(ctx, op, op->args[0], -i); } + fold_setcond_tst_pow2(ctx, op, true); =20 /* Value is {0,-1} so all bits are repetitions of the sign. */ ctx->s_mask =3D -1; return false; } =20 - static bool fold_setcond2(OptContext *ctx, TCGOp *op) { TCGCond cond; @@ -1903,21 +2073,36 @@ static bool fold_setcond2(OptContext *ctx, TCGOp *o= p) case 0: goto do_setcond_const; case 1: - op->args[2] =3D op->args[3]; - op->args[3] =3D cond; - op->opc =3D INDEX_op_setcond_i32; - break; + goto do_setcond_low; + } + break; + + case TCG_COND_TSTEQ: + case TCG_COND_TSTNE: + if (arg_is_const_val(op->args[2], 0)) { + goto do_setcond_high; + } + if (arg_is_const_val(op->args[4], 0)) { + goto do_setcond_low; } break; =20 default: break; =20 + do_setcond_low: + op->args[2] =3D op->args[3]; + op->args[3] =3D cond; + op->opc =3D INDEX_op_setcond_i32; + fold_setcond_tst_pow2(ctx, op, false); + break; + do_setcond_high: op->args[1] =3D op->args[2]; op->args[2] =3D op->args[4]; op->args[3] =3D cond; op->opc =3D INDEX_op_setcond_i32; + fold_setcond_tst_pow2(ctx, op, false); break; } =20 --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 32 +++++++++++++------------------- target/sparc/cpu-feature.h.inc | 19 +++++++++++++++++++ 2 files changed, 32 insertions(+), 19 deletions(-) create mode 100644 target/sparc/cpu-feature.h.inc diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 9fc5c401d2..aaecbf0876 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -291,25 +291,19 @@ struct sparc_def_t { uint32_t maxtl; }; =20 -#define CPU_FEATURE_FLOAT (1 << 0) -#define CPU_FEATURE_FLOAT128 (1 << 1) -#define CPU_FEATURE_SWAP (1 << 2) -#define CPU_FEATURE_MUL (1 << 3) -#define CPU_FEATURE_DIV (1 << 4) -#define CPU_FEATURE_FLUSH (1 << 5) -#define CPU_FEATURE_FSQRT (1 << 6) -#define CPU_FEATURE_FMUL (1 << 7) -#define CPU_FEATURE_VIS1 (1 << 8) -#define CPU_FEATURE_VIS2 (1 << 9) -#define CPU_FEATURE_FSMULD (1 << 10) -#define CPU_FEATURE_HYPV (1 << 11) -#define CPU_FEATURE_CMT (1 << 12) -#define CPU_FEATURE_GL (1 << 13) -#define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */ -#define CPU_FEATURE_ASR17 (1 << 15) -#define CPU_FEATURE_CACHE_CTRL (1 << 16) -#define CPU_FEATURE_POWERDOWN (1 << 17) -#define CPU_FEATURE_CASA (1 << 18) +#define FEATURE(X) CPU_FEATURE_BIT_##X, +enum { +#include "cpu-feature.h.inc" +}; + +#undef FEATURE +#define FEATURE(X) CPU_FEATURE_##X =3D 1u << CPU_FEATURE_BIT_##X, + +enum { +#include "cpu-feature.h.inc" +}; + +#undef FEATURE =20 #ifndef TARGET_SPARC64 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ diff --git a/target/sparc/cpu-feature.h.inc b/target/sparc/cpu-feature.h.inc new file mode 100644 index 0000000000..d35fe90c92 --- /dev/null +++ b/target/sparc/cpu-feature.h.inc @@ -0,0 +1,19 @@ +FEATURE(FLOAT) +FEATURE(FLOAT128) +FEATURE(SWAP) +FEATURE(MUL) +FEATURE(DIV) +FEATURE(FLUSH) +FEATURE(FSQRT) +FEATURE(FMUL) +FEATURE(VIS1) +FEATURE(VIS2) +FEATURE(FSMULD) +FEATURE(HYPV) +FEATURE(CMT) +FEATURE(GL) +FEATURE(TA0_SHUTDOWN) /* Shutdown on "ta 0x0" */ +FEATURE(ASR17) +FEATURE(CACHE_CTRL) +FEATURE(POWERDOWN) +FEATURE(CASA) --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279517; cv=none; d=zohomail.com; s=zohoarc; b=a/KPH4g0NwyLb1OSa+Gzz3JY3n4HFOCFaZ4DyrpD02hSpOgRj71AeO5tSz093/dD+pyp0lCWKIyYFVFabTjt5rmQwmgXT1y71bn9jbC0LX/H0rabXQL7VPWrGjg66mkqq7Y+OWyXbPHExjYZgSgcv6yZlspJt9fTjOoYiJ6meVk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279517; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=grrY6KBqyVlmw+Y1FqG6v+fB0Wl2pAJYFymCVdGaSh4=; b=Dfr/4FcIjEIYcA8zGPR0HKhgkz5CFVh4otiJIaYg+enSSt0LiqsT92ZWyHPEmzE8xsEnsaCBmz+7iygQOYVL2P9/aNPwxZmigmFprJQrDJOIZ5MzNeo6me/jmRGo8Ztdfa0oSTCrx1LsAxJIVJFfsH7UOTmwWiNZ1EDbtiMyQpc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698279517217461.80648420376883; Wed, 25 Oct 2023 17:18:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo2p-00074F-SS; Wed, 25 Oct 2023 20:16:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo2i-00070O-SZ for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:08 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo2g-0004qy-1q for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:08 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1c9b7c234a7so2302255ad.3 for ; Wed, 25 Oct 2023 17:15:57 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279517662100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-con-set.h | 4 +-- tcg/aarch64/tcg-target.c.inc | 58 +++++++++++++++++++++----------- 2 files changed, 41 insertions(+), 21 deletions(-) diff --git a/tcg/aarch64/tcg-target-con-set.h b/tcg/aarch64/tcg-target-con-= set.h index 3fdee26a3d..a927cd11a2 100644 --- a/tcg/aarch64/tcg-target-con-set.h +++ b/tcg/aarch64/tcg-target-con-set.h @@ -10,7 +10,7 @@ * tcg-target-con-str.h; the constraint combination is inclusive or. */ C_O0_I1(r) -C_O0_I2(r, rA) +C_O0_I2(r, rAL) C_O0_I2(rZ, r) C_O0_I2(w, r) C_O0_I3(rZ, rZ, r) @@ -31,6 +31,6 @@ C_O1_I2(w, w, wN) C_O1_I2(w, w, wO) C_O1_I2(w, w, wZ) C_O1_I3(w, w, w, w) -C_O1_I4(r, r, rA, rZ, rZ) +C_O1_I4(r, r, rAL, rZ, rZ) C_O2_I1(r, r, r) C_O2_I4(r, r, rZ, rZ, rA, rMZ) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index a3efa1e67a..2a748b3ee3 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -344,6 +344,9 @@ static const enum aarch64_cond_code tcg_cond_to_aarch64= [] =3D { [TCG_COND_GTU] =3D COND_HI, [TCG_COND_GEU] =3D COND_HS, [TCG_COND_LEU] =3D COND_LS, + /* bit test */ + [TCG_COND_TSTEQ] =3D COND_EQ, + [TCG_COND_TSTNE] =3D COND_NE, }; =20 typedef enum { @@ -1341,20 +1344,35 @@ static inline void tcg_out_dep(TCGContext *s, TCGTy= pe ext, TCGReg rd, tcg_out_bfm(s, ext, rd, rn, a, b); } =20 -static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg a, +static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGCond cond, TCGReg a, tcg_target_long b, bool const_b) { - if (const_b) { - /* Using CMP or CMN aliases. */ - if (b >=3D 0) { - tcg_out_insn(s, 3401, SUBSI, ext, TCG_REG_XZR, a, b); - } else { - tcg_out_insn(s, 3401, ADDSI, ext, TCG_REG_XZR, a, -b); + if (is_tst_cond(cond)) { + if (const_b) { + if (is_limm(b)) { + tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, a, b); + return; + } + tcg_out_movi(s, ext, TCG_REG_TMP0, b); + b =3D TCG_REG_TMP0; } - } else { - /* Using CMP alias SUBS wzr, Wn, Wm */ - tcg_out_insn(s, 3502, SUBS, ext, TCG_REG_XZR, a, b); + tcg_out_insn(s, 3510, ANDS, ext, TCG_REG_XZR, a, b); + return; } + + if (const_b) { + if (is_aimm(b)) { + tcg_out_insn(s, 3401, SUBSI, ext, TCG_REG_XZR, a, b); + return; + } + if (is_aimm(-b)) { + tcg_out_insn(s, 3401, ADDSI, ext, TCG_REG_XZR, a, -b); + return; + } + tcg_out_movi(s, ext, TCG_REG_TMP0, b); + b =3D TCG_REG_TMP0; + } + tcg_out_insn(s, 3502, SUBS, ext, TCG_REG_XZR, a, b); } =20 static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) @@ -1401,7 +1419,7 @@ static void tcg_out_brcond(TCGContext *s, TCGType ext= , TCGCond c, TCGArg a, need_cmp =3D false; } else { need_cmp =3D true; - tcg_out_cmp(s, ext, a, b, b_const); + tcg_out_cmp(s, ext, c, a, b, b_const); } =20 if (!l->has_value) { @@ -1574,7 +1592,7 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, = TCGReg d, } else { AArch64Insn sel =3D I3506_CSEL; =20 - tcg_out_cmp(s, ext, a0, 0, 1); + tcg_out_cmp(s, ext, TCG_COND_NE, a0, 0, 1); tcg_out_insn(s, 3507, CLZ, ext, TCG_REG_TMP0, a1); =20 if (const_b) { @@ -1719,7 +1737,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, addr_adj, compare_mask); =20 /* Perform the address comparison. */ - tcg_out_cmp(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, 0); + tcg_out_cmp(s, addr_type, TCG_COND_NE, TCG_REG_TMP0, TCG_REG_TMP2,= 0); =20 /* If not equal, we jump to the slow path. */ ldst->label_ptr[0] =3D s->code_ptr; @@ -2275,7 +2293,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, a2 =3D (int32_t)a2; /* FALLTHRU */ case INDEX_op_setcond_i64: - tcg_out_cmp(s, ext, a1, a2, c2); + tcg_out_cmp(s, ext, args[3], a1, a2, c2); /* Use CSET alias of CSINC Wd, WZR, WZR, invert(cond). */ tcg_out_insn(s, 3506, CSINC, TCG_TYPE_I32, a0, TCG_REG_XZR, TCG_REG_XZR, tcg_invert_cond(args[3])); @@ -2285,7 +2303,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, a2 =3D (int32_t)a2; /* FALLTHRU */ case INDEX_op_negsetcond_i64: - tcg_out_cmp(s, ext, a1, a2, c2); + tcg_out_cmp(s, ext, args[3], a1, a2, c2); /* Use CSETM alias of CSINV Wd, WZR, WZR, invert(cond). */ tcg_out_insn(s, 3506, CSINV, ext, a0, TCG_REG_XZR, TCG_REG_XZR, tcg_invert_cond(args[3])); @@ -2295,7 +2313,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, a2 =3D (int32_t)a2; /* FALLTHRU */ case INDEX_op_movcond_i64: - tcg_out_cmp(s, ext, a1, a2, c2); + tcg_out_cmp(s, ext, args[5], a1, a2, c2); tcg_out_insn(s, 3506, CSEL, ext, a0, REG0(3), REG0(4), args[5]); break; =20 @@ -2895,11 +2913,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) case INDEX_op_add_i64: case INDEX_op_sub_i32: case INDEX_op_sub_i64: + return C_O1_I2(r, r, rA); + case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: case INDEX_op_negsetcond_i32: case INDEX_op_negsetcond_i64: - return C_O1_I2(r, r, rA); + return C_O1_I2(r, r, rAL); =20 case INDEX_op_mul_i32: case INDEX_op_mul_i64: @@ -2949,11 +2969,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return C_O0_I2(r, rA); + return C_O0_I2(r, rAL); =20 case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return C_O1_I4(r, r, rA, rZ, rZ); + return C_O1_I4(r, r, rAL, rZ, rZ); =20 case INDEX_op_qemu_ld_a32_i32: case INDEX_op_qemu_ld_a64_i32: --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279950; cv=none; d=zohomail.com; s=zohoarc; b=WdTm5kcS52eh3O1AQgBZbKrJPXcLw6TVlvfHDNAfcf/DycyvJz01AVc5cKaBrdmpMmJalW8oKE3fOCzMBJM/5r0upRmNBLouu2GTtxf/3K8xI6bruTDlLKzfgBRCWRqjsYmtT8jMDvJnj2Pj9/haq3xg/DWVNoFB7tNKI5ajKc8= ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:15:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279355; x=1698884155; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=clLDX0OMwpp8pXeARARKHNXdrMJ0cLB2t4O0gfCmBGk=; b=o7XB5SmbbyNIB7uzCnNjuJC8J8yBhT8kWM+1kLRFygp64p/7I8IBi6NX34pE1UQT/M XoU9r933vcDSCvgtEVBh4xs0YSd4K1yq2SenowVixy6CO6HALD2hIZ62hP+jetKqTaLq mZrQui1VkWVOGGWtbpXocc9GKdBpZLkDriNSO29eECwEfM7OHxeOhmls5eqM1lnMpYlm Hjd8o7ArITIYhPZ8nUqJgFXRHzBgsqMbpTK/KokkHow9E7bzyRpYqTAwLqSd+F9hjDkZ lIDfEeNZVoIYJ5p5eQZ4bB3Ceb6ENQLjJp68dYpN4+B71R/WwRzSuZAFtuV8pO66IKuc 1Zpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279355; x=1698884155; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=clLDX0OMwpp8pXeARARKHNXdrMJ0cLB2t4O0gfCmBGk=; b=p9DE3df8As2ruPvmlwr9+qdE2KLsmpI+XJ5De7t0nCvDaYq1TfR5t96yQ8TrDcxOdJ UMlJTIk1iqHSu0HnZQbaJodUoYJzjetnvbHPtuem/OVRYQnwfTCK7utNkjFTjBgR6oJY uzKAzoYQHbIiN7nANGBV8cHoqZgPSTjf6YYJIklKiouEx/75ny0+0Y2PPrfCRDEFxWk3 dTH+iGWtUefX9dvr6Rp6pIAIYYio6IYqfvwt2+62MEPvkWhaoa95kHK7GTD5JI4KrX9n ie3SYRyyeQzTxU3j16vWPt0ylh+WwOrLYU39JuIlEhF0ugOQjLFn+QFgQuennyawRUyu +0FA== X-Gm-Message-State: AOJu0YwrQEe2toET8zvv31vWbEPr+kR1yT9/5ehWeeS7TPV6xuK7iz5s LCesnKqkhq4aJ+g608KOdF433Dn6iAGL6EfY36I= X-Google-Smtp-Source: AGHT+IEMRv3T2JV6zhCZkGyRad8wd6IgWAcIjF4rfVEaLCno7xFzxhmpevrkLmuNJTKQs1iZwn43aQ== X-Received: by 2002:a17:902:ef8e:b0:1c7:2697:ec0a with SMTP id iz14-20020a170902ef8e00b001c72697ec0amr16853834plb.30.1698279355212; Wed, 25 Oct 2023 17:15:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 07/94] target/sparc: Use CPU_FEATURE_BIT_* for cpu properties Date: Wed, 25 Oct 2023 17:13:52 -0700 Message-Id: <20231026001542.1141412-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279950958100003 Content-Type: text/plain; charset="utf-8" Use symbols not integer constants for the bit positions. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/cpu.c | 72 ++++++++++++++++++++++++++++------------------ 1 file changed, 44 insertions(+), 28 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 8ba96ae225..330b7bead3 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -545,21 +545,22 @@ static const sparc_def_t sparc_defs[] =3D { #endif }; =20 +/* This must match sparc_cpu_properties[]. */ static const char * const feature_name[] =3D { - "float", - "float128", - "swap", - "mul", - "div", - "flush", - "fsqrt", - "fmul", - "vis1", - "vis2", - "fsmuld", - "hypv", - "cmt", - "gl", + [CPU_FEATURE_BIT_FLOAT] =3D "float", + [CPU_FEATURE_BIT_FLOAT128] =3D "float128", + [CPU_FEATURE_BIT_SWAP] =3D "swap", + [CPU_FEATURE_BIT_MUL] =3D "mul", + [CPU_FEATURE_BIT_DIV] =3D "div", + [CPU_FEATURE_BIT_FLUSH] =3D "flush", + [CPU_FEATURE_BIT_FSQRT] =3D "fsqrt", + [CPU_FEATURE_BIT_FMUL] =3D "fmul", + [CPU_FEATURE_BIT_VIS1] =3D "vis1", + [CPU_FEATURE_BIT_VIS2] =3D "vis2", + [CPU_FEATURE_BIT_FSMULD] =3D "fsmuld", + [CPU_FEATURE_BIT_HYPV] =3D "hypv", + [CPU_FEATURE_BIT_CMT] =3D "cmt", + [CPU_FEATURE_BIT_GL] =3D "gl", }; =20 static void print_features(uint32_t features, const char *prefix) @@ -835,21 +836,36 @@ static PropertyInfo qdev_prop_nwindows =3D { .set =3D sparc_set_nwindows, }; =20 +/* This must match feature_name[]. */ static Property sparc_cpu_properties[] =3D { - DEFINE_PROP_BIT("float", SPARCCPU, env.def.features, 0, false), - DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features, 1, false), - DEFINE_PROP_BIT("swap", SPARCCPU, env.def.features, 2, false), - DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, 3, false), - DEFINE_PROP_BIT("div", SPARCCPU, env.def.features, 4, false), - DEFINE_PROP_BIT("flush", SPARCCPU, env.def.features, 5, false), - DEFINE_PROP_BIT("fsqrt", SPARCCPU, env.def.features, 6, false), - DEFINE_PROP_BIT("fmul", SPARCCPU, env.def.features, 7, false), - DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features, 8, false), - DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features, 9, false), - DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features, 10, false), - DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features, 11, false), - DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features, 12, false), - DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features, 13, false), + DEFINE_PROP_BIT("float", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_FLOAT, false), + DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_FLOAT128, false), + DEFINE_PROP_BIT("swap", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_SWAP, false), + DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_MUL, false), + DEFINE_PROP_BIT("div", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_DIV, false), + DEFINE_PROP_BIT("flush", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_FLUSH, false), + DEFINE_PROP_BIT("fsqrt", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_FSQRT, false), + DEFINE_PROP_BIT("fmul", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_FMUL, false), + DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_VIS1, false), + DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_VIS2, false), + DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_FSMULD, false), + DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_HYPV, false), + DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_CMT, false), + DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_GL, false), DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0, qdev_prop_uint64, target_ulong), DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0), --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.15.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:15:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279357; x=1698884157; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TM/KRrd2eN3gH2XezGt/xyNTAB3pmf+w8+Xiugmh0j8=; b=bnZ+K/HU2vyv/jXoCms993r3lAslmTpDa61ludEN3Je88fislNbytASVpeFynI+ZhY R71qppsYXL/vwGBfHp1VF2GV7Zryg4k5fniXK2uvFn8Sxyqr6WK68zs0KIVHingxA5nZ rP7GZxyg/9wEzxNnGwOblMNB9ivLdOCsb+MxRfy82ggcGYQ76KLD7yGAk3RGCQtyjmy9 5QaxTAjy7is1HCDD9LviSC8gCD500pggbCxeL/IW5ofUhaBz2zZIGv/MXErijn5Tu6n1 ektd99NVVrxp4X5mslelI+jYYq05gtCW/rnrhfyQgBnKk2FSkLL+pJhVKBlxSaLI9jpO BZ4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279357; x=1698884157; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TM/KRrd2eN3gH2XezGt/xyNTAB3pmf+w8+Xiugmh0j8=; b=WgSZcHMmpcICD+fAMIwKqcf21NJSz+UjkjFiKAM4PulmYmQDg+Qtp9QONlw3O8ejzQ M8sYOw3ItIelL3gh32D3KqQbr9hW/DavmZDEC0t2TndKsPm17fgtZ7vSdLHq8KFoJh5X e7x77A/yaLJZ73RAuIDfrATvQrsTZ8iEYoiPdaklN+V0CbTkvMbqgBxuJDDd8ynRqWpO sSEVWwVCHEbV7I+K90dicNZ2alkTCcrFXcA71fzPCowC9gPc/s4Fzc43UoEgJlqoT1Oz KlvvsJTLr8Dwj+QB0240opG08XC+FocOxkprVcqchlOQ/3m1YGgefhyprUNkfXcZbO0s Qy5w== X-Gm-Message-State: AOJu0Yx95ENYag07Em5ensunowlOIyH3I7N07qQ4a2yPy7C9Ni483bSM 9d8IK2n3w3c60lGXO3DZUgBiovS945hdfaaIsCA= X-Google-Smtp-Source: AGHT+IGhptrmxvre5L7xlygyulNw9b4isrZK76fFkFtDu/BdCrrAs0Q3oSfYGK/F05mgWMLz6vsXMA== X-Received: by 2002:a17:902:da83:b0:1c7:4973:7b34 with SMTP id j3-20020a170902da8300b001c749737b34mr16822669plx.50.1698279357577; Wed, 25 Oct 2023 17:15:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 08/29] tcg/aarch64: Generate TBZ, TBNZ Date: Wed, 25 Oct 2023 17:13:55 -0700 Message-Id: <20231026001542.1141412-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279471494100011 Content-Type: text/plain; charset="utf-8" Test the sign bit for LT/GE vs 0, and TSTNE/EQ vs a power of 2. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 100 ++++++++++++++++++++++++++++------- 1 file changed, 81 insertions(+), 19 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 2a748b3ee3..e65fc415d2 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -105,6 +105,18 @@ static bool reloc_pc19(tcg_insn_unit *src_rw, const tc= g_insn_unit *target) return false; } =20 +static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target) +{ + const tcg_insn_unit *src_rx =3D tcg_splitwx_to_rx(src_rw); + ptrdiff_t offset =3D target - src_rx; + + if (offset =3D=3D sextract64(offset, 0, 14)) { + *src_rw =3D deposit32(*src_rw, 5, 14, offset); + return true; + } + return false; +} + static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { @@ -115,6 +127,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int ty= pe, return reloc_pc26(code_ptr, (const tcg_insn_unit *)value); case R_AARCH64_CONDBR19: return reloc_pc19(code_ptr, (const tcg_insn_unit *)value); + case R_AARCH64_TSTBR14: + return reloc_pc14(code_ptr, (const tcg_insn_unit *)value); default: g_assert_not_reached(); } @@ -369,6 +383,10 @@ typedef enum { /* Conditional branch (immediate). */ I3202_B_C =3D 0x54000000, =20 + /* Test and branch (immediate). */ + I3205_TBZ =3D 0x36000000, + I3205_TBNZ =3D 0x37000000, + /* Unconditional branch (immediate). */ I3206_B =3D 0x14000000, I3206_BL =3D 0x94000000, @@ -649,6 +667,14 @@ static void tcg_out_insn_3202(TCGContext *s, AArch64In= sn insn, tcg_out32(s, insn | tcg_cond_to_aarch64[c] | (imm19 & 0x7ffff) << 5); } =20 +static void tcg_out_insn_3205(TCGContext *s, AArch64Insn insn, + TCGReg rt, int imm6, int imm14) +{ + insn |=3D (imm6 & 0x20) << (31 - 5); + insn |=3D (imm6 & 0x1f) << 19; + tcg_out32(s, insn | (imm14 & 0x3fff) << 5 | rt); +} + static void tcg_out_insn_3206(TCGContext *s, AArch64Insn insn, int imm26) { tcg_out32(s, insn | (imm26 & 0x03ffffff)); @@ -1412,30 +1438,66 @@ static inline void tcg_out_goto_label(TCGContext *s= , TCGLabel *l) static void tcg_out_brcond(TCGContext *s, TCGType ext, TCGCond c, TCGArg a, TCGArg b, bool b_const, TCGLabel *l) { - intptr_t offset; - bool need_cmp; + int tbit =3D -1; + bool need_cmp =3D true; =20 - if (b_const && b =3D=3D 0 && (c =3D=3D TCG_COND_EQ || c =3D=3D TCG_CON= D_NE)) { - need_cmp =3D false; - } else { - need_cmp =3D true; - tcg_out_cmp(s, ext, c, a, b, b_const); - } - - if (!l->has_value) { - tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0); - offset =3D tcg_in32(s) >> 5; - } else { - offset =3D tcg_pcrel_diff(s, l->u.value_ptr) >> 2; - tcg_debug_assert(offset =3D=3D sextract64(offset, 0, 19)); + switch (c) { + case TCG_COND_EQ: + case TCG_COND_NE: + if (b_const && b =3D=3D 0) { + need_cmp =3D false; + } + break; + case TCG_COND_LT: + case TCG_COND_GE: + if (b_const && b =3D=3D 0) { + c =3D (c =3D=3D TCG_COND_LT ? TCG_COND_TSTNE : TCG_COND_TSTEQ); + tbit =3D ext ? 63 : 31; + need_cmp =3D false; + } + break; + case TCG_COND_TSTEQ: + case TCG_COND_TSTNE: + if (b_const && is_power_of_2(b)) { + tbit =3D ctz64(b); + need_cmp =3D false; + } + break; + default: + break; } =20 if (need_cmp) { - tcg_out_insn(s, 3202, B_C, c, offset); - } else if (c =3D=3D TCG_COND_EQ) { - tcg_out_insn(s, 3201, CBZ, ext, a, offset); + tcg_out_cmp(s, ext, c, a, b, b_const); + tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0); + tcg_out_insn(s, 3202, B_C, c, 0); + return; + } + + if (tbit >=3D 0) { + tcg_out_reloc(s, s->code_ptr, R_AARCH64_TSTBR14, l, 0); + switch (c) { + case TCG_COND_TSTEQ: + tcg_out_insn(s, 3205, TBZ, a, tbit, 0); + break; + case TCG_COND_TSTNE: + tcg_out_insn(s, 3205, TBNZ, a, tbit, 0); + break; + default: + g_assert_not_reached(); + } } else { - tcg_out_insn(s, 3201, CBNZ, ext, a, offset); + tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0); + switch (c) { + case TCG_COND_EQ: + tcg_out_insn(s, 3201, CBZ, ext, a, 0); + break; + case TCG_COND_NE: + tcg_out_insn(s, 3201, CBNZ, ext, a, 0); + break; + default: + g_assert_not_reached(); + } } } =20 --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279518; cv=none; d=zohomail.com; s=zohoarc; b=AyhsDy+TCHZ8I79n77FTXBCNiVM3dU22gjkpBNQE7SDfihXjGNqroOMSvU9ptjcQlyCp8a25uy5MuYYhACvLVGlNp17fTyvfySlkpLsUTp2t3lpppmKJt4kpvUXAEz8403rF1jVgJsuDGcOwrV384GWp0IzjV0DbrB7REPRt6RU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279518; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=imDgEUum8PsXbQ/+Z4HhrVdRHwLKWjtXZ1f2ZH8WSQs=; b=IWCHcBg7zHX5J0miv7OlstZXf2udLnhTOhTezz4lzEyOxZOMHyuDUCQzpz8SNigbBtrzia/hp+vOoi53jL60wWfyqEOZZ0zFDo69HnMPBRm4kvf5fI/6obWjw9UviJlFNs9GTWzGxZiioSPkVxyNS0o/kw0CZnoCoz8LTSM5/Kc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698279518858211.24570486464245; Wed, 25 Oct 2023 17:18:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo3B-0007QF-Qb; Wed, 25 Oct 2023 20:16:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo2w-0007HJ-BB for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:22 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo2h-0004r1-LK for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:22 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1ca3a54d2c4so2278555ad.3 for ; Wed, 25 Oct 2023 17:15:57 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.15.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:15:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279357; x=1698884157; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=imDgEUum8PsXbQ/+Z4HhrVdRHwLKWjtXZ1f2ZH8WSQs=; b=Egqdm0bh4dL6SOd/hGqa0G5CSoXKcOibxWz3AAwEsvYBop9dig3Xj7obDkrM0UezXV t57TGEOZmuvI54YJGthF6CUKB8GydZtkjVxiKEsRO8ANrMG/dy6qQy691ib9RxF+R23l 69vf+AJzYG+OzUYWqNGYBv8Py8zvNoSttyNmqfBdsEXP52VxvVdo6EhN3asi01bX2Idh MejvYiEMZOrU5xw9zbm1MSBC0rR6qjUq6IPVoM73xaLzOVNkCgDXTx/zI7u0PB0Fib5T LEmdlKPa9rN+eyNHb8xuUvi8Tyi4ox4g4z3aVTCWbSX5sOgpuB54GToa0tGjMsCAusSy ljDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279357; x=1698884157; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=imDgEUum8PsXbQ/+Z4HhrVdRHwLKWjtXZ1f2ZH8WSQs=; b=MRu+0vVacmSa4vox4oL7U1/fAXTWif0dKTxNrIv6uueVWXnG/bMP5h5th6TpwGH21s EsDFVd+6p8FCMOYJ6yoryKTmykjdlX169jkz9BMNIsSuu0z4AlYSRVev5OkIfvA7O0Oh DAdZ6G3JHXqlbHgsv/7deOCLqPvG31y3FR59xpst0cFlL1lHHmQ8vMN8bEAXC/wPDS5e kPMgLLjeRBD+JsuUbVGOrf0CCcQTAFPUM9Yaw7GNcJPMu/wpM7b2SG92+lQaYjMh1EUk CWn2YWrG1x7XtsWNNQ2VBt6D1QMeWVrIPZVipMoLSp5sWNjbR/FTlmXbElaz5kp6pAi3 HhIQ== X-Gm-Message-State: AOJu0YxgaxtbHwtA3U9wcVnIEygitlaWQgqKexVDTS1MsptbPhHFtZxM M66OW6ttMnEb6XcYxHsEIknUU/I4+ZUDXT1AQ70= X-Google-Smtp-Source: AGHT+IEJPYD1A8tHzIDEQ487Mrm1qYMnSKiiSDgt+9TEXniTeCdgKupuKdYrO133CNTR6lgyV8Q+LQ== X-Received: by 2002:a17:902:ea0e:b0:1c3:6d97:e89e with SMTP id s14-20020a170902ea0e00b001c36d97e89emr17428302plg.58.1698279356782; Wed, 25 Oct 2023 17:15:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 08/94] target/sparc: Remove sparcv7 cpu features Date: Wed, 25 Oct 2023 17:13:54 -0700 Message-Id: <20231026001542.1141412-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279519648100005 Content-Type: text/plain; charset="utf-8" The oldest supported cpu is the microsparc 1; all other cpus use CPU_DEFAULT_FEATURES. Remove the features that must always be present for sparcv7: FLOAT, SWAP, FLUSH, FSQRT, FMUL. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- linux-user/sparc/target_syscall.h | 6 +----- target/sparc/cpu.h | 21 +++++++-------------- target/sparc/cpu-feature.h.inc | 5 ----- target/sparc/cpu.c | 24 +++--------------------- target/sparc/translate.c | 12 ------------ 5 files changed, 11 insertions(+), 57 deletions(-) diff --git a/linux-user/sparc/target_syscall.h b/linux-user/sparc/target_sy= scall.h index be77e44eb8..e421165357 100644 --- a/linux-user/sparc/target_syscall.h +++ b/linux-user/sparc/target_syscall.h @@ -50,11 +50,7 @@ static inline abi_ulong target_shmlba(CPUSPARCState *env) #ifdef TARGET_SPARC64 return MAX(TARGET_PAGE_SIZE, 16 * 1024); #else - if (!(env->def.features & CPU_FEATURE_FLUSH)) { - return 64 * 1024; - } else { - return 256 * 1024; - } + return 256 * 1024; #endif } =20 diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index aaecbf0876..758a4e8aaa 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -306,17 +306,12 @@ enum { #undef FEATURE =20 #ifndef TARGET_SPARC64 -#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ - CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ - CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ - CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD) +#define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ + CPU_FEATURE_FSMULD) #else -#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ - CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ - CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ - CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \ - CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \ - CPU_FEATURE_CASA) +#define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ + CPU_FEATURE_FSMULD | CPU_FEATURE_CASA | \ + CPU_FEATURE_VIS1 | CPU_FEATURE_VIS2) enum { mmu_us_12, // Ultrasparc < III (64 entry TLB) mmu_us_3, // Ultrasparc III (512 entry TLB) @@ -799,14 +794,12 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState= *env, vaddr *pc, if (env->pstate & PS_AM) { flags |=3D TB_FLAG_AM_ENABLED; } - if ((env->def.features & CPU_FEATURE_FLOAT) - && (env->pstate & PS_PEF) - && (env->fprs & FPRS_FEF)) { + if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { flags |=3D TB_FLAG_FPU_ENABLED; } flags |=3D env->asi << TB_FLAG_ASI_SHIFT; #else - if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) { + if (env->psref) { flags |=3D TB_FLAG_FPU_ENABLED; } #endif diff --git a/target/sparc/cpu-feature.h.inc b/target/sparc/cpu-feature.h.inc index d35fe90c92..d800f18c4e 100644 --- a/target/sparc/cpu-feature.h.inc +++ b/target/sparc/cpu-feature.h.inc @@ -1,11 +1,6 @@ -FEATURE(FLOAT) FEATURE(FLOAT128) -FEATURE(SWAP) FEATURE(MUL) FEATURE(DIV) -FEATURE(FLUSH) -FEATURE(FSQRT) -FEATURE(FMUL) FEATURE(VIS1) FEATURE(VIS2) FEATURE(FSMULD) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 330b7bead3..f527244aa4 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -403,9 +403,7 @@ static const sparc_def_t sparc_defs[] =3D { .mmu_sfsr_mask =3D 0x00016fff, .mmu_trcr_mask =3D 0x0000003f, .nwindows =3D 7, - .features =3D CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_M= UL | - CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | - CPU_FEATURE_FMUL, + .features =3D CPU_FEATURE_MUL | CPU_FEATURE_DIV, }, { .name =3D "TI MicroSparc II", @@ -547,14 +545,9 @@ static const sparc_def_t sparc_defs[] =3D { =20 /* This must match sparc_cpu_properties[]. */ static const char * const feature_name[] =3D { - [CPU_FEATURE_BIT_FLOAT] =3D "float", [CPU_FEATURE_BIT_FLOAT128] =3D "float128", - [CPU_FEATURE_BIT_SWAP] =3D "swap", [CPU_FEATURE_BIT_MUL] =3D "mul", [CPU_FEATURE_BIT_DIV] =3D "div", - [CPU_FEATURE_BIT_FLUSH] =3D "flush", - [CPU_FEATURE_BIT_FSQRT] =3D "fsqrt", - [CPU_FEATURE_BIT_FMUL] =3D "fmul", [CPU_FEATURE_BIT_VIS1] =3D "vis1", [CPU_FEATURE_BIT_VIS2] =3D "vis2", [CPU_FEATURE_BIT_FSMULD] =3D "fsmuld", @@ -758,9 +751,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error= **errp) CPUSPARCState *env =3D &cpu->env; =20 #if defined(CONFIG_USER_ONLY) - if ((env->def.features & CPU_FEATURE_FLOAT)) { - env->def.features |=3D CPU_FEATURE_FLOAT128; - } + /* We are emulating the kernel, which will trap and emulate float128. = */ + env->def.features |=3D CPU_FEATURE_FLOAT128; #endif =20 env->version =3D env->def.iu_version; @@ -838,22 +830,12 @@ static PropertyInfo qdev_prop_nwindows =3D { =20 /* This must match feature_name[]. */ static Property sparc_cpu_properties[] =3D { - DEFINE_PROP_BIT("float", SPARCCPU, env.def.features, - CPU_FEATURE_BIT_FLOAT, false), DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features, CPU_FEATURE_BIT_FLOAT128, false), - DEFINE_PROP_BIT("swap", SPARCCPU, env.def.features, - CPU_FEATURE_BIT_SWAP, false), DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, CPU_FEATURE_BIT_MUL, false), DEFINE_PROP_BIT("div", SPARCCPU, env.def.features, CPU_FEATURE_BIT_DIV, false), - DEFINE_PROP_BIT("flush", SPARCCPU, env.def.features, - CPU_FEATURE_BIT_FLUSH, false), - DEFINE_PROP_BIT("fsqrt", SPARCCPU, env.def.features, - CPU_FEATURE_BIT_FSQRT, false), - DEFINE_PROP_BIT("fmul", SPARCCPU, env.def.features, - CPU_FEATURE_BIT_FMUL, false), DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features, CPU_FEATURE_BIT_VIS1, false), DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features, diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 8f6fd453e7..cab9f13421 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -3527,11 +3527,9 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss); break; case 0x29: /* fsqrts */ - CHECK_FPU_FEATURE(dc, FSQRT); gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts); break; case 0x2a: /* fsqrtd */ - CHECK_FPU_FEATURE(dc, FSQRT); gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd); break; case 0x2b: /* fsqrtq */ @@ -3559,16 +3557,13 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq); break; case 0x49: /* fmuls */ - CHECK_FPU_FEATURE(dc, FMUL); gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls); break; case 0x4a: /* fmuld */ - CHECK_FPU_FEATURE(dc, FMUL); gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld); break; case 0x4b: /* fmulq */ CHECK_FPU_FEATURE(dc, FLOAT128); - CHECK_FPU_FEATURE(dc, FMUL); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq); break; case 0x4d: /* fdivs */ @@ -5105,8 +5100,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) goto jmp_insn; #endif case 0x3b: /* flush */ - if (!((dc)->def->features & CPU_FEATURE_FLUSH)) - goto unimp_flush; /* nop */ break; case 0x3c: /* save */ @@ -5224,7 +5217,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) break; case 0x0f: /* swap, swap register with memory. Also atomically */ - CHECK_IU_FEATURE(dc, SWAP); cpu_src1 =3D gen_load_gpr(dc, rd); gen_swap(dc, cpu_val, cpu_src1, cpu_addr, dc->mem_idx, MO_TEUL); @@ -5256,7 +5248,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) break; case 0x1f: /* swapa, swap reg with alt. memory. Also atomically */ - CHECK_IU_FEATURE(dc, SWAP); cpu_src1 =3D gen_load_gpr(dc, rd); gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn); break; @@ -5578,9 +5569,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) illegal_insn: gen_exception(dc, TT_ILL_INSN); return; - unimp_flush: - gen_exception(dc, TT_UNIMP_FLUSH); - return; #if !defined(CONFIG_USER_ONLY) priv_insn: gen_exception(dc, TT_PRIV_INSN); --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279799; cv=none; d=zohomail.com; s=zohoarc; b=TzkUXQVg6MDcCnf/YOfmBBxJp2THF28aQ3xt3+Jzp9FkcaOFyEbzOYb+zP/nbQI9ybqGinvRAdoa/KrwRC8+FFMzo7W4txBwH3m+hbhGTpRIOr0+Qtn9jov7BzdYNmPWZ2ooyX2lW3S4H53iN8g4GYh22ADiL7PKPa/zZiMsAmc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279799; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=iO7a+DcsBv1QUswJrwtg846br5OcYCcDIc2AiP9uJP0=; b=JOQEO1SzQAy1nXnYNnaMsqViTuqA/w/M5BKxz8/9DOfgZsfsjdPk6RGT97S4lNBS6Nc3k/gkGev/cpT6zz+wu7R1Lk2F+UsLiBjytN0jizL0ns40ThCFrEvV1XSaM0SZYpvvqQpvbbOlOKNb1qrQysdMq+8VPz/VmlwHt6AUXHA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169827979934099.4836260140089; Wed, 25 Oct 2023 17:23:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo2r-00076j-Lp; Wed, 25 Oct 2023 20:16:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo2m-00071R-PJ for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:12 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo2h-0004rF-LV for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:12 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1caa7597af9so2154635ad.1 for ; Wed, 25 Oct 2023 17:15:59 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279800578100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 59 ++++++++++++++++++++++++++++++---------- 1 file changed, 44 insertions(+), 15 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index fc78566494..344143cd10 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1190,6 +1190,33 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) } } =20 +static TCGCond tcg_out_cmp(TCGContext *s, TCGCond cond, TCGReg a, + TCGArg b, int b_const) +{ + if (!is_tst_cond(cond)) { + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a, b, b_const= ); + return cond; + } + + cond =3D tcg_tst_eqne_cond(cond); + if (b_const) { + int imm12 =3D encode_imm(b); + + /* + * The compare constraints allow rIN, but TST does not support N. + * Be prepared to load the constant into a scratch register. + */ + if (imm12 >=3D 0) { + tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, a, imm12); + return cond; + } + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, b); + b =3D TCG_REG_TMP; + } + tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, a, b, SHIFT_IMM_LSL(0)); + return cond; +} + static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args, const int *const_args) { @@ -1217,6 +1244,13 @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCG= Arg *args, tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); return cond; =20 + case TCG_COND_TSTEQ: + case TCG_COND_TSTNE: + /* Similar, but with TST instead of CMP. */ + tcg_out_dat_rI(s, COND_AL, ARITH_TST, 0, ah, bh, const_bh); + tcg_out_dat_rI(s, COND_EQ, ARITH_TST, 0, al, bl, const_bl); + return tcg_tst_eqne_cond(cond); + case TCG_COND_LT: case TCG_COND_GE: /* We perform a double-word subtraction and examine the result. @@ -1805,9 +1839,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, /* Constraints mean that v2 is always in the same register as dest, * so we only need to do "if condition passed, move v1 to dest". */ - tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[1], args[2], const_args[2]); - tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[args[5]], ARITH_MOV, + c =3D tcg_out_cmp(s, args[5], args[1], args[2], const_args[2]); + tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[c], ARITH_MOV, ARITH_MVN, args[0], 0, args[3], const_args[3]); break; case INDEX_op_add_i32: @@ -1957,25 +1990,21 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_brcond_i32: - tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[0], args[1], const_args[1]); - tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], - arg_label(args[3])); + c =3D tcg_out_cmp(s, args[2], args[0], args[1], const_args[1]); + tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[3])); break; case INDEX_op_setcond_i32: - tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[1], args[2], const_args[2]); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]], + c =3D tcg_out_cmp(s, args[3], args[1], args[2], const_args[2]); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])], + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], ARITH_MOV, args[0], 0, 0); break; case INDEX_op_negsetcond_i32: - tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[1], args[2], const_args[2]); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]], + c =3D tcg_out_cmp(s, args[3], args[1], args[2], const_args[2]); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MVN, args[0], 0, 0); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])], + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], ARITH_MOV, args[0], 0, 0); break; =20 --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279451; cv=none; d=zohomail.com; s=zohoarc; b=S/2W+dOhB1SGPtkkpLGDPYC4/8cSRPrLLVaWgHkFReRTDIDF+zMQ5tYAdqP/HmrSF/3g7MOKJygraebSmQU0701CYaigyZxkd1n5nGdLu/NC5kcPIjCq4IiJmYiFBE6W6raYMN2v/9a7aK3Nk/JIJQyDY22Z2ciDOoY+0dFvI7s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279451; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=lVqtOTdE26FeikcQeSUZ6gzaDd5J2ZKDmGo0pFRcFos=; b=QTO+4dMLvBAY+Iy0BftB/sa0nvm3fk/Rig2xXG9iXtf74nkzSUTX0ASNgKDMc4ZSoM0LC3rhJc0u8K7GXFasJ59iySoqvI36MBaRE6fH5XfT4+jhBGbGu3NhBLosMbnpnVRVNMc4jkJYAB7nG3GU9OnzmviPl8ZDXCPBEfisslo= ARC-Authentication-Results: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.15.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:15:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279358; x=1698884158; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=lVqtOTdE26FeikcQeSUZ6gzaDd5J2ZKDmGo0pFRcFos=; b=aQWOWJMpzZsMkg3EhGGeBZgGUQJwZox9rkIK6jjHVTyhdcXBo2zPLTYBSKuQJpTYNm nFPrOdEBYmacHsdxjDmz1x5WMSebK89C7YMViBSX5bla28Icex98CbiAdK+acNFQJwip o87xD4ZicZLpyfqcugYR6zqbg3uvWDs1WUlVgwXtdRSPZDeQZCHmBIg1X6PUGcOoPAOa EVOgtyxlJC8gtBlNGbUDAPmFyKGhFGbxTKeEWSVwLSChuMepULvlJmji+hVmihIIsIpN z4YATzl5pQmU3kv+S1s2Q6UKNdVvWs2DHvL0pDMXeA7hdMzWxdjTxSVasceuSdEWTs++ NtUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279358; x=1698884158; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lVqtOTdE26FeikcQeSUZ6gzaDd5J2ZKDmGo0pFRcFos=; b=MQRVPv9uFJ2heaL6xBKoYIOVUvci14tx3r6qB2ivOodKVwddKLyu5rnYzZXJGYfrN/ 9CrDre5yqIoXAqcsZdh+jayOJ2TjN7GuCuwgWGm3Oi7XcUxN1eQKcJTqwwRPE3SusZWa HOkrL2hUcu84ReZ09+SXsZlazbmh2IJssoNRmmolBEp7ul9HHh+AdMsUsgELEZFtm0/1 eIDIDE1pKOIwjRzgFxU0lrx+dFCPLsEEeg/XNYsnQ/iRUW3LbOZRIEG/JGTS7r/tBeKj iXbcb/CKkJu//w95jCquoVlJBPhGdlgsEkmvxyFbDI/ig3nIOjvipXj6lSeQ7cvRSvXC F/rQ== X-Gm-Message-State: AOJu0YxiyCKa8gT16jSr9WvKsLvTxdtaqyyzALY83prIpgZ1nB8W5G7D ZY+d63rX6nKZrmYnsqR6Gzk0UDgLyEPjRPpCnD8= X-Google-Smtp-Source: AGHT+IH5oE+4QHtXH8Br62l2u3Uvj9FTE+MKvI5ULEq5Qje7Ytx19BynHScuRUN00xeTzeDcqAqUAg== X-Received: by 2002:a17:902:c602:b0:1c8:7822:e5c3 with SMTP id r2-20020a170902c60200b001c87822e5c3mr14284444plr.47.1698279358399; Wed, 25 Oct 2023 17:15:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 09/94] target/sparc: Partition cpu features Date: Wed, 25 Oct 2023 17:13:56 -0700 Message-Id: <20231026001542.1141412-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279451536100001 Content-Type: text/plain; charset="utf-8" In the sparc32 binaries, do not advertise features only available to sparc64, so they cannot be enabled. In the sparc64 binaries, do not advertise features mandatory in v9, so they cannot be disabled. Signed-off-by: Richard Henderson --- target/sparc/cpu.c | 42 ++++++++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 18 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index f527244aa4..bb1a155510 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -546,14 +546,17 @@ static const sparc_def_t sparc_defs[] =3D { /* This must match sparc_cpu_properties[]. */ static const char * const feature_name[] =3D { [CPU_FEATURE_BIT_FLOAT128] =3D "float128", - [CPU_FEATURE_BIT_MUL] =3D "mul", - [CPU_FEATURE_BIT_DIV] =3D "div", - [CPU_FEATURE_BIT_VIS1] =3D "vis1", - [CPU_FEATURE_BIT_VIS2] =3D "vis2", - [CPU_FEATURE_BIT_FSMULD] =3D "fsmuld", - [CPU_FEATURE_BIT_HYPV] =3D "hypv", +#ifdef TARGET_SPARC64 [CPU_FEATURE_BIT_CMT] =3D "cmt", [CPU_FEATURE_BIT_GL] =3D "gl", + [CPU_FEATURE_BIT_HYPV] =3D "hypv", + [CPU_FEATURE_BIT_VIS1] =3D "vis1", + [CPU_FEATURE_BIT_VIS2] =3D "vis2", +#else + [CPU_FEATURE_BIT_MUL] =3D "mul", + [CPU_FEATURE_BIT_DIV] =3D "div", + [CPU_FEATURE_BIT_FSMULD] =3D "fsmuld", +#endif }; =20 static void print_features(uint32_t features, const char *prefix) @@ -832,22 +835,25 @@ static PropertyInfo qdev_prop_nwindows =3D { static Property sparc_cpu_properties[] =3D { DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features, CPU_FEATURE_BIT_FLOAT128, false), - DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, - CPU_FEATURE_BIT_MUL, false), - DEFINE_PROP_BIT("div", SPARCCPU, env.def.features, - CPU_FEATURE_BIT_DIV, false), - DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features, - CPU_FEATURE_BIT_VIS1, false), - DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features, - CPU_FEATURE_BIT_VIS2, false), - DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features, - CPU_FEATURE_BIT_FSMULD, false), - DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features, - CPU_FEATURE_BIT_HYPV, false), +#ifdef TARGET_SPARC64 DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features, CPU_FEATURE_BIT_CMT, false), DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features, CPU_FEATURE_BIT_GL, false), + DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_HYPV, false), + DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_VIS1, false), + DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_VIS2, false), +#else + DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_MUL, false), + DEFINE_PROP_BIT("div", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_DIV, false), + DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_FSMULD, false), +#endif DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0, qdev_prop_uint64, target_ulong), DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0), --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.15.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:15:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279360; x=1698884160; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3tqKRfrHgf804PVSbuQwIQNkobvA0TCMv4wurSnK70U=; b=Q7KsIQ+cwLgSl+d5X2Be0oi3HG1QjXMfaTIGH2ZNhS6U8r6r4nBDjr17HinvGfoaAp MGFe2RytQ4R7OpfTRw5Mii9VHbNaGZ0HNOAjKp8i78ZupkIvx4CNTWBTynaFRYoI2CRi cTKUu3rTlQ0mjIB/D8eqxrPlWZdfbwLX+hG2ivw8IQk9dChRjAy7NCVsavmmPgcg8pDB oTEbGwAQx7jZ8tFYoCsMoBx8InR1kH0kt5AW/jQcMsngzBy0YsNRyDtm/wJ5zgGXbp1h WnXH0j4UrcWyQrNwtwEhw8t3l1lsoQsVfMXgznaXXYRKWX57Q7B2MEUnRTxynuwH5TyW j5EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279360; x=1698884160; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280628029100003 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 5 +++ target/sparc/translate.c | 69 ++++++++++++++++++++++++++------------- target/sparc/meson.build | 3 ++ 3 files changed, 55 insertions(+), 22 deletions(-) create mode 100644 target/sparc/insns.decode diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode new file mode 100644 index 0000000000..5811a679db --- /dev/null +++ b/target/sparc/insns.decode @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: LGPL-2.0+ +# +# Sparc instruction decode definitions. +# Copyright (c) 2023 Richard Henderson + diff --git a/target/sparc/translate.c b/target/sparc/translate.c index cab9f13421..080bc5f8a2 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -3003,6 +3003,47 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv = s1, TCGv s2) } #endif =20 +/* Include the auto-generated decoder. */ +#include "decode-insns.c.inc" + +#define TRANS(NAME, AVAIL, FUNC, ...) \ + static bool trans_##NAME(DisasContext *dc, arg_##NAME *a) \ + { return avail_##AVAIL(dc) && FUNC(dc, __VA_ARGS__); } + +#define avail_ALL(C) true +#ifdef TARGET_SPARC64 +# define avail_32(C) false +# define avail_64(C) true +#else +# define avail_32(C) true +# define avail_64(C) false +#endif + +/* Default case for non jump instructions. */ +static bool advance_pc(DisasContext *dc) +{ + if (dc->npc & 3) { + switch (dc->npc) { + case DYNAMIC_PC: + case DYNAMIC_PC_LOOKUP: + dc->pc =3D dc->npc; + gen_op_next_insn(); + break; + case JUMP_PC: + /* we can do a static jump */ + gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); + dc->base.is_jmp =3D DISAS_NORETURN; + break; + default: + g_assert_not_reached(); + } + } else { + dc->pc =3D dc->npc; + dc->npc =3D dc->npc + 4; + } + return true; +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -3011,7 +3052,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s= 1, TCGv s2) goto nfpu_insn; =20 /* before an instruction, dc->pc must be static */ -static void disas_sparc_insn(DisasContext * dc, unsigned int insn) +static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) { unsigned int opc, rs1, rs2, rd; TCGv cpu_src1, cpu_src2; @@ -5544,26 +5585,7 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) } break; } - /* default case for non jump instructions */ - if (dc->npc & 3) { - switch (dc->npc) { - case DYNAMIC_PC: - case DYNAMIC_PC_LOOKUP: - dc->pc =3D dc->npc; - gen_op_next_insn(); - break; - case JUMP_PC: - /* we can do a static jump */ - gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); - dc->base.is_jmp =3D DISAS_NORETURN; - break; - default: - g_assert_not_reached(); - } - } else { - dc->pc =3D dc->npc; - dc->npc =3D dc->npc + 4; - } + advance_pc(dc); jmp_insn: return; illegal_insn: @@ -5654,7 +5676,10 @@ static void sparc_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cs) =20 insn =3D translator_ldl(env, &dc->base, dc->pc); dc->base.pc_next +=3D 4; - disas_sparc_insn(dc, insn); + + if (!decode(dc, insn)) { + disas_sparc_legacy(dc, insn); + } =20 if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { return; diff --git a/target/sparc/meson.build b/target/sparc/meson.build index 48025cce76..c316773db6 100644 --- a/target/sparc/meson.build +++ b/target/sparc/meson.build @@ -1,4 +1,7 @@ +gen =3D decodetree.process('insns.decode') + sparc_ss =3D ss.source_set() +sparc_ss.add(gen) sparc_ss.add(files( 'cc_helper.c', 'cpu.c', --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.15.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:16:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279360; x=1698884160; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=mZENFqh4cY1cxr9SwQWDQ8KTGiGlTUEViewQDnyDP2A=; b=DD2gscnKqIkrx0u0LZ+eF69R0hdVdAsgKdLrvdafU2t69aAN1babDI3nLAkkCi3/Wu CJwY8o31v6lWdKBiBCcQDLL0UlORiHCOscQPQY8/G0i4L5Ptyq7aDV6aKh9e4zyYyuUg GZWuHk0O1NkNRKHCU2Lbyixb0EB9qDOyQWh2vIow6gWjwMPohSHhyxle+Bsc0cx78Z1Y 5nfF7aIUvtPtRcFSZ3oxN3n366+6Qa6Ud38exCAQAjfMN34V6qorjzjxpbVEhJSlREUa z2CI19TqjiB5fkxtfFqGf2f+aKbQOwPhthqQd9z0dSfqzYk7EAPFVNRFZHQoEj8KcyrF eZtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279360; x=1698884160; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mZENFqh4cY1cxr9SwQWDQ8KTGiGlTUEViewQDnyDP2A=; b=S0e14iyPkpqLt4p5xAFKbcVR9rRIlLLN6I28/aza4zNU8TizW7fvxKA5NvXUk3fxqK QyFO88ro3/+f0Tv8Jl1MjTAMbbZRvMf1/FgzTGN2q9Pu9Y0Hn2W5EMoXuNAz9MSrIgNQ gCOcRBqEumkYd1wo9vE16OM8ZaWHZGf7DTMPa0wjIcVSO+hjJ1iliyvF6FcZ7B4OmswI 3IXZ6KI8LUYhgLxXsHcPwufno5m9iu4hmLXLb2Y9VeypFEk0CUKgksyE/LYf7TeC3TJO X9rSflhqB/WkgsaGja813lJzw6FSBZ8eK+R/EshkDR360dTVF6i17S/uvBEAfjqTo5LX Qojg== X-Gm-Message-State: AOJu0YyLB+D5lMk3sykUtlgGKs54L6ND5rOe0Qh+cQVL/UusHd3618hB 246p/MsCgRZDIY4B4/hmo4M40rhBl1S2vnRUAj0= X-Google-Smtp-Source: AGHT+IHIbT3TgC4K9UhSfQ6jJ7cOMoxLaJUvqiBOjjHihLLcKp0zLA0Fpoc5PIoEAW9Gv8+sc/xBow== X-Received: by 2002:a17:903:32d2:b0:1c0:9d6f:9d28 with SMTP id i18-20020a17090332d200b001c09d6f9d28mr16203303plr.11.1698279360554; Wed, 25 Oct 2023 17:16:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 10/29] tcg/i386: Pass x86 condition codes to tcg_out_cmov Date: Wed, 25 Oct 2023 17:13:59 -0700 Message-Id: <20231026001542.1141412-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279469483100004 Content-Type: text/plain; charset="utf-8" Hoist the tcg_cond_to_jcc index outside the function. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index a83f8aab30..0daffb0e70 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1668,14 +1668,14 @@ static void tcg_out_setcond2(TCGContext *s, const T= CGArg *args, } #endif =20 -static void tcg_out_cmov(TCGContext *s, TCGCond cond, int rexw, +static void tcg_out_cmov(TCGContext *s, int jcc, int rexw, TCGReg dest, TCGReg v1) { if (have_cmov) { - tcg_out_modrm(s, OPC_CMOVCC | tcg_cond_to_jcc[cond] | rexw, dest, = v1); + tcg_out_modrm(s, OPC_CMOVCC | jcc | rexw, dest, v1); } else { TCGLabel *over =3D gen_new_label(); - tcg_out_jxx(s, tcg_cond_to_jcc[tcg_invert_cond(cond)], over, 1); + tcg_out_jxx(s, jcc ^ 1, over, 1); tcg_out_mov(s, TCG_TYPE_I32, dest, v1); tcg_out_label(s, over); } @@ -1686,7 +1686,7 @@ static void tcg_out_movcond(TCGContext *s, int rexw, = TCGCond cond, TCGReg v1) { tcg_out_cmp(s, c1, c2, const_c2, rexw); - tcg_out_cmov(s, cond, rexw, dest, v1); + tcg_out_cmov(s, tcg_cond_to_jcc[cond], rexw, dest, v1); } =20 static void tcg_out_ctz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, @@ -1698,12 +1698,12 @@ static void tcg_out_ctz(TCGContext *s, int rexw, TC= GReg dest, TCGReg arg1, tcg_debug_assert(arg2 =3D=3D (rexw ? 64 : 32)); } else { tcg_debug_assert(dest !=3D arg2); - tcg_out_cmov(s, TCG_COND_LTU, rexw, dest, arg2); + tcg_out_cmov(s, JCC_JB, rexw, dest, arg2); } } else { tcg_debug_assert(dest !=3D arg2); tcg_out_modrm(s, OPC_BSF + rexw, dest, arg1); - tcg_out_cmov(s, TCG_COND_EQ, rexw, dest, arg2); + tcg_out_cmov(s, JCC_JE, rexw, dest, arg2); } } =20 @@ -1716,7 +1716,7 @@ static void tcg_out_clz(TCGContext *s, int rexw, TCGR= eg dest, TCGReg arg1, tcg_debug_assert(arg2 =3D=3D (rexw ? 64 : 32)); } else { tcg_debug_assert(dest !=3D arg2); - tcg_out_cmov(s, TCG_COND_LTU, rexw, dest, arg2); + tcg_out_cmov(s, JCC_JB, rexw, dest, arg2); } } else { tcg_debug_assert(!const_a2); @@ -1729,7 +1729,7 @@ static void tcg_out_clz(TCGContext *s, int rexw, TCGR= eg dest, TCGReg arg1, =20 /* Since we have destroyed the flags from BSR, we have to re-test.= */ tcg_out_cmp(s, arg1, 0, 1, rexw); - tcg_out_cmov(s, TCG_COND_EQ, rexw, dest, arg2); + tcg_out_cmov(s, JCC_JE, rexw, dest, arg2); } } =20 --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280706; cv=none; d=zohomail.com; s=zohoarc; b=R08sKf1LTLUnJoEoqXDPHknNVRjJE3ZHoxBEBAFy8gGfJXXoANcEYOGiwwQ4zm40y9uv+tPktU2J1AErPCc760NK5XndMNR5fQ42V0w9iB5YmdaLP49O3lH7BPmb6JaQcTako2wBES9rLHDBQlYdt1mKfPLljTOhvzF7D0pq3JU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280706; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zhJv02LeNSNRi9K7QfhBZ5XwbuSGXoIYziudXEjPl7w=; b=YFr4Sh1xcgLjsmt4zU6KSUwX3SEPPc9q0XvfVVycxuin7fCa2Z9Y34uqWWbtfaeW0WPXtYu8tM7zme2bfNg5aRczCrV9w2kZdMEGMCii+IFjTlJcHIzXF6HAsBwC9g32WfFMRPYkC6V8+8DoudrZh66OpOEV8CM/GYhqvmWEgSQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698280706226662.4845780477665; Wed, 25 Oct 2023 17:38:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo2t-00079n-0P; Wed, 25 Oct 2023 20:16:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo2l-00070s-Fe for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:12 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo2h-0004rS-M5 for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:11 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1cbf47fa563so2273905ad.2 for ; Wed, 25 Oct 2023 17:16:02 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.16.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:16:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279361; x=1698884161; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zhJv02LeNSNRi9K7QfhBZ5XwbuSGXoIYziudXEjPl7w=; b=dexLZLnG8XlB4nwE91iyK5LfQE+ksa6jswIdG2J/GHtuzYXQjur9Qwk+wKi6fkl+jd ltD0zqjwfHDFvmU4ZhihH2AOZCq8GLKJdAPDuOXmSu0jpZ7UJ0c/oYFYt2gWGpvOkipG kOzj/EjZJQXHSFx0XC/ggTDzKhDPPe5/IWioGd+s9CP8Xv+MoAMDnif/IEjAWV1pGwn1 KkHjkftQzU4BDR84P7zG4ow74hOJ0WXXCTFeIVlWu8+90zhPhGZoUHy9d7zKI8TiIpAQ fv87pLf7bb3X/VYzaSsnm7Xty1KAeFRBGUSnYQO3tVvuJv/3tht/vG9kISml6gzqOZA9 f+Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279361; x=1698884161; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zhJv02LeNSNRi9K7QfhBZ5XwbuSGXoIYziudXEjPl7w=; b=XwybAS7lKVjHE0D6NiG5Tk2KIeeKOGxWeiwqcq1cMY7SteWQaNwPaRUVXlvNzsG9jO DT0vsuui8HtgrYVHSaaZ57Y2o9tllsWo0Sl/OCV/PPg4J0JTWvQJp0qH2lhqofDyRrSH 6pzXsvrVnW8cfIRcAEC9u5c1ED9ORc3DJBX4cYT8u5JziuA7BYNfN8h1C1le/4odd5UM xVrQLNiXBGKzbUnFmlswFQVFXzOIkARXBNhfMytE0WIb9ECPaMVXGSa4M4lbUHurX+HS mU+d0Hu4H8SpOAgmqjk8+oIUs4lKDHHTvpFR262YC0Vcxhj0ICISWSpPtTKliy99rSDd 6UXg== X-Gm-Message-State: AOJu0YwFL4Q+XSaVMh5V3k+NyHeTTdwYeA6z8NnGk8JwFiH4s8UrHwQI dYH4MEvHsIx0YQkY2gqhG4EJrX68J4t7pLt298k= X-Google-Smtp-Source: AGHT+IH5f5FVZZvIATnlBQgaPUWXCFOeeZF8s5S1Z8R4RtljZyszVtOCpKYx7WRN1e6o9yhCajRxkg== X-Received: by 2002:a17:902:db0c:b0:1ca:7909:6ee6 with SMTP id m12-20020a170902db0c00b001ca79096ee6mr14908654plx.61.1698279361374; Wed, 25 Oct 2023 17:16:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 11/94] target/sparc: Define AM_CHECK for sparc32 Date: Wed, 25 Oct 2023 17:14:00 -0700 Message-Id: <20231026001542.1141412-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280708284100008 Content-Type: text/plain; charset="utf-8" Define as false, which allows some ifdef removal. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 080bc5f8a2..9eb2b7e52f 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -268,20 +268,21 @@ static void gen_move_Q(DisasContext *dc, unsigned int= rd, unsigned int rs) #endif #endif =20 -#ifdef TARGET_SPARC64 -#ifndef TARGET_ABI32 -#define AM_CHECK(dc) ((dc)->address_mask_32bit) +#if !defined(TARGET_SPARC64) +# define AM_CHECK(dc) false +#elif defined(TARGET_ABI32) +# define AM_CHECK(dc) true +#elif defined(CONFIG_USER_ONLY) +# define AM_CHECK(dc) false #else -#define AM_CHECK(dc) (1) -#endif +# define AM_CHECK(dc) ((dc)->address_mask_32bit) #endif =20 static void gen_address_mask(DisasContext *dc, TCGv addr) { -#ifdef TARGET_SPARC64 - if (AM_CHECK(dc)) + if (AM_CHECK(dc)) { tcg_gen_andi_tl(addr, addr, 0xffffffffULL); -#endif + } } =20 static TCGv gen_load_gpr(DisasContext *dc, int reg) @@ -1366,11 +1367,9 @@ static void do_branch(DisasContext *dc, int32_t offs= et, uint32_t insn, int cc) unsigned int cond =3D GET_FIELD(insn, 3, 6), a =3D (insn & (1 << 29)); target_ulong target =3D dc->pc + offset; =20 -#ifdef TARGET_SPARC64 if (unlikely(AM_CHECK(dc))) { target &=3D 0xffffffffULL; } -#endif if (cond =3D=3D 0x0) { /* unconditional not taken */ if (a) { @@ -1406,11 +1405,9 @@ static void do_fbranch(DisasContext *dc, int32_t off= set, uint32_t insn, int cc) unsigned int cond =3D GET_FIELD(insn, 3, 6), a =3D (insn & (1 << 29)); target_ulong target =3D dc->pc + offset; =20 -#ifdef TARGET_SPARC64 if (unlikely(AM_CHECK(dc))) { target &=3D 0xffffffffULL; } -#endif if (cond =3D=3D 0x0) { /* unconditional not taken */ if (a) { --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280052; cv=none; d=zohomail.com; s=zohoarc; b=l6AtdatxAiq5rbvr8v8FREDsdu5aQbDzRpzgcPNSe4lGCBgfOPBAKeK9p5qDW+ZZ9RsVqA4XwocywN9cayA9abyIgTLqmP8m/OkyEAlWbnldJLWBbmnKTEkn5hieuf7u7qKwy841Gloke5HjvVZWrW/wVAI+eRsvyH4Dvf+JV5A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280052; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=KAuC6MuCUKIHHBxqGTcvXulP9OV1zIYTQIpMzlqMLcg=; b=AptS5yniaGQTsQ0AJVKT+4DX7tCdR15w+Vi7LL9p1Vkyhdl+vhgjwCHobDEKFzu0slVnLUQHB7zWctLh0pth4O/K+CuNxlyMaTCM0hGDUrMGrdG2joyVPT1lYJALgBdu3hF0A2/po0uj87/3sl2AyNahz+qbFVs+l6RUYQDZfLc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698280052680415.38342297582483; Wed, 25 Oct 2023 17:27:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo2r-00076f-Ju; Wed, 25 Oct 2023 20:16:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo2k-00070l-W9 for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:12 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo2g-0004rY-Ji for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:08 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1c434c33ec0so2266925ad.3 for ; Wed, 25 Oct 2023 17:16:03 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.16.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:16:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279362; x=1698884162; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=KAuC6MuCUKIHHBxqGTcvXulP9OV1zIYTQIpMzlqMLcg=; b=a5HtLAIX+A3bemenxWauITQK4CD+rNKOTw1hp0u4LCVGqkOetaWQ26OWanHJcuArjV fJi4MbqDVzjzXtl839Cz9z6r6+3n0DjhJXoMQiqtLF9DqUGMVpaVoK8APkaVeM7ErlTY 1SKROH6BHdd/xYgZj2NzI+QcqnnsPBgRdWeyBllJ0Ky8hPUnu0oFnuwrJoZXMknvXYEa GXZstrsa3g8YxHImuKqmuibpj8Mx+Wm2c9r8CJC4YYWnVwUn4bUporHGZcEy/10q+zzW npmwtj+9+AIq5GvPwvplOOlNcHSOpETiyj1hkgqA87Bn/5GMC6BfadiS4uJT+iuj4lOq YBhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279362; x=1698884162; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KAuC6MuCUKIHHBxqGTcvXulP9OV1zIYTQIpMzlqMLcg=; b=NApVGFBV1cCVMsBuOb4nvdV5WwN6kO7pKxY0Rsb5VAztMzjS44KjX9XvrNNtAlzsht WKtDgx6Cpwr2yn28GK10waQI3Ds2q80VMGNm0j9+t57iNxoWP/7uX4Cdt835M5acVX06 Ffprn5tQt+LC9EI+bPRWy6pPUww7lYu+MqROfzswBaY7/ysWZzMKJ1SvPJDXQh/xV+ZE bKdvtEfBkOOrKEpnwRCysAMn8l8q4R5BKn24/0xQI/uNwq++peOvBYye3IeRuuGxjy5z 20pVCgU/wA2gPLThVIO0CRZKVlIA9P0xaB3rAwzu9HBbf2b4IVAAXxGYGUeKrBhnfmTo QXbw== X-Gm-Message-State: AOJu0Yxj+UfCyGi+03kaTR3B6HOUfItA97fR27L8SQCPGJIlD2bMPX56 o+pbiv/2Ajo7VxeDRCDTUAkBV18WY0LfIohM/3A= X-Google-Smtp-Source: AGHT+IGYHhXQ11OJRBQCDoSGV4Kdb+heZoAAJ2fLbrl4Mc3JKsWYKKTq86fuErY2b3zyybH9FaeauA== X-Received: by 2002:a17:902:cec6:b0:1c5:cbfb:c16f with SMTP id d6-20020a170902cec600b001c5cbfbc16fmr16385499plg.25.1698279362200; Wed, 25 Oct 2023 17:16:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 11/29] tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp Date: Wed, 25 Oct 2023 17:14:01 -0700 Message-Id: <20231026001542.1141412-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280053280100001 Content-Type: text/plain; charset="utf-8" Return the x86 condition codes to use after the compare. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 0daffb0e70..6e8af1fcf6 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1418,8 +1418,8 @@ static void tcg_out_jxx(TCGContext *s, int opc, TCGLa= bel *l, bool small) } } =20 -static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2, - int const_arg2, int rexw) +static int tcg_out_cmp(TCGContext *s, TCGCond cond, TCGArg arg1, + TCGArg arg2, int const_arg2, int rexw) { if (const_arg2) { if (arg2 =3D=3D 0) { @@ -1431,14 +1431,15 @@ static void tcg_out_cmp(TCGContext *s, TCGArg arg1,= TCGArg arg2, } else { tgen_arithr(s, ARITH_CMP + rexw, arg1, arg2); } + return tcg_cond_to_jcc[cond]; } =20 static void tcg_out_brcond(TCGContext *s, int rexw, TCGCond cond, TCGArg arg1, TCGArg arg2, int const_arg2, TCGLabel *label, bool small) { - tcg_out_cmp(s, arg1, arg2, const_arg2, rexw); - tcg_out_jxx(s, tcg_cond_to_jcc[cond], label, small); + int jcc =3D tcg_out_cmp(s, cond, arg1, arg2, const_arg2, rexw); + tcg_out_jxx(s, jcc, label, small); } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 @@ -1530,6 +1531,7 @@ static void tcg_out_setcond(TCGContext *s, int rexw, = TCGCond cond, { bool inv =3D false; bool cleared; + int jcc; =20 switch (cond) { case TCG_COND_NE: @@ -1566,7 +1568,7 @@ static void tcg_out_setcond(TCGContext *s, int rexw, = TCGCond cond, * We can then use NEG or INC to produce the desired result. * This is always smaller than the SETCC expansion. */ - tcg_out_cmp(s, arg1, arg2, const_arg2, rexw); + tcg_out_cmp(s, TCG_COND_LTU, arg1, arg2, const_arg2, rexw); =20 /* X - X - C =3D -C =3D (C ? -1 : 0) */ tgen_arithr(s, ARITH_SBB + (neg ? rexw : 0), dest, dest); @@ -1613,8 +1615,8 @@ static void tcg_out_setcond(TCGContext *s, int rexw, = TCGCond cond, cleared =3D true; } =20 - tcg_out_cmp(s, arg1, arg2, const_arg2, rexw); - tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest); + jcc =3D tcg_out_cmp(s, cond, arg1, arg2, const_arg2, rexw); + tcg_out_modrm(s, OPC_SETCC | jcc, 0, dest); =20 if (!cleared) { tcg_out_ext8u(s, dest, dest); @@ -1685,8 +1687,8 @@ static void tcg_out_movcond(TCGContext *s, int rexw, = TCGCond cond, TCGReg dest, TCGReg c1, TCGArg c2, int const_c= 2, TCGReg v1) { - tcg_out_cmp(s, c1, c2, const_c2, rexw); - tcg_out_cmov(s, tcg_cond_to_jcc[cond], rexw, dest, v1); + int jcc =3D tcg_out_cmp(s, cond, c1, c2, const_c2, rexw); + tcg_out_cmov(s, jcc, rexw, dest, v1); } =20 static void tcg_out_ctz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, @@ -1728,8 +1730,8 @@ static void tcg_out_clz(TCGContext *s, int rexw, TCGR= eg dest, TCGReg arg1, tgen_arithi(s, ARITH_XOR + rexw, dest, rexw ? 63 : 31, 0); =20 /* Since we have destroyed the flags from BSR, we have to re-test.= */ - tcg_out_cmp(s, arg1, 0, 1, rexw); - tcg_out_cmov(s, JCC_JE, rexw, dest, arg2); + int jcc =3D tcg_out_cmp(s, TCG_COND_EQ, arg1, 0, 1, rexw); + tcg_out_cmov(s, jcc, rexw, dest, arg2); } } =20 --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279731; cv=none; d=zohomail.com; s=zohoarc; b=bGCquhe027af+Kj2ESidqNREeMs40pHaN+sRq43DpFUmQPXGWzyh0Fxab5erOsGQoMdYof9f3Aw6P53JOMTczbvMPG/jicKeUZlc18Qum3e4COOFuuCGMom4UxEZ4gVMPlpLW3HJC6lMURjdvxKhBfQlbu/EQzN97fuTKmhT2WA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279731; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=pWAF8Yy1Ybd5ENfcMHYAo9tgOERLXXMk37OKNqP6zdk=; b=ZXKoydhnqC3f+w3TR9mul25Rbrim/gWyXL7C+o6fVTtQdY37Ptdjd51IYpLDLmbueMhBZpI70qPJFGBaSQHmy0PixvZcFpKVTx2y4xbZ1QiZBhwm2QoqXVuRjslyn8Z5KL313yZnDODFI7Xt16zD54YFKnxi/XQZJqdOTV1DnG8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698279731178579.4926952534597; Wed, 25 Oct 2023 17:22:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo2t-0007A5-8m; Wed, 25 Oct 2023 20:16:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo2o-000737-9F for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:14 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo2h-0004rh-Ln for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:13 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1ca052ec63bso2381745ad.1 for ; Wed, 25 Oct 2023 17:16:04 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.16.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:16:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279363; x=1698884163; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=pWAF8Yy1Ybd5ENfcMHYAo9tgOERLXXMk37OKNqP6zdk=; b=G4K8gPGSkpMJ3HklLnruYNFKAXek6Aa4XwFjngdG1ctEkRum3UD+ozZl6w03TM+mHx ec7jM2lZIJRwzuUzGfLchOX1hwZ4dCslOcG5bZxJq9QcfMso+u75udlQmCVXBVqwshaw gIv2mD5vHyd8z9f/U3j+6KMm3l7v99e5pJTxRUGa3UO8uL6aFDcHTmVgtzWP2XpFApkp k9yeZnAkZPdlthsXGbzxQMTxvffieZQejqIs8AF9eCxRcLT4jILAiEcdRwq8U4+WwDKD fiSQJsIY4XQ1Aq5BvZEePIgoDJeJBy009v6RmVJ1qvm2zMuQswrqPJramLIcUQdAbPTt H/QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279363; x=1698884163; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pWAF8Yy1Ybd5ENfcMHYAo9tgOERLXXMk37OKNqP6zdk=; b=IajFDYR8gaL1bcdeZ33p4fCt71WuEPsa0Bm5njF56EbE5jXOb5xyCfZJjn2UoA1xca X52BtVKpNFzpTX6hvtTQzd23apd4nAZR75760b1I2D5TU3HMxU2SeJF5i8UlEG7o4EfV ln1oxMwk93PbowmFJGBmLTJTFinc7iYet4fxaHaEA1xvAYmBichxHaspLFIJyEVvdu5g p9etr9os/66S/CR3bNXEhglUyDVpB/0khdXQfxNYeh6VapTv4ipaEtUiVuTmZAICxPDH gM54wFfGk0M1fbCNWzC/SkVDqybX/Ne+oWvhLqqtpCYolCKsxHQvRAYyu0ww63QdXsZw I9jA== X-Gm-Message-State: AOJu0YwMxuKamU3O6UfwunE+BPXT9IpS0JUCXqknsNPYApY9GrLwjXok 1fJsVJzAPUAoy37ptrV0Q5aYbRBnRvPPEpnOO+Q= X-Google-Smtp-Source: AGHT+IFExYaWAzs3od3OHmCL4k0SEQEP7/m/48QqlzKgMOPraL66hzRcaUjc7QQWSYvs2FnWdrFRqg== X-Received: by 2002:a17:903:1252:b0:1c9:e774:58d9 with SMTP id u18-20020a170903125200b001c9e77458d9mr19621895plh.34.1698279363686; Wed, 25 Oct 2023 17:16:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 12/29] tcg/i386: Add rexw argument to tcg_out_testi Date: Wed, 25 Oct 2023 17:14:03 -0700 Message-Id: <20231026001542.1141412-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279732275100003 Content-Type: text/plain; charset="utf-8" Move up above tcg_out_cmp, where it will be used. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 36 ++++++++++++++++-------------------- 1 file changed, 16 insertions(+), 20 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 6e8af1fcf6..f4f456a2c0 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1418,6 +1418,19 @@ static void tcg_out_jxx(TCGContext *s, int opc, TCGL= abel *l, bool small) } } =20 +/* Test register R vs immediate bits I, setting Z flag for EQ/NE. */ +static void __attribute__((unused)) +tcg_out_testi(TCGContext *s, TCGReg r, uint32_t i, int rexw) +{ + if (i <=3D 0xff && (TCG_TARGET_REG_BITS =3D=3D 64 || r < 4)) { + tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, r); + tcg_out8(s, i); + } else { + tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_TESTi, r); + tcg_out32(s, i); + } +} + static int tcg_out_cmp(TCGContext *s, TCGCond cond, TCGArg arg1, TCGArg arg2, int const_arg2, int rexw) { @@ -1796,23 +1809,6 @@ static void tcg_out_nopn(TCGContext *s, int n) tcg_out8(s, 0x90); } =20 -/* Test register R vs immediate bits I, setting Z flag for EQ/NE. */ -static void __attribute__((unused)) -tcg_out_testi(TCGContext *s, TCGReg r, uint32_t i) -{ - /* - * This is used for testing alignment, so we can usually use testb. - * For i686, we have to use testl for %esi/%edi. - */ - if (i <=3D 0xff && (TCG_TARGET_REG_BITS =3D=3D 64 || r < 4)) { - tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, r); - tcg_out8(s, i); - } else { - tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_TESTi, r); - tcg_out32(s, i); - } -} - typedef struct { TCGReg base; int index; @@ -2080,7 +2076,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, ldst->addrlo_reg =3D addrlo; ldst->addrhi_reg =3D addrhi; =20 - tcg_out_testi(s, addrlo, a_mask); + tcg_out_testi(s, addrlo, a_mask, false); /* jne slow_path */ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); ldst->label_ptr[0] =3D s->code_ptr; @@ -2229,7 +2225,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, TCGLabel *l1 =3D gen_new_label(); TCGLabel *l2 =3D gen_new_label(); =20 - tcg_out_testi(s, h.base, 15); + tcg_out_testi(s, h.base, 15, false); tcg_out_jxx(s, JCC_JNE, l1, true); =20 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_VxWx + h.seg, @@ -2357,7 +2353,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, TCGLabel *l1 =3D gen_new_label(); TCGLabel *l2 =3D gen_new_label(); =20 - tcg_out_testi(s, h.base, 15); + tcg_out_testi(s, h.base, 15, false); tcg_out_jxx(s, JCC_JNE, l1, true); =20 tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_WxVx + h.seg, --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280793; cv=none; d=zohomail.com; s=zohoarc; b=ecXzW+ThxdYh3TDRfJVNMzNW+QHs1dP2Vz2nYcZ+PzUWJBO4hDxRif5Rcer7jfooDXkjAzkACIKVpKpRsk1wt7fYtzLmnSwbM9l7LYQhEQUBGcH8Lu4oH0IjjcgyFzW33s5BgH2RHcba+5I3qK5wB3xh0OSYAmhAFvnS6qSzCNo= ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.16.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:16:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279363; x=1698884163; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HaiE1/bSeMZ+5UImRCGkx6jDgHWHLGDLQF46mh2/Gqw=; b=QcIP/gLsRbPQtBEdXR7pbLVjgSigNds3hbemDgm8ZGcXNRS3sCUvICRvrEfobhPlu2 mz+xryO54onZbeE2be+R5+M8/ilEmO82yR8uGFLpUps9tubVDhQtYsELK+FFsGNkhx6o 8FKpRjuqNnemKTGx8W9ZU10yldIo0ISN4vJXA4DZS/K8DeSrhhWeZfBacJ3hTSYvQrR4 EC+4Smjgzw3kBJxtN1gEyajga1rz6h5Cm9pvaYLDIMcPn9gva4QuwLEy0iRkU8p6uenX bOXWGSpCPAWzhizEwYe2OYERxR+OM4wy2ngOgcJY3Z1f49vrZeev5M3eC5tUDJbPHtYa JeeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279363; x=1698884163; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HaiE1/bSeMZ+5UImRCGkx6jDgHWHLGDLQF46mh2/Gqw=; b=tTMUU/A/GTZWShe6hDxky/4aIQO4DTjB5xlD737iM6b7qtXj4/D7XVuk4VXMCrRrgX MaNIzxV7bEJKmGnNOaZFMtGB/8e3jPfq94GzYwebNZnhOkvaz9V4kkAfdIOf7V4bjGj4 aEBuEVOciF4YeyVFpPr02FJH/6yPV86kBHsQzRwU2Wq+O5JWNord56SI6ddJkQfF+8xx STbmrvobupRImXqF+GV8ZONmgnk1YrLSfPxW9RJGgmieLHvdtAZqxw8UtDper78mayzC LQ/r8cxqnDCfRnytdPk/A8txGRn/5TbxdGUhXb+5AtOYGHxzLAgug8ImmnIL+bykoHsO rXLg== X-Gm-Message-State: AOJu0YwwEadt33uQVAThCQH+IDt3RmXkPnqKUUkbjHNVd7o51G3mwreC niddiHkTByatnHSz2CG2uBJADq3VQCaqeu6z5Jc= X-Google-Smtp-Source: AGHT+IEgcbN+6UL7zB+oGR+rshTMZ2azQ9FvD3QB5yDsx613bWHceONU7Ow2EesC2Od92aI+AAfAuw== X-Received: by 2002:a17:903:1212:b0:1c8:92ee:108a with SMTP id l18-20020a170903121200b001c892ee108amr16888850plh.23.1698279362933; Wed, 25 Oct 2023 17:16:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 12/94] target/sparc: Move CALL to decodetree Date: Wed, 25 Oct 2023 17:14:02 -0700 Message-Id: <20231026001542.1141412-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280794591100007 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 34 +++++++++++++++++----------------- 2 files changed, 18 insertions(+), 17 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 5811a679db..a5f5d2681e 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -3,3 +3,4 @@ # Sparc instruction decode definitions. # Copyright (c) 2023 Richard Henderson =20 +CALL 01 i:s30 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 9eb2b7e52f..7ef4c6d4f7 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -285,6 +285,11 @@ static void gen_address_mask(DisasContext *dc, TCGv ad= dr) } } =20 +static target_ulong address_mask_i(DisasContext *dc, target_ulong addr) +{ + return AM_CHECK(dc) ? (uint32_t)addr : addr; +} + static TCGv gen_load_gpr(DisasContext *dc, int reg) { if (reg > 0) { @@ -3041,6 +3046,16 @@ static bool advance_pc(DisasContext *dc) return true; } =20 +static bool trans_CALL(DisasContext *dc, arg_CALL *a) +{ + target_long target =3D address_mask_i(dc, dc->pc + a->i * 4); + + gen_store_gpr(dc, 15, tcg_constant_tl(dc->pc)); + gen_mov_pc_npc(dc); + dc->npc =3D target; + return true; +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -3146,23 +3161,8 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) break; } break; - case 1: /*CALL*/ - { - target_long target =3D GET_FIELDs(insn, 2, 31) << 2; - TCGv o7 =3D gen_dest_gpr(dc, 15); - - tcg_gen_movi_tl(o7, dc->pc); - gen_store_gpr(dc, 15, o7); - target +=3D dc->pc; - gen_mov_pc_npc(dc); -#ifdef TARGET_SPARC64 - if (unlikely(AM_CHECK(dc))) { - target &=3D 0xffffffffULL; - } -#endif - dc->npc =3D target; - } - goto jmp_insn; + case 1: + g_assert_not_reached(); /* in decodetree */ case 2: /* FPU & Logical Operations */ { unsigned int xop =3D GET_FIELD(insn, 7, 12); --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279797; cv=none; d=zohomail.com; s=zohoarc; b=XguqFwrc6avkoWvO40cl/MDB2Ybf4LrmijTltch97tM83i7nldGa+8spT3ti+APWu892yrNPvXCQcLuzS6d/xoppLzUiH1m91Ty7kPFwgPSBOt9NNXCLhBZax84UZnmDwy/35nsJmjm8X01eMP9Ois8i9vFempUkgy8vQyfWYMY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279797; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=KUL+P8NrKSp/2wsdRODDHeKdHM6SlkUdqF+vGMepqTA=; b=ctBoklTHRqYGh0LXh3PhUDEblOBBzGrUtMmqdvz8D6sAhdeSKhRF0BMO6EED6OAVfjqh7hc8VwRsHS8bn8k33AKBksoZeXUTJZmpsvo+PzXMTAVzSbUokFgebY/gvYgvqSFVHiok+502pwz1kt366hpUbb0TyuBHA7qtAshmU0Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698279797352616.194155385862; Wed, 25 Oct 2023 17:23:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo2t-0007B5-U3; Wed, 25 Oct 2023 20:16:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo2p-00073s-Ic for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:15 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo2i-0004rz-JI for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:15 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1bf55a81eeaso2376285ad.0 for ; Wed, 25 Oct 2023 17:16:06 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279798399100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 43 +++++++++++++++++++++++++++------------ 1 file changed, 30 insertions(+), 13 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index f4f456a2c0..0d97864174 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -504,6 +504,8 @@ static const uint8_t tcg_cond_to_jcc[] =3D { [TCG_COND_GEU] =3D JCC_JAE, [TCG_COND_LEU] =3D JCC_JBE, [TCG_COND_GTU] =3D JCC_JA, + [TCG_COND_TSTEQ] =3D JCC_JE, + [TCG_COND_TSTNE] =3D JCC_JNE, }; =20 #if TCG_TARGET_REG_BITS =3D=3D 64 @@ -1419,12 +1421,14 @@ static void tcg_out_jxx(TCGContext *s, int opc, TCG= Label *l, bool small) } =20 /* Test register R vs immediate bits I, setting Z flag for EQ/NE. */ -static void __attribute__((unused)) -tcg_out_testi(TCGContext *s, TCGReg r, uint32_t i, int rexw) +static void tcg_out_testi(TCGContext *s, TCGReg r, uint32_t i, int rexw) { if (i <=3D 0xff && (TCG_TARGET_REG_BITS =3D=3D 64 || r < 4)) { tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, r); tcg_out8(s, i); + } else if ((i & ~0xff00) =3D=3D 0 && r < 4) { + tcg_out_modrm(s, OPC_GRP3_Eb, EXT3_TESTi, r); + tcg_out8(s, i >> 8); } else { tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_TESTi, r); tcg_out32(s, i); @@ -1434,15 +1438,25 @@ tcg_out_testi(TCGContext *s, TCGReg r, uint32_t i, = int rexw) static int tcg_out_cmp(TCGContext *s, TCGCond cond, TCGArg arg1, TCGArg arg2, int const_arg2, int rexw) { - if (const_arg2) { - if (arg2 =3D=3D 0) { - /* test r, r */ + if (is_tst_cond(cond)) { + if (!const_arg2) { + tcg_out_modrm(s, OPC_TESTL + rexw, arg1, arg2); + } else { + if (!rexw) { + arg2 =3D (uint32_t)arg2; + } else if ((arg2 >> 31 >> 1) =3D=3D 0) { + rexw =3D 0; + } + tcg_out_testi(s, arg1, arg2, rexw); + } + } else { + if (!const_arg2) { + tgen_arithr(s, ARITH_CMP + rexw, arg1, arg2); + } else if (arg2 =3D=3D 0) { tcg_out_modrm(s, OPC_TESTL + rexw, arg1, arg1); } else { tgen_arithi(s, ARITH_CMP + rexw, arg1, arg2, 0); } - } else { - tgen_arithr(s, ARITH_CMP + rexw, arg1, arg2); } return tcg_cond_to_jcc[cond]; } @@ -1461,18 +1475,21 @@ static void tcg_out_brcond2(TCGContext *s, const TC= GArg *args, { TCGLabel *label_next =3D gen_new_label(); TCGLabel *label_this =3D arg_label(args[5]); + TCGCond cond =3D args[4]; =20 - switch(args[4]) { + switch (cond) { case TCG_COND_EQ: - tcg_out_brcond(s, 0, TCG_COND_NE, args[0], args[2], const_args[2], - label_next, 1); - tcg_out_brcond(s, 0, TCG_COND_EQ, args[1], args[3], const_args[3], + case TCG_COND_TSTEQ: + tcg_out_brcond(s, 0, tcg_invert_cond(cond), + args[0], args[2], const_args[2], label_next, 1); + tcg_out_brcond(s, 0, cond, args[1], args[3], const_args[3], label_this, small); break; case TCG_COND_NE: - tcg_out_brcond(s, 0, TCG_COND_NE, args[0], args[2], const_args[2], + case TCG_COND_TSTNE: + tcg_out_brcond(s, 0, cond, args[0], args[2], const_args[2], label_this, small); - tcg_out_brcond(s, 0, TCG_COND_NE, args[1], args[3], const_args[3], + tcg_out_brcond(s, 0, cond, args[1], args[3], const_args[3], label_this, small); break; case TCG_COND_LT: --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279820; cv=none; d=zohomail.com; s=zohoarc; b=A6qChmGpje4wkDa4qMjtKhALQVnfTXPJ+jiLPdgt+3yuZoUoak3K1ux4HuFmZMoFisZ2jTUfJ6VAL393kbeNicMmzVsJOAXZbHGcDbUkXSlzNAoSLCbnqv1ZM4Aj9EWf91uOv7Eh1O2CddoL1RznPzpJ4UiiafXGG3+/2ONmVK8= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279820655100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++ target/sparc/translate.c | 117 +++++++++++++++++++------------------- 2 files changed, 61 insertions(+), 60 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a5f5d2681e..15cd975f4e 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -3,4 +3,8 @@ # Sparc instruction decode definitions. # Copyright (c) 2023 Richard Henderson =20 +&bcc i a cond cc +BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc +Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=3D0 + CALL 01 i:s30 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 7ef4c6d4f7..92ea6bab6b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1367,44 +1367,6 @@ static void gen_cond_reg(TCGv r_dst, int cond, TCGv = r_src) } #endif =20 -static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int= cc) -{ - unsigned int cond =3D GET_FIELD(insn, 3, 6), a =3D (insn & (1 << 29)); - target_ulong target =3D dc->pc + offset; - - if (unlikely(AM_CHECK(dc))) { - target &=3D 0xffffffffULL; - } - if (cond =3D=3D 0x0) { - /* unconditional not taken */ - if (a) { - dc->pc =3D dc->npc + 4; - dc->npc =3D dc->pc + 4; - } else { - dc->pc =3D dc->npc; - dc->npc =3D dc->pc + 4; - } - } else if (cond =3D=3D 0x8) { - /* unconditional taken */ - if (a) { - dc->pc =3D target; - dc->npc =3D dc->pc + 4; - } else { - dc->pc =3D dc->npc; - dc->npc =3D target; - tcg_gen_mov_tl(cpu_pc, cpu_npc); - } - } else { - flush_cond(dc); - gen_cond(cpu_cond, cc, cond, dc); - if (a) { - gen_branch_a(dc, target); - } else { - gen_branch_n(dc, target); - } - } -} - static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, in= t cc) { unsigned int cond =3D GET_FIELD(insn, 3, 6), a =3D (insn & (1 << 29)); @@ -3046,6 +3008,61 @@ static bool advance_pc(DisasContext *dc) return true; } =20 +static bool advance_jump_uncond_never(DisasContext *dc, bool annul) +{ + if (annul) { + dc->pc =3D dc->npc + 4; + dc->npc =3D dc->pc + 4; + } else { + dc->pc =3D dc->npc; + dc->npc =3D dc->pc + 4; + } + return true; +} + +static bool advance_jump_uncond_always(DisasContext *dc, bool annul, + target_ulong dest) +{ + if (annul) { + dc->pc =3D dest; + dc->npc =3D dest + 4; + } else { + dc->pc =3D dc->npc; + dc->npc =3D dest; + tcg_gen_mov_tl(cpu_pc, cpu_npc); + } + return true; +} + +static bool advance_jump_cond(DisasContext *dc, bool annul, target_ulong d= est) +{ + if (annul) { + gen_branch_a(dc, dest); + } else { + gen_branch_n(dc, dest); + } + return true; +} + +static bool do_bpcc(DisasContext *dc, arg_bcc *a) +{ + target_long target =3D address_mask_i(dc, dc->pc + a->i * 4); + + switch (a->cond) { + case 0x0: + return advance_jump_uncond_never(dc, a->a); + case 0x8: + return advance_jump_uncond_always(dc, a->a, target); + default: + flush_cond(dc); + gen_cond(cpu_cond, a->cc, a->cond, dc); + return advance_jump_cond(dc, a->a, target); + } +} + +TRANS(Bicc, ALL, do_bpcc, a) +TRANS(BPcc, 64, do_bpcc, a) + static bool trans_CALL(DisasContext *dc, arg_CALL *a) { target_long target =3D address_mask_i(dc, dc->pc + a->i * 4); @@ -3083,21 +3100,7 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) switch (xop) { #ifdef TARGET_SPARC64 case 0x1: /* V9 BPcc */ - { - int cc; - - target =3D GET_FIELD_SP(insn, 0, 18); - target =3D sign_extend(target, 19); - target <<=3D 2; - cc =3D GET_FIELD_SP(insn, 20, 21); - if (cc =3D=3D 0) - do_branch(dc, target, insn, 0); - else if (cc =3D=3D 2) - do_branch(dc, target, insn, 1); - else - goto illegal_insn; - goto jmp_insn; - } + g_assert_not_reached(); /* in decodetree */ case 0x3: /* V9 BPr */ { target =3D GET_FIELD_SP(insn, 0, 13) | @@ -3127,13 +3130,7 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) } #endif case 0x2: /* BN+x */ - { - target =3D GET_FIELD(insn, 10, 31); - target =3D sign_extend(target, 22); - target <<=3D 2; - do_branch(dc, target, insn, 0); - goto jmp_insn; - } + g_assert_not_reached(); /* in decodetree */ case 0x6: /* FBN+x */ { if (gen_trap_ifnofpu(dc)) { --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279812583100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 56 ++++++++++++++++++++++---------- 1 file changed, 38 insertions(+), 18 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index ccf133db4b..4e850a29e5 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -555,6 +555,7 @@ static int tcg_out_setcond_int(TCGContext *s, TCGCond c= ond, TCGReg ret, case TCG_COND_GEU: /* -> LTU */ case TCG_COND_GT: /* -> LE */ case TCG_COND_GTU: /* -> LEU */ + case TCG_COND_TSTEQ: /* -> TSTNE */ cond =3D tcg_invert_cond(cond); flags ^=3D SETCOND_INV; break; @@ -611,6 +612,18 @@ static int tcg_out_setcond_int(TCGContext *s, TCGCond = cond, TCGReg ret, } break; =20 + case TCG_COND_TSTNE: + flags |=3D SETCOND_NEZ; + if (!c2) { + tcg_out_opc_and(s, ret, arg1, arg2); + } else if (arg2 >=3D 0 && arg2 <=3D 0xfff) { + tcg_out_opc_andi(s, ret, arg1, arg2); + } else { + tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP0, arg2); + tcg_out_opc_and(s, ret, arg1, TCG_REG_TMP0); + } + break; + case TCG_COND_LT: case TCG_COND_LTU: if (c2) { @@ -695,29 +708,36 @@ static void tcg_out_movcond(TCGContext *s, TCGCond co= nd, TCGReg ret, * Branch helpers */ =20 -static const struct { - LoongArchInsn op; - bool swap; -} tcg_brcond_to_loongarch[] =3D { - [TCG_COND_EQ] =3D { OPC_BEQ, false }, - [TCG_COND_NE] =3D { OPC_BNE, false }, - [TCG_COND_LT] =3D { OPC_BGT, true }, - [TCG_COND_GE] =3D { OPC_BLE, true }, - [TCG_COND_LE] =3D { OPC_BLE, false }, - [TCG_COND_GT] =3D { OPC_BGT, false }, - [TCG_COND_LTU] =3D { OPC_BGTU, true }, - [TCG_COND_GEU] =3D { OPC_BLEU, true }, - [TCG_COND_LEU] =3D { OPC_BLEU, false }, - [TCG_COND_GTU] =3D { OPC_BGTU, false } -}; - static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, TCGReg arg2, TCGLabel *l) { - LoongArchInsn op =3D tcg_brcond_to_loongarch[cond].op; + static const struct { + LoongArchInsn op; + bool swap; + } tcg_brcond_to_loongarch[16] =3D { + [TCG_COND_EQ] =3D { OPC_BEQ, false }, + [TCG_COND_NE] =3D { OPC_BNE, false }, + [TCG_COND_LT] =3D { OPC_BGT, true }, + [TCG_COND_GE] =3D { OPC_BLE, true }, + [TCG_COND_LE] =3D { OPC_BLE, false }, + [TCG_COND_GT] =3D { OPC_BGT, false }, + [TCG_COND_LTU] =3D { OPC_BGTU, true }, + [TCG_COND_GEU] =3D { OPC_BLEU, true }, + [TCG_COND_LEU] =3D { OPC_BLEU, false }, + [TCG_COND_GTU] =3D { OPC_BGTU, false } + }; =20 + LoongArchInsn op; + + if (is_tst_cond(cond)) { + tcg_out_opc_and(s, TCG_REG_TMP0, arg1, arg2); + arg1 =3D TCG_REG_TMP0; + arg2 =3D TCG_REG_ZERO; + cond =3D tcg_tst_eqne_cond(cond); + } + + op =3D tcg_brcond_to_loongarch[cond].op tcg_debug_assert(op !=3D 0); - if (tcg_brcond_to_loongarch[cond].swap) { TCGReg t =3D arg1; arg1 =3D arg2; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279696098100009 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 ++ target/sparc/translate.c | 63 ++++++++++++++------------------------- 2 files changed, 25 insertions(+), 41 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 15cd975f4e..838f4cdb1d 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -7,4 +7,7 @@ BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=3D0 =20 +%d16 20:s2 0:14 +BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=3D%d16 + CALL 01 i:s30 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 92ea6bab6b..2d08c81821 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1336,14 +1336,13 @@ static void gen_fcond(TCGv r_dst, unsigned int cc, = unsigned int cond) } } =20 -#ifdef TARGET_SPARC64 // Inverted logic -static const int gen_tcg_cond_reg[8] =3D { - -1, +static const TCGCond gen_tcg_cond_reg[8] =3D { + TCG_COND_NEVER, /* reserved */ TCG_COND_NE, TCG_COND_GT, TCG_COND_GE, - -1, + TCG_COND_NEVER, /* reserved */ TCG_COND_EQ, TCG_COND_LE, TCG_COND_LT, @@ -1357,16 +1356,6 @@ static void gen_compare_reg(DisasCompare *cmp, int c= ond, TCGv r_src) cmp->c2 =3D tcg_constant_tl(0); } =20 -static void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) -{ - DisasCompare cmp; - gen_compare_reg(&cmp, cond, r_src); - - /* The interface is to return a boolean in r_dst. */ - tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2); -} -#endif - static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, in= t cc) { unsigned int cond =3D GET_FIELD(insn, 3, 6), a =3D (insn & (1 << 29)); @@ -1406,24 +1395,6 @@ static void do_fbranch(DisasContext *dc, int32_t off= set, uint32_t insn, int cc) } =20 #ifdef TARGET_SPARC64 -static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn, - TCGv r_reg) -{ - unsigned int cond =3D GET_FIELD_SP(insn, 25, 27), a =3D (insn & (1 << = 29)); - target_ulong target =3D dc->pc + offset; - - if (unlikely(AM_CHECK(dc))) { - target &=3D 0xffffffffULL; - } - flush_cond(dc); - gen_cond_reg(cpu_cond, cond, r_reg); - if (a) { - gen_branch_a(dc, target); - } else { - gen_branch_n(dc, target); - } -} - static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) { switch (fccno) { @@ -3063,6 +3034,24 @@ static bool do_bpcc(DisasContext *dc, arg_bcc *a) TRANS(Bicc, ALL, do_bpcc, a) TRANS(BPcc, 64, do_bpcc, a) =20 +static bool trans_BPr(DisasContext *dc, arg_BPr *a) +{ + target_long target =3D address_mask_i(dc, dc->pc + a->i * 4); + DisasCompare cmp; + + if (!avail_64(dc)) { + return false; + } + if (gen_tcg_cond_reg[a->cond] =3D=3D TCG_COND_NEVER) { + return false; + } + + flush_cond(dc); + gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1)); + tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2); + return advance_jump_cond(dc, a->a, target); +} + static bool trans_CALL(DisasContext *dc, arg_CALL *a) { target_long target =3D address_mask_i(dc, dc->pc + a->i * 4); @@ -3102,15 +3091,7 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) case 0x1: /* V9 BPcc */ g_assert_not_reached(); /* in decodetree */ case 0x3: /* V9 BPr */ - { - target =3D GET_FIELD_SP(insn, 0, 13) | - (GET_FIELD_SP(insn, 20, 21) << 14); - target =3D sign_extend(target, 16); - target <<=3D 2; - cpu_src1 =3D get_src1(dc, insn); - do_branch_reg(dc, target, insn, cpu_src1); - goto jmp_insn; - } + g_assert_not_reached(); /* in decodetree */ case 0x5: /* V9 FBPcc */ { int cc =3D GET_FIELD_SP(insn, 20, 21); --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.16.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:16:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279368; x=1698884168; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=rVEq4DsEieVQejMYJAckiF1y6NMA1Ry2WtOvV/eWoA0=; b=VauoG9ksV41UCMumbIebMMTS1iP6WUnHCYRa+LFJ0Mlw4rdeswa2+R6nVePXnOC6TC /i1KLtKikfZvdal+TrswSgK5+TXIy1gZmECCWhrYUuC1WtezHvjLNEMKcnazTHJkaqIo NXouVhbnDWkoUJiv4GFyhwd1qPwBIYfja1fJSVUt/ozM0FndGAh/HJO2PPCnORBxh4R2 qddwNqXjJUPgxT4w3IzjdmuT8Su71E9hPlf6DDPPYGLR4e+GtP+aSKq3OmM4o08HocfP OvK0upql9/nhRYwswawLxkcfpZ/jo5cChjoFzAcoUGPEWgZgnG108z2Z2obu2+gxdo1C okng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279368; x=1698884168; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rVEq4DsEieVQejMYJAckiF1y6NMA1Ry2WtOvV/eWoA0=; b=qUYldmdW9tQ/ROLYn+ka6349kJR6Uop0cCJryNhdZeO7H5n1CitfCctzCrZ4VrXrsD MVjjj2nnElUWwEGp6EEmUGBrGR44+i+yzlFr/uTLgMr8hllNrwgMUymCKEOhaEuwBgXS elPbC0QXQOjVbNJ/1lVU//E0VZpivzf0pAHoHWrB+/pJ/bhm6nWNCQcxAlzY8Va75Wlp cwRbiaSQ9rXh877AnVWxdAqrw27htfGLi/NxbAol0jnJc9rD9jNAeZkyQGSvTxwp4dPj kG+MNUMDNw98P742Eoox0H1nLAW7CKnyTRiDZxnYY82zvy/RJwuCIsjERBwgiq9xINDp ylUw== X-Gm-Message-State: AOJu0YwD23VsOhLe9JZvfdyTD3DarfPR/Yhf1svHIBkcR4mXbrweRElE wk6OKzRGCa/DQqSHDhbMnr7cIAjW2rvqWR3OLOo= X-Google-Smtp-Source: AGHT+IF+yaS1zFtd4uu3Tc3bp8nTR+VC7SIT7Ake6MkADBlmzdR+YJrWJBaldWUsebo/qHZt/a/nXw== X-Received: by 2002:a17:902:d904:b0:1c0:d7a9:1c48 with SMTP id c4-20020a170902d90400b001c0d7a91c48mr12285786plz.49.1698279368634; Wed, 25 Oct 2023 17:16:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 15/29] tcg/mips: Support TCG_COND_TST{EQ,NE} Date: Wed, 25 Oct 2023 17:14:09 -0700 Message-Id: <20231026001542.1141412-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280175716100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 41 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 328984ccff..739a0f60b7 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -909,6 +909,16 @@ static void tcg_out_setcond(TCGContext *s, TCGCond con= d, TCGReg ret, tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1); break; =20 + case TCG_COND_TSTEQ: + tcg_out_opc_reg(s, OPC_AND, ret, arg1, arg2); + tcg_out_opc_imm(s, OPC_SLTIU, ret, ret, 1); + break; + + case TCG_COND_TSTNE: + tcg_out_opc_reg(s, OPC_AND, ret, arg1, arg2); + tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, ret); + break; + case TCG_COND_LT: case TCG_COND_GE: case TCG_COND_LE: @@ -989,6 +999,14 @@ static void tcg_out_brcond(TCGContext *s, TCGCond cond= , TCGReg arg1, arg2 =3D TCG_REG_ZERO; break; =20 + case TCG_COND_TSTEQ: + case TCG_COND_TSTNE: + tcg_out_opc_reg(s, OPC_AND, TCG_TMP0, arg1, arg2); + arg1 =3D TCG_TMP0; + arg2 =3D TCG_REG_ZERO; + b_opc =3D cond =3D=3D TCG_COND_TSTEQ ? OPC_BEQ : OPC_BNE; + break; + default: g_assert_not_reached(); break; @@ -1052,6 +1070,14 @@ static void tcg_out_setcond2(TCGContext *s, TCGCond = cond, TCGReg ret, tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO); break; =20 + case TCG_COND_TSTEQ: + case TCG_COND_TSTNE: + tcg_out_opc_reg(s, OPC_AND, TCG_TMP0, al, bl); + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, ah, bh); + tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); + tcg_out_setcond(s, tcg_eqne_cond(cond), ret, tmp1, TCG_REG_ZERO); + break; + default: tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh); tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl); @@ -1078,6 +1104,13 @@ static void tcg_out_brcond2(TCGContext *s, TCGCond c= ond, TCGReg al, TCGReg ah, tmp =3D tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh); break; =20 + case TCG_COND_TSTEQ: + case TCG_COND_TSTNE: + tcg_out_opc_reg(s, OPC_AND, TCG_TMP0, al, bl); + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, ah, bh); + tcg_out_opc_reg(s, OPC_OR, TCG_TMP1, TCG_TMP1, TCG_TMP0); + break; + default: /* Minimize code size by preferring a compare not requiring INV. = */ if (mips_cmp_map[cond] & MIPS_CMP_INV) { @@ -1114,6 +1147,14 @@ static void tcg_out_movcond(TCGContext *s, TCGCond c= ond, TCGReg ret, } break; =20 + case TCG_COND_TSTEQ: + eqz =3D true; + /* FALLTHRU */ + case TCG_COND_TSTNE: + tcg_out_opc_reg(s, OPC_AND, TCG_TMP0, c1, c2); + c1 =3D TCG_TMP0; + break; + default: /* Minimize code size by preferring a compare not requiring INV. = */ if (mips_cmp_map[cond] & MIPS_CMP_INV) { --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280973; cv=none; d=zohomail.com; s=zohoarc; b=esbP0Dd8Ss1fbI4TNUy3fWWzDPPF5Xf3QVl9xiJ6W+1TzfhYi325NjwKsRR1sadQK3nOb0ExxZJlLLuS0L/a2mEgtgMarwP765JxsUNXVxJuVRujv0FgMP6cqqyO8XxZ831c8HwotMkgc/oZ6uqEye8fURUxYZFHDoAOpBcbaSQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280973; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=aVUF256SJzOtZnYyvhHTuu241VktS0Mu9MeLZNCREB4=; b=B593OOlDqU6XLsIxZUNaiKYTOMUTODEAd8hv5LpkmC7ntI7oQ0pzwLy43i/hrtTzyf43s6lBka5mWx8kZvcI7mUsiPcpD8Jof6519/ZuoPqH3W+G15i2Br9wbKXtfZoKqE+hbJ1si3KMOPAb1kQAHIuBJrK/GsJZQjHRNixj1R4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169828097324633.41651409868007; Wed, 25 Oct 2023 17:42:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo2x-0007KK-Te; Wed, 25 Oct 2023 20:16:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo2q-00074v-9C for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:16 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo2k-0004sk-JR for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:16 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1caa7597af9so2155305ad.1 for ; Wed, 25 Oct 2023 17:16:08 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.16.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:16:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279368; x=1698884168; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aVUF256SJzOtZnYyvhHTuu241VktS0Mu9MeLZNCREB4=; b=h1Jcw7pvbQfpc/L55J/HnPVwdnsaDT2q/1qXieAq4IAdXuw4pFgFUDYEEC8+a1ANs4 0YsT57t+//zeh6SlxrLwfbhQ/TygtBHPzJ/4kWWznvTBHNp26AUCNIAkRUrwx+KfZUsI 7oQE0uwNT4PBQ/4puAfuKSIYbTeiYh4FRqtgnCpaB2xCoGeQm7RuZU/8DTQ7jm+GLO4z FSccb0YiX7ikGws+efRMxLe7zT0SdVsJCrqvxvkp7mpawSx/XTG6VXnXdn0F07tiRGnQ vjRJtEUB/4ur6UNh7r8iQzwtMMBTcQWe4Mj7qUJ/tjG2IfdUH5MUAwkFGA7eGHrwnzh2 SoSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279368; x=1698884168; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280975095100015 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++ target/sparc/translate.c | 102 +++++++++++++++----------------------- 2 files changed, 43 insertions(+), 63 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 838f4cdb1d..9ab3f2eb82 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -6,8 +6,12 @@ &bcc i a cond cc BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=3D0 +FBPfcc 00 a:1 cond:4 101 cc:2 - i:s19 &bcc +FBfcc 00 a:1 cond:4 110 i:s22 &bcc cc=3D0 =20 %d16 20:s2 0:14 BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=3D%d16 =20 +NCP 00 - ---- 111 ---------------------- # CBcc + CALL 01 i:s30 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 2d08c81821..69e85b1842 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1356,44 +1356,6 @@ static void gen_compare_reg(DisasCompare *cmp, int c= ond, TCGv r_src) cmp->c2 =3D tcg_constant_tl(0); } =20 -static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, in= t cc) -{ - unsigned int cond =3D GET_FIELD(insn, 3, 6), a =3D (insn & (1 << 29)); - target_ulong target =3D dc->pc + offset; - - if (unlikely(AM_CHECK(dc))) { - target &=3D 0xffffffffULL; - } - if (cond =3D=3D 0x0) { - /* unconditional not taken */ - if (a) { - dc->pc =3D dc->npc + 4; - dc->npc =3D dc->pc + 4; - } else { - dc->pc =3D dc->npc; - dc->npc =3D dc->pc + 4; - } - } else if (cond =3D=3D 0x8) { - /* unconditional taken */ - if (a) { - dc->pc =3D target; - dc->npc =3D dc->pc + 4; - } else { - dc->pc =3D dc->npc; - dc->npc =3D target; - tcg_gen_mov_tl(cpu_pc, cpu_npc); - } - } else { - flush_cond(dc); - gen_fcond(cpu_cond, cc, cond); - if (a) { - gen_branch_a(dc, target); - } else { - gen_branch_n(dc, target); - } - } -} - #ifdef TARGET_SPARC64 static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) { @@ -3034,6 +2996,28 @@ static bool do_bpcc(DisasContext *dc, arg_bcc *a) TRANS(Bicc, ALL, do_bpcc, a) TRANS(BPcc, 64, do_bpcc, a) =20 +static bool do_fbpfcc(DisasContext *dc, arg_bcc *a) +{ + target_long target =3D address_mask_i(dc, dc->pc + a->i * 4); + + if (gen_trap_ifnofpu(dc)) { + return true; + } + switch (a->cond) { + case 0x0: + return advance_jump_uncond_never(dc, a->a); + case 0x8: + return advance_jump_uncond_always(dc, a->a, target); + default: + flush_cond(dc); + gen_fcond(cpu_cond, a->cc, a->cond); + return advance_jump_cond(dc, a->a, target); + } +} + +TRANS(FBPfcc, 64, do_fbpfcc, a) +TRANS(FBfcc, ALL, do_fbpfcc, a) + static bool trans_BPr(DisasContext *dc, arg_BPr *a) { target_long target =3D address_mask_i(dc, dc->pc + a->i * 4); @@ -3062,6 +3046,20 @@ static bool trans_CALL(DisasContext *dc, arg_CALL *a) return true; } =20 +static bool trans_NCP(DisasContext *dc, arg_NCP *a) +{ + /* + * For sparc32, always generate the no-coprocessor exception. + * For sparc64, always generate illegal instruction. + */ +#ifdef TARGET_SPARC64 + return false; +#else + gen_exception(dc, TT_NCP_INSN); + return true; +#endif +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -3085,7 +3083,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) case 0: /* branches/sethi */ { unsigned int xop =3D GET_FIELD(insn, 7, 9); - int32_t target; switch (xop) { #ifdef TARGET_SPARC64 case 0x1: /* V9 BPcc */ @@ -3093,36 +3090,15 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 0x3: /* V9 BPr */ g_assert_not_reached(); /* in decodetree */ case 0x5: /* V9 FBPcc */ - { - int cc =3D GET_FIELD_SP(insn, 20, 21); - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - target =3D GET_FIELD_SP(insn, 0, 18); - target =3D sign_extend(target, 19); - target <<=3D 2; - do_fbranch(dc, target, insn, cc); - goto jmp_insn; - } + g_assert_not_reached(); /* in decodetree */ #else case 0x7: /* CBN+x */ - { - goto ncp_insn; - } + g_assert_not_reached(); /* in decodetree */ #endif case 0x2: /* BN+x */ g_assert_not_reached(); /* in decodetree */ case 0x6: /* FBN+x */ - { - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - target =3D GET_FIELD(insn, 10, 31); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279738218100009 Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/sparc/translate.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 69e85b1842..2664db302d 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1309,20 +1309,6 @@ static void gen_fcompare(DisasCompare *cmp, unsigned= int cc, unsigned int cond) } } =20 -static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond, - DisasContext *dc) -{ - DisasCompare cmp; - gen_compare(&cmp, cc, cond, dc); - - /* The interface is to return a boolean in r_dst. */ - if (cmp.is_bool) { - tcg_gen_mov_tl(r_dst, cmp.c1); - } else { - tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2); - } -} - static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) { DisasCompare cmp; @@ -2980,6 +2966,7 @@ static bool advance_jump_cond(DisasContext *dc, bool = annul, target_ulong dest) static bool do_bpcc(DisasContext *dc, arg_bcc *a) { target_long target =3D address_mask_i(dc, dc->pc + a->i * 4); + DisasCompare cmp; =20 switch (a->cond) { case 0x0: @@ -2988,7 +2975,13 @@ static bool do_bpcc(DisasContext *dc, arg_bcc *a) return advance_jump_uncond_always(dc, a->a, target); default: flush_cond(dc); - gen_cond(cpu_cond, a->cc, a->cond, dc); + + gen_compare(&cmp, a->cc, a->cond, dc); + if (cmp.is_bool) { + tcg_gen_mov_tl(cpu_cond, cmp.c1); + } else { + tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2); + } return advance_jump_cond(dc, a->a, target); } } --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279441533100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 34e10e77d9..3997e2f274 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -798,8 +798,14 @@ static const struct { static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, TCGReg arg2, TCGLabel *l) { - RISCVInsn op =3D tcg_brcond_to_riscv[cond].op; + RISCVInsn op; =20 + if (is_tst_cond(cond)) { + tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP0, arg1, arg2); + cond =3D tcg_tst_eqne_cond(cond); + } + + op =3D tcg_brcond_to_riscv[cond].op; tcg_debug_assert(op !=3D 0); =20 if (tcg_brcond_to_riscv[cond].swap) { @@ -827,6 +833,7 @@ static int tcg_out_setcond_int(TCGContext *s, TCGCond c= ond, TCGReg ret, case TCG_COND_GEU: /* -> LTU */ case TCG_COND_GT: /* -> LE */ case TCG_COND_GTU: /* -> LEU */ + case TCG_COND_TSTEQ: /* -> TSTNE */ cond =3D tcg_invert_cond(cond); flags ^=3D SETCOND_INV; break; @@ -886,6 +893,15 @@ static int tcg_out_setcond_int(TCGContext *s, TCGCond = cond, TCGReg ret, } break; =20 + case TCG_COND_TSTNE: + flags |=3D SETCOND_NEZ; + if (c2) { + tcg_out_opc_imm(s, OPC_ANDI, ret, arg1, arg2); + } else { + tcg_out_opc_reg(s, OPC_AND, ret, arg1, arg2); + } + break; + case TCG_COND_LT: if (c2) { tcg_out_opc_imm(s, OPC_SLTI, ret, arg1, arg2); @@ -1079,7 +1095,7 @@ static void tcg_out_movcond(TCGContext *s, TCGCond co= nd, TCGReg ret, int tmpflags; TCGReg t; =20 - if (!have_zicond && (!c_cmp2 || cmp2 =3D=3D 0)) { + if (!have_zicond && (!c_cmp2 || cmp2 =3D=3D 0) && !is_tst_cond(cond)) { tcg_out_movcond_br2(s, cond, ret, cmp1, cmp2, val1, c_val1, val2, c_val2); return; --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279696; cv=none; d=zohomail.com; s=zohoarc; b=KB2IXwZPbcN0TGORuMffmIXGHNqMjo4ZOnXGti4/LkJoNzeJJqF4h7NINHdexHEsPdi82u4sXrIqF5Abav/mNbDvzmc4rY1wk4jI3ixIGDojmwG6+5nE6fzLy1n4xPC9q3iv1G92uks80M4aH9W7NJ/teB6/A2/i1wYzVwYuEcg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279696; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Cc: qemu-stable@nongnu.org Fixes: b8b94ac6753 ("tcg: Split out tcg_out_extrl_i64_i32") Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 19d9df4a09..a91defd0ac 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -529,6 +529,11 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg= rd, TCGReg rs) tcg_out_ext32u(s, rd, rs); } =20 +static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_ext32u(s, rd, rs); +} + static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) { return false; --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279529; cv=none; d=zohomail.com; s=zohoarc; b=I6Takp8rbnmq+DQCj2+QTaZYNniE6TrrGUh1FzA8SRKUUtPHvzYPdNE4b6RKw5BAZ3gLxy7qZ8P8/n2oIPpxCd53Rjko6phvleiS/ifmxLrKX5D2HgpI8Sj+1mKyyJ15S7CQ541Rf8LMA9e1+cQy2+DZhxVnZkpmnXkXLnhA3Og= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279529; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=aIOAJWBVtCMbS0c4KC6cXcYTMMaXIG2tg2FWJOn2ue8=; b=KTM9ed7wO6KiWiYHrGBKSeM3UVi/GpfkllzmR2toDgkHpMk0/mXc+apds2hoSyAvFgODrtKtcy9zf4xvdrIMM6g1aqYOBI1jTudscFFH93lZAF0geyoVg3rHtaFJSnZs13hMOVc+xqhT3DP7gHYk4LWwSuFuXgzMTiJk3t8vU/4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698279529262419.5228844575249; Wed, 25 Oct 2023 17:18:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo3B-0007Pl-Bm; Wed, 25 Oct 2023 20:16:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo2r-00076i-Hk for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:17 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo2m-0004tl-Fr for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:17 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1c77449a6daso2337045ad.0 for ; Wed, 25 Oct 2023 17:16:12 -0700 (PDT) Received: from stoup.. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279529805100001 Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/sparc/translate.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 2664db302d..b8d51d6d64 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1309,19 +1309,6 @@ static void gen_fcompare(DisasCompare *cmp, unsigned= int cc, unsigned int cond) } } =20 -static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) -{ - DisasCompare cmp; - gen_fcompare(&cmp, cc, cond); - - /* The interface is to return a boolean in r_dst. */ - if (cmp.is_bool) { - tcg_gen_mov_tl(r_dst, cmp.c1); - } else { - tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2); - } -} - // Inverted logic static const TCGCond gen_tcg_cond_reg[8] =3D { TCG_COND_NEVER, /* reserved */ @@ -2992,6 +2979,7 @@ TRANS(BPcc, 64, do_bpcc, a) static bool do_fbpfcc(DisasContext *dc, arg_bcc *a) { target_long target =3D address_mask_i(dc, dc->pc + a->i * 4); + DisasCompare cmp; =20 if (gen_trap_ifnofpu(dc)) { return true; @@ -3003,7 +2991,13 @@ static bool do_fbpfcc(DisasContext *dc, arg_bcc *a) return advance_jump_uncond_always(dc, a->a, target); default: flush_cond(dc); - gen_fcond(cpu_cond, a->cc, a->cond); + + gen_fcompare(&cmp, a->cc, a->cond); + if (cmp.is_bool) { + tcg_gen_mov_tl(cpu_cond, cmp.c1); + } else { + tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2); + } return advance_jump_cond(dc, a->a, target); } } --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index a91defd0ac..13ad92b9b6 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -619,7 +619,7 @@ static const uint8_t tcg_cond_to_bcond[] =3D { [TCG_COND_GTU] =3D COND_GU, }; =20 -static const uint8_t tcg_cond_to_rcond[] =3D { +static const uint8_t tcg_cond_to_rcond[16] =3D { [TCG_COND_EQ] =3D RCOND_Z, [TCG_COND_NE] =3D RCOND_NZ, [TCG_COND_LT] =3D RCOND_LZ, @@ -678,7 +678,8 @@ static void tcg_out_brcond_i64(TCGContext *s, TCGCond c= ond, TCGReg arg1, int32_t arg2, int const_arg2, TCGLabel *l) { /* For 64-bit signed comparisons vs zero, we can avoid the compare. */ - if (arg2 =3D=3D 0 && !is_unsigned_cond(cond)) { + int rcond =3D tcg_cond_to_rcond[cond]; + if (arg2 =3D=3D 0 && rcond) { int off16 =3D 0; =20 if (l->has_value) { @@ -687,7 +688,7 @@ static void tcg_out_brcond_i64(TCGContext *s, TCGCond c= ond, TCGReg arg1, tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP16, l, 0); } tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1) - | INSN_COND(tcg_cond_to_rcond[cond]) | off16); + | INSN_COND(rcond) | off16); } else { tcg_out_cmp(s, arg1, arg2, const_arg2); tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, l); @@ -695,11 +696,10 @@ static void tcg_out_brcond_i64(TCGContext *s, TCGCond= cond, TCGReg arg1, tcg_out_nop(s); } =20 -static void tcg_out_movr(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg c= 1, +static void tcg_out_movr(TCGContext *s, int rcond, TCGReg ret, TCGReg c1, int32_t v1, int v1const) { - tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1) - | (tcg_cond_to_rcond[cond] << 10) + tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1) | (rcond << 10) | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1))); } =20 @@ -710,9 +710,9 @@ static void tcg_out_movcond_i64(TCGContext *s, TCGCond = cond, TCGReg ret, /* For 64-bit signed comparisons vs zero, we can avoid the compare. Note that the immediate range is one bit smaller, so we must check for that as well. */ - if (c2 =3D=3D 0 && !is_unsigned_cond(cond) - && (!v1const || check_fit_i32(v1, 10))) { - tcg_out_movr(s, cond, ret, c1, v1, v1const); + int rcond =3D tcg_cond_to_rcond[cond]; + if (c2 =3D=3D 0 && rcond && (!v1const || check_fit_i32(v1, 10))) { + tcg_out_movr(s, rcond, ret, c1, v1, v1const); } else { tcg_out_cmp(s, c1, c2, c2const); tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const); @@ -787,6 +787,8 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond = cond, TCGReg ret, static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg c1, int32_t c2, int c2const, bool n= eg) { + int rcond; + if (use_vis3_instructions && !neg) { switch (cond) { case TCG_COND_NE: @@ -806,9 +808,10 @@ static void tcg_out_setcond_i64(TCGContext *s, TCGCond= cond, TCGReg ret, =20 /* For 64-bit signed comparisons vs zero, we can avoid the compare if the input does not overlap the output. */ - if (c2 =3D=3D 0 && !is_unsigned_cond(cond) && c1 !=3D ret) { + rcond =3D tcg_cond_to_rcond[cond]; + if (c2 =3D=3D 0 && rcond && c1 !=3D ret) { tcg_out_movi_s13(s, ret, 0); - tcg_out_movr(s, cond, ret, c1, neg ? -1 : 1, 1); + tcg_out_movr(s, rcond, ret, c1, neg ? -1 : 1, 1); } else { tcg_out_cmp(s, c1, c2, c2const); tcg_out_movi_s13(s, ret, 0); --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280971; cv=none; d=zohomail.com; s=zohoarc; b=KpwQDr942bFAKGefEqwmWQU5dhMOIHMYAOJrn3Lx1jwJH/lzOAgd/NIFiimWIggAQKxo218CJ99cXV2fCPhXToTw75sJcuNZ+P4RmGvkaJD3PT+Fc3Fw1vvc48yripb0fX5QJTWUayFRTYfSX8omAwMZs7NrPfQIGFjTm2fALoU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280971; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=D3CDbvxaTN0BxklWFCzrNGwroWfsphJJp/UH4zaunfY=; b=CBz+B2nVWxuzAhsMJItwWRHWUCY7/IFyOgVui+SGR9WPUKTkRom4yTXeIaJbkK2UI+sEIKPK7Q4Hf1UE4isRWYWiRlp+k7T5ji1xUgvi/covPYE8ex8odfQWapPxihIP3j2ww1BYfwFZG/+phkEl9xy4kofcg5eFMvsotCs/pNU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698280971830537.9132943479755; Wed, 25 Oct 2023 17:42:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo2x-0007Ju-J9; Wed, 25 Oct 2023 20:16:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo2t-0007AK-Br for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:19 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo2n-0004ud-Ta for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:19 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1ca72f8ff3aso2323335ad.0 for ; Wed, 25 Oct 2023 17:16:13 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280973068100011 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 73 +++++++++++++++++----------------------- 1 file changed, 30 insertions(+), 43 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index b8d51d6d64..503598ed93 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -900,47 +900,6 @@ static void gen_branch2(DisasContext *dc, target_ulong= pc1, gen_goto_tb(dc, 1, pc2, pc2 + 4); } =20 -static void gen_branch_a(DisasContext *dc, target_ulong pc1) -{ - TCGLabel *l1 =3D gen_new_label(); - target_ulong npc =3D dc->npc; - - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1); - - gen_goto_tb(dc, 0, npc, pc1); - - gen_set_label(l1); - gen_goto_tb(dc, 1, npc + 4, npc + 8); - - dc->base.is_jmp =3D DISAS_NORETURN; -} - -static void gen_branch_n(DisasContext *dc, target_ulong pc1) -{ - target_ulong npc =3D dc->npc; - - if (npc & 3) { - switch (npc) { - case DYNAMIC_PC: - case DYNAMIC_PC_LOOKUP: - tcg_gen_mov_tl(cpu_pc, cpu_npc); - tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); - tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, - cpu_cond, tcg_constant_tl(0), - tcg_constant_tl(pc1), cpu_npc); - dc->pc =3D npc; - break; - default: - g_assert_not_reached(); - } - } else { - dc->pc =3D npc; - dc->jump_pc[0] =3D pc1; - dc->jump_pc[1] =3D npc + 4; - dc->npc =3D JUMP_PC; - } -} - static void gen_generic_branch(DisasContext *dc) { TCGv npc0 =3D tcg_constant_tl(dc->jump_pc[0]); @@ -2942,10 +2901,38 @@ static bool advance_jump_uncond_always(DisasContext= *dc, bool annul, =20 static bool advance_jump_cond(DisasContext *dc, bool annul, target_ulong d= est) { + target_ulong npc =3D dc->npc; + if (annul) { - gen_branch_a(dc, dest); + TCGLabel *l1 =3D gen_new_label(); + + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1); + gen_goto_tb(dc, 0, npc, dest); + gen_set_label(l1); + gen_goto_tb(dc, 1, npc + 4, npc + 8); + + dc->base.is_jmp =3D DISAS_NORETURN; } else { - gen_branch_n(dc, dest); + if (npc & 3) { + switch (npc) { + case DYNAMIC_PC: + case DYNAMIC_PC_LOOKUP: + tcg_gen_mov_tl(cpu_pc, cpu_npc); + tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); + tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, + cpu_cond, tcg_constant_tl(0), + tcg_constant_tl(dest), cpu_npc); + dc->pc =3D npc; + break; + default: + g_assert_not_reached(); + } + } else { + dc->pc =3D npc; + dc->jump_pc[0] =3D dest; + dc->jump_pc[1] =3D npc + 4; + dc->npc =3D JUMP_PC; + } } return true; } --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.16.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:16:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279374; x=1698884174; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Die0E9thWWJCvlQ5xUUN0v+CHdwVm8XQRwC6LlIs3H8=; b=A5XwRmpsjEPyFLPEB/9X2gZ83oXiKRVKELx6duFkJwn0XQRthmr15g6cllYQPX/0Oa SYMCw6A+oZ5Xa3RQzMyaAQf4ckoMWyvxhg33Bp7hZCCw0r7Gqtb+mH1o/dZ7ZNG8rlgv qpYCgke7GONysd8sZXSHEwy20TJMjwnMGCqymkz2EM9CVznlu/mRtQ9/DY4Ns4MJ4DYs U1H2rMyhCzbz7WDjCGBX3TnatelFZqZA3gyTce8qSzIAJWq3vGOV1F5LOT88z1yA1DxD QnszUnjuHjz05YJ15kfJbAPJwmhPt7attK7o2t40H3HV3/OfCEgPj3StR49EhcqThFba qogw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279374; x=1698884174; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Die0E9thWWJCvlQ5xUUN0v+CHdwVm8XQRwC6LlIs3H8=; b=p92Mjfd04Fm45Uikhgc35r/FjBENnvrjXlFXemtODAV8BitVMin2mmCOznmBDKQ3hr DHL7lTFURxQjf8yEQ04mLgvUddEXMJVdrkVDT9E0x2usasRnAjHQISv64BFfXiL+6C/s YsHCeuNT4jZEm32wApcSWD3WNp6Yt83zedBaAU1XOCTZkUBz2Fje52Bl82YLXKz9uzli Dtusqe838u4DKCVuy37rayR168V8xLWalRGxEYi8jkxt1N6MyQS2Fr8OcptzNbeuQ8gs AVpTN3CgNFYQB5Fci81etGKlNdluq0712AKXjccNPhLT3hcdfOIulE0dWoWsM/xoPF9w Hfbg== X-Gm-Message-State: AOJu0YyU6u9KCp+4p1ewiBmcqi6ZF7kJfc9ySeJbPAPVPCksLe+O+zvH kdROJ74UwgaFWCeos9eLR6pcNtgxIpBOjz/F5JU= X-Google-Smtp-Source: AGHT+IE8i6BjrU8owR23quEVcVeBw3uHBYhA39+MkiuIYQUqjKDIqUGH+h+PYWPWnFrcdPrpscszkQ== X-Received: by 2002:a17:903:27d0:b0:1c9:ccb3:2352 with SMTP id km16-20020a17090327d000b001c9ccb32352mr16129432plb.12.1698279374429; Wed, 25 Oct 2023 17:16:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 19/94] target/sparc: Pass DisasCompare to advance_jump_cond Date: Wed, 25 Oct 2023 17:14:16 -0700 Message-Id: <20231026001542.1141412-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280281918100009 Content-Type: text/plain; charset="utf-8" Fold the condition into the branch or movcond when possible. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 503598ed93..d12f2b4b87 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2899,14 +2899,15 @@ static bool advance_jump_uncond_always(DisasContext= *dc, bool annul, return true; } =20 -static bool advance_jump_cond(DisasContext *dc, bool annul, target_ulong d= est) +static bool advance_jump_cond(DisasContext *dc, DisasCompare *cmp, + bool annul, target_ulong dest) { target_ulong npc =3D dc->npc; =20 if (annul) { TCGLabel *l1 =3D gen_new_label(); =20 - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1); + tcg_gen_brcond_tl(tcg_invert_cond(cmp->cond), cmp->c1, cmp->c2, l1= ); gen_goto_tb(dc, 0, npc, dest); gen_set_label(l1); gen_goto_tb(dc, 1, npc + 4, npc + 8); @@ -2919,8 +2920,8 @@ static bool advance_jump_cond(DisasContext *dc, bool = annul, target_ulong dest) case DYNAMIC_PC_LOOKUP: tcg_gen_mov_tl(cpu_pc, cpu_npc); tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); - tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, - cpu_cond, tcg_constant_tl(0), + tcg_gen_movcond_tl(cmp->cond, cpu_npc, + cmp->c1, cmp->c2, tcg_constant_tl(dest), cpu_npc); dc->pc =3D npc; break; @@ -2932,6 +2933,11 @@ static bool advance_jump_cond(DisasContext *dc, bool= annul, target_ulong dest) dc->jump_pc[0] =3D dest; dc->jump_pc[1] =3D npc + 4; dc->npc =3D JUMP_PC; + if (cmp->is_bool) { + tcg_gen_mov_tl(cpu_cond, cmp->c1); + } else { + tcg_gen_setcond_tl(cmp->cond, cpu_cond, cmp->c1, cmp->c2); + } } } return true; @@ -2951,12 +2957,7 @@ static bool do_bpcc(DisasContext *dc, arg_bcc *a) flush_cond(dc); =20 gen_compare(&cmp, a->cc, a->cond, dc); - if (cmp.is_bool) { - tcg_gen_mov_tl(cpu_cond, cmp.c1); - } else { - tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2); - } - return advance_jump_cond(dc, a->a, target); + return advance_jump_cond(dc, &cmp, a->a, target); } } =20 @@ -2980,12 +2981,7 @@ static bool do_fbpfcc(DisasContext *dc, arg_bcc *a) flush_cond(dc); =20 gen_fcompare(&cmp, a->cc, a->cond); - if (cmp.is_bool) { - tcg_gen_mov_tl(cpu_cond, cmp.c1); - } else { - tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2); - } - return advance_jump_cond(dc, a->a, target); + return advance_jump_cond(dc, &cmp, a->a, target); } } =20 @@ -3006,8 +3002,7 @@ static bool trans_BPr(DisasContext *dc, arg_BPr *a) =20 flush_cond(dc); gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1)); - tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2); - return advance_jump_cond(dc, a->a, target); + return advance_jump_cond(dc, &cmp, a->a, target); } =20 static bool trans_CALL(DisasContext *dc, arg_CALL *a) --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279696108100010 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 13ad92b9b6..e958e3c242 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -645,7 +645,8 @@ static void tcg_out_bpcc(TCGContext *s, int scond, int = flags, TCGLabel *l) tcg_out_bpcc0(s, scond, flags, off19); } =20 -static void tcg_out_cmp(TCGContext *s, TCGReg c1, int32_t c2, int c2const) +static void tcg_out_cmp(TCGContext *s, TCGCond cond, + TCGReg c1, int32_t c2, int c2const) { tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC); } @@ -653,7 +654,7 @@ static void tcg_out_cmp(TCGContext *s, TCGReg c1, int32= _t c2, int c2const) static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1, int32_t arg2, int const_arg2, TCGLabel *l) { - tcg_out_cmp(s, arg1, arg2, const_arg2); + tcg_out_cmp(s, cond, arg1, arg2, const_arg2); tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, l); tcg_out_nop(s); } @@ -670,7 +671,7 @@ static void tcg_out_movcond_i32(TCGContext *s, TCGCond = cond, TCGReg ret, TCGReg c1, int32_t c2, int c2const, int32_t v1, int v1const) { - tcg_out_cmp(s, c1, c2, c2const); + tcg_out_cmp(s, cond, c1, c2, c2const); tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const); } =20 @@ -690,7 +691,7 @@ static void tcg_out_brcond_i64(TCGContext *s, TCGCond c= ond, TCGReg arg1, tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1) | INSN_COND(rcond) | off16); } else { - tcg_out_cmp(s, arg1, arg2, const_arg2); + tcg_out_cmp(s, cond, arg1, arg2, const_arg2); tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, l); } tcg_out_nop(s); @@ -714,7 +715,7 @@ static void tcg_out_movcond_i64(TCGContext *s, TCGCond = cond, TCGReg ret, if (c2 =3D=3D 0 && rcond && (!v1const || check_fit_i32(v1, 10))) { tcg_out_movr(s, rcond, ret, c1, v1, v1const); } else { - tcg_out_cmp(s, c1, c2, c2const); + tcg_out_cmp(s, cond, c1, c2, c2const); tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const); } } @@ -758,13 +759,13 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCon= d cond, TCGReg ret, /* FALLTHRU */ =20 default: - tcg_out_cmp(s, c1, c2, c2const); + tcg_out_cmp(s, cond, c1, c2, c2const); tcg_out_movi_s13(s, ret, 0); tcg_out_movcc(s, cond, MOVCC_ICC, ret, neg ? -1 : 1, 1); return; } =20 - tcg_out_cmp(s, c1, c2, c2const); + tcg_out_cmp(s, cond, c1, c2, c2const); if (cond =3D=3D TCG_COND_LTU) { if (neg) { /* 0 - 0 - C =3D -C =3D (C ? -1 : 0) */ @@ -798,7 +799,7 @@ static void tcg_out_setcond_i64(TCGContext *s, TCGCond = cond, TCGReg ret, c2 =3D c1, c2const =3D 0, c1 =3D TCG_REG_G0; /* FALLTHRU */ case TCG_COND_LTU: - tcg_out_cmp(s, c1, c2, c2const); + tcg_out_cmp(s, cond, c1, c2, c2const); tcg_out_arith(s, ret, TCG_REG_G0, TCG_REG_G0, ARITH_ADDXC); return; default: @@ -813,7 +814,7 @@ static void tcg_out_setcond_i64(TCGContext *s, TCGCond = cond, TCGReg ret, tcg_out_movi_s13(s, ret, 0); tcg_out_movr(s, rcond, ret, c1, neg ? -1 : 1, 1); } else { - tcg_out_cmp(s, c1, c2, c2const); + tcg_out_cmp(s, cond, c1, c2, c2const); tcg_out_movi_s13(s, ret, 0); tcg_out_movcc(s, cond, MOVCC_XCC, ret, neg ? -1 : 1, 1); } @@ -1101,7 +1102,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, tcg_out_movi_s32(s, TCG_REG_T3, compare_mask); tcg_out_arith(s, TCG_REG_T3, addr_reg, TCG_REG_T3, ARITH_AND); } - tcg_out_cmp(s, TCG_REG_T2, TCG_REG_T3, 0); + tcg_out_cmp(s, TCG_COND_NE, TCG_REG_T2, TCG_REG_T3, 0); =20 ldst =3D new_ldst_label(s); ldst->is_ld =3D is_ld; --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279557; x=1698884357; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=d+t3wVy/FdNCvxU+M502QkXc3hNFmFswkh6xHioaLL8=; b=LkIcs2R4+lDMocz4cT/MQkJZZJy0+SqxfU/x0BfGo3Y2hesmWPMRpMQ0WwYYc3c4h9 wcmPCT4a/MpHjvXibfX0tZAdP7kqLZid9at4YQS31+vRKVEaeljVvu+70fCIxF7wo4q9 vHMHyGvO/M2IW1iSRk34WU6urTTiyj+1794HkDXhHUxuTNjrNc75xk2GUODV0uX/73kJ w0c+0U/5oOoZjB3Oz0SDtp+lHXxSGCoF8xSA/n516XDManvh5SvZzD6ZAo3aETj1n1FL JRCcmXCcBLQu8C1zOX2hHtolr8NybBNTgMtUOMoiGVs6qGpxVxKAvC2a9owdj2mkmAkA tc4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279557; x=1698884357; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d+t3wVy/FdNCvxU+M502QkXc3hNFmFswkh6xHioaLL8=; b=V8TW2aLp8f8fZvV67+0vKI/C+HXw/D7MHFkE1CXttt1Cqbr4810zICQ0JTTs8Kd5Ev 5aIz1j6uDTwSoljRCunOmOGRZppR26ala8YaiMXwT9tKApVgnpq9cbggsXJWJ84gdfgm 7BgHjrAek0TwIADkvu+04ufkn1RfvWmWConKiFBbxqgZzrnW2LMWE3EGx0QxjKhXvWCX p7krnGtKOy+waQhenY3sXenDrLNP18uYpkUdKEQhdsE+TvDq/zoy8e9l/ZCucULTlvJv HzbPQmdniXI71qnbEvy4k6FMscEmOgy3YoY1tskzHHn72kxKcaAy0njuU8WE8yANutjT drhg== X-Gm-Message-State: AOJu0Yzi7x/8pY0W0Dz4t937ncY916uZjW+fngz+lUYcUSQPZ31LVPRF Sn8TaKumEydj5FsdAuEGQY7F7pjSuya8EsT8pYI= X-Google-Smtp-Source: AGHT+IFZRhJV3b1H9cELKCjJ290eAb/7DCAQZcuhm1x8z1jqsX5YibFUNdiW587p/NsbBLVsWjKCLQ== X-Received: by 2002:a17:902:dad2:b0:1c0:cbaf:6954 with SMTP id q18-20020a170902dad200b001c0cbaf6954mr1590652plx.25.1698279557581; Wed, 25 Oct 2023 17:19:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 20/29] tcg/sparc64: Support TCG_COND_TST{EQ,NE} Date: Wed, 25 Oct 2023 17:14:19 -0700 Message-Id: <20231026001542.1141412-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280708269100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index e958e3c242..feeb318c39 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -606,9 +606,11 @@ static void tcg_out_div32(TCGContext *s, TCGReg rd, TC= GReg rs1, uns ? ARITH_UDIV : ARITH_SDIV); } =20 -static const uint8_t tcg_cond_to_bcond[] =3D { +static const uint8_t tcg_cond_to_bcond[16] =3D { [TCG_COND_EQ] =3D COND_E, [TCG_COND_NE] =3D COND_NE, + [TCG_COND_TSTEQ] =3D COND_E, + [TCG_COND_TSTNE] =3D COND_NE, [TCG_COND_LT] =3D COND_L, [TCG_COND_GE] =3D COND_GE, [TCG_COND_LE] =3D COND_LE, @@ -648,7 +650,8 @@ static void tcg_out_bpcc(TCGContext *s, int scond, int = flags, TCGLabel *l) static void tcg_out_cmp(TCGContext *s, TCGCond cond, TCGReg c1, int32_t c2, int c2const) { - tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC); + tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, + is_tst_cond(cond) ? ARITH_ANDCC : ARITH_SUBCC); } =20 static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1, @@ -743,6 +746,15 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond= cond, TCGReg ret, cond =3D (cond =3D=3D TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU); break; =20 + case TCG_COND_TSTEQ: + case TCG_COND_TSTNE: + /* Transform to inequality vs zero. */ + tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_AND); + c1 =3D TCG_REG_G0; + c2 =3D TCG_REG_T1, c2const =3D 0; + cond =3D (cond =3D=3D TCG_COND_TSTEQ ? TCG_COND_GEU : TCG_COND_LTU= ); + break; + case TCG_COND_GTU: case TCG_COND_LEU: /* If we don't need to load a constant into a register, we can --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279592; cv=none; d=zohomail.com; s=zohoarc; b=kLgImaU3/uKRZZDSFlUkRWM/u5jCsmpShoMZAwFybFXPCdcRVEgH+cR8n0/FPjH/vhaO/7FETgwywLg7yIW1hrTQ8vIs7GV+XdVSCcaiLngWWelA92xqhildaldN+hmii4jpX1SBPm7EsnUAzwTEXEbdrm4fOOkuQHLwKug2nZc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279592; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5V/MzDPCPtSl5p/d34/PgkVJsUATuXtmCOJbzl0yEFY=; b=Lmuimjpmw00qCorxVxyhyCN9CSTE3o1VE9pXKWiOkSJSEv3Jw4KtP/e1f9SxxA2xR2hooxvr3acP9mIEk+RWxRUZXMxBrNKKCvE6XHE6oGVAMvulrEjjJpCjlBHCxH9jYlXAih3U3qwMm7ngZSWrxNxM37l9y/DNGKOVa0kJd4I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698279592387504.9169211511413; Wed, 25 Oct 2023 17:19:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo2z-0007Lb-2Z; Wed, 25 Oct 2023 20:16:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo2v-0007Gh-I5 for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:21 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo2r-0004w5-JR for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:16:21 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-6be1bc5aa1cso294899b3a.3 for ; Wed, 25 Oct 2023 17:16:17 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279593868100003 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 6 +++++ target/sparc/translate.c | 50 ++++++++++++--------------------------- 2 files changed, 21 insertions(+), 35 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 9ab3f2eb82..f6f5401b10 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -3,6 +3,10 @@ # Sparc instruction decode definitions. # Copyright (c) 2023 Richard Henderson =20 +## +## Major Opcodes 00 and 01 -- branches, call, and sethi. +## + &bcc i a cond cc BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=3D0 @@ -14,4 +18,6 @@ BPr 00 a:1 0 cond:3 011 .. - rs1:5 ..............= i=3D%d16 =20 NCP 00 - ---- 111 ---------------------- # CBcc =20 +SETHI 00 rd:5 100 i:22 + CALL 01 i:s30 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d12f2b4b87..cdd929282a 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2873,6 +2873,10 @@ static bool advance_pc(DisasContext *dc) return true; } =20 +/* + * Major opcodes 00 and 01 -- branches, call, and sethi + */ + static bool advance_jump_uncond_never(DisasContext *dc, bool annul) { if (annul) { @@ -3029,6 +3033,15 @@ static bool trans_NCP(DisasContext *dc, arg_NCP *a) #endif } =20 +static bool trans_SETHI(DisasContext *dc, arg_SETHI *a) +{ + /* Special-case %g0 because that's the canonical nop. */ + if (a->rd) { + gen_store_gpr(dc, a->rd, tcg_constant_tl((uint32_t)a->i << 10)); + } + return advance_pc(dc); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -3049,41 +3062,8 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) rd =3D GET_FIELD(insn, 2, 6); =20 switch (opc) { - case 0: /* branches/sethi */ - { - unsigned int xop =3D GET_FIELD(insn, 7, 9); - switch (xop) { -#ifdef TARGET_SPARC64 - case 0x1: /* V9 BPcc */ - g_assert_not_reached(); /* in decodetree */ - case 0x3: /* V9 BPr */ - g_assert_not_reached(); /* in decodetree */ - case 0x5: /* V9 FBPcc */ - g_assert_not_reached(); /* in decodetree */ -#else - case 0x7: /* CBN+x */ - g_assert_not_reached(); /* in decodetree */ -#endif - case 0x2: /* BN+x */ - g_assert_not_reached(); /* in decodetree */ - case 0x6: /* FBN+x */ - g_assert_not_reached(); /* in decodetree */ - case 0x4: /* SETHI */ - /* Special-case %g0 because that's the canonical nop. */ - if (rd) { - uint32_t value =3D GET_FIELD(insn, 10, 31); - TCGv t =3D gen_dest_gpr(dc, rd); - tcg_gen_movi_tl(t, value << 10); - gen_store_gpr(dc, rd, t); - } - break; - case 0x0: /* UNIMPL */ - default: - goto illegal_insn; - } - break; - } - break; + case 0: + goto illegal_insn; /* in decodetree */ case 1: g_assert_not_reached(); /* in decodetree */ case 2: /* FPU & Logical Operations */ --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279559; x=1698884359; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Ia7E+sZTkzV+toHLImE8uJD4WD71ICthxvcmZF9Bb/k=; b=QfwWZkPSbSm0BQP78MdhrgO6FQJZeB89pMhD3UCEsl4KOQd1WlmgeqPix7lqIRSnkV DyYX5wkNNdodTtqmAWLp+uq4oMQV0wEtoOq+SxiyVbbaNG+XHz5wMD5uDgEfSh6WUMnn erTDGK1Nf6NyIUdDwkq5xtmwvacNqeULsaCLcfcgatFuwoEmsf4NyHZH0jtGMFaZ+9+0 x7/Wo9tuWhmPrurigK2iVCuWtBVZf9Wp9sZ3H0pxuyKtbkzNRj1DbSbqA7dFE2aw8xKv 4Kuoz51md/gg5XkLgboHPGWjTm2g8WDtH8YTgnBvVa9sfOll0M04IlDnHZKZyrKZMJwm xO9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279559; x=1698884359; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ia7E+sZTkzV+toHLImE8uJD4WD71ICthxvcmZF9Bb/k=; b=hSFoLbNvmocfjslPPDkomrXylx/XijnUphdEChPWPcWWOR3UHrqoDMIcr04LT/hbyo MhE9c5YsDqwt1H71bq8/gJQ1EfmqKs5rsphiO7we3xtAacO55smTJVpMh4jN4jZ45rBk 58yaw4x/JpCYyxXiIxotHlPkyVFWd91yGgzg7d6fkPrexrTwyw+l/tZFjxt9WSixv3+Y noKN1NETcL9G3EIeZQlcvqY1mbzi7AkpMqyORt0Vn63QEVPGKXk4PCe4Nvb3KwUd0Wxy bk6YadADeo6cnPAmUcne0XxUxOD6nFB7RoSKUeniIioAP50qoVlATSDLZvMH0seDhUHt V+iA== X-Gm-Message-State: AOJu0YxAgli0UC4N0RHyblJbeqovHUQKBxXK8t8kixDwPKwYTlQgD0nd MswzbpmwzGU2M3fgRDjmIXpLjPYSBEVWA90TwY8= X-Google-Smtp-Source: AGHT+IGfd8suIyavF2EiSCs/hPEJl1HkeueyHscA62O0DtjZqfGGhjQDcxWTNEOg2GxXX51dLsB/Ng== X-Received: by 2002:a05:6a21:66c9:b0:14b:7d8b:cbaf with SMTP id ze9-20020a056a2166c900b0014b7d8bcbafmr6320475pzb.57.1698279559195; Wed, 25 Oct 2023 17:19:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 21/29] tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc Date: Wed, 25 Oct 2023 17:14:21 -0700 Message-Id: <20231026001542.1141412-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280013190100001 Content-Type: text/plain; charset="utf-8" Rename the current tcg_out_bc function to tcg_out_bc_lab, and create a new function that takes an integer displacement + link. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 856c3b18f5..666d480e86 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1945,14 +1945,20 @@ static void tcg_out_setcond(TCGContext *s, TCGType = type, TCGCond cond, } } =20 -static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l) +static void tcg_out_bc(TCGContext *s, TCGCond cond, int bd) { + tcg_out32(s, tcg_to_bc[cond] | bd); +} + +static void tcg_out_bc_lab(TCGContext *s, TCGCond cond, TCGLabel *l) +{ + int bd =3D 0; if (l->has_value) { - bc |=3D reloc_pc14_val(tcg_splitwx_to_rx(s->code_ptr), l->u.value_= ptr); + bd =3D reloc_pc14_val(tcg_splitwx_to_rx(s->code_ptr), l->u.value_p= tr); } else { tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0); } - tcg_out32(s, bc); + tcg_out_bc(s, cond, bd); } =20 static void tcg_out_brcond(TCGContext *s, TCGCond cond, @@ -1960,7 +1966,7 @@ static void tcg_out_brcond(TCGContext *s, TCGCond con= d, TCGLabel *l, TCGType type) { tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); - tcg_out_bc(s, tcg_to_bc[cond], l); + tcg_out_bc_lab(s, cond, l); } =20 static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond, @@ -2002,7 +2008,7 @@ static void tcg_out_movcond(TCGContext *s, TCGType ty= pe, TCGCond cond, } } /* Branch forward over one insn */ - tcg_out32(s, tcg_to_bc[cond] | 8); + tcg_out_bc(s, cond, 8); if (v2 =3D=3D 0) { tcg_out_movi(s, type, dest, 0); } else { @@ -2023,11 +2029,11 @@ static void tcg_out_cntxz(TCGContext *s, TCGType ty= pe, uint32_t opc, tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1)); tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0= )); } else if (!const_a2 && a0 =3D=3D a2) { - tcg_out32(s, tcg_to_bc[TCG_COND_EQ] | 8); + tcg_out_bc(s, TCG_COND_EQ, 8); tcg_out32(s, opc | RA(a0) | RS(a1)); } else { tcg_out32(s, opc | RA(a0) | RS(a1)); - tcg_out32(s, tcg_to_bc[TCG_COND_NE] | 8); + tcg_out_bc(s, TCG_COND_NE, 8); if (const_a2) { tcg_out_movi(s, type, a0, 0); } else { @@ -2107,11 +2113,11 @@ static void tcg_out_setcond2(TCGContext *s, const T= CGArg *args, tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31); } =20 -static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args, - const int *const_args) +static void tcg_out_brcond2(TCGContext *s, const TCGArg *args, + const int *const_args) { tcg_out_cmp2(s, args, const_args); - tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5])); + tcg_out_bc_lab(s, TCG_COND_EQ, arg_label(args[5])); } =20 static void tcg_out_mb(TCGContext *s, TCGArg a0) @@ -2445,7 +2451,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, =20 /* Load a pointer into the current opcode w/conditional branch-lin= k. */ ldst->label_ptr[0] =3D s->code_ptr; - tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); + tcg_out_bc(s, TCG_COND_NE, LK); =20 h->base =3D TCG_REG_TMP1; } else { --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279558; x=1698884358; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tfImdl249sFCQ5QfdFytfo/W/FXnENZi8z1/TCfyq8o=; b=xc82ynagxBSTyvwTCjPX+lWpAsc+D99wX68e1+toyhpEOoWLg2i1fX7HxgcSwWmUbu 3E3/CIQJm4pzIGw31UeTcynZkCI0KzBU9XAvkzpUtRZzf2BzEdDS/5eu45hCJwNTzg81 TThcY7yfgZVo+PsIa7XWgKEUueOcYko7bAcfCADqwPErsOStd5mi0qsPzts54eKYuoiN MgdwdESKijBh5vzH3gpeGV+c7etsFJ5AZ7UR51wnF551gaOx74bjXpj3IXCoWlxtmJ6d qGEOVgw4tt1sB+reJYNMwsn2oQJcl6guUpG0jP2GWGOVkYftxC2DrmLKHOstJfpeyJqK uxbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279558; x=1698884358; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tfImdl249sFCQ5QfdFytfo/W/FXnENZi8z1/TCfyq8o=; b=XpkbmpsRp09xHj1nLLWgBxKd1Bxn08aBzChLxbKKIjBJG023/wwb5IRhrto2gfNB1S ouZBIPqR9PK2QSAU25QDkluksy9oKjxDcHmvhgbzn5aK1OtyNJG82pZ++7GYNUgTSyRv LFpVhPgAxwhYloGUkZM8wFZRQnF8jSwh3NzYGBqGFr9fqAjze6mLCUFBU9U5gypropf5 G28A30nyEkm1T8OHBaiQcBSf65DgMA3Fk/pWZTmJubemt3viM3cAKFpf25u5wlTrSrgO fSEe09GB9PqZrRBgnT5RBVbGh/RZWixaw45rI78nrAA/qYmI9RdUKSpw0SPRva1OWt2C /SHw== X-Gm-Message-State: AOJu0YyH6kEdw3rtpLVkr3DaPbYDDNCFyuVojtf80ap/AB5Cd+gmHmH3 Jfc1+QG8XvtF+3c8z47HPNEmOnXYbHj9e7BCG2A= X-Google-Smtp-Source: AGHT+IFrOfpSNrUhuUx4e432OhnFUHvQMI8mPSWhkDRum5zXPjq7/xU2rzxe4tkUp7MTyKdK0Nrg7Q== X-Received: by 2002:a17:902:c942:b0:1c9:dcea:33e5 with SMTP id i2-20020a170902c94200b001c9dcea33e5mr18107083pla.67.1698279558475; Wed, 25 Oct 2023 17:19:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 21/94] target/sparc: Move Tcc to decodetree Date: Wed, 25 Oct 2023 17:14:20 -0700 Message-Id: <20231026001542.1141412-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279828685100004 Content-Type: text/plain; charset="utf-8" Use the new delay_exceptionv function in the implementation. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 13 ++++ target/sparc/translate.c | 155 +++++++++++++++++++------------------- 2 files changed, 89 insertions(+), 79 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index f6f5401b10..0517f5591b 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -21,3 +21,16 @@ NCP 00 - ---- 111 ---------------------- = # CBcc SETHI 00 rd:5 100 i:22 =20 CALL 01 i:s30 + +Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 +{ + # For v7, the entire simm13 field is present, but masked to 7 bits. + # For v8, [12:7] are reserved. However, a compatibility note for + # the Tcc insn in the v9 manual suggests that the v8 reserved field + # was ignored and did not produce traps. + Tcc_i_v7 10 0 cond:4 111010 rs1:5 1 ------ i:7 + + # For v9, bits [12:11] are cc1 and cc0 (and cc0 must be 0). + # Bits [10:8] are reserved and the OSA2011 manual says they must be 0. + Tcc_i_v9 10 0 cond:4 111010 rs1:5 1 cc:1 0 000 i:8 +} diff --git a/target/sparc/translate.c b/target/sparc/translate.c index cdd929282a..b927b212ca 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -3042,6 +3042,81 @@ static bool trans_SETHI(DisasContext *dc, arg_SETHI = *a) return advance_pc(dc); } =20 +static bool do_tcc(DisasContext *dc, int cond, int cc, + int rs1, bool imm, int rs2_or_imm) +{ + int mask =3D ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc) + ? UA2005_HTRAP_MASK : V8_TRAP_MASK); + DisasCompare cmp; + TCGLabel *lab; + TCGv_i32 trap; + + /* Trap never. */ + if (cond =3D=3D 0) { + return advance_pc(dc); + } + + /* + * Immediate traps are the most common case. Since this value is + * live across the branch, it really pays to evaluate the constant. + */ + if (rs1 =3D=3D 0 && (imm || rs2_or_imm =3D=3D 0)) { + trap =3D tcg_constant_i32((rs2_or_imm & mask) + TT_TRAP); + } else { + trap =3D tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(trap, gen_load_gpr(dc, rs1)); + if (imm) { + tcg_gen_addi_i32(trap, trap, rs2_or_imm); + } else { + TCGv_i32 t2 =3D tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t2, gen_load_gpr(dc, rs2_or_imm)); + tcg_gen_add_i32(trap, trap, t2); + } + tcg_gen_andi_i32(trap, trap, mask); + tcg_gen_addi_i32(trap, trap, TT_TRAP); + } + + /* Trap always. */ + if (cond =3D=3D 8) { + save_state(dc); + gen_helper_raise_exception(tcg_env, trap); + dc->base.is_jmp =3D DISAS_NORETURN; + return true; + } + + /* Conditional trap. */ + flush_cond(dc); + lab =3D delay_exceptionv(dc, trap); + gen_compare(&cmp, cc, cond, dc); + tcg_gen_brcond_tl(cmp.cond, cmp.c1, cmp.c2, lab); + + return advance_pc(dc); +} + +static bool trans_Tcc_r(DisasContext *dc, arg_Tcc_r *a) +{ + if (avail_32(dc) && a->cc) { + return false; + } + return do_tcc(dc, a->cond, a->cc, a->rs1, false, a->rs2); +} + +static bool trans_Tcc_i_v7(DisasContext *dc, arg_Tcc_i_v7 *a) +{ + if (avail_64(dc)) { + return false; + } + return do_tcc(dc, a->cond, 0, a->rs1, true, a->i); +} + +static bool trans_Tcc_i_v9(DisasContext *dc, arg_Tcc_i_v9 *a) +{ + if (avail_32(dc)) { + return false; + } + return do_tcc(dc, a->cond, a->cc, a->rs1, true, a->i); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -3072,85 +3147,7 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) TCGv cpu_dst =3D tcg_temp_new(); TCGv cpu_tmp0; =20 - if (xop =3D=3D 0x3a) { /* generate trap */ - int cond =3D GET_FIELD(insn, 3, 6); - TCGv_i32 trap; - TCGLabel *l1 =3D NULL; - int mask; - - if (cond =3D=3D 0) { - /* Trap never. */ - break; - } - - save_state(dc); - - if (cond !=3D 8) { - /* Conditional trap. */ - DisasCompare cmp; -#ifdef TARGET_SPARC64 - /* V9 icc/xcc */ - int cc =3D GET_FIELD_SP(insn, 11, 12); - if (cc =3D=3D 0) { - gen_compare(&cmp, 0, cond, dc); - } else if (cc =3D=3D 2) { - gen_compare(&cmp, 1, cond, dc); - } else { - goto illegal_insn; - } -#else - gen_compare(&cmp, 0, cond, dc); -#endif - l1 =3D gen_new_label(); - tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond), - cmp.c1, cmp.c2, l1); - } - - mask =3D ((dc->def->features & CPU_FEATURE_HYPV) && superv= isor(dc) - ? UA2005_HTRAP_MASK : V8_TRAP_MASK); - - /* Don't use the normal temporaries, as they may well have - gone out of scope with the branch above. While we're - doing that we might as well pre-truncate to 32-bit. */ - trap =3D tcg_temp_new_i32(); - - rs1 =3D GET_FIELD_SP(insn, 14, 18); - if (IS_IMM) { - rs2 =3D GET_FIELD_SP(insn, 0, 7); - if (rs1 =3D=3D 0) { - tcg_gen_movi_i32(trap, (rs2 & mask) + TT_TRAP); - /* Signal that the trap value is fully constant. = */ - mask =3D 0; - } else { - TCGv t1 =3D gen_load_gpr(dc, rs1); - tcg_gen_trunc_tl_i32(trap, t1); - tcg_gen_addi_i32(trap, trap, rs2); - } - } else { - TCGv t1, t2; - rs2 =3D GET_FIELD_SP(insn, 0, 4); - t1 =3D gen_load_gpr(dc, rs1); - t2 =3D gen_load_gpr(dc, rs2); - tcg_gen_add_tl(t1, t1, t2); - tcg_gen_trunc_tl_i32(trap, t1); - } - if (mask !=3D 0) { - tcg_gen_andi_i32(trap, trap, mask); - tcg_gen_addi_i32(trap, trap, TT_TRAP); - } - - gen_helper_raise_exception(tcg_env, trap); - - if (cond =3D=3D 8) { - /* An unconditional trap ends the TB. */ - dc->base.is_jmp =3D DISAS_NORETURN; - goto jmp_insn; - } else { - /* A conditional trap falls through to the next insn. = */ - gen_set_label(l1); - break; - } - } else if (xop =3D=3D 0x28) { + if (xop =3D=3D 0x28) { rs1 =3D GET_FIELD(insn, 13, 17); switch(rs1) { case 0: /* rdy */ --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280398; cv=none; d=zohomail.com; s=zohoarc; b=WISy8KyY36DV688FNnZLdpbbQX1wCcWNJYqCprZjJ0tJq2QYnHQiXednZT1KLUV9A8iv3GJqa+3HfSlS3QScuXqD7XEhX/91wKz4r5q+8tmmNll+bk2sRi5xD4/eMm9Ae4Zjad9UmkOjF4M0aCfpctNpwM3yDUlQE26KVWja3c8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280398; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=jvJ/P4HX7554nJIJGIM3vtxFYVYTJFcbVyfLPezXvC4=; b=Jz9LXMUz5+1+67piuDeGxphLpNWUGmIO0tQ4p8Ru7rAvV/mhLuEBUoHOJ/Pp+NJCXylbX91DhlNIsdDKpi2XE62rN4HGxKyVY2GXj1o8bZsvRnwACv42J6CCCAqql/Z17puhWiiNjeydqRBSndIbH+iyl74KevhZkgo8MXQOkhM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698280398752842.5797802044711; Wed, 25 Oct 2023 17:33:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo63-0000pS-90; Wed, 25 Oct 2023 20:19:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo5w-0000kJ-DW for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:28 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo5r-0006as-Iz for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:28 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1bdf4752c3cso2057955ad.2 for ; Wed, 25 Oct 2023 17:19:22 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279561; x=1698884361; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=jvJ/P4HX7554nJIJGIM3vtxFYVYTJFcbVyfLPezXvC4=; b=SznyKQfwwDnqnQ8Uj7XTZo5CD5Fh8wljSmKbVEwCHMDjGP/DdIolk/Hfituf3JqdXc ylCMYkNrTS3TH+PEaeTSlyXyFy8+tvx84wZmjZRa+8E1yyiIQuLB2vEVZfxEZn2ezSZ8 WmBw/K6spfxovNUH6m1VyxY18SoQq6U2T8MBhCbBtUFhCsSxRAOXUtcWm2dW6sO6gOnx +4Adi1zZpTeyn/lqRg+W1zLPiKaAcp/5SGZrKhkt1/f3B1+BL5HtsIG66MVpnZPmm4+U VgAbr9V3SG+QjcGYe1e4/ShWM6Nac3T2u7mdtrMBvpDXw3PwROaQV8siLV97Iu5qJ6eS grEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279561; x=1698884361; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jvJ/P4HX7554nJIJGIM3vtxFYVYTJFcbVyfLPezXvC4=; b=nj7ZSnkemyyevW6N6yd5lPES3rOfGtqFrmYYfu2GW56b0QHLXvb8JMBbFfflnbZzcb yvhkFA0pE22wjFTK+bj5VcGrxxI+F6UTt/Ms27HmJg1wXzX6NoBtWRM76eY9R2fy7+zp OFr/9UZlilrrJ647N4YSvUwPAXuLfra5xxjw2oN3HVx6GA/brKf+3fkdqF4X/WbUMtNw /JnGv0kkQyXhZTRiNJPlGEovRGkL4h25TSrk96cmnMAO8PMzWx47lUzmPPszsC89M/pg 01hd0nhD4IcXv7+BvDBQj+Y9L+RMuKfZV9UM0ze1LAdXV47rUVKOpakaPmh515PBB6Fs Co1g== X-Gm-Message-State: AOJu0YxJMFBcSFxKRXiteUFl5Lcbhs4ZO2h6P/79Fjy21NXizlS+qkra 3rB9F7BAVfp+ZMH78+dhwGV9qDr9KSH7sRLQba4= X-Google-Smtp-Source: AGHT+IHJHseCxsnGDmJyh40a+nBOxs9igp7Dbu5OYOQMr5g9LfQNAZPJDFgZ2ppwmb9XczdTyhXPHQ== X-Received: by 2002:a17:902:d502:b0:1c4:4dbc:92bc with SMTP id b2-20020a170902d50200b001c44dbc92bcmr15605010plg.16.1698279560941; Wed, 25 Oct 2023 17:19:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 22/29] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel Date: Wed, 25 Oct 2023 17:14:23 -0700 Message-Id: <20231026001542.1141412-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280399289100009 Content-Type: text/plain; charset="utf-8" Using cr0 means we could choose to use rc=3D1 to compute the condition. Adjust the tables and tcg_out_cmp that feeds them. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 68 ++++++++++++++++++++-------------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 666d480e86..3c2ec4db4b 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -670,30 +670,30 @@ enum { }; =20 static const uint32_t tcg_to_bc[] =3D { - [TCG_COND_EQ] =3D BC | BI(7, CR_EQ) | BO_COND_TRUE, - [TCG_COND_NE] =3D BC | BI(7, CR_EQ) | BO_COND_FALSE, - [TCG_COND_LT] =3D BC | BI(7, CR_LT) | BO_COND_TRUE, - [TCG_COND_GE] =3D BC | BI(7, CR_LT) | BO_COND_FALSE, - [TCG_COND_LE] =3D BC | BI(7, CR_GT) | BO_COND_FALSE, - [TCG_COND_GT] =3D BC | BI(7, CR_GT) | BO_COND_TRUE, - [TCG_COND_LTU] =3D BC | BI(7, CR_LT) | BO_COND_TRUE, - [TCG_COND_GEU] =3D BC | BI(7, CR_LT) | BO_COND_FALSE, - [TCG_COND_LEU] =3D BC | BI(7, CR_GT) | BO_COND_FALSE, - [TCG_COND_GTU] =3D BC | BI(7, CR_GT) | BO_COND_TRUE, + [TCG_COND_EQ] =3D BC | BI(0, CR_EQ) | BO_COND_TRUE, + [TCG_COND_NE] =3D BC | BI(0, CR_EQ) | BO_COND_FALSE, + [TCG_COND_LT] =3D BC | BI(0, CR_LT) | BO_COND_TRUE, + [TCG_COND_GE] =3D BC | BI(0, CR_LT) | BO_COND_FALSE, + [TCG_COND_LE] =3D BC | BI(0, CR_GT) | BO_COND_FALSE, + [TCG_COND_GT] =3D BC | BI(0, CR_GT) | BO_COND_TRUE, + [TCG_COND_LTU] =3D BC | BI(0, CR_LT) | BO_COND_TRUE, + [TCG_COND_GEU] =3D BC | BI(0, CR_LT) | BO_COND_FALSE, + [TCG_COND_LEU] =3D BC | BI(0, CR_GT) | BO_COND_FALSE, + [TCG_COND_GTU] =3D BC | BI(0, CR_GT) | BO_COND_TRUE, }; =20 /* The low bit here is set if the RA and RB fields must be inverted. */ static const uint32_t tcg_to_isel[] =3D { - [TCG_COND_EQ] =3D ISEL | BC_(7, CR_EQ), - [TCG_COND_NE] =3D ISEL | BC_(7, CR_EQ) | 1, - [TCG_COND_LT] =3D ISEL | BC_(7, CR_LT), - [TCG_COND_GE] =3D ISEL | BC_(7, CR_LT) | 1, - [TCG_COND_LE] =3D ISEL | BC_(7, CR_GT) | 1, - [TCG_COND_GT] =3D ISEL | BC_(7, CR_GT), - [TCG_COND_LTU] =3D ISEL | BC_(7, CR_LT), - [TCG_COND_GEU] =3D ISEL | BC_(7, CR_LT) | 1, - [TCG_COND_LEU] =3D ISEL | BC_(7, CR_GT) | 1, - [TCG_COND_GTU] =3D ISEL | BC_(7, CR_GT), + [TCG_COND_EQ] =3D ISEL | BC_(0, CR_EQ), + [TCG_COND_NE] =3D ISEL | BC_(0, CR_EQ) | 1, + [TCG_COND_LT] =3D ISEL | BC_(0, CR_LT), + [TCG_COND_GE] =3D ISEL | BC_(0, CR_LT) | 1, + [TCG_COND_LE] =3D ISEL | BC_(0, CR_GT) | 1, + [TCG_COND_GT] =3D ISEL | BC_(0, CR_GT), + [TCG_COND_LTU] =3D ISEL | BC_(0, CR_LT), + [TCG_COND_GEU] =3D ISEL | BC_(0, CR_LT) | 1, + [TCG_COND_LEU] =3D ISEL | BC_(0, CR_GT) | 1, + [TCG_COND_GTU] =3D ISEL | BC_(0, CR_GT), }; =20 static bool patch_reloc(tcg_insn_unit *code_ptr, int type, @@ -1826,7 +1826,7 @@ static void tcg_out_setcond(TCGContext *s, TCGType ty= pe, TCGCond cond, if (have_isa_3_10) { tcg_insn_unit bi, opc; =20 - tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); + tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 0, type); =20 /* Re-use tcg_to_bc for BI and BO_COND_{TRUE,FALSE}. */ bi =3D tcg_to_bc[cond] & (0x1f << 16); @@ -1879,7 +1879,7 @@ static void tcg_out_setcond(TCGContext *s, TCGType ty= pe, TCGCond cond, if (have_isel) { int isel, tab; =20 - tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); + tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 0, type); =20 isel =3D tcg_to_isel[cond]; =20 @@ -1965,7 +1965,7 @@ static void tcg_out_brcond(TCGContext *s, TCGCond con= d, TCGArg arg1, TCGArg arg2, int const_arg2, TCGLabel *l, TCGType type) { - tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); + tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 0, type); tcg_out_bc_lab(s, cond, l); } =20 @@ -1979,7 +1979,7 @@ static void tcg_out_movcond(TCGContext *s, TCGType ty= pe, TCGCond cond, return; } =20 - tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type); + tcg_out_cmp(s, cond, c1, c2, const_c2, 0, type); =20 if (have_isel) { int isel =3D tcg_to_isel[cond]; @@ -2023,7 +2023,7 @@ static void tcg_out_cntxz(TCGContext *s, TCGType type= , uint32_t opc, if (const_a2 && a2 =3D=3D (type =3D=3D TCG_TYPE_I32 ? 32 : 64)) { tcg_out32(s, opc | RA(a0) | RS(a1)); } else { - tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type); + tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 0, type); /* Note that the only other valid constant for a2 is 0. */ if (have_isel) { tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1)); @@ -2078,7 +2078,7 @@ static void tcg_out_cmp2(TCGContext *s, const TCGArg = *args, do_equality: tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32); tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32); - tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); + tcg_out32(s, op | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); break; =20 case TCG_COND_LT: @@ -2096,8 +2096,8 @@ static void tcg_out_cmp2(TCGContext *s, const TCGArg = *args, =20 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32); tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32); - tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2)); - tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ)); + tcg_out32(s, op | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2)); + tcg_out32(s, CROR | BT(0, CR_EQ) | BA(6, bit1) | BB(0, CR_EQ)); break; =20 default: @@ -2109,8 +2109,8 @@ static void tcg_out_setcond2(TCGContext *s, const TCG= Arg *args, const int *const_args) { tcg_out_cmp2(s, args + 1, const_args + 1); - tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); - tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31); + tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(0)); + tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, CR_EQ + 0*4 + 1, 31, 31); } =20 static void tcg_out_brcond2(TCGContext *s, const TCGArg *args, @@ -2441,12 +2441,12 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_TMP2, 0, 6, TCG_TYPE_I32); =20 - /* Combine comparisons into cr7. */ - tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ= )); + /* Combine comparisons into cr0. */ + tcg_out32(s, CRAND | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ= )); } else { - /* Full comparison into cr7. */ + /* Full comparison into cr0. */ tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, - 0, 7, addr_type); + 0, 0, addr_type); } =20 /* Load a pointer into the current opcode w/conditional branch-lin= k. */ --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279949; cv=none; d=zohomail.com; s=zohoarc; b=VtwgGXRLz1cI+7nSedMeaGUft/9O1lrVfWS/eaCH2Wr4l0MZm8nupyPmHzW+mx+RaNhfn7YWXHZBy0BvVTPs+xfHAbMie9igMuLYiYCisUlKvwR/l0omXxJTCxhTgrzawSav49givbbvuqmXwxfcUSIyFwHW/SfTjSFteHKk6F8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279949; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0ZFkVjJElMHbZrG486UGB9YDXc8kwMsHMbCp6rWCfS4=; b=niiEiSUIM8bjM+KJaMem2E1tbvOdzFqJ0v0O4adUAglDxL3Y7rFkcFflqPBsBvL+a/bFxF415P2j108bLffrQaGcAhnCvrfEi3Ozkhh3Ql0Aw6rNkDPYGxrFIToK3vUhSZemwLgd6pKbgQV/VdgYws5TmGqX6MnZ2vFKCyZP7xY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698279949265880.0308098524679; Wed, 25 Oct 2023 17:25:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo6E-00012W-NO; Wed, 25 Oct 2023 20:19:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo61-0000qo-Fv for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:35 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo5r-0006ah-2f for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:33 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1caa371dcd8so2468165ad.0 for ; Wed, 25 Oct 2023 17:19:21 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279950994100005 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 22 +++ target/sparc/translate.c | 342 ++++++++++++++++++++++++-------------- 2 files changed, 235 insertions(+), 129 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 0517f5591b..1b084c5b97 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -22,6 +22,28 @@ SETHI 00 rd:5 100 i:22 =20 CALL 01 i:s30 =20 +{ + [ + STBAR 10 00000 101000 01111 0 0000000000000 + MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4 + + RDCCR 10 rd:5 101000 00010 0 0000000000000 + RDASI 10 rd:5 101000 00011 0 0000000000000 + RDTICK 10 rd:5 101000 00100 0 0000000000000 + RDPC 10 rd:5 101000 00101 0 0000000000000 + RDFPRS 10 rd:5 101000 00110 0 0000000000000 + RDASR17 10 rd:5 101000 10001 0 0000000000000 + RDGSR 10 rd:5 101000 10011 0 0000000000000 + RDSOFTINT 10 rd:5 101000 10110 0 0000000000000 + RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000 + RDSTICK 10 rd:5 101000 11000 0 0000000000000 + RDSTICK_CMPR 10 rd:5 101000 11001 0 0000000000000 + RDSTRAND_STATUS 10 rd:5 101000 11010 0 0000000000000 + ] + # Before v8, all rs1 accepted; otherwise rs1=3D=3D0. + RDY 10 rd:5 101000 rs1:5 0 0000000000000 +} + Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 { # For v7, the entire simm13 field is present, but masked to 7 bits. diff --git a/target/sparc/translate.c b/target/sparc/translate.c index b927b212ca..9af4578525 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -36,6 +36,11 @@ #include "exec/helper-info.c.inc" #undef HELPER_H =20 +#ifndef TARGET_SPARC64 +# define gen_helper_rdccr(D, E) qemu_build_not_reached() +# define gen_helper_tick_get_count(D, E, T, C) qemu_build_not_reached() +#endif + /* Dynamic PC, must exit to main loop. */ #define DYNAMIC_PC 1 /* Dynamic PC, one of two values according to jump_pc[T2]. */ @@ -64,10 +69,21 @@ static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_c= mpr; static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver; #else static TCGv cpu_wim; +# define cpu_fprs ({ qemu_build_not_reached(); (TCGv)NULL; }) +# define cpu_gsr ({ qemu_build_not_reached(); (TCGv)NULL; }) +# define cpu_tick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; }) +# define cpu_stick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; }) #endif /* Floating point registers */ static TCGv_i64 cpu_fpr[TARGET_DPREGS]; =20 +#define env_field_offsetof(X) offsetof(CPUSPARCState, X) +#ifdef TARGET_SPARC64 +# define env64_field_offsetof(X) env_field_offsetof(X) +#else +# define env64_field_offsetof(X) ({ qemu_build_not_reached(); 0; }) +#endif + typedef struct DisasDelayException { struct DisasDelayException *next; TCGLabel *lab; @@ -2842,10 +2858,14 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv= s1, TCGv s2) #define avail_ALL(C) true #ifdef TARGET_SPARC64 # define avail_32(C) false +# define avail_ASR17(C) false # define avail_64(C) true +# define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV) #else # define avail_32(C) true +# define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17) # define avail_64(C) false +# define avail_HYPV(C) false #endif =20 /* Default case for non jump instructions. */ @@ -2947,6 +2967,12 @@ static bool advance_jump_cond(DisasContext *dc, Disa= sCompare *cmp, return true; } =20 +static bool raise_priv(DisasContext *dc) +{ + gen_exception(dc, TT_PRIV_INSN); + return true; +} + static bool do_bpcc(DisasContext *dc, arg_bcc *a) { target_long target =3D address_mask_i(dc, dc->pc + a->i * 4); @@ -3117,6 +3143,183 @@ static bool trans_Tcc_i_v9(DisasContext *dc, arg_Tc= c_i_v9 *a) return do_tcc(dc, a->cond, a->cc, a->rs1, true, a->i); } =20 +static bool trans_STBAR(DisasContext *dc, arg_STBAR *a) +{ + tcg_gen_mb(TCG_MO_ST_ST | TCG_BAR_SC); + return advance_pc(dc); +} + +static bool trans_MEMBAR(DisasContext *dc, arg_MEMBAR *a) +{ + if (avail_32(dc)) { + return false; + } + if (a->mmask) { + /* Note TCG_MO_* was modeled on sparc64, so mmask matches. */ + tcg_gen_mb(a->mmask | TCG_BAR_SC); + } + if (a->cmask) { + /* For #Sync, etc, end the TB to recognize interrupts. */ + dc->base.is_jmp =3D DISAS_EXIT; + } + return advance_pc(dc); +} + +static bool do_rd_special(DisasContext *dc, bool priv, int rd, + TCGv (*func)(DisasContext *, TCGv)) +{ + if (!priv) { + return raise_priv(dc); + } + gen_store_gpr(dc, rd, func(dc, gen_dest_gpr(dc, rd))); + return advance_pc(dc); +} + +static TCGv do_rdy(DisasContext *dc, TCGv dst) +{ + return cpu_y; +} + +static bool trans_RDY(DisasContext *dc, arg_RDY *a) +{ + /* + * TODO: Need a feature bit for sparcv8. In the meantime, treat all + * 32-bit cpus like sparcv7, which ignores the rs1 field. + * This matches after all other ASR, so Leon3 Asr17 is handled first. + */ + if (avail_64(dc) && a->rs1 !=3D 0) { + return false; + } + return do_rd_special(dc, true, a->rd, do_rdy); +} + +static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst) +{ + uint32_t val; + + /* + * TODO: There are many more fields to be filled, + * some of which are writable. + */ + val =3D dc->def->nwindows - 1; /* [4:0] NWIN */ + val |=3D 1 << 8; /* [8] V8 */ + + return tcg_constant_tl(val); +} + +TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config) + +static TCGv do_rdccr(DisasContext *dc, TCGv dst) +{ + update_psr(dc); + gen_helper_rdccr(dst, tcg_env); + return dst; +} + +TRANS(RDCCR, 64, do_rd_special, true, a->rd, do_rdccr) + +static TCGv do_rdasi(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + return tcg_constant_tl(dc->asi); +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDASI, 64, do_rd_special, true, a->rd, do_rdasi) + +static TCGv do_rdtick(DisasContext *dc, TCGv dst) +{ + TCGv_ptr r_tickptr =3D tcg_temp_new_ptr(); + + tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(tick)); + if (translator_io_start(&dc->base)) { + dc->base.is_jmp =3D DISAS_EXIT; + } + gen_helper_tick_get_count(dst, tcg_env, r_tickptr, + tcg_constant_i32(dc->mem_idx)); + return dst; +} + +/* TODO: non-priv access only allowed when enabled. */ +TRANS(RDTICK, 64, do_rd_special, true, a->rd, do_rdtick) + +static TCGv do_rdpc(DisasContext *dc, TCGv dst) +{ + return tcg_constant_tl(address_mask_i(dc, dc->pc)); +} + +TRANS(RDPC, 64, do_rd_special, true, a->rd, do_rdpc) + +static TCGv do_rdfprs(DisasContext *dc, TCGv dst) +{ + tcg_gen_ext_i32_tl(dst, cpu_fprs); + return dst; +} + +TRANS(RDFPRS, 64, do_rd_special, true, a->rd, do_rdfprs) + +static TCGv do_rdgsr(DisasContext *dc, TCGv dst) +{ + gen_trap_ifnofpu(dc); + return cpu_gsr; +} + +TRANS(RDGSR, 64, do_rd_special, true, a->rd, do_rdgsr) + +static TCGv do_rdsoftint(DisasContext *dc, TCGv dst) +{ + tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(softint)); + return dst; +} + +TRANS(RDSOFTINT, 64, do_rd_special, supervisor(dc), a->rd, do_rdsoftint) + +static TCGv do_rdtick_cmpr(DisasContext *dc, TCGv dst) +{ + return cpu_tick_cmpr; +} + +/* TODO: non-priv access only allowed when enabled. */ +TRANS(RDTICK_CMPR, 64, do_rd_special, true, a->rd, do_rdtick_cmpr) + +static TCGv do_rdstick(DisasContext *dc, TCGv dst) +{ + TCGv_ptr r_tickptr =3D tcg_temp_new_ptr(); + + tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(stick)); + if (translator_io_start(&dc->base)) { + dc->base.is_jmp =3D DISAS_EXIT; + } + gen_helper_tick_get_count(dst, tcg_env, r_tickptr, + tcg_constant_i32(dc->mem_idx)); + return dst; +} + +/* TODO: non-priv access only allowed when enabled. */ +TRANS(RDSTICK, 64, do_rd_special, true, a->rd, do_rdstick) + +static TCGv do_rdstick_cmpr(DisasContext *dc, TCGv dst) +{ + return cpu_stick_cmpr; +} + +/* TODO: supervisor access only allowed when enabled by hypervisor. */ +TRANS(RDSTICK_CMPR, 64, do_rd_special, supervisor(dc), a->rd, do_rdstick_c= mpr) + +/* + * UltraSPARC-T1 Strand status. + * HYPV check maybe not enough, UA2005 & UA2007 describe + * this ASR as impl. dep + */ +static TCGv do_rdstrand_status(DisasContext *dc, TCGv dst) +{ + return tcg_constant_tl(1); +} + +TRANS(RDSTRAND_STATUS, HYPV, do_rd_special, true, a->rd, do_rdstrand_statu= s) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -3143,134 +3346,12 @@ static void disas_sparc_legacy(DisasContext *dc, u= nsigned int insn) g_assert_not_reached(); /* in decodetree */ case 2: /* FPU & Logical Operations */ { - unsigned int xop =3D GET_FIELD(insn, 7, 12); - TCGv cpu_dst =3D tcg_temp_new(); - TCGv cpu_tmp0; + unsigned int xop __attribute__((unused)) =3D GET_FIELD(insn, 7= , 12); + TCGv cpu_dst __attribute__((unused)) =3D tcg_temp_new(); + TCGv cpu_tmp0 __attribute__((unused)); =20 - if (xop =3D=3D 0x28) { - rs1 =3D GET_FIELD(insn, 13, 17); - switch(rs1) { - case 0: /* rdy */ -#ifndef TARGET_SPARC64 - case 0x01 ... 0x0e: /* undefined in the SPARCv8 - manual, rdy on the microSPARC - II */ - case 0x0f: /* stbar in the SPARCv8 manual, - rdy on the microSPARC II */ - case 0x10 ... 0x1f: /* implementation-dependent in the - SPARCv8 manual, rdy on the - microSPARC II */ - /* Read Asr17 */ - if (rs1 =3D=3D 0x11 && dc->def->features & CPU_FEATURE= _ASR17) { - TCGv t =3D gen_dest_gpr(dc, rd); - /* Read Asr17 for a Leon3 monoprocessor */ - tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows -= 1)); - gen_store_gpr(dc, rd, t); - break; - } -#endif - gen_store_gpr(dc, rd, cpu_y); - break; -#ifdef TARGET_SPARC64 - case 0x2: /* V9 rdccr */ - update_psr(dc); - gen_helper_rdccr(cpu_dst, tcg_env); - gen_store_gpr(dc, rd, cpu_dst); - break; - case 0x3: /* V9 rdasi */ - tcg_gen_movi_tl(cpu_dst, dc->asi); - gen_store_gpr(dc, rd, cpu_dst); - break; - case 0x4: /* V9 rdtick */ - { - TCGv_ptr r_tickptr; - TCGv_i32 r_const; - - r_tickptr =3D tcg_temp_new_ptr(); - r_const =3D tcg_constant_i32(dc->mem_idx); - tcg_gen_ld_ptr(r_tickptr, tcg_env, - offsetof(CPUSPARCState, tick)); - if (translator_io_start(&dc->base)) { - dc->base.is_jmp =3D DISAS_EXIT; - } - gen_helper_tick_get_count(cpu_dst, tcg_env, r_tick= ptr, - r_const); - gen_store_gpr(dc, rd, cpu_dst); - } - break; - case 0x5: /* V9 rdpc */ - { - TCGv t =3D gen_dest_gpr(dc, rd); - if (unlikely(AM_CHECK(dc))) { - tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL); - } else { - tcg_gen_movi_tl(t, dc->pc); - } - gen_store_gpr(dc, rd, t); - } - break; - case 0x6: /* V9 rdfprs */ - tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs); - gen_store_gpr(dc, rd, cpu_dst); - break; - case 0xf: /* V9 membar */ - break; /* no effect */ - case 0x13: /* Graphics Status */ - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - gen_store_gpr(dc, rd, cpu_gsr); - break; - case 0x16: /* Softint */ - tcg_gen_ld32s_tl(cpu_dst, tcg_env, - offsetof(CPUSPARCState, softint)); - gen_store_gpr(dc, rd, cpu_dst); - break; - case 0x17: /* Tick compare */ - gen_store_gpr(dc, rd, cpu_tick_cmpr); - break; - case 0x18: /* System tick */ - { - TCGv_ptr r_tickptr; - TCGv_i32 r_const; - - r_tickptr =3D tcg_temp_new_ptr(); - r_const =3D tcg_constant_i32(dc->mem_idx); - tcg_gen_ld_ptr(r_tickptr, tcg_env, - offsetof(CPUSPARCState, stick)); - if (translator_io_start(&dc->base)) { - dc->base.is_jmp =3D DISAS_EXIT; - } - gen_helper_tick_get_count(cpu_dst, tcg_env, r_tick= ptr, - r_const); - gen_store_gpr(dc, rd, cpu_dst); - } - break; - case 0x19: /* System tick compare */ - gen_store_gpr(dc, rd, cpu_stick_cmpr); - break; - case 0x1a: /* UltraSPARC-T1 Strand status */ - /* XXX HYPV check maybe not enough, UA2005 & UA2007 de= scribe - * this ASR as impl. dep - */ - CHECK_IU_FEATURE(dc, HYPV); - { - TCGv t =3D gen_dest_gpr(dc, rd); - tcg_gen_movi_tl(t, 1UL); - gen_store_gpr(dc, rd, t); - } - break; - case 0x10: /* Performance Control */ - case 0x11: /* Performance Instrumentation Counter */ - case 0x12: /* Dispatch Control */ - case 0x14: /* Softint set, WO */ - case 0x15: /* Softint clear, WO */ -#endif - default: - goto illegal_insn; - } #if !defined(CONFIG_USER_ONLY) - } else if (xop =3D=3D 0x29) { /* rdpsr / UA2005 rdhpr */ + if (xop =3D=3D 0x29) { /* rdpsr / UA2005 rdhpr */ #ifndef TARGET_SPARC64 if (!supervisor(dc)) { goto priv_insn; @@ -3308,7 +3389,8 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) #endif gen_store_gpr(dc, rd, cpu_dst); break; - } else if (xop =3D=3D 0x2a) { /* rdwim / V9 rdpr */ + } + if (xop =3D=3D 0x2a) { /* rdwim / V9 rdpr */ if (!supervisor(dc)) { goto priv_insn; } @@ -3432,9 +3514,10 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) #endif gen_store_gpr(dc, rd, cpu_tmp0); break; + } #endif #if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY) - } else if (xop =3D=3D 0x2b) { /* rdtbr / V9 flushw */ + if (xop =3D=3D 0x2b) { /* rdtbr / V9 flushw */ #ifdef TARGET_SPARC64 gen_helper_flushw(tcg_env); #else @@ -3443,8 +3526,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) gen_store_gpr(dc, rd, cpu_tbr); #endif break; + } #endif - } else if (xop =3D=3D 0x34) { /* FPU Operations */ + if (xop =3D=3D 0x34) { /* FPU Operations */ if (gen_trap_ifnofpu(dc)) { goto jmp_insn; } --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279562; x=1698884362; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y4JjGfXc1ZK0slmW0Mduo2FRxtvtvRQNj+3A0+w7cQs=; b=xvyihsaN/IL8J7P+zIMxfb6AwFMCQQ1iMFuLQtMNCS7b/cU7zP6ceLuQHnsw1d3WvX G2DaR9S41nAzrqnvh5mtZp9chOyco1x+IiRZosB63rONfe+LEX2D0QI7L2wTsy9IYfQM 2huZDanWtVsYleMmP4G0ezD4pJzsA9IU1bpKAmjwJZ1iKlvkD+KO04ts4GTZBy0HafwC 6D0WT3y+dS6HzlWvCZxcrztknSKclWTaS3/+/ocHeL5I6ahbyiQopiksLRrDLhh5nOps MwaZHDqmFYMMRe96g1Ozd+qjroTOteirTY6Q0+nSUrGy8lWU5Ry3VneR7Adx777pmBvJ /VYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279562; x=1698884362; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y4JjGfXc1ZK0slmW0Mduo2FRxtvtvRQNj+3A0+w7cQs=; b=gjhUIqpoaGu2KFP0RfTWqPsHeiOToPxdELodY7VbKivzOgUywq7u2tczYEQ21lwNU3 y05MwbwvcEQJO7A6rhPzWmn3wejor/4R0rqMgvxtknQxvcxzaf/QvGoK+j3NxDsYU/Hb +DVpk00X/XilbMV3YfALTTMsyLEoiiB8iKZ2qmMvP5LHishAYE+AqfTM+VCWNbo1Dkeq P5ApCDmT/DBD1/TWJBFSvjsws8Bal0DcigZ9ujHOKfavd+UrrJxcVe4eCynyYvfUiwI2 MB08sOJO6MuSPgRCrZdM+NscItA06+ES3Ei0spXrH8REWqefUkHVzUhy0TJO7ro1imWu PRTg== X-Gm-Message-State: AOJu0Yxh5NyP2VJrX4AZvlteCSUSrEXyyWDttotrMfiA0EeSq8GLPCku FXiV0KC3CU2L2ZUY65sneH6IPbime1u7UEDDVXA= X-Google-Smtp-Source: AGHT+IGjPxVnXCor5bTesqG30xwM8Wk7zsAV8lSK+56Yi3Wwd700AwwXJn+RxVtuRgaf0KNMRuSBYQ== X-Received: by 2002:a17:903:493:b0:1ca:344f:46e6 with SMTP id jj19-20020a170903049300b001ca344f46e6mr12113594plb.33.1698279561777; Wed, 25 Oct 2023 17:19:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 23/94] target/sparc: Move RDPSR, RDHPR to decodetree Date: Wed, 25 Oct 2023 17:14:24 -0700 Message-Id: <20231026001542.1141412-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279886839100005 Content-Type: text/plain; charset="utf-8" Implement htstate in the obvious way. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/847 Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 10 ++++ target/sparc/translate.c | 116 ++++++++++++++++++++++++-------------- 2 files changed, 83 insertions(+), 43 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 1b084c5b97..a7d78eb6c6 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -44,6 +44,16 @@ CALL 01 i:s30 RDY 10 rd:5 101000 rs1:5 0 0000000000000 } =20 +{ + RDPSR 10 rd:5 101001 00000 0 0000000000000 + RDHPR_hpstate 10 rd:5 101001 00000 0 0000000000000 +} +RDHPR_htstate 10 rd:5 101001 00001 0 0000000000000 +RDHPR_hintp 10 rd:5 101001 00011 0 0000000000000 +RDHPR_htba 10 rd:5 101001 00101 0 0000000000000 +RDHPR_hver 10 rd:5 101001 00110 0 0000000000000 +RDHPR_hstick_cmpr 10 rd:5 101001 11111 0 0000000000000 + Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 { # For v7, the entire simm13 field is present, but masked to 7 bits. diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 9af4578525..b58c2594ca 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -36,9 +36,12 @@ #include "exec/helper-info.c.inc" #undef HELPER_H =20 -#ifndef TARGET_SPARC64 +#ifdef TARGET_SPARC64 +# define gen_helper_rdpsr(D, E) qemu_build_not_reached() +#else # define gen_helper_rdccr(D, E) qemu_build_not_reached() # define gen_helper_tick_get_count(D, E, T, C) qemu_build_not_reached() +# define MAXTL_MASK 0 #endif =20 /* Dynamic PC, must exit to main loop. */ @@ -71,8 +74,12 @@ static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_= ver; static TCGv cpu_wim; # define cpu_fprs ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_gsr ({ qemu_build_not_reached(); (TCGv)NULL; }) -# define cpu_tick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; }) +# define cpu_hintp ({ qemu_build_not_reached(); (TCGv)NULL; }) +# define cpu_hstick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; }) +# define cpu_htba ({ qemu_build_not_reached(); (TCGv)NULL; }) +# define cpu_hver ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_stick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; }) +# define cpu_tick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; }) #endif /* Floating point registers */ static TCGv_i64 cpu_fpr[TARGET_DPREGS]; @@ -272,15 +279,14 @@ static void gen_move_Q(DisasContext *dc, unsigned int= rd, unsigned int rs) /* moves */ #ifdef CONFIG_USER_ONLY #define supervisor(dc) 0 -#ifdef TARGET_SPARC64 #define hypervisor(dc) 0 -#endif #else #ifdef TARGET_SPARC64 #define hypervisor(dc) (dc->hypervisor) #define supervisor(dc) (dc->supervisor | dc->hypervisor) #else #define supervisor(dc) (dc->supervisor) +#define hypervisor(dc) 0 #endif #endif =20 @@ -3320,6 +3326,69 @@ static TCGv do_rdstrand_status(DisasContext *dc, TCG= v dst) =20 TRANS(RDSTRAND_STATUS, HYPV, do_rd_special, true, a->rd, do_rdstrand_statu= s) =20 +static TCGv do_rdpsr(DisasContext *dc, TCGv dst) +{ + update_psr(dc); + gen_helper_rdpsr(dst, tcg_env); + return dst; +} + +TRANS(RDPSR, 32, do_rd_special, supervisor(dc), a->rd, do_rdpsr) + +static TCGv do_rdhpstate(DisasContext *dc, TCGv dst) +{ + tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(hpstate)); + return dst; +} + +TRANS(RDHPR_hpstate, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhpst= ate) + +static TCGv do_rdhtstate(DisasContext *dc, TCGv dst) +{ + TCGv_i32 tl =3D tcg_temp_new_i32(); + TCGv_ptr tp =3D tcg_temp_new_ptr(); + + tcg_gen_ld_i32(tl, tcg_env, env64_field_offsetof(tl)); + tcg_gen_andi_i32(tl, tl, MAXTL_MASK); + tcg_gen_shli_i32(tl, tl, 3); + tcg_gen_ext_i32_ptr(tp, tl); + tcg_gen_add_ptr(tp, tp, tcg_env); + + tcg_gen_ld_tl(dst, tp, env64_field_offsetof(htstate)); + return dst; +} + +TRANS(RDHPR_htstate, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhtst= ate) + +static TCGv do_rdhintp(DisasContext *dc, TCGv dst) +{ + return cpu_hintp; +} + +TRANS(RDHPR_hintp, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhintp) + +static TCGv do_rdhtba(DisasContext *dc, TCGv dst) +{ + return cpu_htba; +} + +TRANS(RDHPR_htba, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhtba) + +static TCGv do_rdhver(DisasContext *dc, TCGv dst) +{ + return cpu_hver; +} + +TRANS(RDHPR_hver, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhver) + +static TCGv do_rdhstick_cmpr(DisasContext *dc, TCGv dst) +{ + return cpu_hstick_cmpr; +} + +TRANS(RDHPR_hstick_cmpr, HYPV, do_rd_special, hypervisor(dc), a->rd, + do_rdhstick_cmpr) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -3351,45 +3420,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) TCGv cpu_tmp0 __attribute__((unused)); =20 #if !defined(CONFIG_USER_ONLY) - if (xop =3D=3D 0x29) { /* rdpsr / UA2005 rdhpr */ -#ifndef TARGET_SPARC64 - if (!supervisor(dc)) { - goto priv_insn; - } - update_psr(dc); - gen_helper_rdpsr(cpu_dst, tcg_env); -#else - CHECK_IU_FEATURE(dc, HYPV); - if (!hypervisor(dc)) - goto priv_insn; - rs1 =3D GET_FIELD(insn, 13, 17); - switch (rs1) { - case 0: // hpstate - tcg_gen_ld_i64(cpu_dst, tcg_env, - offsetof(CPUSPARCState, hpstate)); - break; - case 1: // htstate - // gen_op_rdhtstate(); - break; - case 3: // hintp - tcg_gen_mov_tl(cpu_dst, cpu_hintp); - break; - case 5: // htba - tcg_gen_mov_tl(cpu_dst, cpu_htba); - break; - case 6: // hver - tcg_gen_mov_tl(cpu_dst, cpu_hver); - break; - case 31: // hstick_cmpr - tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr); - break; - default: - goto illegal_insn; - } -#endif - gen_store_gpr(dc, rd, cpu_dst); - break; - } if (xop =3D=3D 0x2a) { /* rdwim / V9 rdpr */ if (!supervisor(dc)) { goto priv_insn; --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280875; cv=none; d=zohomail.com; s=zohoarc; b=eKs5PShsIg74vGtURTIDjGC3HYo/koOmzhbw4js/tzZZq9WTZNXFYj31LSlSBmmWV7rU52ICD99CWIi4ek3irjZol6QQa/kC0guyOfzNoLQyMRF7t8IdRURz/tG5zPMZ6cmAv468N54TRr8+Za3XqRYIQSt/cQHKLBwwzmxe06w= ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279563; x=1698884363; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=1RxoerkT+NW6NNN31T+6nx4K1n73GgW/XA4Cu7hakcY=; b=wU9LH+couZfWkzvfoVy4rXoiUqeBErKRRxNREIvmtqjLgc/TNYbS3qDJJzyufyAe1N PDQjGzTBJsSH8xsswscGRv/FoBTYFn1DeJuFShVUe2zcauHYgV/kPVpXBZInZv+12MqO wLJN7glcsBnnN8Uc3SDnBkCsBqRHvMPsmvF+4YFnO96iy6a4HqitBimuJnAp493eFd5s w1mGjysgi8MYk/NjhqxJVJ65PrLas8VSss2taawE6TwV/jOqKjcAKsfy9Oh5KzQdtlTd Sf/kKvwbSM9jWSUFqSMOPW9YviCUkJJPHGTfQSIyJmgedHzz7Bx1F07LhKMqKdtzTiaj e1cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279563; x=1698884363; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1RxoerkT+NW6NNN31T+6nx4K1n73GgW/XA4Cu7hakcY=; b=iZigFnxrqnP+7jUMRRURIP3HBU7ouZiveNsXvqCNGl15eU8yS59IdT3g8abPR6hUyv Ayw/jbAOIbk1K+EcN2HvFMXuDDM+N2F74ACPtQGslzNwdQkTnDfzDxgQqKFNY7MklYGm f/80Mtw3GA5Z+3Pv6RY8sRJQt62ButMR8f1p4JrYFbL53l+iU9elprgs5eEJU0NqRgaB gJdeSJ9emGlLo2snqMoCOCDVmpJETTycuXnlUajx6++6U2AFVVyBY0YEGZ7AF2nG1QQa KaDs0wLBOPqRGnA0ezL8QOmo5fwLjyq+dKTyW7LTxLGP5vzTHq/U44XLX7XE/N6pGP8A 38/A== X-Gm-Message-State: AOJu0YwfjLyHwEE28sfBoCb6bBRCZ12/nhtExvxRbrpjTjSuvbmUnw7j Hob8X2QcILvJpSfcmqC3vYWDs4GwlmWAUIOG8O8= X-Google-Smtp-Source: AGHT+IFDGKyl0sLRb1S4IjEkiXsDYS2HHiY82rE6ju0s5SjLNT0nZ851EXrOZzrKNc0x+Spj+O4szQ== X-Received: by 2002:a17:902:d48f:b0:1c9:dff6:58e8 with SMTP id c15-20020a170902d48f00b001c9dff658e8mr14737692plg.54.1698279562675; Wed, 25 Oct 2023 17:19:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 23/29] tcg/ppc: Create tcg_out_and_rc Date: Wed, 25 Oct 2023 17:14:25 -0700 Message-Id: <20231026001542.1141412-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280876866100005 Content-Type: text/plain; charset="utf-8" Merge tcg_out_andi32, tcg_out_andi64, and code to handle two register inputs. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 86 +++++++++++++++++++--------------------- 1 file changed, 40 insertions(+), 46 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 3c2ec4db4b..fe141a26f9 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1363,44 +1363,44 @@ static bool mask64_operand(uint64_t c, int *mb, int= *me) return false; } =20 -static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t= c) +static void tcg_out_and_rc(TCGContext *s, TCGType type, TCGReg dst, + TCGReg arg1, TCGArg arg2, bool const_arg2, bool= rc) { - int mb, me; - - if (mask_operand(c, &mb, &me)) { - tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me); - } else if ((c & 0xffff) =3D=3D c) { - tcg_out32(s, ANDI | SAI(src, dst, c)); + if (!const_arg2) { + tcg_out32(s, AND | SAB(arg1, dst, arg2) | rc); return; - } else if ((c & 0xffff0000) =3D=3D c) { - tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); - return; - } else { - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c); - tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); } -} =20 -static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t= c) -{ - int mb, me; + if (!rc) { + int mb, me; =20 - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); - if (mask64_operand(c, &mb, &me)) { - if (mb =3D=3D 0) { - tcg_out_rld(s, RLDICR, dst, src, 0, me); + if (TCG_TARGET_REG_BITS =3D=3D 32 || type =3D=3D TCG_TYPE_I32) { + if (mask_operand(arg2, &mb, &me)) { + tcg_out_rlw(s, RLWINM, dst, arg1, 0, mb, me); + return; + } } else { - tcg_out_rld(s, RLDICL, dst, src, 0, mb); + if (mask64_operand(arg2, &mb, &me)) { + if (mb =3D=3D 0) { + tcg_out_rld(s, RLDICR, dst, arg1, 0, me); + } else { + tcg_out_rld(s, RLDICL, dst, arg1, 0, mb); + } + return; + } } - } else if ((c & 0xffff) =3D=3D c) { - tcg_out32(s, ANDI | SAI(src, dst, c)); - return; - } else if ((c & 0xffff0000) =3D=3D c) { - tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); - return; + } + + if (type =3D=3D TCG_TYPE_I32) { + arg2 =3D (uint32_t)arg2; + } + if ((arg2 & 0xffff) =3D=3D arg2) { + tcg_out32(s, ANDI | SAI(arg1, dst, arg2)); + } else if ((arg2 & 0xffff0000u) =3D=3D arg2) { + tcg_out32(s, ANDIS | SAI(arg1, dst, arg2 >> 16)); } else { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c); - tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); + tcg_out_movi(s, type, TCG_REG_R0, arg2); + tcg_out32(s, AND | SAB(arg1, dst, TCG_REG_R0) | rc); } } =20 @@ -2892,20 +2892,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_and_i32: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; - if (const_args[2]) { - tcg_out_andi32(s, a0, a1, a2); - } else { - tcg_out32(s, AND | SAB(a1, a0, a2)); - } + tcg_out_and_rc(s, TCG_TYPE_I32, args[0], args[1], + args[2], const_args[2], false); break; case INDEX_op_and_i64: - a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; - if (const_args[2]) { - tcg_out_andi64(s, a0, a1, a2); - } else { - tcg_out32(s, AND | SAB(a1, a0, a2)); - } + tcg_out_and_rc(s, TCG_TYPE_I64, args[0], args[1], + args[2], const_args[2], false); break; case INDEX_op_or_i64: case INDEX_op_or_i32: @@ -2928,7 +2920,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_andc_i32: a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { - tcg_out_andi32(s, a0, a1, ~a2); + tcg_out_and_rc(s, TCG_TYPE_I32, a0, a1, ~a2, true, false); } else { tcg_out32(s, ANDC | SAB(a1, a0, a2)); } @@ -2936,7 +2928,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_andc_i64: a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { - tcg_out_andi64(s, a0, a1, ~a2); + tcg_out_and_rc(s, TCG_TYPE_I64, a0, a1, ~a2, true, false); } else { tcg_out32(s, ANDC | SAB(a1, a0, a2)); } @@ -3270,7 +3262,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_deposit_i32: if (const_args[2]) { uint32_t mask =3D ((2u << (args[4] - 1)) - 1) << args[3]; - tcg_out_andi32(s, args[0], args[0], ~mask); + tcg_out_and_rc(s, TCG_TYPE_I32, args[0], args[0], + ~mask, true, false); } else { tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3], 32 - args[3] - args[4], 31 - args[3]); @@ -3279,7 +3272,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_deposit_i64: if (const_args[2]) { uint64_t mask =3D ((2ull << (args[4] - 1)) - 1) << args[3]; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279698157100019 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 22 +++ target/sparc/translate.c | 320 ++++++++++++++++++++++---------------- 2 files changed, 204 insertions(+), 138 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a7d78eb6c6..7d91a7bc83 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -54,6 +54,28 @@ RDHPR_htba 10 rd:5 101001 00101 0 0000000000000 RDHPR_hver 10 rd:5 101001 00110 0 0000000000000 RDHPR_hstick_cmpr 10 rd:5 101001 11111 0 0000000000000 =20 +{ + RDWIM 10 rd:5 101010 00000 0 0000000000000 + RDPR_tpc 10 rd:5 101010 00000 0 0000000000000 +} +RDPR_tnpc 10 rd:5 101010 00001 0 0000000000000 +RDPR_tstate 10 rd:5 101010 00010 0 0000000000000 +RDPR_tt 10 rd:5 101010 00011 0 0000000000000 +RDPR_tick 10 rd:5 101010 00100 0 0000000000000 +RDPR_tba 10 rd:5 101010 00101 0 0000000000000 +RDPR_pstate 10 rd:5 101010 00110 0 0000000000000 +RDPR_tl 10 rd:5 101010 00111 0 0000000000000 +RDPR_pil 10 rd:5 101010 01000 0 0000000000000 +RDPR_cwp 10 rd:5 101010 01001 0 0000000000000 +RDPR_cansave 10 rd:5 101010 01010 0 0000000000000 +RDPR_canrestore 10 rd:5 101010 01011 0 0000000000000 +RDPR_cleanwin 10 rd:5 101010 01100 0 0000000000000 +RDPR_otherwin 10 rd:5 101010 01101 0 0000000000000 +RDPR_wstate 10 rd:5 101010 01110 0 0000000000000 +RDPR_gl 10 rd:5 101010 10000 0 0000000000000 +RDPR_strand_status 10 rd:5 101010 11010 0 0000000000000 +RDPR_ver 10 rd:5 101010 11111 0 0000000000000 + Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 { # For v7, the entire simm13 field is present, but masked to 7 bits. diff --git a/target/sparc/translate.c b/target/sparc/translate.c index b58c2594ca..6e415d7070 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -40,6 +40,7 @@ # define gen_helper_rdpsr(D, E) qemu_build_not_reached() #else # define gen_helper_rdccr(D, E) qemu_build_not_reached() +# define gen_helper_rdcwp(D, E) qemu_build_not_reached() # define gen_helper_tick_get_count(D, E, T, C) qemu_build_not_reached() # define MAXTL_MASK 0 #endif @@ -61,15 +62,14 @@ static TCGv_i32 cpu_psr; static TCGv cpu_fsr, cpu_pc, cpu_npc; static TCGv cpu_regs[32]; static TCGv cpu_y; -#ifndef CONFIG_USER_ONLY static TCGv cpu_tbr; -#endif static TCGv cpu_cond; #ifdef TARGET_SPARC64 static TCGv_i32 cpu_xcc, cpu_fprs; static TCGv cpu_gsr; static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr; static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver; +# define cpu_wim ({ qemu_build_not_reached(); (TCGv)NULL; }) #else static TCGv cpu_wim; # define cpu_fprs ({ qemu_build_not_reached(); (TCGv)NULL; }) @@ -78,8 +78,10 @@ static TCGv cpu_wim; # define cpu_hstick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_htba ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_hver ({ qemu_build_not_reached(); (TCGv)NULL; }) +# define cpu_ssr ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_stick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_tick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; }) +# define cpu_ver ({ qemu_build_not_reached(); (TCGv)NULL; }) #endif /* Floating point registers */ static TCGv_i64 cpu_fpr[TARGET_DPREGS]; @@ -2709,8 +2711,7 @@ static void gen_fmovq(DisasContext *dc, DisasCompare = *cmp, int rd, int rs) gen_update_fprs_dirty(dc, qd); } =20 -#ifndef CONFIG_USER_ONLY -static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env tcg_env) +static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr) { TCGv_i32 r_tl =3D tcg_temp_new_i32(); =20 @@ -2731,7 +2732,6 @@ static void gen_load_trap_state_at_tl(TCGv_ptr r_tspt= r, TCGv_env tcg_env) tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp); } } -#endif =20 static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, int width, bool cc, bool left) @@ -2866,11 +2866,13 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv= s1, TCGv s2) # define avail_32(C) false # define avail_ASR17(C) false # define avail_64(C) true +# define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL) # define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV) #else # define avail_32(C) true # define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17) # define avail_64(C) false +# define avail_GL(C) false # define avail_HYPV(C) false #endif =20 @@ -3389,6 +3391,177 @@ static TCGv do_rdhstick_cmpr(DisasContext *dc, TCGv= dst) TRANS(RDHPR_hstick_cmpr, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhstick_cmpr) =20 +static TCGv do_rdwim(DisasContext *dc, TCGv dst) +{ + return cpu_wim; +} + +TRANS(RDWIM, 32, do_rd_special, supervisor(dc), a->rd, do_rdwim) + +static TCGv do_rdtpc(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tsptr =3D tcg_temp_new_ptr(); + + gen_load_trap_state_at_tl(r_tsptr); + tcg_gen_ld_tl(dst, r_tsptr, offsetof(trap_state, tpc)); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDPR_tpc, 64, do_rd_special, supervisor(dc), a->rd, do_rdtpc) + +static TCGv do_rdtnpc(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tsptr =3D tcg_temp_new_ptr(); + + gen_load_trap_state_at_tl(r_tsptr); + tcg_gen_ld_tl(dst, r_tsptr, offsetof(trap_state, tnpc)); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDPR_tnpc, 64, do_rd_special, supervisor(dc), a->rd, do_rdtnpc) + +static TCGv do_rdtstate(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tsptr =3D tcg_temp_new_ptr(); + + gen_load_trap_state_at_tl(r_tsptr); + tcg_gen_ld_tl(dst, r_tsptr, offsetof(trap_state, tstate)); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDPR_tstate, 64, do_rd_special, supervisor(dc), a->rd, do_rdtstate) + +static TCGv do_rdtt(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tsptr =3D tcg_temp_new_ptr(); + + gen_load_trap_state_at_tl(r_tsptr); + tcg_gen_ld32s_tl(dst, r_tsptr, offsetof(trap_state, tt)); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDPR_tt, 64, do_rd_special, supervisor(dc), a->rd, do_rdtt) +TRANS(RDPR_tick, 64, do_rd_special, supervisor(dc), a->rd, do_rdtick) + +static TCGv do_rdtba(DisasContext *dc, TCGv dst) +{ + return cpu_tbr; +} + +TRANS(RDPR_tba, 64, do_rd_special, supervisor(dc), a->rd, do_rdtba) + +static TCGv do_rdpstate(DisasContext *dc, TCGv dst) +{ + tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(pstate)); + return dst; +} + +TRANS(RDPR_pstate, 64, do_rd_special, supervisor(dc), a->rd, do_rdpstate) + +static TCGv do_rdtl(DisasContext *dc, TCGv dst) +{ + tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(tl)); + return dst; +} + +TRANS(RDPR_tl, 64, do_rd_special, supervisor(dc), a->rd, do_rdtl) + +static TCGv do_rdpil(DisasContext *dc, TCGv dst) +{ + tcg_gen_ld32s_tl(dst, tcg_env, env_field_offsetof(psrpil)); + return dst; +} + +TRANS(RDPR_pil, 64, do_rd_special, supervisor(dc), a->rd, do_rdpil) + +static TCGv do_rdcwp(DisasContext *dc, TCGv dst) +{ + gen_helper_rdcwp(dst, tcg_env); + return dst; +} + +TRANS(RDPR_cwp, 64, do_rd_special, supervisor(dc), a->rd, do_rdcwp) + +static TCGv do_rdcansave(DisasContext *dc, TCGv dst) +{ + tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(cansave)); + return dst; +} + +TRANS(RDPR_cansave, 64, do_rd_special, supervisor(dc), a->rd, do_rdcansave) + +static TCGv do_rdcanrestore(DisasContext *dc, TCGv dst) +{ + tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(canrestore)); + return dst; +} + +TRANS(RDPR_canrestore, 64, do_rd_special, supervisor(dc), a->rd, + do_rdcanrestore) + +static TCGv do_rdcleanwin(DisasContext *dc, TCGv dst) +{ + tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(cleanwin)); + return dst; +} + +TRANS(RDPR_cleanwin, 64, do_rd_special, supervisor(dc), a->rd, do_rdcleanw= in) + +static TCGv do_rdotherwin(DisasContext *dc, TCGv dst) +{ + tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(otherwin)); + return dst; +} + +TRANS(RDPR_otherwin, 64, do_rd_special, supervisor(dc), a->rd, do_rdotherw= in) + +static TCGv do_rdwstate(DisasContext *dc, TCGv dst) +{ + tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(wstate)); + return dst; +} + +TRANS(RDPR_wstate, 64, do_rd_special, supervisor(dc), a->rd, do_rdwstate) + +static TCGv do_rdgl(DisasContext *dc, TCGv dst) +{ + tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(gl)); + return dst; +} + +TRANS(RDPR_gl, GL, do_rd_special, supervisor(dc), a->rd, do_rdgl) + +/* UA2005 strand status */ +static TCGv do_rdssr(DisasContext *dc, TCGv dst) +{ + return cpu_ssr; +} + +TRANS(RDPR_strand_status, HYPV, do_rd_special, hypervisor(dc), a->rd, do_r= dssr) + +static TCGv do_rdver(DisasContext *dc, TCGv dst) +{ + return cpu_ver; +} + +TRANS(RDPR_ver, 64, do_rd_special, supervisor(dc), a->rd, do_rdver) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -3419,133 +3592,6 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) TCGv cpu_dst __attribute__((unused)) =3D tcg_temp_new(); TCGv cpu_tmp0 __attribute__((unused)); =20 -#if !defined(CONFIG_USER_ONLY) - if (xop =3D=3D 0x2a) { /* rdwim / V9 rdpr */ - if (!supervisor(dc)) { - goto priv_insn; - } - cpu_tmp0 =3D tcg_temp_new(); -#ifdef TARGET_SPARC64 - rs1 =3D GET_FIELD(insn, 13, 17); - switch (rs1) { - case 0: // tpc - { - TCGv_ptr r_tsptr; - - r_tsptr =3D tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, tcg_env); - tcg_gen_ld_tl(cpu_tmp0, r_tsptr, - offsetof(trap_state, tpc)); - } - break; - case 1: // tnpc - { - TCGv_ptr r_tsptr; - - r_tsptr =3D tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, tcg_env); - tcg_gen_ld_tl(cpu_tmp0, r_tsptr, - offsetof(trap_state, tnpc)); - } - break; - case 2: // tstate - { - TCGv_ptr r_tsptr; - - r_tsptr =3D tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, tcg_env); - tcg_gen_ld_tl(cpu_tmp0, r_tsptr, - offsetof(trap_state, tstate)); - } - break; - case 3: // tt - { - TCGv_ptr r_tsptr =3D tcg_temp_new_ptr(); - - gen_load_trap_state_at_tl(r_tsptr, tcg_env); - tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr, - offsetof(trap_state, tt)); - } - break; - case 4: // tick - { - TCGv_ptr r_tickptr; - TCGv_i32 r_const; - - r_tickptr =3D tcg_temp_new_ptr(); - r_const =3D tcg_constant_i32(dc->mem_idx); - tcg_gen_ld_ptr(r_tickptr, tcg_env, - offsetof(CPUSPARCState, tick)); - if (translator_io_start(&dc->base)) { - dc->base.is_jmp =3D DISAS_EXIT; - } - gen_helper_tick_get_count(cpu_tmp0, tcg_env, - r_tickptr, r_const); - } - break; - case 5: // tba - tcg_gen_mov_tl(cpu_tmp0, cpu_tbr); - break; - case 6: // pstate - tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, pstate)); - break; - case 7: // tl - tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, tl)); - break; - case 8: // pil - tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, psrpil)); - break; - case 9: // cwp - gen_helper_rdcwp(cpu_tmp0, tcg_env); - break; - case 10: // cansave - tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, cansave)); - break; - case 11: // canrestore - tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, canrestore)); - break; - case 12: // cleanwin - tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, cleanwin)); - break; - case 13: // otherwin - tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, otherwin)); - break; - case 14: // wstate - tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, wstate)); - break; - case 16: // UA2005 gl - CHECK_IU_FEATURE(dc, GL); - tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, gl)); - break; - case 26: // UA2005 strand status - CHECK_IU_FEATURE(dc, HYPV); - if (!hypervisor(dc)) - goto priv_insn; - tcg_gen_mov_tl(cpu_tmp0, cpu_ssr); - break; - case 31: // ver - tcg_gen_mov_tl(cpu_tmp0, cpu_ver); - break; - case 15: // fq - default: - goto illegal_insn; - } -#else - tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim); -#endif - gen_store_gpr(dc, rd, cpu_tmp0); - break; - } -#endif #if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY) if (xop =3D=3D 0x2b) { /* rdtbr / V9 flushw */ #ifdef TARGET_SPARC64 @@ -4391,7 +4437,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) TCGv_ptr r_tsptr; =20 r_tsptr =3D tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, tcg= _env); + gen_load_trap_state_at_tl(r_tsptr); tcg_gen_st_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tpc= )); } @@ -4401,7 +4447,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) TCGv_ptr r_tsptr; =20 r_tsptr =3D tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, tcg= _env); + gen_load_trap_state_at_tl(r_tsptr); tcg_gen_st_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tnp= c)); } @@ -4411,7 +4457,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) TCGv_ptr r_tsptr; =20 r_tsptr =3D tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, tcg= _env); + gen_load_trap_state_at_tl(r_tsptr); tcg_gen_st_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tstate)); @@ -4422,7 +4468,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) TCGv_ptr r_tsptr; =20 r_tsptr =3D tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, tcg= _env); + gen_load_trap_state_at_tl(r_tsptr); tcg_gen_st32_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, t= t)); } @@ -5851,9 +5897,7 @@ void sparc_tcg_init(void) { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" }, { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" }, { &cpu_y, offsetof(CPUSPARCState, y), "y" }, -#ifndef CONFIG_USER_ONLY { &cpu_tbr, offsetof(CPUSPARCState, tbr), "tbr" }, -#endif }; =20 unsigned int i; --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280680238100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index fe141a26f9..5a316f364d 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -669,9 +669,11 @@ enum { CR_SO }; =20 -static const uint32_t tcg_to_bc[] =3D { +static const uint32_t tcg_to_bc[16] =3D { [TCG_COND_EQ] =3D BC | BI(0, CR_EQ) | BO_COND_TRUE, [TCG_COND_NE] =3D BC | BI(0, CR_EQ) | BO_COND_FALSE, + [TCG_COND_TSTEQ] =3D BC | BI(0, CR_EQ) | BO_COND_TRUE, + [TCG_COND_TSTNE] =3D BC | BI(0, CR_EQ) | BO_COND_FALSE, [TCG_COND_LT] =3D BC | BI(0, CR_LT) | BO_COND_TRUE, [TCG_COND_GE] =3D BC | BI(0, CR_LT) | BO_COND_FALSE, [TCG_COND_LE] =3D BC | BI(0, CR_GT) | BO_COND_FALSE, @@ -683,9 +685,11 @@ static const uint32_t tcg_to_bc[] =3D { }; =20 /* The low bit here is set if the RA and RB fields must be inverted. */ -static const uint32_t tcg_to_isel[] =3D { +static const uint32_t tcg_to_isel[16] =3D { [TCG_COND_EQ] =3D ISEL | BC_(0, CR_EQ), [TCG_COND_NE] =3D ISEL | BC_(0, CR_EQ) | 1, + [TCG_COND_TSTEQ] =3D ISEL | BC_(0, CR_EQ), + [TCG_COND_TSTNE] =3D ISEL | BC_(0, CR_EQ) | 1, [TCG_COND_LT] =3D ISEL | BC_(0, CR_LT), [TCG_COND_GE] =3D ISEL | BC_(0, CR_LT) | 1, [TCG_COND_LE] =3D ISEL | BC_(0, CR_GT) | 1, @@ -1699,6 +1703,12 @@ static void tcg_out_cmp(TCGContext *s, int cond, TCG= Arg arg1, TCGArg arg2, imm =3D 0; break; =20 + case TCG_COND_TSTEQ: + case TCG_COND_TSTNE: + tcg_debug_assert(cr =3D=3D 0); + tcg_out_and_rc(s, type, TCG_REG_R0, arg1, arg2, const_arg2, true); + return; + case TCG_COND_LT: case TCG_COND_GE: case TCG_COND_LE: @@ -1909,6 +1919,16 @@ static void tcg_out_setcond(TCGContext *s, TCGType t= ype, TCGCond cond, tcg_out_setcond_ne0(s, type, arg0, arg1, neg); break; =20 + case TCG_COND_TSTEQ: + tcg_out_and_rc(s, type, TCG_REG_R0, arg1, arg2, const_arg2, false); + tcg_out_setcond_eq0(s, type, arg0, TCG_REG_R0, neg); + break; + + case TCG_COND_TSTNE: + tcg_out_and_rc(s, type, TCG_REG_R0, arg1, arg2, const_arg2, false); + tcg_out_setcond_ne0(s, type, arg0, TCG_REG_R0, neg); + break; + case TCG_COND_LE: case TCG_COND_LEU: inv =3D true; @@ -2081,6 +2101,13 @@ static void tcg_out_cmp2(TCGContext *s, const TCGArg= *args, tcg_out32(s, op | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); break; =20 + case TCG_COND_TSTEQ: + case TCG_COND_TSTNE: + tcg_out_and_rc(s, TCG_TYPE_I32, TCG_REG_R0, al, bl, blconst, false= ); + tcg_out_and_rc(s, TCG_TYPE_I32, TCG_REG_TMP1, ah, bh, bhconst, fal= se); + tcg_out32(s, OR | SAB(TCG_REG_R0, TCG_REG_R0, TCG_REG_TMP1) | 1); + break; + case TCG_COND_LT: case TCG_COND_LE: case TCG_COND_GT: --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279735; cv=none; d=zohomail.com; s=zohoarc; b=FA9NV3K9givYu++Z3tmjInEK5uedAhXoCrbEzuYZZ2jUSIw45BPNcFUcghwmcwxUoWCofRc4EKF7frbe9/zXnodckIol5MAELrsMd8murs9QHJHbJaG14h1i7KteZqVG/G3xoxavUsoeR43JE5v9qVYCFX1CDOVYWdwLPOHEkzk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279735; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279736379100002 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 5 +++++ target/sparc/translate.c | 23 +++++++++++------------ 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 7d91a7bc83..0b6f4c9c38 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -76,6 +76,11 @@ RDPR_gl 10 rd:5 101010 10000 0 0000000000000 RDPR_strand_status 10 rd:5 101010 11010 0 0000000000000 RDPR_ver 10 rd:5 101010 11111 0 0000000000000 =20 +{ + FLUSHW 10 00000 101011 00000 0 0000000000000 + RDTBR 10 rd:5 101011 00000 0 0000000000000 +} + Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 { # For v7, the entire simm13 field is present, but masked to 7 bits. diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 6e415d7070..67d3292e68 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -39,6 +39,7 @@ #ifdef TARGET_SPARC64 # define gen_helper_rdpsr(D, E) qemu_build_not_reached() #else +# define gen_helper_flushw(E) qemu_build_not_reached() # define gen_helper_rdccr(D, E) qemu_build_not_reached() # define gen_helper_rdcwp(D, E) qemu_build_not_reached() # define gen_helper_tick_get_count(D, E, T, C) qemu_build_not_reached() @@ -3464,6 +3465,7 @@ static TCGv do_rdtba(DisasContext *dc, TCGv dst) return cpu_tbr; } =20 +TRANS(RDTBR, 32, do_rd_special, supervisor(dc), a->rd, do_rdtba) TRANS(RDPR_tba, 64, do_rd_special, supervisor(dc), a->rd, do_rdtba) =20 static TCGv do_rdpstate(DisasContext *dc, TCGv dst) @@ -3562,6 +3564,15 @@ static TCGv do_rdver(DisasContext *dc, TCGv dst) =20 TRANS(RDPR_ver, 64, do_rd_special, supervisor(dc), a->rd, do_rdver) =20 +static bool trans_FLUSHW(DisasContext *dc, arg_FLUSHW *a) +{ + if (avail_64(dc)) { + gen_helper_flushw(tcg_env); + return advance_pc(dc); + } + return false; +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -3592,18 +3603,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) TCGv cpu_dst __attribute__((unused)) =3D tcg_temp_new(); TCGv cpu_tmp0 __attribute__((unused)); =20 -#if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY) - if (xop =3D=3D 0x2b) { /* rdtbr / V9 flushw */ -#ifdef TARGET_SPARC64 - gen_helper_flushw(tcg_env); -#else - if (!supervisor(dc)) - goto priv_insn; - gen_store_gpr(dc, rd, cpu_tbr); -#endif - break; - } -#endif if (xop =3D=3D 0x34) { /* FPU Operations */ if (gen_trap_ifnofpu(dc)) { goto jmp_insn; --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280127; cv=none; d=zohomail.com; s=zohoarc; b=kY4PnO+9fyxaDt1TcloidLHnryFJWp+KYJW7pOU1LnIiOtTCDlxbXSTUK4JhmrdZi0v5FtkPRUNdYHNMB2jlnZgx3W4Q3pKHwStSPbzSreQWNTKG+fYGf3rpxy92bx+rTuYOxlMrRkiRy/PAwMl/m4XJXK3Iay0EEbXYSRZUZ9Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280127; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279566; x=1698884366; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wPe+9mvEGZleEWGbkTca1tKdwjbDs6ccbxNSMhBGMcE=; b=u4WrU2RDOIOiLKOCL9ymNOTtSaaE6QadfzrVtAz11IRGjoq975nv52aYZFyo/jeEqJ osBcDnMMpkOaCcJQK4ReNNzIvdPQD5cwcwXQDxGIibwgPqhcEfjI4ex8cDZQUpYAWjCq sehthAdcw/xLMf7a3p48Qn1SVDyycQ5ue3GQllhRoZC4a1hzWfayfwsy9VmTP9w55RTk 7HAMXTDJf64bvoq3sEE0+Wlrk9AIIH7VxnZ8uqlN1NYSw405AKnaI9ttuP4pqUqLCU7j zd2mNr/XCmPLXBCUCoxNLrOpvJkZopXKrtnkLvVOSf2o3IzADAJYy63npphFNwLn0Bdq xVaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279566; x=1698884366; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wPe+9mvEGZleEWGbkTca1tKdwjbDs6ccbxNSMhBGMcE=; b=rfm8aC2XdeQsfdfK7CgqMfP90rq2f5/0MRBoJiikSDn5XyQCE19XosiPrwl/QPT1NR NBD0Bf19nYTsvsn7XCEb3hNst9GPXcswx8/hM+6O0LoqWF/SpR2qrr0yKAqf/gwzFqxy KjhulbPA7ynfRMRdXaUaDLcO5EPTjfvSUihts2M33uv7BfAJPG2nSPfvcW8mQWSEUBpt VMbi2jRMGn/bq/GSu3U1QoDFfG67uiHfnqq7K8d57qoTQayz9ylajiBYO7qtY1NWuOlS bCq3PXESW+I1dkOQEYXa9XdCXS9L5bgPgkbfnACOsvzI0W34uCnGINNsdxkV7o4W9Xh6 IOpw== X-Gm-Message-State: AOJu0Yw72kdvqIboRt2ZGxZdYt2xCOJEbCqlPk3ruZ2jXFUPBNEoo+Wv sdweBJSmo/ukZjQ2Es50b28+NLzjxR+D0GKEfmA= X-Google-Smtp-Source: AGHT+IG92UXMDL9U9OPXM4Y2ElX603uxk6Kcn7Q9OuzDC48UI7OslQo4LQS2Bp7puaMOXXeQE0wbuw== X-Received: by 2002:a17:903:11c5:b0:1c7:23c9:a7e1 with SMTP id q5-20020a17090311c500b001c723c9a7e1mr16159020plh.26.1698279565651; Wed, 25 Oct 2023 17:19:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 25/29] tcg/s390x: Support TCG_COND_TST{EQ,NE} Date: Wed, 25 Oct 2023 17:14:29 -0700 Message-Id: <20231026001542.1141412-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280127487100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 127 +++++++++++++++++++++++++------------ 1 file changed, 88 insertions(+), 39 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index fbee43d3b0..ef3cb87e9f 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -111,6 +111,9 @@ typedef enum S390Opcode { RI_OILH =3D 0xa50a, RI_OILL =3D 0xa50b, RI_TMLL =3D 0xa701, + RI_TMLH =3D 0xa700, + RI_TMHL =3D 0xa703, + RI_TMHH =3D 0xa702, =20 RIEb_CGRJ =3D 0xec64, RIEb_CLGRJ =3D 0xec65, @@ -403,10 +406,15 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnK= ind kind, int slot) #define S390_CC_NEVER 0 #define S390_CC_ALWAYS 15 =20 +#define S390_TM_EQ 8 /* CC =3D=3D 0 */ +#define S390_TM_NE 7 /* CC in {1,2,3} */ + /* Condition codes that result from a COMPARE and COMPARE LOGICAL. */ -static const uint8_t tcg_cond_to_s390_cond[] =3D { +static const uint8_t tcg_cond_to_s390_cond[16] =3D { [TCG_COND_EQ] =3D S390_CC_EQ, [TCG_COND_NE] =3D S390_CC_NE, + [TCG_COND_TSTEQ] =3D S390_CC_EQ, + [TCG_COND_TSTNE] =3D S390_CC_NE, [TCG_COND_LT] =3D S390_CC_LT, [TCG_COND_LE] =3D S390_CC_LE, [TCG_COND_GT] =3D S390_CC_GT, @@ -420,9 +428,11 @@ static const uint8_t tcg_cond_to_s390_cond[] =3D { /* Condition codes that result from a LOAD AND TEST. Here, we have no unsigned instruction variation, however since the test is vs zero we can re-map the outcomes appropriately. */ -static const uint8_t tcg_cond_to_ltr_cond[] =3D { +static const uint8_t tcg_cond_to_ltr_cond[16] =3D { [TCG_COND_EQ] =3D S390_CC_EQ, [TCG_COND_NE] =3D S390_CC_NE, + [TCG_COND_TSTEQ] =3D S390_CC_ALWAYS, + [TCG_COND_TSTNE] =3D S390_CC_NEVER, [TCG_COND_LT] =3D S390_CC_LT, [TCG_COND_LE] =3D S390_CC_LE, [TCG_COND_GT] =3D S390_CC_GT, @@ -843,6 +853,9 @@ static const S390Opcode oi_insns[4] =3D { static const S390Opcode lif_insns[2] =3D { RIL_LLILF, RIL_LLIHF, }; +static const S390Opcode tm_insns[4] =3D { + RI_TMLL, RI_TMLH, RI_TMHL, RI_TMHH +}; =20 /* load a register with an immediate value */ static void tcg_out_movi(TCGContext *s, TCGType type, @@ -1203,6 +1216,40 @@ static int tgen_cmp2(TCGContext *s, TCGType type, TC= GCond c, TCGReg r1, TCGCond inv_c =3D tcg_invert_cond(c); S390Opcode op; =20 + if (is_tst_cond(c)) { + tcg_debug_assert(!need_carry); + + if (c2const) { + int i; + + if (type =3D=3D TCG_TYPE_I32) { + c2 =3D (uint32_t)c2; + } + + i =3D is_const_p16(c2); + if (i >=3D 0) { + tcg_out_insn_RI(s, tm_insns[i], r1, c2 >> (i * 16)); + *inv_cc =3D TCG_COND_TSTEQ ? S390_TM_NE : S390_TM_EQ; + return *inv_cc ^ 15; + } + + if (risbg_mask(c2)) { + tgen_andi_risbg(s, TCG_REG_R0, r1, c2); + goto exit; + } + + tcg_out_movi(s, type, TCG_REG_R0, c2); + c2 =3D TCG_REG_R0; + } + + if (type =3D=3D TCG_TYPE_I32) { + tcg_out_insn(s, RRFa, NRK, TCG_REG_R0, r1, c2); + } else { + tcg_out_insn(s, RRFa, NGRK, TCG_REG_R0, r1, c2); + } + goto exit; + } + if (c2const) { if (c2 =3D=3D 0) { if (!(is_unsigned && need_carry)) { @@ -1516,46 +1563,49 @@ static void tgen_brcond(TCGContext *s, TCGType type= , TCGCond c, TCGReg r1, TCGArg c2, int c2const, TCGLabel *l) { int cc; - bool is_unsigned =3D is_unsigned_cond(c); - bool in_range; - S390Opcode opc; =20 - cc =3D tcg_cond_to_s390_cond[c]; + if (!is_tst_cond(c)) { + bool is_unsigned =3D is_unsigned_cond(c); + bool in_range; + S390Opcode opc; =20 - if (!c2const) { - opc =3D (type =3D=3D TCG_TYPE_I32 - ? (is_unsigned ? RIEb_CLRJ : RIEb_CRJ) - : (is_unsigned ? RIEb_CLGRJ : RIEb_CGRJ)); - tgen_compare_branch(s, opc, cc, r1, c2, l); - return; - } + cc =3D tcg_cond_to_s390_cond[c]; =20 - /* - * COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field. - * If the immediate we've been given does not fit that range, we'll - * fall back to separate compare and branch instructions using the - * larger comparison range afforded by COMPARE IMMEDIATE. - */ - if (type =3D=3D TCG_TYPE_I32) { - if (is_unsigned) { - opc =3D RIEc_CLIJ; - in_range =3D (uint32_t)c2 =3D=3D (uint8_t)c2; - } else { - opc =3D RIEc_CIJ; - in_range =3D (int32_t)c2 =3D=3D (int8_t)c2; + if (!c2const) { + opc =3D (type =3D=3D TCG_TYPE_I32 + ? (is_unsigned ? RIEb_CLRJ : RIEb_CRJ) + : (is_unsigned ? RIEb_CLGRJ : RIEb_CGRJ)); + tgen_compare_branch(s, opc, cc, r1, c2, l); + return; } - } else { - if (is_unsigned) { - opc =3D RIEc_CLGIJ; - in_range =3D (uint64_t)c2 =3D=3D (uint8_t)c2; + + /* + * COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate fi= eld. + * If the immediate we've been given does not fit that range, we'll + * fall back to separate compare and branch instructions using the + * larger comparison range afforded by COMPARE IMMEDIATE. + */ + if (type =3D=3D TCG_TYPE_I32) { + if (is_unsigned) { + opc =3D RIEc_CLIJ; + in_range =3D (uint32_t)c2 =3D=3D (uint8_t)c2; + } else { + opc =3D RIEc_CIJ; + in_range =3D (int32_t)c2 =3D=3D (int8_t)c2; + } } else { - opc =3D RIEc_CGIJ; - in_range =3D (int64_t)c2 =3D=3D (int8_t)c2; + if (is_unsigned) { + opc =3D RIEc_CLGIJ; + in_range =3D (uint64_t)c2 =3D=3D (uint8_t)c2; + } else { + opc =3D RIEc_CGIJ; + in_range =3D (int64_t)c2 =3D=3D (int8_t)c2; + } + } + if (in_range) { + tgen_compare_imm_branch(s, opc, cc, r1, c2, l); + return; } - } - if (in_range) { - tgen_compare_imm_branch(s, opc, cc, r1, c2, l); - return; } =20 cc =3D tgen_cmp(s, type, c, r1, c2, c2const, false); @@ -1834,11 +1884,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, ldst->oi =3D oi; ldst->addrlo_reg =3D addr_reg; =20 - /* We are expecting a_bits to max out at 7, much lower than TM= LL. */ tcg_debug_assert(a_mask <=3D 0xffff); tcg_out_insn(s, RI, TMLL, addr_reg, a_mask); =20 - tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */ + tcg_out16(s, RI_BRC | (S390_TM_NE << 4)); ldst->label_ptr[0] =3D s->code_ptr++; } =20 @@ -1919,7 +1968,7 @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCG= Reg datalo, TCGReg datahi, l2 =3D gen_new_label(); =20 tcg_out_insn(s, RI, TMLL, addr_reg, 15); - tgen_branch(s, 7, l1); /* CC in {1,2,3} */ + tgen_branch(s, S390_TM_NE, l1); } =20 tcg_debug_assert(!need_bswap); --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279912; cv=none; d=zohomail.com; s=zohoarc; b=SJXQZaQA6+UXBIfKGu2VxAy/If+kUqOwPsOeSOypsItA4MA95IjXQFtQQbq20fIh7vWPAlyEIZJdW4wNcX6N/B6Dpig327fCTNtIJ61oFioc01vwLcShcMxia5TYKO43c72x96ZlgdQJvRIf7i7wON7DTvR1bN26QPtAFBU/JH8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279912; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gGK19oqCFLGpJxLElL4pMg6Vo+LqjA3vsLHYvqIIZnI=; b=TUauP3h5a8Wt+v/gU/b3tQRDYws4RozL09uDnksxYdxX9OAtfwGwPM4jL7YhrY8y+UCFtb3Rmfvh3E0wJO/wlEmikDindgvWgXF9xXHL84BVP7d8TetWrcoCPngi32LWxZlgNKFQ//6/i0dkKt6kk+3asqFgdoibPFL71XBG8YI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698279912271828.2983871781787; Wed, 25 Oct 2023 17:25:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo6K-0001PU-RY; Wed, 25 Oct 2023 20:19:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo68-0000v2-KZ for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:42 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo5v-0006bz-WE for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:40 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1c9c5a1b87bso2052185ad.3 for ; Wed, 25 Oct 2023 17:19:27 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279912902100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 31 ++++ target/sparc/translate.c | 341 +++++++++++++++++++++----------------- 2 files changed, 216 insertions(+), 156 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 0b6f4c9c38..118f0f1f17 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -22,6 +22,13 @@ SETHI 00 rd:5 100 i:22 =20 CALL 01 i:s30 =20 +## +## Major Opcode 10 -- integer, floating-point, vis, and system insns. +## + +&r_r_ri rd rs1 rs2_or_imm imm:bool +@n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=3D0 + { [ STBAR 10 00000 101000 01111 0 0000000000000 @@ -44,6 +51,30 @@ CALL 01 i:s30 RDY 10 rd:5 101000 rs1:5 0 0000000000000 } =20 +{ + [ + WRY 10 00000 110000 ..... . ............. @n_r_ri + WRCCR 10 00010 110000 ..... . ............. @n_r_ri + WRASI 10 00011 110000 ..... . ............. @n_r_ri + WRFPRS 10 00110 110000 ..... . ............. @n_r_ri + { + WRGSR 10 10011 110000 ..... . ............. @n_r_ri + WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri + } + WRSOFTINT_SET 10 10100 110000 ..... . ............. @n_r_ri + WRSOFTINT_CLR 10 10101 110000 ..... . ............. @n_r_ri + WRSOFTINT 10 10110 110000 ..... . ............. @n_r_ri + WRTICK_CMPR 10 10111 110000 ..... . ............. @n_r_ri + WRSTICK 10 11000 110000 ..... . ............. @n_r_ri + WRSTICK_CMPR 10 11001 110000 ..... . ............. @n_r_ri + ] + # Before v8, rs1=3D=3D0 was WRY, and the rest executed as nop. + [ + NOP_v7 10 ----- 110000 ----- 0 00000000 ----- + NOP_v7 10 ----- 110000 ----- 1 -------- ----- + ] +} + { RDPSR 10 rd:5 101001 00000 0 0000000000000 RDHPR_hpstate 10 rd:5 101001 00000 0 0000000000000 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 67d3292e68..83716307f6 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -38,11 +38,16 @@ =20 #ifdef TARGET_SPARC64 # define gen_helper_rdpsr(D, E) qemu_build_not_reached() +# define gen_helper_power_down(E) qemu_build_not_reached() #else +# define gen_helper_clear_softint(E, S) qemu_build_not_reached() # define gen_helper_flushw(E) qemu_build_not_reached() # define gen_helper_rdccr(D, E) qemu_build_not_reached() # define gen_helper_rdcwp(D, E) qemu_build_not_reached() +# define gen_helper_set_softint(E, S) qemu_build_not_reached() # define gen_helper_tick_get_count(D, E, T, C) qemu_build_not_reached() +# define gen_helper_wrccr(E, S) qemu_build_not_reached() +# define gen_helper_write_softint(E, S) qemu_build_not_reached() # define MAXTL_MASK 0 #endif =20 @@ -2866,12 +2871,14 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv= s1, TCGv s2) #ifdef TARGET_SPARC64 # define avail_32(C) false # define avail_ASR17(C) false +# define avail_POWERDOWN(C) false # define avail_64(C) true # define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL) # define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV) #else # define avail_32(C) true # define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17) +# define avail_POWERDOWN(C) ((C)->def->features & CPU_FEATURE_POWERDOWN) # define avail_64(C) false # define avail_GL(C) false # define avail_HYPV(C) false @@ -3077,6 +3084,10 @@ static bool trans_SETHI(DisasContext *dc, arg_SETHI = *a) return advance_pc(dc); } =20 +/* + * Major Opcode 10 -- integer, floating-point, vis, and system insns. + */ + static bool do_tcc(DisasContext *dc, int cond, int cc, int rs1, bool imm, int rs2_or_imm) { @@ -3573,6 +3584,179 @@ static bool trans_FLUSHW(DisasContext *dc, arg_FLUS= HW *a) return false; } =20 +static bool do_wr_special(DisasContext *dc, arg_r_r_ri *a, bool priv, + void (*func)(DisasContext *, TCGv)) +{ + TCGv src; + + /* For simplicity, we under-decoded the rs2 form. */ + if (!a->imm && (a->rs2_or_imm & ~0x1f)) { + return false; + } + if (!priv) { + return raise_priv(dc); + } + + if (a->rs1 =3D=3D 0 && (a->imm || a->rs2_or_imm =3D=3D 0)) { + src =3D tcg_constant_tl(a->rs2_or_imm); + } else { + TCGv src1 =3D gen_load_gpr(dc, a->rs1); + if (a->rs2_or_imm =3D=3D 0) { + src =3D src1; + } else { + src =3D tcg_temp_new(); + if (a->imm) { + tcg_gen_xori_tl(src, src1, a->rs2_or_imm); + } else { + tcg_gen_xor_tl(src, src1, gen_load_gpr(dc, a->rs2_or_imm)); + } + } + } + func(dc, src); + return advance_pc(dc); +} + +static void do_wry(DisasContext *dc, TCGv src) +{ + tcg_gen_ext32u_tl(cpu_y, src); +} + +TRANS(WRY, ALL, do_wr_special, a, true, do_wry) + +static void do_wrccr(DisasContext *dc, TCGv src) +{ + gen_helper_wrccr(tcg_env, src); +} + +TRANS(WRCCR, 64, do_wr_special, a, true, do_wrccr) + +static void do_wrasi(DisasContext *dc, TCGv src) +{ + TCGv tmp =3D tcg_temp_new(); + + tcg_gen_ext8u_tl(tmp, src); + tcg_gen_st32_tl(tmp, tcg_env, env64_field_offsetof(asi)); + /* End TB to notice changed ASI. */ + dc->base.is_jmp =3D DISAS_EXIT; +} + +TRANS(WRASI, 64, do_wr_special, a, true, do_wrasi) + +static void do_wrfprs(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + tcg_gen_trunc_tl_i32(cpu_fprs, src); + dc->fprs_dirty =3D 0; + dc->base.is_jmp =3D DISAS_EXIT; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRFPRS, 64, do_wr_special, a, true, do_wrfprs) + +static void do_wrgsr(DisasContext *dc, TCGv src) +{ + gen_trap_ifnofpu(dc); + tcg_gen_mov_tl(cpu_gsr, src); +} + +TRANS(WRGSR, 64, do_wr_special, a, true, do_wrgsr) + +static void do_wrsoftint_set(DisasContext *dc, TCGv src) +{ + gen_helper_set_softint(tcg_env, src); +} + +TRANS(WRSOFTINT_SET, 64, do_wr_special, a, supervisor(dc), do_wrsoftint_se= t) + +static void do_wrsoftint_clr(DisasContext *dc, TCGv src) +{ + gen_helper_clear_softint(tcg_env, src); +} + +TRANS(WRSOFTINT_CLR, 64, do_wr_special, a, supervisor(dc), do_wrsoftint_cl= r) + +static void do_wrsoftint(DisasContext *dc, TCGv src) +{ + gen_helper_write_softint(tcg_env, src); +} + +TRANS(WRSOFTINT, 64, do_wr_special, a, supervisor(dc), do_wrsoftint) + +static void do_wrtick_cmpr(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tickptr =3D tcg_temp_new_ptr(); + + tcg_gen_mov_tl(cpu_tick_cmpr, src); + tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, tick)); + translator_io_start(&dc->base); + gen_helper_tick_set_limit(r_tickptr, cpu_tick_cmpr); + /* End TB to handle timer interrupt */ + dc->base.is_jmp =3D DISAS_EXIT; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRTICK_CMPR, 64, do_wr_special, a, supervisor(dc), do_wrtick_cmpr) + +static void do_wrstick(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tickptr =3D tcg_temp_new_ptr(); + + tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, stick)); + translator_io_start(&dc->base); + gen_helper_tick_set_count(r_tickptr, src); + /* End TB to handle timer interrupt */ + dc->base.is_jmp =3D DISAS_EXIT; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRSTICK, 64, do_wr_special, a, supervisor(dc), do_wrstick) + +static void do_wrstick_cmpr(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tickptr =3D tcg_temp_new_ptr(); + + tcg_gen_mov_tl(cpu_stick_cmpr, src); + tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, stick)); + translator_io_start(&dc->base); + gen_helper_tick_set_limit(r_tickptr, cpu_stick_cmpr); + /* End TB to handle timer interrupt */ + dc->base.is_jmp =3D DISAS_EXIT; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRSTICK_CMPR, 64, do_wr_special, a, supervisor(dc), do_wrstick_cmpr) + +static void do_wrpowerdown(DisasContext *dc, TCGv src) +{ + save_state(dc); + gen_helper_power_down(tcg_env); +} + +TRANS(WRPOWERDOWN, POWERDOWN, do_wr_special, a, supervisor(dc), do_wrpower= down) + +static bool trans_NOP_v7(DisasContext *dc, arg_NOP_v7 *a) +{ + /* + * TODO: Need a feature bit for sparcv8. + * In the meantime, treat all 32-bit cpus like sparcv7. + */ + if (avail_32(dc)) { + return advance_pc(dc); + } + return false; +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4233,162 +4417,7 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) break; #endif case 0x30: - { - cpu_tmp0 =3D tcg_temp_new(); - switch(rd) { - case 0: /* wry */ - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src= 2); - tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xfffffff= f); - break; -#ifndef TARGET_SPARC64 - case 0x01 ... 0x0f: /* undefined in the - SPARCv8 manual, nop - on the microSPARC - II */ - case 0x10 ... 0x1f: /* implementation-dependent - in the SPARCv8 - manual, nop on the - microSPARC II */ - if ((rd =3D=3D 0x13) && (dc->def->features= & - CPU_FEATURE_POWERDOWN= )) { - /* LEON3 power-down */ - save_state(dc); - gen_helper_power_down(tcg_env); - } - break; -#else - case 0x2: /* V9 wrccr */ - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src= 2); - gen_helper_wrccr(tcg_env, cpu_tmp0); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); - dc->cc_op =3D CC_OP_FLAGS; - break; - case 0x3: /* V9 wrasi */ - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src= 2); - tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff); - tcg_gen_st32_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, as= i)); - /* - * End TB to notice changed ASI. - * TODO: Could notice src1 =3D %g0 and IS_= IMM, - * update DisasContext and not exit the TB. - */ - save_state(dc); - gen_op_next_insn(); - tcg_gen_lookup_and_goto_ptr(); - dc->base.is_jmp =3D DISAS_NORETURN; - break; - case 0x6: /* V9 wrfprs */ - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src= 2); - tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0); - dc->fprs_dirty =3D 0; - save_state(dc); - gen_op_next_insn(); - tcg_gen_exit_tb(NULL, 0); - dc->base.is_jmp =3D DISAS_NORETURN; - break; - case 0xf: /* V9 sir, nop if user */ -#if !defined(CONFIG_USER_ONLY) - if (supervisor(dc)) { - ; // XXX - } -#endif - break; - case 0x13: /* Graphics Status */ - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2= ); - break; - case 0x14: /* Softint set */ - if (!supervisor(dc)) - goto illegal_insn; - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src= 2); - gen_helper_set_softint(tcg_env, cpu_tmp0); - break; - case 0x15: /* Softint clear */ - if (!supervisor(dc)) - goto illegal_insn; - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src= 2); - gen_helper_clear_softint(tcg_env, cpu_tmp0= ); - break; - case 0x16: /* Softint write */ - if (!supervisor(dc)) - goto illegal_insn; - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src= 2); - gen_helper_write_softint(tcg_env, cpu_tmp0= ); - break; - case 0x17: /* Tick compare */ -#if !defined(CONFIG_USER_ONLY) - if (!supervisor(dc)) - goto illegal_insn; -#endif - { - TCGv_ptr r_tickptr; - - tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1, - cpu_src2); - r_tickptr =3D tcg_temp_new_ptr(); - tcg_gen_ld_ptr(r_tickptr, tcg_env, - offsetof(CPUSPARCState,= tick)); - translator_io_start(&dc->base); - gen_helper_tick_set_limit(r_tickptr, - cpu_tick_cmp= r); - /* End TB to handle timer interrupt */ - dc->base.is_jmp =3D DISAS_EXIT; - } - break; - case 0x18: /* System tick */ -#if !defined(CONFIG_USER_ONLY) - if (!supervisor(dc)) - goto illegal_insn; -#endif - { - TCGv_ptr r_tickptr; - - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, - cpu_src2); - r_tickptr =3D tcg_temp_new_ptr(); - tcg_gen_ld_ptr(r_tickptr, tcg_env, - offsetof(CPUSPARCState,= stick)); - translator_io_start(&dc->base); - gen_helper_tick_set_count(r_tickptr, - cpu_tmp0); - /* End TB to handle timer interrupt */ - dc->base.is_jmp =3D DISAS_EXIT; - } - break; - case 0x19: /* System tick compare */ -#if !defined(CONFIG_USER_ONLY) - if (!supervisor(dc)) - goto illegal_insn; -#endif - { - TCGv_ptr r_tickptr; - - tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src= 1, - cpu_src2); - r_tickptr =3D tcg_temp_new_ptr(); - tcg_gen_ld_ptr(r_tickptr, tcg_env, - offsetof(CPUSPARCState,= stick)); - translator_io_start(&dc->base); - gen_helper_tick_set_limit(r_tickptr, - cpu_stick_cm= pr); - /* End TB to handle timer interrupt */ - dc->base.is_jmp =3D DISAS_EXIT; - } - break; - - case 0x10: /* Performance Control */ - case 0x11: /* Performance Instrumentation - Counter */ - case 0x12: /* Dispatch Control */ -#endif - default: - goto illegal_insn; - } - } - break; + goto illegal_insn; /* WRASR in decodetree */ #if !defined(CONFIG_USER_ONLY) case 0x31: /* wrpsr, V9 saved, restored */ { --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280627; cv=none; d=zohomail.com; s=zohoarc; b=CwLGmX0EcIfCuDbhT8kmD1Jhq1hE7K+g70f1YcIZW1PpnEHYPeHWs2Qs6QyhKawf/NnFdmZBaJvR3x0zKiIgD7z3OD59mgeKAyx+iueJ33awclAmvhjUZM5GwAoHd53G5GCaVzQSfISBlB4FUyQ9KHcsEwcAxsozt5DNt28ODRo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280627; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280628035100004 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/tcg/tci.c b/tcg/tci.c index 4640902c88..5e1c4a491d 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -228,6 +228,12 @@ static bool tci_compare32(uint32_t u0, uint32_t u1, TC= GCond condition) case TCG_COND_GTU: result =3D (u0 > u1); break; + case TCG_COND_TSTEQ: + result =3D (u0 & u1) =3D=3D 0; + break; + case TCG_COND_TSTNE: + result =3D (u0 & u1) !=3D 0; + break; default: g_assert_not_reached(); } @@ -270,6 +276,12 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TC= GCond condition) case TCG_COND_GTU: result =3D (u0 > u1); break; + case TCG_COND_TSTEQ: + result =3D (u0 & u1) =3D=3D 0; + break; + case TCG_COND_TSTNE: + result =3D (u0 & u1) !=3D 0; + break; default: g_assert_not_reached(); } @@ -1043,6 +1055,8 @@ static const char *str_c(TCGCond c) [TCG_COND_GEU] =3D "geu", [TCG_COND_LEU] =3D "leu", [TCG_COND_GTU] =3D "gtu", + [TCG_COND_TSTEQ] =3D "tsteq", + [TCG_COND_TSTNE] =3D "tstne", }; =20 assert((unsigned)c < ARRAY_SIZE(cond)); --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280710284100017 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 10 +++++++ target/sparc/translate.c | 62 ++++++++++++++++++--------------------- 2 files changed, 39 insertions(+), 33 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 118f0f1f17..45cf47a32f 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -85,6 +85,16 @@ RDHPR_htba 10 rd:5 101001 00101 0 0000000000000 RDHPR_hver 10 rd:5 101001 00110 0 0000000000000 RDHPR_hstick_cmpr 10 rd:5 101001 11111 0 0000000000000 =20 +{ + WRPSR 10 00000 110001 ..... . ............. @n_r_ri + SAVED 10 00000 110001 00000 0 0000000000000 +} +RESTORED 10 00001 110001 00000 0 0000000000000 +# UA2005 ALLCLEAN +# UA2005 OTHERW +# UA2005 NORMALW +# UA2005 INVALW + { RDWIM 10 rd:5 101010 00000 0 0000000000000 RDPR_tpc 10 rd:5 101010 00000 0 0000000000000 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 83716307f6..58ea3b2ba7 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -39,11 +39,14 @@ #ifdef TARGET_SPARC64 # define gen_helper_rdpsr(D, E) qemu_build_not_reached() # define gen_helper_power_down(E) qemu_build_not_reached() +# define gen_helper_wrpsr(E, S) qemu_build_not_reached() #else # define gen_helper_clear_softint(E, S) qemu_build_not_reached() # define gen_helper_flushw(E) qemu_build_not_reached() # define gen_helper_rdccr(D, E) qemu_build_not_reached() # define gen_helper_rdcwp(D, E) qemu_build_not_reached() +# define gen_helper_restored(E) qemu_build_not_reached() +# define gen_helper_saved(E) qemu_build_not_reached() # define gen_helper_set_softint(E, S) qemu_build_not_reached() # define gen_helper_tick_get_count(D, E, T, C) qemu_build_not_reached() # define gen_helper_wrccr(E, S) qemu_build_not_reached() @@ -3745,6 +3748,32 @@ static void do_wrpowerdown(DisasContext *dc, TCGv sr= c) =20 TRANS(WRPOWERDOWN, POWERDOWN, do_wr_special, a, supervisor(dc), do_wrpower= down) =20 +static void do_wrpsr(DisasContext *dc, TCGv src) +{ + gen_helper_wrpsr(tcg_env, src); + tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); + dc->cc_op =3D CC_OP_FLAGS; + dc->base.is_jmp =3D DISAS_EXIT; +} + +TRANS(WRPSR, 32, do_wr_special, a, supervisor(dc), do_wrpsr) + +static bool do_saved_restored(DisasContext *dc, bool saved) +{ + if (!supervisor(dc)) { + return raise_priv(dc); + } + if (saved) { + gen_helper_saved(tcg_env); + } else { + gen_helper_restored(tcg_env); + } + return advance_pc(dc); +} + +TRANS(SAVED, 64, do_saved_restored, true) +TRANS(RESTORED, 64, do_saved_restored, false) + static bool trans_NOP_v7(DisasContext *dc, arg_NOP_v7 *a) { /* @@ -4419,39 +4448,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) case 0x30: goto illegal_insn; /* WRASR in decodetree */ #if !defined(CONFIG_USER_ONLY) - case 0x31: /* wrpsr, V9 saved, restored */ - { - if (!supervisor(dc)) - goto priv_insn; -#ifdef TARGET_SPARC64 - switch (rd) { - case 0: - gen_helper_saved(tcg_env); - break; - case 1: - gen_helper_restored(tcg_env); - break; - case 2: /* UA2005 allclean */ - case 3: /* UA2005 otherw */ - case 4: /* UA2005 normalw */ - case 5: /* UA2005 invalw */ - // XXX - default: - goto illegal_insn; - } -#else - cpu_tmp0 =3D tcg_temp_new(); - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); - gen_helper_wrpsr(tcg_env, cpu_tmp0); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); - dc->cc_op =3D CC_OP_FLAGS; - save_state(dc); - gen_op_next_insn(); - tcg_gen_exit_tb(NULL, 0); - dc->base.is_jmp =3D DISAS_NORETURN; -#endif - } - break; case 0x32: /* wrwim, V9 wrpr */ { if (!supervisor(dc)) --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279983; cv=none; d=zohomail.com; s=zohoarc; b=FdSFO/9vOWpyXi76cH5K17e+aiQYnxzBTcc9zAcF58TJLa3bJkOJaiEh9NGKjYQySxpgrhJr+GetbT4TMXoX+gQMgwW0LZM+oMl3B7IkmEp7vHG0otb0fEER9rVW+/N0jmPQrdan2s2+3EWLwpVD7tbR42ITbcZPkByrAm+sniU= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279985131100002 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/alpha/translate.c | 39 ++++++++++++++++----------------------- 1 file changed, 16 insertions(+), 23 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 32333081d8..49e6a7b62d 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -453,13 +453,13 @@ static DisasJumpType gen_bdirect(DisasContext *ctx, i= nt ra, int32_t disp) } =20 static DisasJumpType gen_bcond_internal(DisasContext *ctx, TCGCond cond, - TCGv cmp, int32_t disp) + TCGv cmp, uint64_t imm, int32_t di= sp) { uint64_t dest =3D ctx->base.pc_next + (disp << 2); TCGLabel *lab_true =3D gen_new_label(); =20 if (use_goto_tb(ctx, dest)) { - tcg_gen_brcondi_i64(cond, cmp, 0, lab_true); + tcg_gen_brcondi_i64(cond, cmp, imm, lab_true); =20 tcg_gen_goto_tb(0); tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next); @@ -472,27 +472,20 @@ static DisasJumpType gen_bcond_internal(DisasContext = *ctx, TCGCond cond, =20 return DISAS_NORETURN; } else { - TCGv_i64 z =3D load_zero(ctx); + TCGv_i64 i =3D tcg_constant_i64(imm); TCGv_i64 d =3D tcg_constant_i64(dest); TCGv_i64 p =3D tcg_constant_i64(ctx->base.pc_next); =20 - tcg_gen_movcond_i64(cond, cpu_pc, cmp, z, d, p); + tcg_gen_movcond_i64(cond, cpu_pc, cmp, i, d, p); return DISAS_PC_UPDATED; } } =20 static DisasJumpType gen_bcond(DisasContext *ctx, TCGCond cond, int ra, - int32_t disp, int mask) + int32_t disp) { - if (mask) { - TCGv tmp =3D tcg_temp_new(); - DisasJumpType ret; - - tcg_gen_andi_i64(tmp, load_gpr(ctx, ra), 1); - ret =3D gen_bcond_internal(ctx, cond, tmp, disp); - return ret; - } - return gen_bcond_internal(ctx, cond, load_gpr(ctx, ra), disp); + return gen_bcond_internal(ctx, cond, load_gpr(ctx, ra), + is_tst_cond(cond), disp); } =20 /* Fold -0.0 for comparison with COND. */ @@ -533,7 +526,7 @@ static DisasJumpType gen_fbcond(DisasContext *ctx, TCGC= ond cond, int ra, DisasJumpType ret; =20 gen_fold_mzero(cond, cmp_tmp, load_fpr(ctx, ra)); - ret =3D gen_bcond_internal(ctx, cond, cmp_tmp, disp); + ret =3D gen_bcond_internal(ctx, cond, cmp_tmp, 0, disp); return ret; } =20 @@ -2827,35 +2820,35 @@ static DisasJumpType translate_one(DisasContext *ct= x, uint32_t insn) break; case 0x38: /* BLBC */ - ret =3D gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 1); + ret =3D gen_bcond(ctx, TCG_COND_TSTEQ, ra, disp21); break; case 0x39: /* BEQ */ - ret =3D gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 0); + ret =3D gen_bcond(ctx, TCG_COND_EQ, ra, disp21); break; case 0x3A: /* BLT */ - ret =3D gen_bcond(ctx, TCG_COND_LT, ra, disp21, 0); + ret =3D gen_bcond(ctx, TCG_COND_LT, ra, disp21); break; case 0x3B: /* BLE */ - ret =3D gen_bcond(ctx, TCG_COND_LE, ra, disp21, 0); + ret =3D gen_bcond(ctx, TCG_COND_LE, ra, disp21); break; case 0x3C: /* BLBS */ - ret =3D gen_bcond(ctx, TCG_COND_NE, ra, disp21, 1); + ret =3D gen_bcond(ctx, TCG_COND_TSTNE, ra, disp21); break; case 0x3D: /* BNE */ - ret =3D gen_bcond(ctx, TCG_COND_NE, ra, disp21, 0); + ret =3D gen_bcond(ctx, TCG_COND_NE, ra, disp21); break; case 0x3E: /* BGE */ - ret =3D gen_bcond(ctx, TCG_COND_GE, ra, disp21, 0); + ret =3D gen_bcond(ctx, TCG_COND_GE, ra, disp21); break; case 0x3F: /* BGT */ - ret =3D gen_bcond(ctx, TCG_COND_GT, ra, disp21, 0); + ret =3D gen_bcond(ctx, TCG_COND_GT, ra, disp21); break; invalid_opc: ret =3D gen_invalid(ctx); --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280704244100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/alpha/translate.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 49e6a7b62d..c7daf46de7 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -1676,16 +1676,12 @@ static DisasJumpType translate_one(DisasContext *ct= x, uint32_t insn) break; case 0x14: /* CMOVLBS */ - tmp =3D tcg_temp_new(); - tcg_gen_andi_i64(tmp, va, 1); - tcg_gen_movcond_i64(TCG_COND_NE, vc, tmp, load_zero(ctx), + tcg_gen_movcond_i64(TCG_COND_TSTNE, vc, va, tcg_constant_i64(1= ), vb, load_gpr(ctx, rc)); break; case 0x16: /* CMOVLBC */ - tmp =3D tcg_temp_new(); - tcg_gen_andi_i64(tmp, va, 1); - tcg_gen_movcond_i64(TCG_COND_EQ, vc, tmp, load_zero(ctx), + tcg_gen_movcond_i64(TCG_COND_TSTEQ, vc, va, tcg_constant_i64(1= ), vb, load_gpr(ctx, rc)); break; case 0x20: --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280730; cv=none; d=zohomail.com; s=zohoarc; b=HCNisCOk805ahiB7rzaqq9e9FPka29ig1iGz3YibSK95sl5BbSV5SBgNb4cpzUFimwJovlW2YkGr+6wkOv0lguVGyF2OpToV6HaGdgliudDdI63ZMIjQxNF41O8mFT9k44DNu11/ip4vU/Zx46ShDX3fNCJMGyXLSC6ZKJcnqew= ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279570; x=1698884370; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nbJ5KxWyhlR+ZXSgbwYcSWOLjJWJ7eGX43nHAlQDHUg=; b=GwIjqvqmgWJdogbvrpWbmYbDIKsbZmdIZx3s44okfrjaZWAcqiDtKw8T+bxlmeZmBg SiWDNeuFYrpZGM6KXiDeoL0VfCCfyCDhw0vz99nBGmJtLqnqXZgoVg2mG4OZFvAXcQYv RqgLXDko3sikEwE9M+Z9ow+Ufiy9OT7iIOynkcCpwv9vZvMilRSwhMKJw/XYVY8ruf4l +l8pBcUgdSRC6TQkLJBlpBQgiSBsaLPF3nkavaUftjdiNZHhQFitjexYTLxBscJ4UsjW 4X5rtheYT6mniHGJRAN+j+EHONZrmv97ObG0GoAy8hJXBqcxm8TmkWf74Yv3kAby81ws rDng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279570; x=1698884370; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280732467100005 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 21 +++ target/sparc/translate.c | 315 ++++++++++++++++++++++---------------- 2 files changed, 200 insertions(+), 136 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 45cf47a32f..f478999ee1 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -117,6 +117,27 @@ RDPR_gl 10 rd:5 101010 10000 0 0000000000= 000 RDPR_strand_status 10 rd:5 101010 11010 0 0000000000000 RDPR_ver 10 rd:5 101010 11111 0 0000000000000 =20 +{ + WRWIM 10 00000 110010 ..... . ............. @n_r_ri + WRPR_tpc 10 00000 110010 ..... . ............. @n_r_ri +} +WRPR_tnpc 10 00001 110010 ..... . ............. @n_r_ri +WRPR_tstate 10 00010 110010 ..... . ............. @n_r_ri +WRPR_tt 10 00011 110010 ..... . ............. @n_r_ri +WRPR_tick 10 00100 110010 ..... . ............. @n_r_ri +WRPR_tba 10 00101 110010 ..... . ............. @n_r_ri +WRPR_pstate 10 00110 110010 ..... . ............. @n_r_ri +WRPR_tl 10 00111 110010 ..... . ............. @n_r_ri +WRPR_pil 10 01000 110010 ..... . ............. @n_r_ri +WRPR_cwp 10 01001 110010 ..... . ............. @n_r_ri +WRPR_cansave 10 01010 110010 ..... . ............. @n_r_ri +WRPR_canrestore 10 01011 110010 ..... . ............. @n_r_ri +WRPR_cleanwin 10 01100 110010 ..... . ............. @n_r_ri +WRPR_otherwin 10 01101 110010 ..... . ............. @n_r_ri +WRPR_wstate 10 01110 110010 ..... . ............. @n_r_ri +WRPR_gl 10 10000 110010 ..... . ............. @n_r_ri +WRPR_strand_status 10 11010 110010 ..... . ............. @n_r_ri + { FLUSHW 10 00000 101011 00000 0 0000000000000 RDTBR 10 rd:5 101011 00000 0 0000000000000 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 58ea3b2ba7..9b82e2bf6f 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -49,8 +49,13 @@ # define gen_helper_saved(E) qemu_build_not_reached() # define gen_helper_set_softint(E, S) qemu_build_not_reached() # define gen_helper_tick_get_count(D, E, T, C) qemu_build_not_reached() +# define gen_helper_tick_set_count(P, S) qemu_build_not_reached() # define gen_helper_wrccr(E, S) qemu_build_not_reached() +# define gen_helper_wrcwp(E, S) qemu_build_not_reached() +# define gen_helper_wrgl(E, S) qemu_build_not_reached() # define gen_helper_write_softint(E, S) qemu_build_not_reached() +# define gen_helper_wrpil(E, S) qemu_build_not_reached() +# define gen_helper_wrpstate(E, S) qemu_build_not_reached() # define MAXTL_MASK 0 #endif =20 @@ -3758,6 +3763,178 @@ static void do_wrpsr(DisasContext *dc, TCGv src) =20 TRANS(WRPSR, 32, do_wr_special, a, supervisor(dc), do_wrpsr) =20 +static void do_wrwim(DisasContext *dc, TCGv src) +{ + target_ulong mask =3D MAKE_64BIT_MASK(0, dc->def->nwindows); + tcg_gen_andi_tl(cpu_wim, src, mask); +} + +TRANS(WRWIM, 32, do_wr_special, a, supervisor(dc), do_wrwim) + +static void do_wrtpc(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tsptr =3D tcg_temp_new_ptr(); + + gen_load_trap_state_at_tl(r_tsptr); + tcg_gen_st_tl(src, r_tsptr, offsetof(trap_state, tpc)); +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRPR_tpc, 64, do_wr_special, a, supervisor(dc), do_wrtpc) + +static void do_wrtnpc(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tsptr =3D tcg_temp_new_ptr(); + + gen_load_trap_state_at_tl(r_tsptr); + tcg_gen_st_tl(src, r_tsptr, offsetof(trap_state, tnpc)); +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRPR_tnpc, 64, do_wr_special, a, supervisor(dc), do_wrtnpc) + +static void do_wrtstate(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tsptr =3D tcg_temp_new_ptr(); + + gen_load_trap_state_at_tl(r_tsptr); + tcg_gen_st_tl(src, r_tsptr, offsetof(trap_state, tstate)); +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRPR_tstate, 64, do_wr_special, a, supervisor(dc), do_wrtstate) + +static void do_wrtt(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tsptr =3D tcg_temp_new_ptr(); + + gen_load_trap_state_at_tl(r_tsptr); + tcg_gen_st32_tl(src, r_tsptr, offsetof(trap_state, tt)); +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRPR_tt, 64, do_wr_special, a, supervisor(dc), do_wrtt) + +static void do_wrtick(DisasContext *dc, TCGv src) +{ + TCGv_ptr r_tickptr =3D tcg_temp_new_ptr(); + + tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(tick)); + translator_io_start(&dc->base); + gen_helper_tick_set_count(r_tickptr, src); + /* End TB to handle timer interrupt */ + dc->base.is_jmp =3D DISAS_EXIT; +} + +TRANS(WRPR_tick, 64, do_wr_special, a, supervisor(dc), do_wrtick) + +static void do_wrtba(DisasContext *dc, TCGv src) +{ + tcg_gen_mov_tl(cpu_tbr, src); +} + +TRANS(WRPR_tba, 64, do_wr_special, a, supervisor(dc), do_wrtba) + +static void do_wrpstate(DisasContext *dc, TCGv src) +{ + save_state(dc); + if (translator_io_start(&dc->base)) { + dc->base.is_jmp =3D DISAS_EXIT; + } + gen_helper_wrpstate(tcg_env, src); + dc->npc =3D DYNAMIC_PC; +} + +TRANS(WRPR_pstate, 64, do_wr_special, a, supervisor(dc), do_wrpstate) + +static void do_wrtl(DisasContext *dc, TCGv src) +{ + save_state(dc); + tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(tl)); + dc->npc =3D DYNAMIC_PC; +} + +TRANS(WRPR_tl, 64, do_wr_special, a, supervisor(dc), do_wrtl) + +static void do_wrpil(DisasContext *dc, TCGv src) +{ + if (translator_io_start(&dc->base)) { + dc->base.is_jmp =3D DISAS_EXIT; + } + gen_helper_wrpil(tcg_env, src); +} + +TRANS(WRPR_pil, 64, do_wr_special, a, supervisor(dc), do_wrpil) + +static void do_wrcwp(DisasContext *dc, TCGv src) +{ + gen_helper_wrcwp(tcg_env, src); +} + +TRANS(WRPR_cwp, 64, do_wr_special, a, supervisor(dc), do_wrcwp) + +static void do_wrcansave(DisasContext *dc, TCGv src) +{ + tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(cansave)); +} + +TRANS(WRPR_cansave, 64, do_wr_special, a, supervisor(dc), do_wrcansave) + +static void do_wrcanrestore(DisasContext *dc, TCGv src) +{ + tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(canrestore)); +} + +TRANS(WRPR_canrestore, 64, do_wr_special, a, supervisor(dc), do_wrcanresto= re) + +static void do_wrcleanwin(DisasContext *dc, TCGv src) +{ + tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(cleanwin)); +} + +TRANS(WRPR_cleanwin, 64, do_wr_special, a, supervisor(dc), do_wrcleanwin) + +static void do_wrotherwin(DisasContext *dc, TCGv src) +{ + tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(otherwin)); +} + +TRANS(WRPR_otherwin, 64, do_wr_special, a, supervisor(dc), do_wrotherwin) + +static void do_wrwstate(DisasContext *dc, TCGv src) +{ + tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(wstate)); +} + +TRANS(WRPR_wstate, 64, do_wr_special, a, supervisor(dc), do_wrwstate) + +static void do_wrgl(DisasContext *dc, TCGv src) +{ + gen_helper_wrgl(tcg_env, src); +} + +TRANS(WRPR_gl, GL, do_wr_special, a, supervisor(dc), do_wrgl) + +/* UA2005 strand status */ +static void do_wrssr(DisasContext *dc, TCGv src) +{ + tcg_gen_mov_tl(cpu_ssr, src); +} + +TRANS(WRPR_strand_status, HYPV, do_wr_special, a, hypervisor(dc), do_wrssr) + static bool do_saved_restored(DisasContext *dc, bool saved) { if (!supervisor(dc)) { @@ -4448,142 +4625,8 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 0x30: goto illegal_insn; /* WRASR in decodetree */ #if !defined(CONFIG_USER_ONLY) - case 0x32: /* wrwim, V9 wrpr */ - { - if (!supervisor(dc)) - goto priv_insn; - cpu_tmp0 =3D tcg_temp_new(); - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); -#ifdef TARGET_SPARC64 - switch (rd) { - case 0: // tpc - { - TCGv_ptr r_tsptr; - - r_tsptr =3D tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr); - tcg_gen_st_tl(cpu_tmp0, r_tsptr, - offsetof(trap_state, tpc= )); - } - break; - case 1: // tnpc - { - TCGv_ptr r_tsptr; - - r_tsptr =3D tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr); - tcg_gen_st_tl(cpu_tmp0, r_tsptr, - offsetof(trap_state, tnp= c)); - } - break; - case 2: // tstate - { - TCGv_ptr r_tsptr; - - r_tsptr =3D tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr); - tcg_gen_st_tl(cpu_tmp0, r_tsptr, - offsetof(trap_state, - tstate)); - } - break; - case 3: // tt - { - TCGv_ptr r_tsptr; - - r_tsptr =3D tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr); - tcg_gen_st32_tl(cpu_tmp0, r_tsptr, - offsetof(trap_state, t= t)); - } - break; - case 4: // tick - { - TCGv_ptr r_tickptr; - - r_tickptr =3D tcg_temp_new_ptr(); - tcg_gen_ld_ptr(r_tickptr, tcg_env, - offsetof(CPUSPARCState,= tick)); - translator_io_start(&dc->base); - gen_helper_tick_set_count(r_tickptr, - cpu_tmp0); - /* End TB to handle timer interrupt */ - dc->base.is_jmp =3D DISAS_EXIT; - } - break; - case 5: // tba - tcg_gen_mov_tl(cpu_tbr, cpu_tmp0); - break; - case 6: // pstate - save_state(dc); - if (translator_io_start(&dc->base)) { - dc->base.is_jmp =3D DISAS_EXIT; - } - gen_helper_wrpstate(tcg_env, cpu_tmp0); - dc->npc =3D DYNAMIC_PC; - break; - case 7: // tl - save_state(dc); - tcg_gen_st32_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, tl)= ); - dc->npc =3D DYNAMIC_PC; - break; - case 8: // pil - if (translator_io_start(&dc->base)) { - dc->base.is_jmp =3D DISAS_EXIT; - } - gen_helper_wrpil(tcg_env, cpu_tmp0); - break; - case 9: // cwp - gen_helper_wrcwp(tcg_env, cpu_tmp0); - break; - case 10: // cansave - tcg_gen_st32_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, - cansave)); - break; - case 11: // canrestore - tcg_gen_st32_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, - canrestore)); - break; - case 12: // cleanwin - tcg_gen_st32_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, - cleanwin)); - break; - case 13: // otherwin - tcg_gen_st32_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, - otherwin)); - break; - case 14: // wstate - tcg_gen_st32_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, - wstate)); - break; - case 16: // UA2005 gl - CHECK_IU_FEATURE(dc, GL); - gen_helper_wrgl(tcg_env, cpu_tmp0); - break; - case 26: // UA2005 strand status - CHECK_IU_FEATURE(dc, HYPV); - if (!hypervisor(dc)) - goto priv_insn; - tcg_gen_mov_tl(cpu_ssr, cpu_tmp0); - break; - default: - goto illegal_insn; - } -#else - tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0); - if (dc->def->nwindows !=3D 32) { - tcg_gen_andi_tl(cpu_wim, cpu_wim, - (1 << dc->def->nwindows) -= 1); - } -#endif - } - break; + case 0x32: + goto illegal_insn; /* WRPR in decodetree */ case 0x33: /* wrtbr, UA2005 wrhpr */ { #ifndef TARGET_SPARC64 --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279572; x=1698884372; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IRKpWuzD73nLvUgHfXSktD82HmfIC39HF668MZpjq5M=; b=a9okAxE7NNTwnJTd/84QZDiZsy4ar1bPwOIhM4LV86FVlgxNeyw2cf3Ti7fIll0+sc EoF+k/mYSl0e2bCqZBwhikq33DupW693VOH5m1Wfs5HIzGKYN+CvCDGP2qO53aLmzOc4 //BYeuDJtq6Jh1U9kdGPwLfNSttw5E/mplAgJivvanl1KFEEaHmHbvpf9YBzQbvWSO4I AjKm+SHX56CEMq7ga1qVTwQ6KHmGjpWoC0ElR0b9kVB7xNoHNhLl+UdIbopEGejOu7dH sPszECaXR05b5mJCWEeforVEG+biBN5rTcZwqs1YYHdB7DguIEDfYVXgg/bWOsGhY5e+ +ngg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279572; x=1698884372; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IRKpWuzD73nLvUgHfXSktD82HmfIC39HF668MZpjq5M=; b=L7+EHZGNu+El8/KSaYrhRA/bYqozzkxR31euGH+Mf6sywQ6dBP6C21XXKj7C4dGTys xe5NdZX/HpqN49RuFNLTJw8kQDy9u3+ifGY31L2FD0ZgByD/GUINQY2SDkWOgc09Xl6C GnI84gIJxW5HjDja9rbbVyNMZe410J7vVjtEDYv6tp8cV5pmdv3PK4EaixATQR11DsY9 QIng79wTKCEHgY1ialZBxR7VXUef8NXy4w7FA11LLhb09cCl40gwy7KAhhP4r9y42+gF nwRsnWMJw2rzTocSknd7fnVcAUzZHFOIK/oUnSqhUBNhkOvcm1EdN1Oi6Ht040glQcMr WAuw== X-Gm-Message-State: AOJu0Yx9WTvZiwaWW1BjkuFjEBggOft+4ZkXopos23DyFfDYy7x0sBie R2SbXlJMlIplhRHYS+wvOE2B2AjAFmpRnDqHFJU= X-Google-Smtp-Source: AGHT+IEby4tBSU132ovJd1L0V6L1/VsQA0yRhQFGl+zzItpKOUv8MZ5sbTX+6r3z1Xaos+RNpPAOMw== X-Received: by 2002:a17:903:2291:b0:1c0:a5c9:e072 with SMTP id b17-20020a170903229100b001c0a5c9e072mr16183057plh.11.1698279572469; Wed, 25 Oct 2023 17:19:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 29/94] target/sparc: Move WRTBR, WRHPR to decodetree Date: Wed, 25 Oct 2023 17:14:37 -0700 Message-Id: <20231026001542.1141412-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279886854100006 Content-Type: text/plain; charset="utf-8" Implement htstate in the obvious way. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 9 ++++ target/sparc/translate.c | 111 +++++++++++++++++++------------------- 2 files changed, 66 insertions(+), 54 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index f478999ee1..eab737fdcc 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -143,6 +143,15 @@ WRPR_strand_status 10 11010 110010 ..... . ..........= ... @n_r_ri RDTBR 10 rd:5 101011 00000 0 0000000000000 } =20 +{ + WRTBR 10 00000 110011 ..... . ............. @n_r_ri + WRHPR_hpstate 10 00000 110011 ..... . ............. @n_r_ri +} +WRHPR_htstate 10 00001 110011 ..... . ............. @n_r_ri +WRHPR_hintp 10 00011 110011 ..... . ............. @n_r_ri +WRHPR_htba 10 00101 110011 ..... . ............. @n_r_ri +WRHPR_hstick_cmpr 10 11111 110011 ..... . ............. @n_r_ri + Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 { # For v7, the entire simm13 field is present, but masked to 7 bits. diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 9b82e2bf6f..d87c08c18c 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -50,6 +50,7 @@ # define gen_helper_set_softint(E, S) qemu_build_not_reached() # define gen_helper_tick_get_count(D, E, T, C) qemu_build_not_reached() # define gen_helper_tick_set_count(P, S) qemu_build_not_reached() +# define gen_helper_tick_set_limit(P, S) qemu_build_not_reached() # define gen_helper_wrccr(E, S) qemu_build_not_reached() # define gen_helper_wrcwp(E, S) qemu_build_not_reached() # define gen_helper_wrgl(E, S) qemu_build_not_reached() @@ -3935,6 +3936,61 @@ static void do_wrssr(DisasContext *dc, TCGv src) =20 TRANS(WRPR_strand_status, HYPV, do_wr_special, a, hypervisor(dc), do_wrssr) =20 +TRANS(WRTBR, 32, do_wr_special, a, supervisor(dc), do_wrtba) + +static void do_wrhpstate(DisasContext *dc, TCGv src) +{ + tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(hpstate)); + dc->base.is_jmp =3D DISAS_EXIT; +} + +TRANS(WRHPR_hpstate, HYPV, do_wr_special, a, hypervisor(dc), do_wrhpstate) + +static void do_wrhtstate(DisasContext *dc, TCGv src) +{ + TCGv_i32 tl =3D tcg_temp_new_i32(); + TCGv_ptr tp =3D tcg_temp_new_ptr(); + + tcg_gen_ld_i32(tl, tcg_env, env64_field_offsetof(tl)); + tcg_gen_andi_i32(tl, tl, MAXTL_MASK); + tcg_gen_shli_i32(tl, tl, 3); + tcg_gen_ext_i32_ptr(tp, tl); + tcg_gen_add_ptr(tp, tp, tcg_env); + + tcg_gen_st_tl(src, tp, env64_field_offsetof(htstate)); +} + +TRANS(WRHPR_htstate, HYPV, do_wr_special, a, hypervisor(dc), do_wrhtstate) + +static void do_wrhintp(DisasContext *dc, TCGv src) +{ + tcg_gen_mov_tl(cpu_hintp, src); +} + +TRANS(WRHPR_hintp, HYPV, do_wr_special, a, hypervisor(dc), do_wrhintp) + +static void do_wrhtba(DisasContext *dc, TCGv src) +{ + tcg_gen_mov_tl(cpu_htba, src); +} + +TRANS(WRHPR_htba, HYPV, do_wr_special, a, hypervisor(dc), do_wrhtba) + +static void do_wrhstick_cmpr(DisasContext *dc, TCGv src) +{ + TCGv_ptr r_tickptr =3D tcg_temp_new_ptr(); + + tcg_gen_mov_tl(cpu_hstick_cmpr, src); + tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(hstick)); + translator_io_start(&dc->base); + gen_helper_tick_set_limit(r_tickptr, cpu_hstick_cmpr); + /* End TB to handle timer interrupt */ + dc->base.is_jmp =3D DISAS_EXIT; +} + +TRANS(WRHPR_hstick_cmpr, HYPV, do_wr_special, a, hypervisor(dc), + do_wrhstick_cmpr) + static bool do_saved_restored(DisasContext *dc, bool saved) { if (!supervisor(dc)) { @@ -4624,63 +4680,10 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) #endif case 0x30: goto illegal_insn; /* WRASR in decodetree */ -#if !defined(CONFIG_USER_ONLY) case 0x32: goto illegal_insn; /* WRPR in decodetree */ case 0x33: /* wrtbr, UA2005 wrhpr */ - { -#ifndef TARGET_SPARC64 - if (!supervisor(dc)) - goto priv_insn; - tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2); -#else - CHECK_IU_FEATURE(dc, HYPV); - if (!hypervisor(dc)) - goto priv_insn; - cpu_tmp0 =3D tcg_temp_new(); - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); - switch (rd) { - case 0: // hpstate - tcg_gen_st_i64(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, - hpstate)); - save_state(dc); - gen_op_next_insn(); - tcg_gen_exit_tb(NULL, 0); - dc->base.is_jmp =3D DISAS_NORETURN; - break; - case 1: // htstate - // XXX gen_op_wrhtstate(); - break; - case 3: // hintp - tcg_gen_mov_tl(cpu_hintp, cpu_tmp0); - break; - case 5: // htba - tcg_gen_mov_tl(cpu_htba, cpu_tmp0); - break; - case 31: // hstick_cmpr - { - TCGv_ptr r_tickptr; - - tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tm= p0); - r_tickptr =3D tcg_temp_new_ptr(); - tcg_gen_ld_ptr(r_tickptr, tcg_env, - offsetof(CPUSPARCState,= hstick)); - translator_io_start(&dc->base); - gen_helper_tick_set_limit(r_tickptr, - cpu_hstick_c= mpr); - /* End TB to handle timer interrupt */ - dc->base.is_jmp =3D DISAS_EXIT; - } - break; - case 6: // hver readonly - default: - goto illegal_insn; - } -#endif - } - break; -#endif + goto illegal_insn; /* WRTBR, WRHPR in decodetree = */ #ifdef TARGET_SPARC64 case 0x2c: /* V9 movcc */ { --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279571; x=1698884371; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=jVGlwsfbm4sLINQJ1C25FK0LHbR26UwjjqtCg2xAyg8=; b=FeJMXiYGlpWU+R4zX53zg7iprgSjuBBAFS2uUI1P3LyrWoauPOkKSrgBHCvad3MUt4 sBFqjzRKA0tVeUtj03z2HFky4k/cfibXmLhVcu2s4eFr9UFz6H0Qkl/Rv8zbo2cHWYF1 FzxhPpoAwSlWmulFv5YpcRXNK2w2v0I5liK2hhZle1LBkrP8nTBm/FiFW23o3hM6o8mP Mgae4Valtq4JM6SxIeupEIw8raWsbEwQ4/ZXGz00kltWXyfbMwlkmChBh7uilo4eNLsu CS/kz6qQwqTjBrdHvmNCTl3i654XuwUjNnaYq3zYKOsLotKNFw009a3RCN6aLyobbTnR 7/4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279571; x=1698884371; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jVGlwsfbm4sLINQJ1C25FK0LHbR26UwjjqtCg2xAyg8=; b=XO8Jw/JnvlIjQwitRoDjNG3RY6Yw4IR0MyGRjcSOm7ANPdIPZK2aXmq6euh6l4YkOe vKcN0IJdsn44XeIGjG1izpZuYqRwXZCLQdtRnOZYVJMxrhokBxlE9ypzEvsudKQ8rT8B Rf51XE77iJENOgzQsEK0easc6fFbDRfZwV6Q2lH2P2k2DpwYCQGAmo7MqFLfA2/0t5tg TXXKW1zn3HPxvk8E3Kn/XY33Y6jiG1VnrTU7ouHcTsOGpATJRCm62geSTZBUQbamPmdk Y4NkhmuCJoR26NkkckN0nqvGNE7jBNLTVAY4UbBRxShXXe6z4iRadXlqzYXgbz9z/+Pb JOtQ== X-Gm-Message-State: AOJu0YyPXuHkcx8ruKseCJ+S0h1HZbZuDVDQBu6f9FlRMlavTZYJmY67 10HJpHpD+unvlcyeC0hM1sF6I1v6Vun0U66ZWwU= X-Google-Smtp-Source: AGHT+IEoe4rqU7bXUwPqYyYLqfs7FC5egsca0B+Yx7z+rfU2XtPuaErBwvkcUbkDs2f1JftVsc2O6g== X-Received: by 2002:a17:902:d2c1:b0:1c7:495c:87df with SMTP id n1-20020a170902d2c100b001c7495c87dfmr17741585plc.53.1698279571171; Wed, 25 Oct 2023 17:19:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 29/29] target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero Date: Wed, 25 Oct 2023 17:14:36 -0700 Message-Id: <20231026001542.1141412-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279744226100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/alpha/translate.c | 49 +++++++++++++++++++--------------------- 1 file changed, 23 insertions(+), 26 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index c7daf46de7..c68c2bcd21 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -490,56 +490,53 @@ static DisasJumpType gen_bcond(DisasContext *ctx, TCG= Cond cond, int ra, =20 /* Fold -0.0 for comparison with COND. */ =20 -static void gen_fold_mzero(TCGCond cond, TCGv dest, TCGv src) +static TCGv_i64 gen_fold_mzero(TCGCond *pcond, uint64_t *pimm, TCGv_i64 sr= c) { - uint64_t mzero =3D 1ull << 63; + TCGv_i64 tmp; =20 - switch (cond) { + *pimm =3D 0; + switch (*pcond) { case TCG_COND_LE: case TCG_COND_GT: /* For <=3D or >, the -0.0 value directly compares the way we want= . */ - tcg_gen_mov_i64(dest, src); - break; + return src; =20 case TCG_COND_EQ: case TCG_COND_NE: - /* For =3D=3D or !=3D, we can simply mask off the sign bit and com= pare. */ - tcg_gen_andi_i64(dest, src, mzero - 1); - break; + /* For =3D=3D or !=3D, we can compare without the sign bit. */ + *pcond =3D *pcond =3D=3D TCG_COND_EQ ? TCG_COND_TSTEQ : TCG_COND_T= STNE; + *pimm =3D INT64_MAX; + return src; =20 case TCG_COND_GE: case TCG_COND_LT: /* For >=3D or <, map -0.0 to +0.0. */ - tcg_gen_movcond_i64(TCG_COND_NE, dest, src, tcg_constant_i64(mzero= ), - src, tcg_constant_i64(0)); - break; + tmp =3D tcg_temp_new_i64(); + tcg_gen_movcond_i64(TCG_COND_EQ, tmp, + src, tcg_constant_i64(INT64_MIN), + tcg_constant_i64(0), src); + return tmp; =20 default: - abort(); + g_assert_not_reached(); } } =20 static DisasJumpType gen_fbcond(DisasContext *ctx, TCGCond cond, int ra, int32_t disp) { - TCGv cmp_tmp =3D tcg_temp_new(); - DisasJumpType ret; - - gen_fold_mzero(cond, cmp_tmp, load_fpr(ctx, ra)); - ret =3D gen_bcond_internal(ctx, cond, cmp_tmp, 0, disp); - return ret; + uint64_t imm; + TCGv_i64 tmp =3D gen_fold_mzero(&cond, &imm, load_fpr(ctx, ra)); + return gen_bcond_internal(ctx, cond, tmp, imm, disp); } =20 static void gen_fcmov(DisasContext *ctx, TCGCond cond, int ra, int rb, int= rc) { - TCGv_i64 va, vb, z; - - z =3D load_zero(ctx); - vb =3D load_fpr(ctx, rb); - va =3D tcg_temp_new(); - gen_fold_mzero(cond, va, load_fpr(ctx, ra)); - - tcg_gen_movcond_i64(cond, dest_fpr(ctx, rc), va, z, vb, load_fpr(ctx, = rc)); + uint64_t imm; + TCGv_i64 tmp =3D gen_fold_mzero(&cond, &imm, load_fpr(ctx, ra)); + tcg_gen_movcond_i64(cond, dest_fpr(ctx, rc), + tmp, tcg_constant_i64(imm), + load_fpr(ctx, rb), load_fpr(ctx, rc)); } =20 #define QUAL_RM_N 0x080 /* Round mode nearest even */ --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280662; cv=none; d=zohomail.com; s=zohoarc; b=LqndKBHq9pJZd1Ndh0+YMOtx9hi0vuXWUauauWQ9rn8Y4wcRvq626m7nvPDNnxmXNa+nTFxK7hOz8O5ZRxFpwvYStYGk5lqjV2nf6PNLtk9ZdsrE2WkHe0O/bRewggKjhK3w1eb5sCkmNuZFSSsVLtSnJM9Ga+DpH0lbpOQPNH4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280662; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=qScZs44s00L/oLLs4eIUKTqGk+BatBxWrSAikGLStjw=; b=RgdbS6GYx9OSgyDz5KT3br1KHk97klxi0hchZ37lTSp/Sw8z+Cv6t1Dj5O/NtEKPQ5QOJnjuC14f01q+1vWGAzd76mNGi51ttef2Rg2a+4jY/g8s/lgh9ijIAiucN1WKHHDQLZr5kczUw2TqqVZMqh6SIKYvAyPZXOmpSNuAhyc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698280662499717.2374737121306; Wed, 25 Oct 2023 17:37:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo6f-00026j-KN; Wed, 25 Oct 2023 20:20:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo6F-000162-1O for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:47 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo63-0006de-Ox for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:46 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1cace3e142eso2220845ad.3 for ; Wed, 25 Oct 2023 17:19:35 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279573; x=1698884373; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=qScZs44s00L/oLLs4eIUKTqGk+BatBxWrSAikGLStjw=; b=CQpL95TqoRalMAy5AGV6wpYOJ3YSszC6uCoHCtRERtLvtRBe+EeJ9V8Qsi0b6YDXmT fGXHKykq+lmuTQ3t81xw2Nc0WwIg2mXgJOGlL4x2MqyNKxV+jGs6bOjNH6q9cdjRzC7/ yEHG5ta329YlDutrRFaP/ZLLrW1i2nm7ltcxdyolOme3St4DBH6058b9TTwzRXGbKvhM uc1d9btqOCx0sSl4zI/HeNoCdUjdr14Vt2F1d/UGAdaxoPppBBu0zHYsYK8ADXvORGR+ Q4+k50G9HWK+cFsN9gutmFR/nZo9dEn+E96GZPQ9pAAtAFLgCmk3Sv48X7dzu7zXf7Jt iNsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279573; x=1698884373; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qScZs44s00L/oLLs4eIUKTqGk+BatBxWrSAikGLStjw=; b=R8zLF/4CQCz8zEPNrZq+i72bdGDBwszyTI2h+gaMW8I9KjJcscxBoN9eOC6FTfTz2D IXpOpOtgmwD4KBO81S3TN9PZY4UNGWylXJoEGzTo5WZOmtgvlf8ojOuFpZsJFmRVzFMv K75381CvbSD5+1lBi1ld76L0Fdv0XhvMUW9DUtQnBIOLKplRJGcLbFFo07NUp9lLZihq CM7R9+fjnkfB1sz7GpRAXNDp35kVkybU9ZO4FKyUhM1w+6355cig8u34jB09+2gWBL8H 5LUTeXShj0PDHwNOhekirNW98F31bMTgaf3bc232x9z4sn+qEzXn0Qi8+7EsIoipXoWy ommA== X-Gm-Message-State: AOJu0YzQKEpKa71w/KsYIV6MIHM9yBFDCG01DWi308rT1QB0wGQupLTn bnT3n2y5tpHzWCyZXFp8e5U+FEXO1l37hJls6wk= X-Google-Smtp-Source: AGHT+IFeW+aZPPjOdiigJiz/QENE9ZspgfkxUQw3aiIX1Q6qNBFHnVgRYZQnPcNfHoA6EoTVv5TwGg== X-Received: by 2002:a17:902:e402:b0:1c9:ca02:645c with SMTP id m2-20020a170902e40200b001c9ca02645cmr11144143ple.36.1698279573133; Wed, 25 Oct 2023 17:19:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 30/94] target/sparc: Remove cpu_wim Date: Wed, 25 Oct 2023 17:14:38 -0700 Message-Id: <20231026001542.1141412-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280664123100011 Content-Type: text/plain; charset="utf-8" Use direct loads and stores to env instead. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d87c08c18c..096cbb869f 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -84,9 +84,7 @@ static TCGv_i32 cpu_xcc, cpu_fprs; static TCGv cpu_gsr; static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr; static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver; -# define cpu_wim ({ qemu_build_not_reached(); (TCGv)NULL; }) #else -static TCGv cpu_wim; # define cpu_fprs ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_gsr ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_hintp ({ qemu_build_not_reached(); (TCGv)NULL; }) @@ -103,8 +101,10 @@ static TCGv_i64 cpu_fpr[TARGET_DPREGS]; =20 #define env_field_offsetof(X) offsetof(CPUSPARCState, X) #ifdef TARGET_SPARC64 +# define env32_field_offsetof(X) ({ qemu_build_not_reached(); 0; }) # define env64_field_offsetof(X) env_field_offsetof(X) #else +# define env32_field_offsetof(X) env_field_offsetof(X) # define env64_field_offsetof(X) ({ qemu_build_not_reached(); 0; }) #endif =20 @@ -3414,7 +3414,8 @@ TRANS(RDHPR_hstick_cmpr, HYPV, do_rd_special, hypervi= sor(dc), a->rd, =20 static TCGv do_rdwim(DisasContext *dc, TCGv dst) { - return cpu_wim; + tcg_gen_ld_tl(dst, tcg_env, env32_field_offsetof(wim)); + return dst; } =20 TRANS(RDWIM, 32, do_rd_special, supervisor(dc), a->rd, do_rdwim) @@ -3767,7 +3768,10 @@ TRANS(WRPSR, 32, do_wr_special, a, supervisor(dc), d= o_wrpsr) static void do_wrwim(DisasContext *dc, TCGv src) { target_ulong mask =3D MAKE_64BIT_MASK(0, dc->def->nwindows); - tcg_gen_andi_tl(cpu_wim, src, mask); + TCGv tmp =3D tcg_temp_new(); + + tcg_gen_andi_tl(tmp, src, mask); + tcg_gen_st_tl(tmp, tcg_env, env32_field_offsetof(wim)); } =20 TRANS(WRWIM, 32, do_wr_special, a, supervisor(dc), do_wrwim) @@ -5939,8 +5943,6 @@ void sparc_tcg_init(void) #ifdef TARGET_SPARC64 { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" }, { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" }, -#else - { &cpu_wim, offsetof(CPUSPARCState, wim), "wim" }, #endif { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" }, { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" }, --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280529; cv=none; d=zohomail.com; s=zohoarc; b=lpOabh4e7wH3erYOBZSnVzk3klSnWOTH1nDJveGsTvh6HmEfcM6NoQyNhEyrKhIvRf72t3tgExopfZ2JexDFNLJbvYYmoeMfZI9B2TJL23TwYOipMg0TyTxJqbwLe9jX1LLfbzAy1Hllw/0HAgMJB958dX0mqKsFF2ZqEWlbNqc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280529; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=70Ansy+qoBySZPBjDOmIfy2SuZzlDjYJIwvEAx7FQ7k=; b=CjIMRyQGJiq2DhbHMEQtqDUc7rGXILK03jHx5oOIBNa8w3q3vYYUh0vak6dxl1sXuX4QJBedJfU+WJrNLuLNimtGH2iDjsIc/Q3lN4dNJhmbNbots+/yQ8sUYw5EpfojZey5kDjAmjy8A7tASdbonpWwjrtAh6VdFg7jUjyBFgA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698280529826800.712587803069; Wed, 25 Oct 2023 17:35:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo6M-0001Tp-V7; Wed, 25 Oct 2023 20:19:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo6E-00015U-U9 for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:46 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo63-0006dk-Ou for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:46 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-6b36e1fcee9so287053b3a.3 for ; Wed, 25 Oct 2023 17:19:34 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279574; x=1698884374; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=70Ansy+qoBySZPBjDOmIfy2SuZzlDjYJIwvEAx7FQ7k=; b=UxdnknKc2UdpsNtVa/eZj4gSW5imARaL6UR9CkddUZq15cpAoqwqEtnbZfTT4PKf7A kQxIJ2g88OU046/tw2M/NYH+yfatxOQpme5BuwNyJhGZegSFyDAV79aup6wRsCXNAbt/ Wq7YxvaiC4dG0TCmJB9gFW6orNS4u2s+x7h61+FzYKv/kQuieaUtaHlomx/KLENpga73 Hg7eQNgdqNHIfNkKWbK74zeNtv5BFtD5YZNpvZXuVjwoMF6cHO7XolDkQUKk9H9Lu4Du 0PKJvB9xUqZmbk6bYF5IdnR89BMYtD8sBTktVFe+KYOZNTTHWOkPPn6nscgwUOX62rMH N7Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279574; x=1698884374; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=70Ansy+qoBySZPBjDOmIfy2SuZzlDjYJIwvEAx7FQ7k=; b=R4GzoD79Jq8BwVLiGUKEijYMApDMBt+bCVZc2cEgl0jKjfB62mYElzQCdELVsRygAJ NrKjpjCRqd+vz5rxHT20IsTrPaOHNFfvbhbo6ssa/iUYtRwugdseevbpCFbuVAzkDcZu ZcMIuxoaGQd8nm3o2bpssBBjuK07a/KbX9/2tGNwaszSn2VvJNn4cGIwf4DUb/nbERQU 0yYlVEhWgKawqVbeOdAwrhbIZeUXTJEQUX1fzxsQM9LMFldDYYA9o7qVzLRN3OVQ7T1I +BlW6sUapfZ2EvqJ64E0LHtxSqMa0n+DXD0rt78Yp0Bd68E8BtZnhfX2nePqi+W39jzj rk0A== X-Gm-Message-State: AOJu0YzfvSAdTqp8HSPJp/QzWWUqcdY0c2UkiGwaYEWHiX/57QdceFtR RfB6+BttpPkzQ2W3InB65veB6B6cs1H3oTPCkYU= X-Google-Smtp-Source: AGHT+IGw/vl4AnYVG4huI6OuxKvwYpTDjAu9reWI6xUxr1PtBZkoNb5USAKXb5Q7JprHxAtAndPU9w== X-Received: by 2002:a05:6a21:4984:b0:179:fbe5:f535 with SMTP id ax4-20020a056a21498400b00179fbe5f535mr6310504pzc.58.1698279573841; Wed, 25 Oct 2023 17:19:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 31/94] target/sparc: Remove cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr Date: Wed, 25 Oct 2023 17:14:39 -0700 Message-Id: <20231026001542.1141412-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280531764100003 Content-Type: text/plain; charset="utf-8" Use direct loads and stores to env instead. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 41 ++++++++++++++-------------------------- 1 file changed, 14 insertions(+), 27 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 096cbb869f..65b71dd931 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -82,18 +82,14 @@ static TCGv cpu_cond; #ifdef TARGET_SPARC64 static TCGv_i32 cpu_xcc, cpu_fprs; static TCGv cpu_gsr; -static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr; static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver; #else # define cpu_fprs ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_gsr ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_hintp ({ qemu_build_not_reached(); (TCGv)NULL; }) -# define cpu_hstick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_htba ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_hver ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_ssr ({ qemu_build_not_reached(); (TCGv)NULL; }) -# define cpu_stick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; }) -# define cpu_tick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_ver ({ qemu_build_not_reached(); (TCGv)NULL; }) #endif /* Floating point registers */ @@ -3307,7 +3303,8 @@ TRANS(RDSOFTINT, 64, do_rd_special, supervisor(dc), a= ->rd, do_rdsoftint) =20 static TCGv do_rdtick_cmpr(DisasContext *dc, TCGv dst) { - return cpu_tick_cmpr; + tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(tick_cmpr)); + return dst; } =20 /* TODO: non-priv access only allowed when enabled. */ @@ -3331,7 +3328,8 @@ TRANS(RDSTICK, 64, do_rd_special, true, a->rd, do_rds= tick) =20 static TCGv do_rdstick_cmpr(DisasContext *dc, TCGv dst) { - return cpu_stick_cmpr; + tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(stick_cmpr)); + return dst; } =20 /* TODO: supervisor access only allowed when enabled by hypervisor. */ @@ -3406,7 +3404,8 @@ TRANS(RDHPR_hver, HYPV, do_rd_special, hypervisor(dc)= , a->rd, do_rdhver) =20 static TCGv do_rdhstick_cmpr(DisasContext *dc, TCGv dst) { - return cpu_hstick_cmpr; + tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(hstick_cmpr)); + return dst; } =20 TRANS(RDHPR_hstick_cmpr, HYPV, do_rd_special, hypervisor(dc), a->rd, @@ -3696,18 +3695,14 @@ TRANS(WRSOFTINT, 64, do_wr_special, a, supervisor(d= c), do_wrsoftint) =20 static void do_wrtick_cmpr(DisasContext *dc, TCGv src) { -#ifdef TARGET_SPARC64 TCGv_ptr r_tickptr =3D tcg_temp_new_ptr(); =20 - tcg_gen_mov_tl(cpu_tick_cmpr, src); - tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, tick)); + tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(tick_cmpr)); + tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(tick)); translator_io_start(&dc->base); - gen_helper_tick_set_limit(r_tickptr, cpu_tick_cmpr); + gen_helper_tick_set_limit(r_tickptr, src); /* End TB to handle timer interrupt */ dc->base.is_jmp =3D DISAS_EXIT; -#else - qemu_build_not_reached(); -#endif } =20 TRANS(WRTICK_CMPR, 64, do_wr_special, a, supervisor(dc), do_wrtick_cmpr) @@ -3731,18 +3726,14 @@ TRANS(WRSTICK, 64, do_wr_special, a, supervisor(dc)= , do_wrstick) =20 static void do_wrstick_cmpr(DisasContext *dc, TCGv src) { -#ifdef TARGET_SPARC64 TCGv_ptr r_tickptr =3D tcg_temp_new_ptr(); =20 - tcg_gen_mov_tl(cpu_stick_cmpr, src); - tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, stick)); + tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(stick_cmpr)); + tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(stick)); translator_io_start(&dc->base); - gen_helper_tick_set_limit(r_tickptr, cpu_stick_cmpr); + gen_helper_tick_set_limit(r_tickptr, src); /* End TB to handle timer interrupt */ dc->base.is_jmp =3D DISAS_EXIT; -#else - qemu_build_not_reached(); -#endif } =20 TRANS(WRSTICK_CMPR, 64, do_wr_special, a, supervisor(dc), do_wrstick_cmpr) @@ -3984,10 +3975,10 @@ static void do_wrhstick_cmpr(DisasContext *dc, TCGv= src) { TCGv_ptr r_tickptr =3D tcg_temp_new_ptr(); =20 - tcg_gen_mov_tl(cpu_hstick_cmpr, src); + tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(hstick_cmpr)); tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(hstick)); translator_io_start(&dc->base); - gen_helper_tick_set_limit(r_tickptr, cpu_hstick_cmpr); + gen_helper_tick_set_limit(r_tickptr, src); /* End TB to handle timer interrupt */ dc->base.is_jmp =3D DISAS_EXIT; } @@ -5951,10 +5942,6 @@ void sparc_tcg_init(void) static const struct { TCGv *ptr; int off; const char *name; } rtl[] = =3D { #ifdef TARGET_SPARC64 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" }, - { &cpu_tick_cmpr, offsetof(CPUSPARCState, tick_cmpr), "tick_cmpr" = }, - { &cpu_stick_cmpr, offsetof(CPUSPARCState, stick_cmpr), "stick_cmp= r" }, - { &cpu_hstick_cmpr, offsetof(CPUSPARCState, hstick_cmpr), - "hstick_cmpr" }, { &cpu_hintp, offsetof(CPUSPARCState, hintp), "hintp" }, { &cpu_htba, offsetof(CPUSPARCState, htba), "htba" }, { &cpu_hver, offsetof(CPUSPARCState, hver), "hver" }, --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279574; x=1698884374; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=WZI9/ICpEQ1X/D+ks7TjhuKKwZOzznFfbKaTh1LluXE=; b=FVpbBpIIeEjPGHqcohu0CzvZ7pohimPQ5hsuZD4zqukdaqn1QCzeYFcBSfkM+8c361 ce94p7D8ED9fRLFd0GChdyKI8TN8cxF78FatHJVJa98JyTc6kNIBFO2Arn3fLo8mjcPo WAAxzdaN/CZleILv/GgSZnFhFrLyq9DXsB1RfC4aZIZkriJWzboshr5SX3P7RjbO7BgU j4JHVCajvqabxV8j2N+k5ZPZFM3zAjGwpQwoSYmdNWNfOxhhs6dNRPkd8Pa1rZs24VCf ywT/1S2q3CmR1BmNjQerXZypCmP4lfWBiRc0OYJqH+wEm+0JibSapiAPMjMXNR3oGH4S QY1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279574; x=1698884374; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WZI9/ICpEQ1X/D+ks7TjhuKKwZOzznFfbKaTh1LluXE=; b=VPZ7gfL8shkkv9NNaVlY9kXm4IQgJpemvOxYxDvs7fmcJ23kyca6x2PU0LU1c9u5U5 dGOSSwKcyLgelWApzwDJHgIPW3b7slr3WX9Pq+sLMLN0P+8MbQYSXO56ZvB6wGrrEohZ gqMZqNHVSbjhBMT9MVCsD6a8EaV6ohc/9ZPhcaIY3gzKU9IL0yOrCQ9AU82f97lCKkZG +yWufXV1fvZKLeAVSMtKuQdIMkvKfxljNKiTbkLFCWxFYOwLoQAH6mf2PiUsvcgm1cvL nDZviCo5PnpVrsR6UVyHW8vLgAq/r9+Ep94eYOMTO6mDArDAXb3bFTjoVh/yJOCgLwgU bypA== X-Gm-Message-State: AOJu0YyRGNZ8bQvhq894aiDnNW8D+iyYVpP1hQP8UXcKbW0sn0hzv+lj UMR00u9jefWF2JxfmwZHOFx0GujATl6Cl6HIdVM= X-Google-Smtp-Source: AGHT+IEVuD59T7krfTxF0o6GAoI7XSTNSb9iqO2qN/nKDvlmJuJOXYqZkZEkopSbVTR/EBgffs/wVw== X-Received: by 2002:a17:902:b48d:b0:1c5:de4c:f079 with SMTP id y13-20020a170902b48d00b001c5de4cf079mr13419776plr.33.1698279574561; Wed, 25 Oct 2023 17:19:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 32/94] target/sparc: Remove cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver Date: Wed, 25 Oct 2023 17:14:40 -0700 Message-Id: <20231026001542.1141412-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280043296100001 Content-Type: text/plain; charset="utf-8" Use direct loads and stores to env instead. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 65b71dd931..7b83803b6b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -82,15 +82,9 @@ static TCGv cpu_cond; #ifdef TARGET_SPARC64 static TCGv_i32 cpu_xcc, cpu_fprs; static TCGv cpu_gsr; -static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver; #else # define cpu_fprs ({ qemu_build_not_reached(); (TCGv)NULL; }) # define cpu_gsr ({ qemu_build_not_reached(); (TCGv)NULL; }) -# define cpu_hintp ({ qemu_build_not_reached(); (TCGv)NULL; }) -# define cpu_htba ({ qemu_build_not_reached(); (TCGv)NULL; }) -# define cpu_hver ({ qemu_build_not_reached(); (TCGv)NULL; }) -# define cpu_ssr ({ qemu_build_not_reached(); (TCGv)NULL; }) -# define cpu_ver ({ qemu_build_not_reached(); (TCGv)NULL; }) #endif /* Floating point registers */ static TCGv_i64 cpu_fpr[TARGET_DPREGS]; @@ -3383,21 +3377,24 @@ TRANS(RDHPR_htstate, HYPV, do_rd_special, hyperviso= r(dc), a->rd, do_rdhtstate) =20 static TCGv do_rdhintp(DisasContext *dc, TCGv dst) { - return cpu_hintp; + tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(hintp)); + return dst; } =20 TRANS(RDHPR_hintp, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhintp) =20 static TCGv do_rdhtba(DisasContext *dc, TCGv dst) { - return cpu_htba; + tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(htba)); + return dst; } =20 TRANS(RDHPR_htba, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhtba) =20 static TCGv do_rdhver(DisasContext *dc, TCGv dst) { - return cpu_hver; + tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(hver)); + return dst; } =20 TRANS(RDHPR_hver, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhver) @@ -3572,14 +3569,16 @@ TRANS(RDPR_gl, GL, do_rd_special, supervisor(dc), a= ->rd, do_rdgl) /* UA2005 strand status */ static TCGv do_rdssr(DisasContext *dc, TCGv dst) { - return cpu_ssr; + tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(ssr)); + return dst; } =20 TRANS(RDPR_strand_status, HYPV, do_rd_special, hypervisor(dc), a->rd, do_r= dssr) =20 static TCGv do_rdver(DisasContext *dc, TCGv dst) { - return cpu_ver; + tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(version)); + return dst; } =20 TRANS(RDPR_ver, 64, do_rd_special, supervisor(dc), a->rd, do_rdver) @@ -3926,7 +3925,7 @@ TRANS(WRPR_gl, GL, do_wr_special, a, supervisor(dc), = do_wrgl) /* UA2005 strand status */ static void do_wrssr(DisasContext *dc, TCGv src) { - tcg_gen_mov_tl(cpu_ssr, src); + tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(ssr)); } =20 TRANS(WRPR_strand_status, HYPV, do_wr_special, a, hypervisor(dc), do_wrssr) @@ -3959,14 +3958,14 @@ TRANS(WRHPR_htstate, HYPV, do_wr_special, a, hyperv= isor(dc), do_wrhtstate) =20 static void do_wrhintp(DisasContext *dc, TCGv src) { - tcg_gen_mov_tl(cpu_hintp, src); + tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(hintp)); } =20 TRANS(WRHPR_hintp, HYPV, do_wr_special, a, hypervisor(dc), do_wrhintp) =20 static void do_wrhtba(DisasContext *dc, TCGv src) { - tcg_gen_mov_tl(cpu_htba, src); + tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(htba)); } =20 TRANS(WRHPR_htba, HYPV, do_wr_special, a, hypervisor(dc), do_wrhtba) @@ -5942,11 +5941,6 @@ void sparc_tcg_init(void) static const struct { TCGv *ptr; int off; const char *name; } rtl[] = =3D { #ifdef TARGET_SPARC64 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" }, - { &cpu_hintp, offsetof(CPUSPARCState, hintp), "hintp" }, - { &cpu_htba, offsetof(CPUSPARCState, htba), "htba" }, - { &cpu_hver, offsetof(CPUSPARCState, hver), "hver" }, - { &cpu_ssr, offsetof(CPUSPARCState, ssr), "ssr" }, - { &cpu_ver, offsetof(CPUSPARCState, version), "ver" }, #endif { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" }, { &cpu_cc_src, offsetof(CPUSPARCState, cc_src), "cc_src" }, --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279575; x=1698884375; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7e32GXOdclDt5koO1LuGMoCHPHXAx66CjXFcUXyFykw=; b=LUn77a60hp8NIaNn/3xeTYwyNoGN3Vv8vwkWHSPsClzx4zZhE+ICKAEg9Adl5XdklC 1HC5K4s6MEePHmTkm08wTl6cawywYnqjEon1XeJj3+zUJy3exD50lGeBdwNxdeB6++Kw E1ShMQrvMMHJWHWWTQuCDleVvbt/IOQiOQQUiG12QLVLt/m/9IqmAIw0DCz+7iLSnouv JG44ujjHr87WLWwquJnIPBFViRAuZjVqdwSip8AZfnYjWNW3MQyxbbkDgSz0zo4nGtF4 gpqO3e1Z/XwAztdbtN/KErftOmXm7381gmCe3Kyk2XD1CMJZlADK9CiElskLJ1urAfdX AETQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279575; x=1698884375; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7e32GXOdclDt5koO1LuGMoCHPHXAx66CjXFcUXyFykw=; b=AJyornbfsGbW7SNXD203qsOL7oXfwuz+5xxZbCxW2jSnW9YAtJdXUVKqf3hGttiO0R 6NydybGg777E+kgizJ6ZimZGkAJEkdRdYwsggJ/+1BtYVAy1EUzANXkvmB/ihBWSfpJo OUpZXGV6GllIi4FmQvrzIMePCw/rwHwcb/tDf6sIJvTB1/UlIIbzeDOGE9BE0Jj/ktvV Uy5yYTBYsPfjWr33vyGALmtoISRK1a9hM+l8VWGrOuRN07yN9b/SUw2CLtbKYf5Ic2FP 405g6vaTI85pW4xKK4IbrJRpCDf3mdeLJ7E6wpUbD1wRAmJ9CmwvmmEIbhM4ch3BsKqL K4Bw== X-Gm-Message-State: AOJu0YyniPNiySA5ojuEDmc4Qi3bWYRkysRYYppJNfq2htbwNumbQ6Vk 4ohxT5X3+gt1TFYNfslKN/cV91ayuBExlQeouv4= X-Google-Smtp-Source: AGHT+IFutXMUHbdR7vClKg8kXI2eFPOO1nt02RFQ+SO1a1j+z+plLNtHWSvYX2VnDTOGeaWCdSMqQQ== X-Received: by 2002:a17:902:f202:b0:1ca:87e0:93e3 with SMTP id m2-20020a170902f20200b001ca87e093e3mr13462956plc.7.1698279575377; Wed, 25 Oct 2023 17:19:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 33/94] target/sparc: Move basic arithmetic to decodetree Date: Wed, 25 Oct 2023 17:14:41 -0700 Message-Id: <20231026001542.1141412-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279700142100023 Content-Type: text/plain; charset="utf-8" Move ADD, AND, OR, XOR, SUB, ANDN, ORN, XORN. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 12 +++ target/sparc/translate.c | 185 +++++++++++++++++--------------------- 2 files changed, 94 insertions(+), 103 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index eab737fdcc..3271c2997d 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -29,6 +29,9 @@ CALL 01 i:s30 &r_r_ri rd rs1 rs2_or_imm imm:bool @n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=3D0 =20 +&r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool +@r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc + { [ STBAR 10 00000 101000 01111 0 0000000000000 @@ -152,6 +155,15 @@ WRHPR_hintp 10 00011 110011 ..... . ..........= ... @n_r_ri WRHPR_htba 10 00101 110011 ..... . ............. @n_r_ri WRHPR_hstick_cmpr 10 11111 110011 ..... . ............. @n_r_ri =20 +ADD 10 ..... 0.0000 ..... . ............. @r_r_ri_cc +AND 10 ..... 0.0001 ..... . ............. @r_r_ri_cc +OR 10 ..... 0.0010 ..... . ............. @r_r_ri_cc +XOR 10 ..... 0.0011 ..... . ............. @r_r_ri_cc +SUB 10 ..... 0.0100 ..... . ............. @r_r_ri_cc +ANDN 10 ..... 0.0101 ..... . ............. @r_r_ri_cc +ORN 10 ..... 0.0110 ..... . ............. @r_r_ri_cc +XORN 10 ..... 0.0111 ..... . ............. @r_r_ri_cc + Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 { # For v7, the entire simm13 field is present, but masked to 7 bits. diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 7b83803b6b..2a8846f2ac 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4013,6 +4013,88 @@ static bool trans_NOP_v7(DisasContext *dc, arg_NOP_v= 7 *a) return false; } =20 +static bool do_arith_int(DisasContext *dc, arg_r_r_ri_cc *a, int cc_op, + void (*func)(TCGv, TCGv, TCGv), + void (*funci)(TCGv, TCGv, target_long)) +{ + TCGv dst, src1; + + /* For simplicity, we under-decoded the rs2 form. */ + if (!a->imm && a->rs2_or_imm & ~0x1f) { + return false; + } + + if (a->cc) { + dst =3D cpu_cc_dst; + } else { + dst =3D gen_dest_gpr(dc, a->rd); + } + src1 =3D gen_load_gpr(dc, a->rs1); + + if (a->imm || a->rs2_or_imm =3D=3D 0) { + if (funci) { + funci(dst, src1, a->rs2_or_imm); + } else { + func(dst, src1, tcg_constant_tl(a->rs2_or_imm)); + } + } else { + func(dst, src1, cpu_regs[a->rs2_or_imm]); + } + gen_store_gpr(dc, a->rd, dst); + + if (a->cc) { + tcg_gen_movi_i32(cpu_cc_op, cc_op); + dc->cc_op =3D cc_op; + } + return advance_pc(dc); +} + +static bool do_arith(DisasContext *dc, arg_r_r_ri_cc *a, int cc_op, + void (*func)(TCGv, TCGv, TCGv), + void (*funci)(TCGv, TCGv, target_long), + void (*func_cc)(TCGv, TCGv, TCGv)) +{ + if (a->cc) { + return do_arith_int(dc, a, cc_op, func_cc, NULL); + } + return do_arith_int(dc, a, cc_op, func, funci); +} + +static bool do_logic(DisasContext *dc, arg_r_r_ri_cc *a, + void (*func)(TCGv, TCGv, TCGv), + void (*funci)(TCGv, TCGv, target_long)) +{ + return do_arith_int(dc, a, CC_OP_LOGIC, func, funci); +} + +TRANS(ADD, ALL, do_arith, a, CC_OP_ADD, + tcg_gen_add_tl, tcg_gen_addi_tl, gen_op_add_cc) +TRANS(SUB, ALL, do_arith, a, CC_OP_SUB, + tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_sub_cc) + +TRANS(AND, ALL, do_logic, a, tcg_gen_and_tl, tcg_gen_andi_tl) +TRANS(XOR, ALL, do_logic, a, tcg_gen_xor_tl, tcg_gen_xori_tl) +TRANS(ANDN, ALL, do_logic, a, tcg_gen_andc_tl, NULL) +TRANS(ORN, ALL, do_logic, a, tcg_gen_orc_tl, NULL) +TRANS(XORN, ALL, do_logic, a, tcg_gen_eqv_tl, NULL) + +static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a) +{ + /* OR with %g0 is the canonical alias for MOV. */ + if (!a->cc && a->rs1 =3D=3D 0) { + if (a->imm || a->rs2_or_imm =3D=3D 0) { + gen_store_gpr(dc, a->rd, tcg_constant_tl(a->rs2_or_imm)); + } else if (a->rs2_or_imm & ~0x1f) { + /* For simplicity, we under-decoded the rs2 form. */ + return false; + } else { + gen_store_gpr(dc, a->rd, cpu_regs[a->rs2_or_imm]); + } + return advance_pc(dc); + } + return do_logic(dc, a, tcg_gen_or_tl, tcg_gen_ori_tl); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4361,43 +4443,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) default: goto illegal_insn; } - } else if (xop =3D=3D 0x2) { - TCGv dst =3D gen_dest_gpr(dc, rd); - rs1 =3D GET_FIELD(insn, 13, 17); - if (rs1 =3D=3D 0) { - /* clr/mov shortcut : or %g0, x, y -> mov x, y */ - if (IS_IMM) { /* immediate */ - simm =3D GET_FIELDs(insn, 19, 31); - tcg_gen_movi_tl(dst, simm); - gen_store_gpr(dc, rd, dst); - } else { /* register */ - rs2 =3D GET_FIELD(insn, 27, 31); - if (rs2 =3D=3D 0) { - tcg_gen_movi_tl(dst, 0); - gen_store_gpr(dc, rd, dst); - } else { - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_store_gpr(dc, rd, cpu_src2); - } - } - } else { - cpu_src1 =3D get_src1(dc, insn); - if (IS_IMM) { /* immediate */ - simm =3D GET_FIELDs(insn, 19, 31); - tcg_gen_ori_tl(dst, cpu_src1, simm); - gen_store_gpr(dc, rd, dst); - } else { /* register */ - rs2 =3D GET_FIELD(insn, 27, 31); - if (rs2 =3D=3D 0) { - /* mov shortcut: or x, %g0, y -> mov x, y */ - gen_store_gpr(dc, rd, cpu_src1); - } else { - cpu_src2 =3D gen_load_gpr(dc, rs2); - tcg_gen_or_tl(dst, cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, dst); - } - } - } #ifdef TARGET_SPARC64 } else if (xop =3D=3D 0x25) { /* sll, V9 sllx */ cpu_src1 =3D get_src1(dc, insn); @@ -4474,72 +4519,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) cpu_src1 =3D get_src1(dc, insn); cpu_src2 =3D get_src2(dc, insn); switch (xop & ~0x10) { - case 0x0: /* add */ - if (xop & 0x10) { - gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); - dc->cc_op =3D CC_OP_ADD; - } else { - tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); - } - break; - case 0x1: /* and */ - tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2); - if (xop & 0x10) { - tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); - dc->cc_op =3D CC_OP_LOGIC; - } - break; - case 0x2: /* or */ - tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); - if (xop & 0x10) { - tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); - dc->cc_op =3D CC_OP_LOGIC; - } - break; - case 0x3: /* xor */ - tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); - if (xop & 0x10) { - tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); - dc->cc_op =3D CC_OP_LOGIC; - } - break; - case 0x4: /* sub */ - if (xop & 0x10) { - gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); - dc->cc_op =3D CC_OP_SUB; - } else { - tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2); - } - break; - case 0x5: /* andn */ - tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2); - if (xop & 0x10) { - tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); - dc->cc_op =3D CC_OP_LOGIC; - } - break; - case 0x6: /* orn */ - tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2); - if (xop & 0x10) { - tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); - dc->cc_op =3D CC_OP_LOGIC; - } - break; - case 0x7: /* xorn */ - tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2); - if (xop & 0x10) { - tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); - dc->cc_op =3D CC_OP_LOGIC; - } - break; case 0x8: /* addx, V9 addc */ gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2, (xop & 0x10)); --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280279; cv=none; d=zohomail.com; s=zohoarc; b=jPZjVlXC5kef0IBoo+8lorSIf8sy1/v+t/HRbJUeppG2Bb2HEEX84jtSPCdn/fZWAv5yUM/awLUUK5QB8XmCs8el8cCm8svH1myUg0RQ9cyaHngRxaAxP2elBWf9APYUP93TdcLxNRb4D6CBeYVlTXZsZej1T1eR8vaG0+YtT+A= ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279576; x=1698884376; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xoLBlyu7idL5AbpDPBt4MB7Nht6Rv+NOTvRkK60g84Q=; b=uqX+qJ2GN6PP4lFMKzaRkH9OOFuHKmNI7TlU8k/Zjrmru8wBJvnhrwIitQuo5r/lwX r3ZdvP8Q6Z8eW7GdxpnBtB1C6cz8P4Ajwl3CG80z+xg3OscCTLeCGdpIB9gHLhRcFDEO fB40WxZZIoBzRW+7nmWxqYrn23CVV6clZRBLrVSXmy+IN2/VEArsgmX0aDWabEwSPqnw HaNumatN9jGvkMYVZ4p3AYKy5Rk6ltN94emM0eZaupM0YE8Q9DC6zyPcGOMFzphrCQxA b27direZYUhLcPqpfBAjMAJz7uKPix8ghV99+JUKcOxbkdLOKzwzHxkMg2ROkMtEDGcE 39ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279576; x=1698884376; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xoLBlyu7idL5AbpDPBt4MB7Nht6Rv+NOTvRkK60g84Q=; b=waOqkltDGgKUR21wOkkLc1mxR1jJkSlmbqe6Pf7PwhyXp1Fme2exATxK01TJn6haSl u+qze2OQXBGOHc9fM40X1pi3opx1+a5eGWzMQa+cLsAmxBGedhqU0OAASQkM8wWdmKYF yndR1L0NPrJzkFamFNKE3VgRioDDaBWJamhFJoRXgexYb6rBTzhXYrX90zoMakrVxhzH hb1YWVFJHqBWNQETayL2dfoykTmozTat5mdHXfDfH9WshdsTuCgTY8bsZIXYSoCBykb9 vR88oOy733WJcumyhUM655LruMuBVP8edGWUFQ93eDISJijJZyEJPb5eCghmqZcDJsyl EL1Q== X-Gm-Message-State: AOJu0YzOJrq5DnLTQDVNQWNO6MLSZ2RI970D2LNrCV7ofujh0bNeqD4n HBUWgbNFBGnGjm6mrRpBrg7FFbalrgE2cz16ykQ= X-Google-Smtp-Source: AGHT+IG9YgMxbmG5wYwrH1+a0D7a5NHOsUnqXdT+YDydmhLQWXMQdILdCySi9LzQmA5cf4BO0BAgfA== X-Received: by 2002:a17:902:a417:b0:1bb:b855:db3c with SMTP id p23-20020a170902a41700b001bbb855db3cmr11839100plq.41.1698279576244; Wed, 25 Oct 2023 17:19:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 34/94] target/sparc: Move ADDC to decodetree Date: Wed, 25 Oct 2023 17:14:42 -0700 Message-Id: <20231026001542.1141412-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280279970100003 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 154 ++++++++++++++++++++++++-------------- 2 files changed, 97 insertions(+), 58 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 3271c2997d..1cff18fa1f 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -163,6 +163,7 @@ SUB 10 ..... 0.0100 ..... . ............. = @r_r_ri_cc ANDN 10 ..... 0.0101 ..... . ............. @r_r_ri_cc ORN 10 ..... 0.0110 ..... . ............. @r_r_ri_cc XORN 10 ..... 0.0111 ..... . ............. @r_r_ri_cc +ADDC 10 ..... 0.1000 ..... . ............. @r_r_ri_cc =20 Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 { diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 2a8846f2ac..eb829acc68 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -447,71 +447,89 @@ static TCGv_i32 gen_sub32_carry32(void) return carry_32; } =20 -static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1, - TCGv src2, int update_cc) +static void gen_op_addc_int(TCGv dst, TCGv src1, TCGv src2, + TCGv_i32 carry_32, bool update_cc) { - TCGv_i32 carry_32; - TCGv carry; + tcg_gen_add_tl(dst, src1, src2); =20 - switch (dc->cc_op) { - case CC_OP_DIV: - case CC_OP_LOGIC: - /* Carry is known to be zero. Fall back to plain ADD. */ - if (update_cc) { - gen_op_add_cc(dst, src1, src2); - } else { - tcg_gen_add_tl(dst, src1, src2); - } - return; - - case CC_OP_ADD: - case CC_OP_TADD: - case CC_OP_TADDTV: - if (TARGET_LONG_BITS =3D=3D 32) { - /* We can re-use the host's hardware carry generation by using - an ADD2 opcode. We discard the low part of the output. - Ideally we'd combine this operation with the add that - generated the carry in the first place. */ - carry =3D tcg_temp_new(); - tcg_gen_add2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src= 2); - goto add_done; - } - carry_32 =3D gen_add32_carry32(); - break; - - case CC_OP_SUB: - case CC_OP_TSUB: - case CC_OP_TSUBTV: - carry_32 =3D gen_sub32_carry32(); - break; - - default: - /* We need external help to produce the carry. */ - carry_32 =3D tcg_temp_new_i32(); - gen_helper_compute_C_icc(carry_32, tcg_env); - break; - } - -#if TARGET_LONG_BITS =3D=3D 64 - carry =3D tcg_temp_new(); - tcg_gen_extu_i32_i64(carry, carry_32); +#ifdef TARGET_SPARC64 + TCGv carry =3D tcg_temp_new(); + tcg_gen_extu_i32_tl(carry, carry_32); + tcg_gen_add_tl(dst, dst, carry); #else - carry =3D carry_32; + tcg_gen_add_i32(dst, dst, carry_32); #endif =20 - tcg_gen_add_tl(dst, src1, src2); - tcg_gen_add_tl(dst, dst, carry); - - add_done: if (update_cc) { + tcg_debug_assert(dst =3D=3D cpu_cc_dst); tcg_gen_mov_tl(cpu_cc_src, src1); tcg_gen_mov_tl(cpu_cc_src2, src2); - tcg_gen_mov_tl(cpu_cc_dst, dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX); - dc->cc_op =3D CC_OP_ADDX; } } =20 +static void gen_op_addc_int_add(TCGv dst, TCGv src1, TCGv src2, bool updat= e_cc) +{ + TCGv discard; + + if (TARGET_LONG_BITS =3D=3D 64) { + gen_op_addc_int(dst, src1, src2, gen_add32_carry32(), update_cc); + return; + } + + /* + * We can re-use the host's hardware carry generation by using + * an ADD2 opcode. We discard the low part of the output. + * Ideally we'd combine this operation with the add that + * generated the carry in the first place. + */ + discard =3D tcg_temp_new(); + tcg_gen_add2_tl(discard, dst, cpu_cc_src, src1, cpu_cc_src2, src2); + + if (update_cc) { + tcg_debug_assert(dst =3D=3D cpu_cc_dst); + tcg_gen_mov_tl(cpu_cc_src, src1); + tcg_gen_mov_tl(cpu_cc_src2, src2); + } +} + +static void gen_op_addc_add(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_addc_int_add(dst, src1, src2, false); +} + +static void gen_op_addccc_add(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_addc_int_add(dst, src1, src2, true); +} + +static void gen_op_addc_sub(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_addc_int(dst, src1, src2, gen_sub32_carry32(), false); +} + +static void gen_op_addccc_sub(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_addc_int(dst, src1, src2, gen_sub32_carry32(), true); +} + +static void gen_op_addc_int_generic(TCGv dst, TCGv src1, TCGv src2, + bool update_cc) +{ + TCGv_i32 carry_32 =3D tcg_temp_new_i32(); + gen_helper_compute_C_icc(carry_32, tcg_env); + gen_op_addc_int(dst, src1, src2, carry_32, update_cc); +} + +static void gen_op_addc_generic(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_addc_int_generic(dst, src1, src2, false); +} + +static void gen_op_addccc_generic(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_addc_int_generic(dst, src1, src2, true); +} + static void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) { tcg_gen_mov_tl(cpu_cc_src, src1); @@ -4095,6 +4113,30 @@ static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc= *a) return do_logic(dc, a, tcg_gen_or_tl, tcg_gen_ori_tl); } =20 +static bool trans_ADDC(DisasContext *dc, arg_r_r_ri_cc *a) +{ + switch (dc->cc_op) { + case CC_OP_DIV: + case CC_OP_LOGIC: + /* Carry is known to be zero. Fall back to plain ADD. */ + return do_arith(dc, a, CC_OP_ADD, + tcg_gen_add_tl, tcg_gen_addi_tl, gen_op_add_cc); + case CC_OP_ADD: + case CC_OP_TADD: + case CC_OP_TADDTV: + return do_arith(dc, a, CC_OP_ADDX, + gen_op_addc_add, NULL, gen_op_addccc_add); + case CC_OP_SUB: + case CC_OP_TSUB: + case CC_OP_TSUBTV: + return do_arith(dc, a, CC_OP_ADDX, + gen_op_addc_sub, NULL, gen_op_addccc_sub); + default: + return do_arith(dc, a, CC_OP_ADDX, + gen_op_addc_generic, NULL, gen_op_addccc_generic); + } +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4519,10 +4561,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) cpu_src1 =3D get_src1(dc, insn); cpu_src2 =3D get_src2(dc, insn); switch (xop & ~0x10) { - case 0x8: /* addx, V9 addc */ - gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2, - (xop & 0x10)); - break; #ifdef TARGET_SPARC64 case 0x9: /* V9 mulx */ tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2); --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279880; cv=none; d=zohomail.com; s=zohoarc; b=BfVmkzEexd5xKkIR3938NhOvBU4noFlunkmZ6fbrt9up+QNbZznI9oQP+3aq0YuXDvzj+I5pYHyxKzI3gEOZsh0AKSz6ipRpw4HKXZD0/GhIWT6ge9uF9MhXDhD9pRlMpxaBO7l+NrpmpD8d0Jgq/1zkAs8304C2t8Y/Yqy4PNg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279880; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ii+UgCJP+tPdYxSJC+tW/iaYho3LkDYSDzYDIA5OxYY=; b=BRahDKhThu2vb5xR3eA816aSqGAkLTT1rUp0n6ripgClZqMw5qdxL4JLAZ4eycEtYvLUTuUQrskxG9cNqkbyuclvK9XoyRFqDTVJADEgcwbgQYwfHOGukzrm8/EfOgPyeRfOiCi9zfW0KSNtUCFoPIAI0HerVKLbFAm3PaqtYGo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698279880564292.26567917751356; Wed, 25 Oct 2023 17:24:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo6z-0002Mx-Mc; Wed, 25 Oct 2023 20:20:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo6G-0001Dz-OI for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:48 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo66-0006eJ-G9 for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:48 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1c9b7c234a7so2320485ad.3 for ; Wed, 25 Oct 2023 17:19:38 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279880813100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 8 +++----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 1cff18fa1f..1a04a8e229 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -31,6 +31,7 @@ CALL 01 i:s30 =20 &r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool @r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc +@r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc = cc=3D0 =20 { [ @@ -165,6 +166,8 @@ ORN 10 ..... 0.0110 ..... . ............. = @r_r_ri_cc XORN 10 ..... 0.0111 ..... . ............. @r_r_ri_cc ADDC 10 ..... 0.1000 ..... . ............. @r_r_ri_cc =20 +MULX 10 ..... 001001 ..... . ............. @r_r_ri_cc0 + Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 { # For v7, the entire simm13 field is present, but masked to 7 bits. diff --git a/target/sparc/translate.c b/target/sparc/translate.c index eb829acc68..2ecd9edb33 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4073,6 +4073,7 @@ static bool do_arith(DisasContext *dc, arg_r_r_ri_cc = *a, int cc_op, void (*func_cc)(TCGv, TCGv, TCGv)) { if (a->cc) { + assert(cc_op >=3D 0); return do_arith_int(dc, a, cc_op, func_cc, NULL); } return do_arith_int(dc, a, cc_op, func, funci); @@ -4096,6 +4097,8 @@ TRANS(ANDN, ALL, do_logic, a, tcg_gen_andc_tl, NULL) TRANS(ORN, ALL, do_logic, a, tcg_gen_orc_tl, NULL) TRANS(XORN, ALL, do_logic, a, tcg_gen_eqv_tl, NULL) =20 +TRANS(MULX, 64, do_arith, a, -1, tcg_gen_mul_tl, tcg_gen_muli_tl, NULL) + static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a) { /* OR with %g0 is the canonical alias for MOV. */ @@ -4561,11 +4564,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) cpu_src1 =3D get_src1(dc, insn); cpu_src2 =3D get_src2(dc, insn); switch (xop & ~0x10) { -#ifdef TARGET_SPARC64 - case 0x9: /* V9 mulx */ - tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2); - break; -#endif case 0xa: /* umul */ CHECK_IU_FEATURE(dc, MUL); gen_op_umul(cpu_dst, cpu_src1, cpu_src2); --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280732391100003 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 22 ++++------------------ 2 files changed, 6 insertions(+), 18 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 1a04a8e229..d6a7256e71 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -167,6 +167,8 @@ XORN 10 ..... 0.0111 ..... . ............. = @r_r_ri_cc ADDC 10 ..... 0.1000 ..... . ............. @r_r_ri_cc =20 MULX 10 ..... 001001 ..... . ............. @r_r_ri_cc0 +UMUL 10 ..... 0.1010 ..... . ............. @r_r_ri_cc +SMUL 10 ..... 0.1011 ..... . ............. @r_r_ri_cc =20 Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 { diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 2ecd9edb33..e7c3c68402 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2888,6 +2888,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s= 1, TCGv s2) #ifdef TARGET_SPARC64 # define avail_32(C) false # define avail_ASR17(C) false +# define avail_MUL(C) true # define avail_POWERDOWN(C) false # define avail_64(C) true # define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL) @@ -2895,6 +2896,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s= 1, TCGv s2) #else # define avail_32(C) true # define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17) +# define avail_MUL(C) ((C)->def->features & CPU_FEATURE_MUL) # define avail_POWERDOWN(C) ((C)->def->features & CPU_FEATURE_POWERDOWN) # define avail_64(C) false # define avail_GL(C) false @@ -4098,6 +4100,8 @@ TRANS(ORN, ALL, do_logic, a, tcg_gen_orc_tl, NULL) TRANS(XORN, ALL, do_logic, a, tcg_gen_eqv_tl, NULL) =20 TRANS(MULX, 64, do_arith, a, -1, tcg_gen_mul_tl, tcg_gen_muli_tl, NULL) +TRANS(UMUL, MUL, do_logic, a, gen_op_umul, NULL) +TRANS(SMUL, MUL, do_logic, a, gen_op_smul, NULL) =20 static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a) { @@ -4564,24 +4568,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) cpu_src1 =3D get_src1(dc, insn); cpu_src2 =3D get_src2(dc, insn); switch (xop & ~0x10) { - case 0xa: /* umul */ - CHECK_IU_FEATURE(dc, MUL); - gen_op_umul(cpu_dst, cpu_src1, cpu_src2); - if (xop & 0x10) { - tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); - dc->cc_op =3D CC_OP_LOGIC; - } - break; - case 0xb: /* smul */ - CHECK_IU_FEATURE(dc, MUL); - gen_op_smul(cpu_dst, cpu_src1, cpu_src2); - if (xop & 0x10) { - tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); - dc->cc_op =3D CC_OP_LOGIC; - } - break; case 0xc: /* subx, V9 subc */ gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2, (xop & 0x10)); --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279579; x=1698884379; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hha0FUqXQ6TXOMfH2RRgnruE6/BvIlYzO4Xx1oTtT4o=; b=KslmL5a11SbbeH1AQmNHkQOZOoOC7r8sCHrMapvNNxQ3yC3E/nauII9xz2NtY3pRxM 4vGOdIv2OT1lu/v6jbYcBzOG9tRKpwRRis7KPXo1fwFZbBmKwef9Yt8sDdaROhdyBCHG PoosUfMxyy5FPdwpXwFMe1MuVLcIZMakP51vzoHn3TIM7GLq+YEX44rDSQFzoB5luwgm NEsWjvyx9htoEMfjA1Ijy6WxTWzat/TSka6n6iY+tKkWKP48wuEp0BWdNLm1FphdcAdr MwHV6/2GDTffi8ejUXlJ5y4drdAheQ17TeXpYnvBqDor9bhJbatxyJB5/LAJcqfYY1yt 3gFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279579; x=1698884379; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hha0FUqXQ6TXOMfH2RRgnruE6/BvIlYzO4Xx1oTtT4o=; b=LSeXwRpxc9jT1yvoIBmXqwftbRceSya6mrB7y8kfCSXBm8J2dRK5kj6lunqArW+EaJ D3N3CS8P/yF+PQ7OqxlKWQk90zjIWlKkf0BKtCVolR50RI5kRN2n9/Mmb1wirsWhkA/O 7VbLa62US8NNIvPZdMXG5/P8S3fBawzTDsjXEkE9Gr1EvhHimhXwtTrflcfNLQiFKgP2 mJgl1SQlxPVHWAHAr5aeZRz333DBig8orvUAJWxMV3CWHzZqSh/t1FckrOU60DRaXS9X /45yDb7kiLQl7kNc9s2d9q5NjtBTnGNa+X07aZl82sdpPNMvYpNGeXNUqY7rhTjFMpBA PuuQ== X-Gm-Message-State: AOJu0Ywaingqvu+DOvlXO9Im5bno5tF6BrzpqAjiX1XEL8jQzHxWMoN/ XRG4GaIA2QXtsZJxhHT8u5VtJiYknGzjSQMw/UY= X-Google-Smtp-Source: AGHT+IGsaMrYcmWdQDyHlzdIAN7ywXmowIbrceEUWHZtWvnMi90nCqNzTo3bWKowMSYzYO05MjIsAw== X-Received: by 2002:a17:902:e545:b0:1c9:ddd8:9950 with SMTP id n5-20020a170902e54500b001c9ddd89950mr1584571plf.21.1698279578755; Wed, 25 Oct 2023 17:19:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 37/94] target/sparc: Move SUBC to decodetree Date: Wed, 25 Oct 2023 17:14:45 -0700 Message-Id: <20231026001542.1141412-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280399280100008 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 139 ++++++++++++++++++++++++-------------- 2 files changed, 90 insertions(+), 50 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index d6a7256e71..a188452d2e 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -165,6 +165,7 @@ ANDN 10 ..... 0.0101 ..... . ............. = @r_r_ri_cc ORN 10 ..... 0.0110 ..... . ............. @r_r_ri_cc XORN 10 ..... 0.0111 ..... . ............. @r_r_ri_cc ADDC 10 ..... 0.1000 ..... . ............. @r_r_ri_cc +SUBC 10 ..... 0.1100 ..... . ............. @r_r_ri_cc =20 MULX 10 ..... 001001 ..... . ............. @r_r_ri_cc0 UMUL 10 ..... 0.1010 ..... . ............. @r_r_ri_cc diff --git a/target/sparc/translate.c b/target/sparc/translate.c index e7c3c68402..b8fbd18a4c 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -538,51 +538,11 @@ static void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv s= rc2) tcg_gen_mov_tl(dst, cpu_cc_dst); } =20 -static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1, - TCGv src2, int update_cc) +static void gen_op_subc_int(TCGv dst, TCGv src1, TCGv src2, + TCGv_i32 carry_32, bool update_cc) { - TCGv_i32 carry_32; TCGv carry; =20 - switch (dc->cc_op) { - case CC_OP_DIV: - case CC_OP_LOGIC: - /* Carry is known to be zero. Fall back to plain SUB. */ - if (update_cc) { - gen_op_sub_cc(dst, src1, src2); - } else { - tcg_gen_sub_tl(dst, src1, src2); - } - return; - - case CC_OP_ADD: - case CC_OP_TADD: - case CC_OP_TADDTV: - carry_32 =3D gen_add32_carry32(); - break; - - case CC_OP_SUB: - case CC_OP_TSUB: - case CC_OP_TSUBTV: - if (TARGET_LONG_BITS =3D=3D 32) { - /* We can re-use the host's hardware carry generation by using - a SUB2 opcode. We discard the low part of the output. - Ideally we'd combine this operation with the add that - generated the carry in the first place. */ - carry =3D tcg_temp_new(); - tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src= 2); - goto sub_done; - } - carry_32 =3D gen_sub32_carry32(); - break; - - default: - /* We need external help to produce the carry. */ - carry_32 =3D tcg_temp_new_i32(); - gen_helper_compute_C_icc(carry_32, tcg_env); - break; - } - #if TARGET_LONG_BITS =3D=3D 64 carry =3D tcg_temp_new(); tcg_gen_extu_i32_i64(carry, carry_32); @@ -593,16 +553,75 @@ static void gen_op_subx_int(DisasContext *dc, TCGv ds= t, TCGv src1, tcg_gen_sub_tl(dst, src1, src2); tcg_gen_sub_tl(dst, dst, carry); =20 - sub_done: if (update_cc) { + tcg_debug_assert(dst =3D=3D cpu_cc_dst); tcg_gen_mov_tl(cpu_cc_src, src1); tcg_gen_mov_tl(cpu_cc_src2, src2); - tcg_gen_mov_tl(cpu_cc_dst, dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX); - dc->cc_op =3D CC_OP_SUBX; } } =20 +static void gen_op_subc_add(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_subc_int(dst, src1, src2, gen_add32_carry32(), false); +} + +static void gen_op_subccc_add(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_subc_int(dst, src1, src2, gen_add32_carry32(), true); +} + +static void gen_op_subc_int_sub(TCGv dst, TCGv src1, TCGv src2, bool updat= e_cc) +{ + TCGv discard; + + if (TARGET_LONG_BITS =3D=3D 64) { + gen_op_subc_int(dst, src1, src2, gen_sub32_carry32(), update_cc); + return; + } + + /* + * We can re-use the host's hardware carry generation by using + * a SUB2 opcode. We discard the low part of the output. + */ + discard =3D tcg_temp_new(); + tcg_gen_sub2_tl(discard, dst, cpu_cc_src, src1, cpu_cc_src2, src2); + + if (update_cc) { + tcg_debug_assert(dst =3D=3D cpu_cc_dst); + tcg_gen_mov_tl(cpu_cc_src, src1); + tcg_gen_mov_tl(cpu_cc_src2, src2); + } +} + +static void gen_op_subc_sub(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_subc_int_sub(dst, src1, src2, false); +} + +static void gen_op_subccc_sub(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_subc_int_sub(dst, src1, src2, true); +} + +static void gen_op_subc_int_generic(TCGv dst, TCGv src1, TCGv src2, + bool update_cc) +{ + TCGv_i32 carry_32 =3D tcg_temp_new_i32(); + + gen_helper_compute_C_icc(carry_32, tcg_env); + gen_op_subc_int(dst, src1, src2, carry_32, update_cc); +} + +static void gen_op_subc_generic(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_subc_int_generic(dst, src1, src2, false); +} + +static void gen_op_subccc_generic(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_subc_int_generic(dst, src1, src2, true); +} + static void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) { TCGv r_temp, zero, t0; @@ -4144,6 +4163,30 @@ static bool trans_ADDC(DisasContext *dc, arg_r_r_ri_= cc *a) } } =20 +static bool trans_SUBC(DisasContext *dc, arg_r_r_ri_cc *a) +{ + switch (dc->cc_op) { + case CC_OP_DIV: + case CC_OP_LOGIC: + /* Carry is known to be zero. Fall back to plain SUB. */ + return do_arith(dc, a, CC_OP_SUB, + tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_sub_cc); + case CC_OP_ADD: + case CC_OP_TADD: + case CC_OP_TADDTV: + return do_arith(dc, a, CC_OP_SUBX, + gen_op_subc_add, NULL, gen_op_subccc_add); + case CC_OP_SUB: + case CC_OP_TSUB: + case CC_OP_TSUBTV: + return do_arith(dc, a, CC_OP_SUBX, + gen_op_subc_sub, NULL, gen_op_subccc_sub); + default: + return do_arith(dc, a, CC_OP_SUBX, + gen_op_subc_generic, NULL, gen_op_subccc_generic); + } +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4568,10 +4611,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) cpu_src1 =3D get_src1(dc, insn); cpu_src2 =3D get_src2(dc, insn); switch (xop & ~0x10) { - case 0xc: /* subx, V9 subc */ - gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2, - (xop & 0x10)); - break; #ifdef TARGET_SPARC64 case 0xd: /* V9 udivx */ gen_helper_udivx(cpu_dst, tcg_env, cpu_src1, cpu_s= rc2); --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280716; cv=none; d=zohomail.com; s=zohoarc; b=Xn+uy7Xk8KqSSLRT0YEIVetXxJVF6vDoZtQk30Nvbo7RwW92NyIPAiTwBPVID62CyYGb+m6nZPNDw8t/tDo4wcTWl2mDXsBCksi1HrxdkF7I3t89gaRruu1yt+YgHfML0dMfHWVZZ2EpFN/+c4Kia4m5NNIYqKK9bkO0DyAN2vo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280716; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bPj9+ObK+DfulKal4BkwqX+PvjoTqBOnoBqmRlb19e8=; b=BNWSOLDuDh5xBB8pzEGHadBJSxVlgjGEOJfT3HyL5xuTw4/3MiFNmU4Kpa4TOOV3Ky7HNRMBa/SH4eRSW/z7THR1yyMNX6quB0fjiv0s9gQDnSu9VO/u4Vh9rAk5UVCdAH4Rw/jXv2VbmfC5FeV5F1q/y4sVAfLCkyNd/xjNbbs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698280716033398.67070088825756; Wed, 25 Oct 2023 17:38:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo6q-0002Hg-Rv; Wed, 25 Oct 2023 20:20:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo6L-0001Rb-6S for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:53 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo6A-0006iP-6z for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:52 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1c8a1541232so2483755ad.0 for ; Wed, 25 Oct 2023 17:19:40 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280716330100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 24 +++++++++++++++--------- 2 files changed, 18 insertions(+), 9 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a188452d2e..dd0ed3a993 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -171,6 +171,9 @@ MULX 10 ..... 001001 ..... . ............. = @r_r_ri_cc0 UMUL 10 ..... 0.1010 ..... . ............. @r_r_ri_cc SMUL 10 ..... 0.1011 ..... . ............. @r_r_ri_cc =20 +UDIVX 10 ..... 001101 ..... . ............. @r_r_ri_cc0 +SDIVX 10 ..... 101101 ..... . ............. @r_r_ri_cc0 + Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 { # For v7, the entire simm13 field is present, but masked to 7 bits. diff --git a/target/sparc/translate.c b/target/sparc/translate.c index b8fbd18a4c..826ba0441b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -47,10 +47,12 @@ # define gen_helper_rdcwp(D, E) qemu_build_not_reached() # define gen_helper_restored(E) qemu_build_not_reached() # define gen_helper_saved(E) qemu_build_not_reached() +# define gen_helper_sdivx(D, E, A, B) qemu_build_not_reached() # define gen_helper_set_softint(E, S) qemu_build_not_reached() # define gen_helper_tick_get_count(D, E, T, C) qemu_build_not_reached() # define gen_helper_tick_set_count(P, S) qemu_build_not_reached() # define gen_helper_tick_set_limit(P, S) qemu_build_not_reached() +# define gen_helper_udivx(D, E, A, B) qemu_build_not_reached() # define gen_helper_wrccr(E, S) qemu_build_not_reached() # define gen_helper_wrcwp(E, S) qemu_build_not_reached() # define gen_helper_wrgl(E, S) qemu_build_not_reached() @@ -698,6 +700,16 @@ static void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) gen_op_multiply(dst, src1, src2, 1); } =20 +static void gen_op_udivx(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_udivx(dst, tcg_env, src1, src2); +} + +static void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_sdivx(dst, tcg_env, src1, src2); +} + // 1 static void gen_op_eval_ba(TCGv dst) { @@ -4122,6 +4134,9 @@ TRANS(MULX, 64, do_arith, a, -1, tcg_gen_mul_tl, tcg_= gen_muli_tl, NULL) TRANS(UMUL, MUL, do_logic, a, gen_op_umul, NULL) TRANS(SMUL, MUL, do_logic, a, gen_op_smul, NULL) =20 +TRANS(UDIVX, 64, do_arith, a, -1, gen_op_udivx, NULL, NULL) +TRANS(SDIVX, 64, do_arith, a, -1, gen_op_sdivx, NULL, NULL) + static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a) { /* OR with %g0 is the canonical alias for MOV. */ @@ -4611,11 +4626,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) cpu_src1 =3D get_src1(dc, insn); cpu_src2 =3D get_src2(dc, insn); switch (xop & ~0x10) { -#ifdef TARGET_SPARC64 - case 0xd: /* V9 udivx */ - gen_helper_udivx(cpu_dst, tcg_env, cpu_src1, cpu_s= rc2); - break; -#endif case 0xe: /* udiv */ CHECK_IU_FEATURE(dc, DIV); if (xop & 0x10) { @@ -4753,10 +4763,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) gen_store_gpr(dc, rd, dst); break; } - case 0x2d: /* V9 sdivx */ - gen_helper_sdivx(cpu_dst, tcg_env, cpu_src1, cpu_s= rc2); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x2e: /* V9 popc */ tcg_gen_ctpop_tl(cpu_dst, cpu_src2); gen_store_gpr(dc, rd, cpu_dst); --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280026; cv=none; d=zohomail.com; s=zohoarc; b=AB+i/ay3xxCulYWovPiIQlvvxh1WwWECsYxV6dEbnqVbfanUSC1unq7dUfxZMGyCYX/zcMA0exsivCgJGPImlZUIpkIefh0VVqAmHQcSDuyD9j/a60kmm/dTuDdSXBlc9014bh8hren+VzlBAQrYEADI5xVvNrShoJRHPqOHM5I= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280027475100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/helper.c | 4 --- target/sparc/translate.c | 54 ++++++++++++++++++--------------------- 3 files changed, 27 insertions(+), 33 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index dd0ed3a993..4415d03858 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -173,6 +173,8 @@ SMUL 10 ..... 0.1011 ..... . ............. = @r_r_ri_cc =20 UDIVX 10 ..... 001101 ..... . ............. @r_r_ri_cc0 SDIVX 10 ..... 101101 ..... . ............. @r_r_ri_cc0 +UDIV 10 ..... 0.1110 ..... . ............. @r_r_ri_cc +SDIV 10 ..... 0.1111 ..... . ............. @r_r_ri_cc =20 Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 { diff --git a/target/sparc/helper.c b/target/sparc/helper.c index c4358bba84..e25fdaeedd 100644 --- a/target/sparc/helper.c +++ b/target/sparc/helper.c @@ -102,9 +102,7 @@ static target_ulong do_udiv(CPUSPARCState *env, target_= ulong a, } =20 if (cc) { - env->cc_dst =3D x0; env->cc_src2 =3D overflow; - env->cc_op =3D CC_OP_DIV; } return x0; } @@ -143,9 +141,7 @@ static target_ulong do_sdiv(CPUSPARCState *env, target_= ulong a, } =20 if (cc) { - env->cc_dst =3D x0; env->cc_src2 =3D overflow; - env->cc_op =3D CC_OP_DIV; } return x0; } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 826ba0441b..1ebaaa1114 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -710,6 +710,26 @@ static void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src= 2) gen_helper_sdivx(dst, tcg_env, src1, src2); } =20 +static void gen_op_udiv(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_udiv(dst, tcg_env, src1, src2); +} + +static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_sdiv(dst, tcg_env, src1, src2); +} + +static void gen_op_udivcc(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_udiv_cc(dst, tcg_env, src1, src2); +} + +static void gen_op_sdivcc(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_sdiv_cc(dst, tcg_env, src1, src2); +} + // 1 static void gen_op_eval_ba(TCGv dst) { @@ -2919,6 +2939,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s= 1, TCGv s2) #ifdef TARGET_SPARC64 # define avail_32(C) false # define avail_ASR17(C) false +# define avail_DIV(C) true # define avail_MUL(C) true # define avail_POWERDOWN(C) false # define avail_64(C) true @@ -2927,6 +2948,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s= 1, TCGv s2) #else # define avail_32(C) true # define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17) +# define avail_DIV(C) ((C)->def->features & CPU_FEATURE_DIV) # define avail_MUL(C) ((C)->def->features & CPU_FEATURE_MUL) # define avail_POWERDOWN(C) ((C)->def->features & CPU_FEATURE_POWERDOWN) # define avail_64(C) false @@ -4136,6 +4158,8 @@ TRANS(SMUL, MUL, do_logic, a, gen_op_smul, NULL) =20 TRANS(UDIVX, 64, do_arith, a, -1, gen_op_udivx, NULL, NULL) TRANS(SDIVX, 64, do_arith, a, -1, gen_op_sdivx, NULL, NULL) +TRANS(UDIV, DIV, do_arith, a, CC_OP_DIV, gen_op_udiv, NULL, gen_op_udivcc) +TRANS(SDIV, DIV, do_arith, a, CC_OP_DIV, gen_op_sdiv, NULL, gen_op_sdivcc) =20 static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a) { @@ -4623,35 +4647,7 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) #endif } else if (xop < 0x36) { if (xop < 0x20) { - cpu_src1 =3D get_src1(dc, insn); - cpu_src2 =3D get_src2(dc, insn); - switch (xop & ~0x10) { - case 0xe: /* udiv */ - CHECK_IU_FEATURE(dc, DIV); - if (xop & 0x10) { - gen_helper_udiv_cc(cpu_dst, tcg_env, cpu_src1, - cpu_src2); - dc->cc_op =3D CC_OP_DIV; - } else { - gen_helper_udiv(cpu_dst, tcg_env, cpu_src1, - cpu_src2); - } - break; - case 0xf: /* sdiv */ - CHECK_IU_FEATURE(dc, DIV); - if (xop & 0x10) { - gen_helper_sdiv_cc(cpu_dst, tcg_env, cpu_src1, - cpu_src2); - dc->cc_op =3D CC_OP_DIV; - } else { - gen_helper_sdiv(cpu_dst, tcg_env, cpu_src1, - cpu_src2); - } - break; - default: - goto illegal_insn; - } - gen_store_gpr(dc, rd, cpu_dst); + goto illegal_insn; } else { cpu_src1 =3D get_src1(dc, insn); cpu_src2 =3D get_src2(dc, insn); --=20 2.34.1 From nobody Wed Nov 27 12:34:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280405332100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 7 ++++++ target/sparc/helper.c | 4 ---- target/sparc/translate.c | 48 ++++++++++++++++++--------------------- 3 files changed, 29 insertions(+), 30 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 4415d03858..b35921aabb 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -32,6 +32,7 @@ CALL 01 i:s30 &r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool @r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc @r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc = cc=3D0 +@r_r_ri_cc1 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc = cc=3D1 =20 { [ @@ -170,12 +171,18 @@ SUBC 10 ..... 0.1100 ..... . ............. = @r_r_ri_cc MULX 10 ..... 001001 ..... . ............. @r_r_ri_cc0 UMUL 10 ..... 0.1010 ..... . ............. @r_r_ri_cc SMUL 10 ..... 0.1011 ..... . ............. @r_r_ri_cc +MULScc 10 ..... 100100 ..... . ............. @r_r_ri_cc1 =20 UDIVX 10 ..... 001101 ..... . ............. @r_r_ri_cc0 SDIVX 10 ..... 101101 ..... . ............. @r_r_ri_cc0 UDIV 10 ..... 0.1110 ..... . ............. @r_r_ri_cc SDIV 10 ..... 0.1111 ..... . ............. @r_r_ri_cc =20 +TADDcc 10 ..... 100000 ..... . ............. @r_r_ri_cc1 +TSUBcc 10 ..... 100001 ..... . ............. @r_r_ri_cc1 +TADDccTV 10 ..... 100010 ..... . ............. @r_r_ri_cc1 +TSUBccTV 10 ..... 100011 ..... . ............. @r_r_ri_cc1 + Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 { # For v7, the entire simm13 field is present, but masked to 7 bits. diff --git a/target/sparc/helper.c b/target/sparc/helper.c index e25fdaeedd..2bcdc81d54 100644 --- a/target/sparc/helper.c +++ b/target/sparc/helper.c @@ -198,10 +198,8 @@ target_ulong helper_taddcctv(CPUSPARCState *env, targe= t_ulong src1, } =20 /* Only modify the CC after any exceptions have been generated. */ - env->cc_op =3D CC_OP_TADDTV; env->cc_src =3D src1; env->cc_src2 =3D src2; - env->cc_dst =3D dst; return dst; =20 tag_overflow: @@ -226,10 +224,8 @@ target_ulong helper_tsubcctv(CPUSPARCState *env, targe= t_ulong src1, } =20 /* Only modify the CC after any exceptions have been generated. */ - env->cc_op =3D CC_OP_TSUBTV; env->cc_src =3D src1; env->cc_src2 =3D src2; - env->cc_dst =3D dst; return dst; =20 tag_overflow: diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 1ebaaa1114..861c6e8f1e 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -730,6 +730,16 @@ static void gen_op_sdivcc(TCGv dst, TCGv src1, TCGv sr= c2) gen_helper_sdiv_cc(dst, tcg_env, src1, src2); } =20 +static void gen_op_taddcctv(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_taddcctv(dst, tcg_env, src1, src2); +} + +static void gen_op_tsubcctv(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_tsubcctv(dst, tcg_env, src1, src2); +} + // 1 static void gen_op_eval_ba(TCGv dst) { @@ -4146,6 +4156,11 @@ TRANS(ADD, ALL, do_arith, a, CC_OP_ADD, TRANS(SUB, ALL, do_arith, a, CC_OP_SUB, tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_sub_cc) =20 +TRANS(TADDcc, ALL, do_arith, a, CC_OP_TADD, NULL, NULL, gen_op_add_cc) +TRANS(TSUBcc, ALL, do_arith, a, CC_OP_TSUB, NULL, NULL, gen_op_sub_cc) +TRANS(TADDccTV, ALL, do_arith, a, CC_OP_TADDTV, NULL, NULL, gen_op_taddcct= v) +TRANS(TSUBccTV, ALL, do_arith, a, CC_OP_TSUBTV, NULL, NULL, gen_op_tsubcct= v) + TRANS(AND, ALL, do_logic, a, tcg_gen_and_tl, tcg_gen_andi_tl) TRANS(XOR, ALL, do_logic, a, tcg_gen_xor_tl, tcg_gen_xori_tl) TRANS(ANDN, ALL, do_logic, a, tcg_gen_andc_tl, NULL) @@ -4226,6 +4241,12 @@ static bool trans_SUBC(DisasContext *dc, arg_r_r_ri_= cc *a) } } =20 +static bool trans_MULScc(DisasContext *dc, arg_r_r_ri_cc *a) +{ + update_psr(dc); + return do_arith(dc, a, CC_OP_ADD, NULL, NULL, gen_op_mulscc); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4653,36 +4674,11 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) cpu_src2 =3D get_src2(dc, insn); switch (xop) { case 0x20: /* taddcc */ - gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD); - dc->cc_op =3D CC_OP_TADD; - break; case 0x21: /* tsubcc */ - gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB); - dc->cc_op =3D CC_OP_TSUB; - break; case 0x22: /* taddcctv */ - gen_helper_taddcctv(cpu_dst, tcg_env, - cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - dc->cc_op =3D CC_OP_TADDTV; - break; case 0x23: /* tsubcctv */ - gen_helper_tsubcctv(cpu_dst, tcg_env, - cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - dc->cc_op =3D CC_OP_TSUBTV; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279732245100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 14 +++ target/sparc/translate.c | 182 ++++++++++++++++---------------------- 2 files changed, 92 insertions(+), 104 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index b35921aabb..51cddc826d 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -183,6 +183,20 @@ TSUBcc 10 ..... 100001 ..... . ............. = @r_r_ri_cc1 TADDccTV 10 ..... 100010 ..... . ............. @r_r_ri_cc1 TSUBccTV 10 ..... 100011 ..... . ............. @r_r_ri_cc1 =20 +&shiftr rd rs1 rs2 x:bool +@shiftr .. rd:5 ...... rs1:5 . x:1 ....... rs2:5 &shiftr + +SLL_r 10 ..... 100101 ..... 0 . 0000000 ..... @shiftr +SRL_r 10 ..... 100110 ..... 0 . 0000000 ..... @shiftr +SRA_r 10 ..... 100111 ..... 0 . 0000000 ..... @shiftr + +&shifti rd rs1 i x:bool +@shifti .. rd:5 ...... rs1:5 . x:1 ...... i:6 &shifti + +SLL_i 10 ..... 100101 ..... 1 . 000000 ...... @shifti +SRL_i 10 ..... 100110 ..... 1 . 000000 ...... @shifti +SRA_i 10 ..... 100111 ..... 1 . 000000 ...... @shifti + Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 { # For v7, the entire simm13 field is present, but masked to 7 bits. diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 861c6e8f1e..ac8cd40aa1 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4247,6 +4247,83 @@ static bool trans_MULScc(DisasContext *dc, arg_r_r_r= i_cc *a) return do_arith(dc, a, CC_OP_ADD, NULL, NULL, gen_op_mulscc); } =20 +static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u) +{ + TCGv dst, src1, src2; + + /* Reject 64-bit shifts for sparc32. */ + if (avail_32(dc) && a->x) { + return false; + } + + src2 =3D tcg_temp_new(); + tcg_gen_andi_tl(src2, gen_load_gpr(dc, a->rs2), a->x ? 63 : 31); + src1 =3D gen_load_gpr(dc, a->rs1); + dst =3D gen_dest_gpr(dc, a->rd); + + if (l) { + tcg_gen_shl_tl(dst, src1, src2); + if (!a->x) { + tcg_gen_ext32u_tl(dst, dst); + } + } else if (u) { + if (!a->x) { + tcg_gen_ext32u_tl(dst, src1); + src1 =3D dst; + } + tcg_gen_shr_tl(dst, src1, src2); + } else { + if (!a->x) { + tcg_gen_ext32s_tl(dst, src1); + src1 =3D dst; + } + tcg_gen_sar_tl(dst, src1, src2); + } + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(SLL_r, ALL, do_shift_r, a, true, true) +TRANS(SRL_r, ALL, do_shift_r, a, false, true) +TRANS(SRA_r, ALL, do_shift_r, a, false, false) + +static bool do_shift_i(DisasContext *dc, arg_shifti *a, bool l, bool u) +{ + TCGv dst, src1; + + /* Reject 64-bit shifts for sparc32. */ + if (avail_32(dc) && (a->x || a->i >=3D 32)) { + return false; + } + + src1 =3D gen_load_gpr(dc, a->rs1); + dst =3D gen_dest_gpr(dc, a->rd); + + if (avail_32(dc) || a->x) { + if (l) { + tcg_gen_shli_tl(dst, src1, a->i); + } else if (u) { + tcg_gen_shri_tl(dst, src1, a->i); + } else { + tcg_gen_sari_tl(dst, src1, a->i); + } + } else { + if (l) { + tcg_gen_deposit_z_tl(dst, src1, a->i, 32 - a->i); + } else if (u) { + tcg_gen_extract_tl(dst, src1, a->i, 32 - a->i); + } else { + tcg_gen_sextract_tl(dst, src1, a->i, 32 - a->i); + } + } + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(SLL_i, ALL, do_shift_i, a, true, true) +TRANS(SRL_i, ALL, do_shift_i, a, false, true) +TRANS(SRA_i, ALL, do_shift_i, a, false, false) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4595,77 +4672,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) default: goto illegal_insn; } -#ifdef TARGET_SPARC64 - } else if (xop =3D=3D 0x25) { /* sll, V9 sllx */ - cpu_src1 =3D get_src1(dc, insn); - if (IS_IMM) { /* immediate */ - simm =3D GET_FIELDs(insn, 20, 31); - if (insn & (1 << 12)) { - tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f); - } else { - tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f); - } - } else { /* register */ - rs2 =3D GET_FIELD(insn, 27, 31); - cpu_src2 =3D gen_load_gpr(dc, rs2); - cpu_tmp0 =3D tcg_temp_new(); - if (insn & (1 << 12)) { - tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); - } else { - tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); - } - tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0); - } - gen_store_gpr(dc, rd, cpu_dst); - } else if (xop =3D=3D 0x26) { /* srl, V9 srlx */ - cpu_src1 =3D get_src1(dc, insn); - if (IS_IMM) { /* immediate */ - simm =3D GET_FIELDs(insn, 20, 31); - if (insn & (1 << 12)) { - tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f); - } else { - tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); - tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f); - } - } else { /* register */ - rs2 =3D GET_FIELD(insn, 27, 31); - cpu_src2 =3D gen_load_gpr(dc, rs2); - cpu_tmp0 =3D tcg_temp_new(); - if (insn & (1 << 12)) { - tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); - tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0); - } else { - tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); - tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); - tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0); - } - } - gen_store_gpr(dc, rd, cpu_dst); - } else if (xop =3D=3D 0x27) { /* sra, V9 srax */ - cpu_src1 =3D get_src1(dc, insn); - if (IS_IMM) { /* immediate */ - simm =3D GET_FIELDs(insn, 20, 31); - if (insn & (1 << 12)) { - tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f); - } else { - tcg_gen_ext32s_i64(cpu_dst, cpu_src1); - tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f); - } - } else { /* register */ - rs2 =3D GET_FIELD(insn, 27, 31); - cpu_src2 =3D gen_load_gpr(dc, rs2); - cpu_tmp0 =3D tcg_temp_new(); - if (insn & (1 << 12)) { - tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); - tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0); - } else { - tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); - tcg_gen_ext32s_i64(cpu_dst, cpu_src1); - tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0); - } - } - gen_store_gpr(dc, rd, cpu_dst); -#endif } else if (xop < 0x36) { if (xop < 0x20) { goto illegal_insn; @@ -4678,42 +4684,10 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 0x22: /* taddcctv */ case 0x23: /* tsubcctv */ case 0x24: /* mulscc */ - goto illegal_insn; /* in decodetree */ -#ifndef TARGET_SPARC64 case 0x25: /* sll */ - if (IS_IMM) { /* immediate */ - simm =3D GET_FIELDs(insn, 20, 31); - tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f= ); - } else { /* register */ - cpu_tmp0 =3D tcg_temp_new(); - tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); - tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); - } - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x26: /* srl */ - if (IS_IMM) { /* immediate */ - simm =3D GET_FIELDs(insn, 20, 31); - tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f= ); - } else { /* register */ - cpu_tmp0 =3D tcg_temp_new(); - tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); - tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); - } - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x27: /* sra */ - if (IS_IMM) { /* immediate */ - simm =3D GET_FIELDs(insn, 20, 31); - tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f= ); - } else { /* register */ - cpu_tmp0 =3D tcg_temp_new(); - tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); - tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); - } - gen_store_gpr(dc, rd, cpu_dst); - break; -#endif + goto illegal_insn; /* in decodetree */ case 0x30: goto illegal_insn; /* WRASR in decodetree */ case 0x32: --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280037; cv=none; d=zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279583; x=1698884383; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=liEvRl/jRK+MVWBVMKhq34S1ClVtdANFLOiARj777ck=; b=ecVImq/GEllIv6JWm6jsYmAB8WmtADpsUUrA0k3e8zBHzya9QzH3Qpl+pMFC+i6iKO wE1rLtierjbZCXJ8+WvNWcq6m3acCcNj3fs3wB9eAqMuJNeUQYHrcPu5MlNil58G1lv7 E8agpjZOVz71IXh9m1V6X8+ec5m6bIwydDPAv68Jn0ys96I0gv2Ut9gU1NQcFxkr0/00 B6j0xQtTVhVANPqd9QNcsPrCKefR86lJLMHaz2RJFvMVr9Ji4ZLf/yqTntY3O9SqidEB XN93AvF03VLt6TZjkx/hXkgptLAZ7XKsuPuIL3mGIj85pSTqd6gUs7NCIucpPuwrUsCO 8vCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279583; x=1698884383; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=liEvRl/jRK+MVWBVMKhq34S1ClVtdANFLOiARj777ck=; b=nvucWjm2HGMyCtbdnF8fima0ghYDHB8jk446yjNSPWEt/Dmnmhad3m0iENJkljG31o kh1NF9QbFvsiwqWzOOiYKH6QZWu5FesKapCteXJtbXwiBYHUvnzJdCAhbQcy5oCkxHZw W6d0mjTISw3ew5LsXETuqOPuRkKAuLqcRmsxurst3DH8bARZ3k7iYTnwYxumUqa99gD3 fGNv/A1IrpsM4wyfz3U/bUeOwRjcd59BGHiYeBuQvqrkwmajUxF6KZ87jqJ7mw9QYrJf /e6YzvcGbFmzox5FIaueMwEKJY99PC+WsYXT6YDMXKcWOMVVa8edAmjS3JxJKq6Ycwmm 0c+w== X-Gm-Message-State: AOJu0Yw1dY4zdjxeFBq0vIhx+dSDk+qlU0LnkyrZoo0ubDV3wfV9CLp1 toe6nYgC5Ti66VzMmjJyRzwg7Kt/E/YXOiwnPXI= X-Google-Smtp-Source: AGHT+IGRCGmi6Rk+Qi71KMpUidBXzhwShprD/pWonutSdTQfxYobx4/3VJXImBDJIIo6T8SALjhIwQ== X-Received: by 2002:a17:902:e88f:b0:1bc:2abb:4e98 with SMTP id w15-20020a170902e88f00b001bc2abb4e98mr15631700plg.21.1698279583047; Wed, 25 Oct 2023 17:19:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 42/94] target/sparc: Move MOVcc, MOVR to decodetree Date: Wed, 25 Oct 2023 17:14:50 -0700 Message-Id: <20231026001542.1141412-72-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280039295100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++ target/sparc/translate.c | 116 ++++++++++++++++++++------------------ 2 files changed, 64 insertions(+), 56 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 51cddc826d..cb21405e1a 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -209,3 +209,7 @@ Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2= :5 # Bits [10:8] are reserved and the OSA2011 manual says they must be 0. Tcc_i_v9 10 0 cond:4 111010 rs1:5 1 cc:1 0 000 i:8 } + +MOVcc 10 rd:5 101100 1 cond:4 imm:1 cc:1 0 rs2_or_imm:s11 +MOVfcc 10 rd:5 101100 0 cond:4 imm:1 cc:2 rs2_or_imm:s11 +MOVR 10 rd:5 101111 rs1:5 imm:1 cond:3 rs2_or_imm:s10 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ac8cd40aa1..10b2d1b578 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4324,6 +4324,64 @@ TRANS(SLL_i, ALL, do_shift_i, a, true, true) TRANS(SRL_i, ALL, do_shift_i, a, false, true) TRANS(SRA_i, ALL, do_shift_i, a, false, false) =20 +static TCGv gen_rs2_or_imm(DisasContext *dc, bool imm, int rs2_or_imm) +{ + /* For simplicity, we under-decoded the rs2 form. */ + if (!imm && rs2_or_imm & ~0x1f) { + return NULL; + } + if (imm || rs2_or_imm =3D=3D 0) { + return tcg_constant_tl(rs2_or_imm); + } else { + return cpu_regs[rs2_or_imm]; + } +} + +static bool do_mov_cond(DisasContext *dc, DisasCompare *cmp, int rd, TCGv = src2) +{ + TCGv dst =3D gen_load_gpr(dc, rd); + + tcg_gen_movcond_tl(cmp->cond, dst, cmp->c1, cmp->c2, src2, dst); + gen_store_gpr(dc, rd, dst); + return advance_pc(dc); +} + +static bool trans_MOVcc(DisasContext *dc, arg_MOVcc *a) +{ + TCGv src2 =3D gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm); + DisasCompare cmp; + + if (src2 =3D=3D NULL) { + return false; + } + gen_compare(&cmp, a->cc, a->cond, dc); + return do_mov_cond(dc, &cmp, a->rd, src2); +} + +static bool trans_MOVfcc(DisasContext *dc, arg_MOVfcc *a) +{ + TCGv src2 =3D gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm); + DisasCompare cmp; + + if (src2 =3D=3D NULL) { + return false; + } + gen_fcompare(&cmp, a->cc, a->cond); + return do_mov_cond(dc, &cmp, a->rd, src2); +} + +static bool trans_MOVR(DisasContext *dc, arg_MOVR *a) +{ + TCGv src2 =3D gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm); + DisasCompare cmp; + + if (src2 =3D=3D NULL) { + return false; + } + gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1)); + return do_mov_cond(dc, &cmp, a->rd, src2); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4696,66 +4754,12 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) goto illegal_insn; /* WRTBR, WRHPR in decodetree = */ #ifdef TARGET_SPARC64 case 0x2c: /* V9 movcc */ - { - int cc =3D GET_FIELD_SP(insn, 11, 12); - int cond =3D GET_FIELD_SP(insn, 14, 17); - DisasCompare cmp; - TCGv dst; - - if (insn & (1 << 18)) { - if (cc =3D=3D 0) { - gen_compare(&cmp, 0, cond, dc); - } else if (cc =3D=3D 2) { - gen_compare(&cmp, 1, cond, dc); - } else { - goto illegal_insn; - } - } else { - gen_fcompare(&cmp, cc, cond); - } - - /* The get_src2 above loaded the normal 13-bit - immediate field, not the 11-bit field we ha= ve - in movcc. But it did handle the reg case. = */ - if (IS_IMM) { - simm =3D GET_FIELD_SPs(insn, 0, 10); - tcg_gen_movi_tl(cpu_src2, simm); - } - - dst =3D gen_load_gpr(dc, rd); - tcg_gen_movcond_tl(cmp.cond, dst, - cmp.c1, cmp.c2, - cpu_src2, dst); - gen_store_gpr(dc, rd, dst); - break; - } + case 0x2f: /* V9 movr */ + goto illegal_insn; /* in decodetree */ case 0x2e: /* V9 popc */ tcg_gen_ctpop_tl(cpu_dst, cpu_src2); gen_store_gpr(dc, rd, cpu_dst); break; - case 0x2f: /* V9 movr */ - { - int cond =3D GET_FIELD_SP(insn, 10, 12); - DisasCompare cmp; - TCGv dst; - - gen_compare_reg(&cmp, cond, cpu_src1); - - /* The get_src2 above loaded the normal 13-bit - immediate field, not the 10-bit field we ha= ve - in movr. But it did handle the reg case. = */ - if (IS_IMM) { - simm =3D GET_FIELD_SPs(insn, 0, 9); - tcg_gen_movi_tl(cpu_src2, simm); - } - - dst =3D gen_load_gpr(dc, rd); - tcg_gen_movcond_tl(cmp.cond, dst, - cmp.c1, cmp.c2, - cpu_src2, dst); - gen_store_gpr(dc, rd, dst); - break; - } #endif default: goto illegal_insn; --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279902; cv=none; d=zohomail.com; s=zohoarc; b=G9HVmtglJDDHlUBhSKVZ6FSGNBj4sxm4E6bXvIxd4ekTph2CPMficfsuZ8wvMCQ9GxoLnz6/sAsAn4q2+0p/QpOI81e1VRW09Leu42rAgDiBDoNITT0hLJo5uWRw9mETiDFIkdPJt4JHOLgF7QyCpfLuhMhQ0ZDsmU17/Qlogpk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279902; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=UaLDZUlxbnEBMWQWA0yY43XdPUXdultOeDE7cUVCPGo=; b=NbCpZSU3PMAYpmr1J923WdQhlbwmUVX9xu/6IpR7PrmoAlgK48cFW0JxvpVLGbdhmh+UXGdi5uOpsKknXzTfGj3gJk4G0wwYl/LBwGkbL5VoE5piDOo0xweTZIVtEcRzeuFNt9KfSWI1ttSFtmnuo2oaP/MiKFsP/nQKOIaRWRE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698279902326529.9744058205129; Wed, 25 Oct 2023 17:25:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo6e-00025s-4W; Wed, 25 Oct 2023 20:20:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo6K-0001Mz-0y for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:52 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo6E-0006sc-2b for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:51 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1c9e06f058bso11227355ad.0 for ; Wed, 25 Oct 2023 17:19:44 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279902847100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 56 +++++++-------------------------------- 2 files changed, 12 insertions(+), 47 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index cb21405e1a..a596b0fc85 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -183,6 +183,9 @@ TSUBcc 10 ..... 100001 ..... . ............. = @r_r_ri_cc1 TADDccTV 10 ..... 100010 ..... . ............. @r_r_ri_cc1 TSUBccTV 10 ..... 100011 ..... . ............. @r_r_ri_cc1 =20 +POPC 10 rd:5 101110 00000 imm:1 rs2_or_imm:s13 \ + &r_r_ri_cc rs1=3D0 cc=3D0 + &shiftr rd rs1 rs2 x:bool @shiftr .. rd:5 ...... rs1:5 . x:1 ....... rs2:5 &shiftr =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 10b2d1b578..9122f82844 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -740,6 +740,11 @@ static void gen_op_tsubcctv(TCGv dst, TCGv src1, TCGv = src2) gen_helper_tsubcctv(dst, tcg_env, src1, src2); } =20 +static void gen_op_popc(TCGv dst, TCGv src1, TCGv src2) +{ + tcg_gen_ctpop_tl(dst, src2); +} + // 1 static void gen_op_eval_ba(TCGv dst) { @@ -2733,19 +2738,6 @@ static TCGv get_src1(DisasContext *dc, unsigned int = insn) return gen_load_gpr(dc, rs1); } =20 -static TCGv get_src2(DisasContext *dc, unsigned int insn) -{ - if (IS_IMM) { /* immediate */ - target_long simm =3D GET_FIELDs(insn, 19, 31); - TCGv t =3D tcg_temp_new(); - tcg_gen_movi_tl(t, simm); - return t; - } else { /* register */ - unsigned int rs2 =3D GET_FIELD(insn, 27, 31); - return gen_load_gpr(dc, rs2); - } -} - #ifdef TARGET_SPARC64 static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs) { @@ -4176,6 +4168,9 @@ TRANS(SDIVX, 64, do_arith, a, -1, gen_op_sdivx, NULL,= NULL) TRANS(UDIV, DIV, do_arith, a, CC_OP_DIV, gen_op_udiv, NULL, gen_op_udivcc) TRANS(SDIV, DIV, do_arith, a, CC_OP_DIV, gen_op_sdiv, NULL, gen_op_sdivcc) =20 +/* TODO: Should have feature bit -- comes in with UltraSparc T2. */ +TRANS(POPC, 64, do_arith, a, -1, gen_op_popc, NULL, NULL) + static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a) { /* OR with %g0 is the canonical alias for MOV. */ @@ -4731,40 +4726,7 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) goto illegal_insn; } } else if (xop < 0x36) { - if (xop < 0x20) { - goto illegal_insn; - } else { - cpu_src1 =3D get_src1(dc, insn); - cpu_src2 =3D get_src2(dc, insn); - switch (xop) { - case 0x20: /* taddcc */ - case 0x21: /* tsubcc */ - case 0x22: /* taddcctv */ - case 0x23: /* tsubcctv */ - case 0x24: /* mulscc */ - case 0x25: /* sll */ - case 0x26: /* srl */ - case 0x27: /* sra */ - goto illegal_insn; /* in decodetree */ - case 0x30: - goto illegal_insn; /* WRASR in decodetree */ - case 0x32: - goto illegal_insn; /* WRPR in decodetree */ - case 0x33: /* wrtbr, UA2005 wrhpr */ - goto illegal_insn; /* WRTBR, WRHPR in decodetree = */ -#ifdef TARGET_SPARC64 - case 0x2c: /* V9 movcc */ - case 0x2f: /* V9 movr */ - goto illegal_insn; /* in decodetree */ - case 0x2e: /* V9 popc */ - tcg_gen_ctpop_tl(cpu_dst, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - break; -#endif - default: - goto illegal_insn; - } - } + goto illegal_insn; /* in decodetree */ } else if (xop =3D=3D 0x36) { /* UltraSparc shutdown, VIS, V8 = CPop1 */ #ifdef TARGET_SPARC64 int opf =3D GET_FIELD_SP(insn, 5, 13); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280658; cv=none; d=zohomail.com; s=zohoarc; b=kbbQQPLSXJKxt4apFILT/+qRtTTiDr34IeHmvcvH/JHzwFuPERqL6SoYF8DBsk57ET67fJBGWLGas1KRY+2pNoCmR3WRzg3YrOdnK++C1Ozu9Np0Mgx65gPZetsfCN+iBLjgGm7e58H2BxdyRfhaCaBVqgQaAO9QWZJhh6aT5QU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280658; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=NTjsxTEB+wSbTivrTvElIlgrS7SAqTr5YpOJzPS1BFA=; b=DljVSIV77sRFrpOlvKE1boF9VN8nnWxLCJcQuu4vxr5BIthD9ml3FWVhC4bmEICgwEBmsYE2Kjf/oqh55PVfXrDf66WjLrwXn3kXuHP7wSbfumVh3JEBpIX4Or9SQU++8Ysqd1+SRybGuY6LH9Y+PkyisyNIKL/ievqMY0KA9TI= ARC-Authentication-Results: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280660127100002 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 11 +++++++++++ target/sparc/translate.c | 32 ++++++-------------------------- 2 files changed, 17 insertions(+), 26 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a596b0fc85..8de986f0bb 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -216,3 +216,14 @@ Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs= 2:5 MOVcc 10 rd:5 101100 1 cond:4 imm:1 cc:1 0 rs2_or_imm:s11 MOVfcc 10 rd:5 101100 0 cond:4 imm:1 cc:2 rs2_or_imm:s11 MOVR 10 rd:5 101111 rs1:5 imm:1 cond:3 rs2_or_imm:s10 + +NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 +NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 + +NCP 11 ----- 110000 ----- --------- ----- # v8 LDC +NCP 11 ----- 110001 ----- --------- ----- # v8 LDCSR +NCP 11 ----- 110011 ----- --------- ----- # v8 LDDC +NCP 11 ----- 110100 ----- --------- ----- # v8 STC +NCP 11 ----- 110101 ----- --------- ----- # v8 STCSR +NCP 11 ----- 110110 ----- --------- ----- # v8 STDCQ +NCP 11 ----- 110111 ----- --------- ----- # v8 STDC diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 9122f82844..7cd1af1014 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4727,8 +4727,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) } } else if (xop < 0x36) { goto illegal_insn; /* in decodetree */ - } else if (xop =3D=3D 0x36) { /* UltraSparc shutdown, VIS, V8 = CPop1 */ + } else if (xop =3D=3D 0x36) { #ifdef TARGET_SPARC64 + /* VIS */ int opf =3D GET_FIELD_SP(insn, 5, 13); rs1 =3D GET_FIELD(insn, 13, 17); rs2 =3D GET_FIELD(insn, 27, 31); @@ -5168,14 +5169,11 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) goto illegal_insn; } #else - goto ncp_insn; -#endif - } else if (xop =3D=3D 0x37) { /* V8 CPop2, V9 impdep2 */ -#ifdef TARGET_SPARC64 - goto illegal_insn; -#else - goto ncp_insn; + g_assert_not_reached(); /* in decodetree */ #endif + } else if (xop =3D=3D 0x37) { + /* V8 CPop2, V9 impdep2 */ + goto illegal_insn; /* in decodetree */ #ifdef TARGET_SPARC64 } else if (xop =3D=3D 0x39) { /* V9 return */ save_state(dc); @@ -5391,13 +5389,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) cpu_src1 =3D gen_load_gpr(dc, rd); gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn); break; - -#ifndef TARGET_SPARC64 - case 0x30: /* ldc */ - case 0x31: /* ldcsr */ - case 0x33: /* lddc */ - goto ncp_insn; -#endif #endif #ifdef TARGET_SPARC64 case 0x08: /* V9 ldsw */ @@ -5658,12 +5649,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) cpu_src2 =3D gen_load_gpr(dc, rs2); gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd); break; -#else - case 0x34: /* stc */ - case 0x35: /* stcsr */ - case 0x36: /* stdcq */ - case 0x37: /* stdc */ - goto ncp_insn; #endif #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x3c: /* V9 or LEON3 casa */ @@ -5703,11 +5688,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR); return; #endif -#ifndef TARGET_SPARC64 - ncp_insn: - gen_exception(dc, TT_NCP_INSN); - return; -#endif } =20 static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279585; x=1698884385; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ohRPCpHejAizc95/5iNRUGKyBYgA+JY/mkKKy87OBpc=; b=vGmSKpy9zh6ZrrOoUOI0GX1d4PnYcXjqLQBxykTwEFT1TEAvSJTtCCJzFYcPS66T0F yOAv0Daoh7ZDRUCdo5qmQNJI7pjFJwvyxCKEhmC3KGEG8miPiyASiMB+r8rvZiezxSkh vNQn2/fDCppsfKXaig+gK/IaKFAWsiqFSAUeMFTcKSPF8qPexcApwjAnsFGEEvU+C+H6 uAvmd9c3Gm7AHTXIT74n5PGSYk5UdFYRmB2etnLGZTTq64rBgdwb6zdSIILWwct6w3/1 4hmtJ5fzBqMavWv+6la8xcTuMfSlCZuVVR3pBocXtCD7Owdiw3owS71yUuSZFqRiQkcG 58hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279585; x=1698884385; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279750302100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 7 +++ target/sparc/translate.c | 126 ++++++++++++++++++++++++-------------- 2 files changed, 88 insertions(+), 45 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 8de986f0bb..271789ac13 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -28,6 +28,7 @@ CALL 01 i:s30 =20 &r_r_ri rd rs1 rs2_or_imm imm:bool @n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=3D0 +@r_r_ri .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri =20 &r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool @r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc @@ -217,6 +218,12 @@ MOVcc 10 rd:5 101100 1 cond:4 imm:1 cc:1 0 rs2_= or_imm:s11 MOVfcc 10 rd:5 101100 0 cond:4 imm:1 cc:2 rs2_or_imm:s11 MOVR 10 rd:5 101111 rs1:5 imm:1 cond:3 rs2_or_imm:s10 =20 +JMPL 10 ..... 111000 ..... . ............. @r_r_ri +{ + RETT 10 00000 111001 ..... . ............. @n_r_ri + RETURN 10 00000 111001 ..... . ............. @n_r_ri +} + NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 7cd1af1014..91de0b1206 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -38,6 +38,7 @@ =20 #ifdef TARGET_SPARC64 # define gen_helper_rdpsr(D, E) qemu_build_not_reached() +# define gen_helper_rett(E) qemu_build_not_reached() # define gen_helper_power_down(E) qemu_build_not_reached() # define gen_helper_wrpsr(E, S) qemu_build_not_reached() #else @@ -4377,6 +4378,85 @@ static bool trans_MOVR(DisasContext *dc, arg_MOVR *a) return do_mov_cond(dc, &cmp, a->rd, src2); } =20 +static bool do_add_special(DisasContext *dc, arg_r_r_ri *a, + bool (*func)(DisasContext *dc, int rd, TCGv src= )) +{ + TCGv src1, sum; + + /* For simplicity, we under-decoded the rs2 form. */ + if (!a->imm && a->rs2_or_imm & ~0x1f) { + return false; + } + + /* + * Always load the sum into a new temporary. + * This is required to capture the value across a window change, + * e.g. SAVE and RESTORE, and may be optimized away otherwise. + */ + sum =3D tcg_temp_new(); + src1 =3D gen_load_gpr(dc, a->rs1); + if (a->imm || a->rs2_or_imm =3D=3D 0) { + tcg_gen_addi_tl(sum, src1, a->rs2_or_imm); + } else { + tcg_gen_add_tl(sum, src1, cpu_regs[a->rs2_or_imm]); + } + return func(dc, a->rd, sum); +} + +static bool do_jmpl(DisasContext *dc, int rd, TCGv src) +{ + /* + * Preserve pc across advance, so that we can delay + * the writeback to rd until after src is consumed. + */ + target_ulong cur_pc =3D dc->pc; + + gen_check_align(dc, src, 3); + + gen_mov_pc_npc(dc); + tcg_gen_mov_tl(cpu_npc, src); + gen_address_mask(dc, cpu_npc); + gen_store_gpr(dc, rd, tcg_constant_tl(cur_pc)); + + dc->npc =3D DYNAMIC_PC_LOOKUP; + return true; +} + +TRANS(JMPL, ALL, do_add_special, a, do_jmpl) + +static bool do_rett(DisasContext *dc, int rd, TCGv src) +{ + if (!supervisor(dc)) { + return raise_priv(dc); + } + + gen_check_align(dc, src, 3); + + gen_mov_pc_npc(dc); + tcg_gen_mov_tl(cpu_npc, src); + gen_helper_rett(tcg_env); + + dc->npc =3D DYNAMIC_PC; + return true; +} + +TRANS(RETT, 32, do_add_special, a, do_rett) + +static bool do_return(DisasContext *dc, int rd, TCGv src) +{ + gen_check_align(dc, src, 3); + + gen_mov_pc_npc(dc); + tcg_gen_mov_tl(cpu_npc, src); + gen_address_mask(dc, cpu_npc); + + gen_helper_restore(tcg_env); + dc->npc =3D DYNAMIC_PC_LOOKUP; + return true; +} + +TRANS(RETURN, 64, do_add_special, a, do_return) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5174,30 +5254,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) } else if (xop =3D=3D 0x37) { /* V8 CPop2, V9 impdep2 */ goto illegal_insn; /* in decodetree */ -#ifdef TARGET_SPARC64 - } else if (xop =3D=3D 0x39) { /* V9 return */ - save_state(dc); - cpu_src1 =3D get_src1(dc, insn); - cpu_tmp0 =3D tcg_temp_new(); - if (IS_IMM) { /* immediate */ - simm =3D GET_FIELDs(insn, 19, 31); - tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm); - } else { /* register */ - rs2 =3D GET_FIELD(insn, 27, 31); - if (rs2) { - cpu_src2 =3D gen_load_gpr(dc, rs2); - tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2); - } else { - tcg_gen_mov_tl(cpu_tmp0, cpu_src1); - } - } - gen_check_align(dc, cpu_tmp0, 3); - gen_helper_restore(tcg_env); - gen_mov_pc_npc(dc); - tcg_gen_mov_tl(cpu_npc, cpu_tmp0); - dc->npc =3D DYNAMIC_PC_LOOKUP; - goto jmp_insn; -#endif } else { cpu_src1 =3D get_src1(dc, insn); cpu_tmp0 =3D tcg_temp_new(); @@ -5215,28 +5271,8 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) } switch (xop) { case 0x38: /* jmpl */ - { - gen_check_align(dc, cpu_tmp0, 3); - gen_store_gpr(dc, rd, tcg_constant_tl(dc->pc)); - gen_mov_pc_npc(dc); - gen_address_mask(dc, cpu_tmp0); - tcg_gen_mov_tl(cpu_npc, cpu_tmp0); - dc->npc =3D DYNAMIC_PC_LOOKUP; - } - goto jmp_insn; -#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) case 0x39: /* rett, V9 return */ - { - if (!supervisor(dc)) - goto priv_insn; - gen_check_align(dc, cpu_tmp0, 3); - gen_mov_pc_npc(dc); - tcg_gen_mov_tl(cpu_npc, cpu_tmp0); - dc->npc =3D DYNAMIC_PC; - gen_helper_rett(tcg_env); - } - goto jmp_insn; -#endif + g_assert_not_reached(); /* in decode tree */ case 0x3b: /* flush */ /* nop */ break; --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280403; cv=none; d=zohomail.com; s=zohoarc; b=VQoAXpZyTP6BX7suwvykoEk3c9n6CHAxeC7LDOTj2zVd651KB6P79TuYSyLcVA0RY5ZzDDz6vfjJKQF1GhBMVYZWq3XwstZW9krAi2i8eMopGTHiczVj0LWqwjWV8iQiA+Jf+UEfL7n3r02hUM8O7NbsL4AsHI4uR/U+Dnhp3q8= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280405341100002 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++++ target/sparc/translate.c | 35 +++++++++++++++++++++++++---------- 2 files changed, 29 insertions(+), 10 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 271789ac13..aa90b5c5bb 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -223,6 +223,10 @@ JMPL 10 ..... 111000 ..... . ............. = @r_r_ri RETT 10 00000 111001 ..... . ............. @n_r_ri RETURN 10 00000 111001 ..... . ............. @n_r_ri } +NOP 10 00000 111011 ----- 0 00000000----- # FLUSH reg+reg +NOP 10 00000 111011 ----- 1 ------------- # FLUSH reg+imm +SAVE 10 ..... 111100 ..... . ............. @r_r_ri +RESTORE 10 ..... 111101 ..... . ............. @r_r_ri =20 NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 91de0b1206..e0a13e5d29 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4077,6 +4077,11 @@ static bool do_saved_restored(DisasContext *dc, bool= saved) TRANS(SAVED, 64, do_saved_restored, true) TRANS(RESTORED, 64, do_saved_restored, false) =20 +static bool trans_NOP(DisasContext *dc, arg_NOP *a) +{ + return advance_pc(dc); +} + static bool trans_NOP_v7(DisasContext *dc, arg_NOP_v7 *a) { /* @@ -4457,6 +4462,24 @@ static bool do_return(DisasContext *dc, int rd, TCGv= src) =20 TRANS(RETURN, 64, do_add_special, a, do_return) =20 +static bool do_save(DisasContext *dc, int rd, TCGv src) +{ + gen_helper_save(tcg_env); + gen_store_gpr(dc, rd, src); + return advance_pc(dc); +} + +TRANS(SAVE, ALL, do_add_special, a, do_save) + +static bool do_restore(DisasContext *dc, int rd, TCGv src) +{ + gen_helper_restore(tcg_env); + gen_store_gpr(dc, rd, src); + return advance_pc(dc); +} + +TRANS(RESTORE, ALL, do_add_special, a, do_restore) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5272,18 +5295,10 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) switch (xop) { case 0x38: /* jmpl */ case 0x39: /* rett, V9 return */ - g_assert_not_reached(); /* in decode tree */ - case 0x3b: /* flush */ - /* nop */ - break; + case 0x3b: /* flush */ case 0x3c: /* save */ - gen_helper_save(tcg_env); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280322094100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 ++ target/sparc/translate.c | 88 ++++++++++++--------------------------- 2 files changed, 29 insertions(+), 62 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index aa90b5c5bb..137b7eb3c6 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -228,6 +228,9 @@ NOP 10 00000 111011 ----- 1 ------------- = # FLUSH reg+imm SAVE 10 ..... 111100 ..... . ............. @r_r_ri RESTORE 10 ..... 111101 ..... . ............. @r_r_ri =20 +DONE 10 00000 111110 00000 0 0000000000000 +RETRY 10 00001 111110 00000 0 0000000000000 + NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index e0a13e5d29..8faf2c59b2 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -43,10 +43,12 @@ # define gen_helper_wrpsr(E, S) qemu_build_not_reached() #else # define gen_helper_clear_softint(E, S) qemu_build_not_reached() +# define gen_helper_done(E) qemu_build_not_reached() # define gen_helper_flushw(E) qemu_build_not_reached() # define gen_helper_rdccr(D, E) qemu_build_not_reached() # define gen_helper_rdcwp(D, E) qemu_build_not_reached() # define gen_helper_restored(E) qemu_build_not_reached() +# define gen_helper_retry(E) qemu_build_not_reached() # define gen_helper_saved(E) qemu_build_not_reached() # define gen_helper_sdivx(D, E, A, B) qemu_build_not_reached() # define gen_helper_set_softint(E, S) qemu_build_not_reached() @@ -4480,6 +4482,25 @@ static bool do_restore(DisasContext *dc, int rd, TCG= v src) =20 TRANS(RESTORE, ALL, do_add_special, a, do_restore) =20 +static bool do_done_retry(DisasContext *dc, bool done) +{ + if (!supervisor(dc)) { + return raise_priv(dc); + } + dc->npc =3D DYNAMIC_PC; + dc->pc =3D DYNAMIC_PC; + translator_io_start(&dc->base); + if (done) { + gen_helper_done(tcg_env); + } else { + gen_helper_retry(tcg_env); + } + return true; +} + +TRANS(DONE, 64, do_done_retry, true) +TRANS(RETRY, 64, do_done_retry, false) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4491,7 +4512,8 @@ TRANS(RESTORE, ALL, do_add_special, a, do_restore) static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) { unsigned int opc, rs1, rs2, rd; - TCGv cpu_src1, cpu_src2; + TCGv cpu_src1; + TCGv cpu_src2 __attribute__((unused)); TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32; TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64; target_long simm; @@ -4506,9 +4528,8 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) g_assert_not_reached(); /* in decodetree */ case 2: /* FPU & Logical Operations */ { - unsigned int xop __attribute__((unused)) =3D GET_FIELD(insn, 7= , 12); + unsigned int xop =3D GET_FIELD(insn, 7, 12); TCGv cpu_dst __attribute__((unused)) =3D tcg_temp_new(); - TCGv cpu_tmp0 __attribute__((unused)); =20 if (xop =3D=3D 0x34) { /* FPU Operations */ if (gen_trap_ifnofpu(dc)) { @@ -4828,8 +4849,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) default: goto illegal_insn; } - } else if (xop < 0x36) { - goto illegal_insn; /* in decodetree */ } else if (xop =3D=3D 0x36) { #ifdef TARGET_SPARC64 /* VIS */ @@ -5271,65 +5290,10 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) default: goto illegal_insn; } -#else - g_assert_not_reached(); /* in decodetree */ #endif - } else if (xop =3D=3D 0x37) { - /* V8 CPop2, V9 impdep2 */ - goto illegal_insn; /* in decodetree */ } else { - cpu_src1 =3D get_src1(dc, insn); - cpu_tmp0 =3D tcg_temp_new(); - if (IS_IMM) { /* immediate */ - simm =3D GET_FIELDs(insn, 19, 31); - tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm); - } else { /* register */ - rs2 =3D GET_FIELD(insn, 27, 31); - if (rs2) { - cpu_src2 =3D gen_load_gpr(dc, rs2); - tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2); - } else { - tcg_gen_mov_tl(cpu_tmp0, cpu_src1); - } - } - switch (xop) { - case 0x38: /* jmpl */ - case 0x39: /* rett, V9 return */ - case 0x3b: /* flush */ - case 0x3c: /* save */ - case 0x3d: /* restore */ - g_assert_not_reached(); /* in decode tree */ -#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) - case 0x3e: /* V9 done/retry */ - { - switch (rd) { - case 0: - if (!supervisor(dc)) - goto priv_insn; - dc->npc =3D DYNAMIC_PC; - dc->pc =3D DYNAMIC_PC; - translator_io_start(&dc->base); - gen_helper_done(tcg_env); - goto jmp_insn; - case 1: - if (!supervisor(dc)) - goto priv_insn; - dc->npc =3D DYNAMIC_PC; - dc->pc =3D DYNAMIC_PC; - translator_io_start(&dc->base); - gen_helper_retry(tcg_env); - goto jmp_insn; - default: - goto illegal_insn; - } - } - break; -#endif - default: - goto illegal_insn; - } + goto illegal_insn; /* in decodetree */ } - break; } break; case 3: /* load/store instructions */ @@ -5726,7 +5690,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) illegal_insn: gen_exception(dc, TT_ILL_INSN); return; -#if !defined(CONFIG_USER_ONLY) +#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) priv_insn: gen_exception(dc, TT_PRIV_INSN); return; --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280697; cv=none; d=zohomail.com; s=zohoarc; b=LHChdfdQvGrQE/46CQsvv5fnY8G9CLmaaijpLzXWwpCF8kUdC4jRs+QhUB0bouDZfE9p4ziwpT3VbujiouTeazlaYHsFIzVjxGSDm7aLV9uS4XPiMefZJGsGsG3u9CtL5Khj3Vo62ZG24QcrPtZDF2D1a7vUjgWsmVizDMnrYI0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280697; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280698357100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 8faf2c59b2..6c1610486e 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1919,15 +1919,25 @@ typedef struct { MemOp memop; } DisasASI; =20 -static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop) +/* + * Build DisasASI. + * For asi =3D=3D -1, treat as non-asi. + * For ask =3D=3D -2, treat as immediate offset (v8 error, v9 %asi). + */ +static DisasASI resolve_asi(DisasContext *dc, int asi, MemOp memop) { - int asi =3D GET_FIELD(insn, 19, 26); ASIType type =3D GET_ASI_HELPER; int mem_idx =3D dc->mem_idx; =20 + if (asi =3D=3D -1) { + /* Artificial "non-asi" case. */ + type =3D GET_ASI_DIRECT; + goto done; + } + #ifndef TARGET_SPARC64 /* Before v9, all asis are immediate and privileged. */ - if (IS_IMM) { + if (asi < 0) { gen_exception(dc, TT_ILL_INSN); type =3D GET_ASI_EXCP; } else if (supervisor(dc) @@ -1970,7 +1980,7 @@ static DisasASI get_asi(DisasContext *dc, int insn, M= emOp memop) type =3D GET_ASI_EXCP; } #else - if (IS_IMM) { + if (asi < 0) { asi =3D dc->asi; } /* With v9, all asis below 0x80 are privileged. */ @@ -2129,9 +2139,16 @@ static DisasASI get_asi(DisasContext *dc, int insn, = MemOp memop) } #endif =20 + done: return (DisasASI){ type, asi, mem_idx, memop }; } =20 +static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop) +{ + int asi =3D IS_IMM ? -2 : GET_FIELD(insn, 19, 26); + return resolve_asi(dc, asi, memop); +} + static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop) { --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280796; cv=none; d=zohomail.com; s=zohoarc; b=ZpWdN6NUzMTblZPqkN3fY8btO8CCPEb1hEjrqWLdK9UFOPIyFfQryRzqK1zLht3aLOuGpJyGwc2ilOABB3fhmLE2hGiS8c+wS5ZDFk5Wod5Fu8h0Ao+jb+2azjXS5errAJarH/XhYsbzMRJ/Ffp+ZZ61yOYM9nrvbm5hPGe8CtI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280796; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279588; x=1698884388; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eZLc1NKbNfziRuoiZu6Ior80vSayHdq/c4RE66LCIXM=; b=twVIQHdu4KUpK/rBt/EN13Hwb0tDQbEZA6bfLbtpfZX1ljQuMdg7vGHX2CnvuHP/n/ mr1751dWtl8LATNNxcRE9XQ4U73JWNi4DmMZHpOv8DUe/f4I2vMSDoNJvI5zR0MDkGpa mTKGC0cBjKs4MVphKYF3yXl6uyRfJkHwpLQORiKAHmGCkK1OJCyYP2RRlkhGpuUF52yF 8+DJdv2ZjvzgACZ9y/PfSkEOFic+dlc6z0d/nRmO+T2kj+vlCw1r2RgtUCRjZK8h+ReZ jBj8wpJ4zXMeir5S+tuv77rR6m+9yHKflbA3xiqmw4bMPiFxY3zXrBbT+6uvxgcaCq8O xP7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279588; x=1698884388; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eZLc1NKbNfziRuoiZu6Ior80vSayHdq/c4RE66LCIXM=; b=RReWFYa7x6evE8hdwoWXC/owGOzDA6R490/Tzjqiv10aV+G4vsfL4IOyV9yHn6tA65 SrYSECydxY5gA2lTQkM2Zo6DRnIyIHyaII9thkzZDaOhoubz3E/yWxoAq4CXOYPqDG8W NvRThrBK/nUR9zjuqiXUkrVAaSZZUl3F3r4cW3hdcu3TI8DHh9Lon3Vz7aPljpmLK+n+ M05wfv29sb0S5BVvHxCoFgh8DIbJovFZdUNYtK8ZYj1OEYBtFytpHzPwCx0AjpbB/AG3 PWyeUi78Vz0ApbR1LezfI2BgVknn1B9rC6eU76dLk7otmxt5q39arVfxVkSAxSBifxQ/ DXOw== X-Gm-Message-State: AOJu0YyOQereVwwa70OLVqHNkU50NdZB4tBT2eXkvqX0b809RiRJsogq 1/JPB5+0Vi+ITkFkBuUl+l8lgxcVZge7qRckBBY= X-Google-Smtp-Source: AGHT+IEp4LjWNNum+eCCYja+sNrARWWuFwZI3f5elHbJNDcf/WlL+nUwpBzOxWArz3sJNLgTJ4ZS6g== X-Received: by 2002:a17:902:c653:b0:1c7:495c:87e0 with SMTP id s19-20020a170902c65300b001c7495c87e0mr14634746pls.37.1698279588397; Wed, 25 Oct 2023 17:19:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 49/94] target/sparc: Drop ifdef around get_asi and friends Date: Wed, 25 Oct 2023 17:14:57 -0700 Message-Id: <20231026001542.1141412-79-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280798586100005 Content-Type: text/plain; charset="utf-8" Mark some of the functions as unused, temporarily. Fix up some tl vs i64 issues revealed in the process. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 189 +++++++++++++++------------------------ 1 file changed, 72 insertions(+), 117 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 6c1610486e..09b01ccf77 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1900,7 +1900,6 @@ static void gen_ldstub(DisasContext *dc, TCGv dst, TC= Gv addr, int mmu_idx) } =20 /* asi moves */ -#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) typedef enum { GET_ASI_HELPER, GET_ASI_EXCP, @@ -2149,8 +2148,22 @@ static DisasASI get_asi(DisasContext *dc, int insn, = MemOp memop) return resolve_asi(dc, asi, memop); } =20 -static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, - int insn, MemOp memop) +#if defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) +static void gen_helper_ld_asi(TCGv_i64 r, TCGv_env e, TCGv a, + TCGv_i32 asi, TCGv_i32 mop) +{ + g_assert_not_reached(); +} + +static void gen_helper_st_asi(TCGv_env e, TCGv a, TCGv_i64 r, + TCGv_i32 asi, TCGv_i32 mop) +{ + g_assert_not_reached(); +} +#endif + +static void __attribute__((unused)) +gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop) { DisasASI da =3D get_asi(dc, insn, memop); =20 @@ -2184,8 +2197,8 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TC= Gv addr, } } =20 -static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, - int insn, MemOp memop) +static void __attribute__((unused)) +gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop) { DisasASI da =3D get_asi(dc, insn, memop); =20 @@ -2260,8 +2273,8 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TC= Gv addr, } } =20 -static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, - TCGv addr, int insn) +static void __attribute__((unused)) +gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, TCGv addr, int insn) { DisasASI da =3D get_asi(dc, insn, MO_TEUL); =20 @@ -2278,8 +2291,8 @@ static void gen_swap_asi(DisasContext *dc, TCGv dst, = TCGv src, } } =20 -static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, - int insn, int rd) +static void __attribute__((unused)) +gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) { DisasASI da =3D get_asi(dc, insn, MO_TEUL); TCGv oldv; @@ -2300,7 +2313,8 @@ static void gen_cas_asi(DisasContext *dc, TCGv addr, = TCGv cmpv, } } =20 -static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) +static void __attribute__((unused)) +gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) { DisasASI da =3D get_asi(dc, insn, MO_UB); =20 @@ -2335,11 +2349,9 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv ds= t, TCGv addr, int insn) break; } } -#endif =20 -#ifdef TARGET_SPARC64 -static void gen_ldf_asi(DisasContext *dc, TCGv addr, - int insn, int size, int rd) +static void __attribute__((unused)) +gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) { DisasASI da =3D get_asi(dc, insn, (size =3D=3D 4 ? MO_TEUL : MO_TEUQ)); TCGv_i32 d32; @@ -2447,8 +2459,8 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, } } =20 -static void gen_stf_asi(DisasContext *dc, TCGv addr, - int insn, int size, int rd) +static void __attribute__((unused)) +gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) { DisasASI da =3D get_asi(dc, insn, (size =3D=3D 4 ? MO_TEUL : MO_TEUQ)); TCGv_i32 d32; @@ -2530,21 +2542,23 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr, } } =20 -static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) +static void __attribute__((unused)) +gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) { DisasASI da =3D get_asi(dc, insn, MO_TEUQ); - TCGv_i64 hi =3D gen_dest_gpr(dc, rd); - TCGv_i64 lo =3D gen_dest_gpr(dc, rd + 1); + TCGv hi =3D gen_dest_gpr(dc, rd); + TCGv lo =3D gen_dest_gpr(dc, rd + 1); =20 switch (da.type) { case GET_ASI_EXCP: return; =20 case GET_ASI_DTWINX: + assert(TARGET_LONG_BITS =3D=3D 64); gen_address_mask(dc, addr); - tcg_gen_qemu_ld_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); + tcg_gen_qemu_ld_tl(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_ld_i64(lo, addr, da.mem_idx, da.memop); + tcg_gen_qemu_ld_tl(lo, addr, da.mem_idx, da.memop); break; =20 case GET_ASI_DIRECT: @@ -2558,9 +2572,9 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr,= int insn, int rd) result is byte swapped. Having just performed one 64-bit bswap, we need now to swap the writebacks. */ if ((da.memop & MO_BSWAP) =3D=3D MO_TE) { - tcg_gen_extr32_i64(lo, hi, tmp); + tcg_gen_extr_i64_tl(lo, hi, tmp); } else { - tcg_gen_extr32_i64(hi, lo, tmp); + tcg_gen_extr_i64_tl(hi, lo, tmp); } } break; @@ -2580,9 +2594,9 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr,= int insn, int rd) =20 /* See above. */ if ((da.memop & MO_BSWAP) =3D=3D MO_TE) { - tcg_gen_extr32_i64(lo, hi, tmp); + tcg_gen_extr_i64_tl(lo, hi, tmp); } else { - tcg_gen_extr32_i64(hi, lo, tmp); + tcg_gen_extr_i64_tl(hi, lo, tmp); } } break; @@ -2592,8 +2606,8 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr,= int insn, int rd) gen_store_gpr(dc, rd + 1, lo); } =20 -static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, - int insn, int rd) +static void __attribute__((unused)) +gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd) { DisasASI da =3D get_asi(dc, insn, MO_TEUQ); TCGv lo =3D gen_load_gpr(dc, rd + 1); @@ -2603,10 +2617,11 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi,= TCGv addr, break; =20 case GET_ASI_DTWINX: + assert(TARGET_LONG_BITS =3D=3D 64); gen_address_mask(dc, addr); - tcg_gen_qemu_st_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); + tcg_gen_qemu_st_tl(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_st_i64(lo, addr, da.mem_idx, da.memop); + tcg_gen_qemu_st_tl(lo, addr, da.mem_idx, da.memop); break; =20 case GET_ASI_DIRECT: @@ -2617,15 +2632,37 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi,= TCGv addr, byte swapped. We will perform one 64-bit LE store, so now we must swap the order of the construction. */ if ((da.memop & MO_BSWAP) =3D=3D MO_TE) { - tcg_gen_concat32_i64(t64, lo, hi); + tcg_gen_concat_tl_i64(t64, lo, hi); } else { - tcg_gen_concat32_i64(t64, hi, lo); + tcg_gen_concat_tl_i64(t64, hi, lo); } gen_address_mask(dc, addr); tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN= ); } break; =20 + case GET_ASI_BFILL: + assert(TARGET_LONG_BITS =3D=3D 32); + /* Store 32 bytes of T64 to ADDR. */ + /* ??? The original qemu code suggests 8-byte alignment, dropping + the low bits, but the only place I can see this used is in the + Linux kernel with 32 byte alignment, which would make more sense + as a cacheline-style operation. */ + { + TCGv_i64 t64 =3D tcg_temp_new_i64(); + TCGv d_addr =3D tcg_temp_new(); + TCGv eight =3D tcg_constant_tl(8); + int i; + + tcg_gen_concat_tl_i64(t64, lo, hi); + tcg_gen_andi_tl(d_addr, addr, -8); + for (i =3D 0; i < 32; i +=3D 8) { + tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop); + tcg_gen_add_tl(d_addr, d_addr, eight); + } + } + break; + default: /* ??? In theory we've handled all of the ASIs that are valid for stda, and this should raise DAE_invalid_asi. */ @@ -2636,9 +2673,9 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, T= CGv addr, =20 /* See above. */ if ((da.memop & MO_BSWAP) =3D=3D MO_TE) { - tcg_gen_concat32_i64(t64, lo, hi); + tcg_gen_concat_tl_i64(t64, lo, hi); } else { - tcg_gen_concat32_i64(t64, hi, lo); + tcg_gen_concat_tl_i64(t64, hi, lo); } =20 save_state(dc); @@ -2648,8 +2685,8 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, T= CGv addr, } } =20 -static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, - int insn, int rd) +static void __attribute__((unused)) +gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) { DisasASI da =3D get_asi(dc, insn, MO_TEUQ); TCGv oldv; @@ -2670,88 +2707,6 @@ static void gen_casx_asi(DisasContext *dc, TCGv addr= , TCGv cmpv, } } =20 -#elif !defined(CONFIG_USER_ONLY) -static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) -{ - /* ??? Work around an apparent bug in Ubuntu gcc 4.8.2-10ubuntu2+12, - whereby "rd + 1" elicits "error: array subscript is above array". - Since we have already asserted that rd is even, the semantics - are unchanged. */ - TCGv lo =3D gen_dest_gpr(dc, rd | 1); - TCGv hi =3D gen_dest_gpr(dc, rd); - TCGv_i64 t64 =3D tcg_temp_new_i64(); - DisasASI da =3D get_asi(dc, insn, MO_TEUQ); - - switch (da.type) { - case GET_ASI_EXCP: - return; - case GET_ASI_DIRECT: - gen_address_mask(dc, addr); - tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN); - break; - default: - { - TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); - TCGv_i32 r_mop =3D tcg_constant_i32(MO_UQ); - - save_state(dc); - gen_helper_ld_asi(t64, tcg_env, addr, r_asi, r_mop); - } - break; - } - - tcg_gen_extr_i64_i32(lo, hi, t64); - gen_store_gpr(dc, rd | 1, lo); - gen_store_gpr(dc, rd, hi); -} - -static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, - int insn, int rd) -{ - DisasASI da =3D get_asi(dc, insn, MO_TEUQ); - TCGv lo =3D gen_load_gpr(dc, rd + 1); - TCGv_i64 t64 =3D tcg_temp_new_i64(); - - tcg_gen_concat_tl_i64(t64, lo, hi); - - switch (da.type) { - case GET_ASI_EXCP: - break; - case GET_ASI_DIRECT: - gen_address_mask(dc, addr); - tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN); - break; - case GET_ASI_BFILL: - /* Store 32 bytes of T64 to ADDR. */ - /* ??? The original qemu code suggests 8-byte alignment, dropping - the low bits, but the only place I can see this used is in the - Linux kernel with 32 byte alignment, which would make more sense - as a cacheline-style operation. */ - { - TCGv d_addr =3D tcg_temp_new(); - TCGv eight =3D tcg_constant_tl(8); - int i; - - tcg_gen_andi_tl(d_addr, addr, -8); - for (i =3D 0; i < 32; i +=3D 8) { - tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop); - tcg_gen_add_tl(d_addr, d_addr, eight); - } - } - break; - default: - { - TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); - TCGv_i32 r_mop =3D tcg_constant_i32(MO_UQ); - - save_state(dc); - gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop); - } - break; - } -} -#endif - static TCGv get_src1(DisasContext *dc, unsigned int insn) { unsigned int rs1 =3D GET_FIELD(insn, 13, 17); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279827; cv=none; d=zohomail.com; s=zohoarc; b=eC7MDQf4JM9XBPGNUOy8tJ4DbDGb4EegKLuWtujzqCm/EBFhsLDdICCcSPSj4YAG7BNQ81JOgPHtbcIitieSZqGZflfpD6KxiNfrq3T9xYAMdk9nRKrnNNahY5cjQ5kDgyEa40y3MZg4AG+vZGGe6mHJtSTEoKL9l9OaFMtEvKc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279827; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=FJWQTSXIVaWpvvHhP9KgF/nTwAogXnm2BnoIdB4YZKA=; b=jHt25TvI01ZwZL7iEcxLtWZap1LIOSeZIBR6hR1NQ0KAE5ZYJtuleMtrbTKdFRP/jIhqhHbZ5pxJ/pm7VSRDPa5Pviw7EWJOPZTO5IP2SRkqpwNlsxlUTy8Qm9/sUm/RhPC1T+4fluenM1vD8ynId1b07a7SNgNzCE2xJbJBWEo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698279827288393.5395951970572; Wed, 25 Oct 2023 17:23:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo6z-0002KE-6n; Wed, 25 Oct 2023 20:20:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo6O-0001dG-Ab for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:56 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo6I-0006xe-HC for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:56 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1ca052ec63bso2400465ad.1 for ; Wed, 25 Oct 2023 17:19:50 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279589; x=1698884389; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FJWQTSXIVaWpvvHhP9KgF/nTwAogXnm2BnoIdB4YZKA=; b=mRrGtxEwAzlyy8tbSip8Xx/kwvpMClMXkEPMvrQGydmdu5nqBryAn2Uk7qr0zLeni3 OVTjeFMigz/odrBWLo07+FSSZc29vroXayt1BA/pXxOZb2Y/PXn86KRq03cWCIvkeHVV vl5WAiKVetnh/fx/R1O8/NpR3werMLvIqQlbK3LsDF9QCIf3IuVz9aunS3mtaydV/8mh l2kuVvC8dWRELZSUiuPmDnWheazWv/rhBBoxGLnn3P0XMdzxfS6eph14Br6Luitj2Upc VGT7MeJeO+uGQt80zK/NvOCVf9D807ORpoHdUv9GvqOraXwFkV0qWR50DTz80VHY9JWy YfSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279589; x=1698884389; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FJWQTSXIVaWpvvHhP9KgF/nTwAogXnm2BnoIdB4YZKA=; b=ulp2USFaHuTLXeRn0YKPlO3UvbCarpThsgpSzBuq9PxvGN0yVpbZ1MbCYnHbL27PCm wjLzvBFV1wJv7/83oqkI4oNbXYvyP9+qnaFpNp+AMwTdvgpHZtpfoUXrckBZTLf1RIQP bbxkYhTgxVjjM0Z13Nk4sydoKZnPfsjJHzZmZiA+00EmPlIbMgDIgKHlsJSwUluQAQ4t nte9WSLFhGtVy36tzA5Aczg2MpjwQSwyA29rU+OkfF2shPyQjLU73MM5PX2HtRiZewju 6Hv2kM9QweLsqqQqmwiCFpZAhhO1IUgG3Qru8pjWUJnTceJnfxT7uXsPKO77ZHxuFidE BBkg== X-Gm-Message-State: AOJu0Yxq4+p9MsxLEKnUEFR3eYhiCRd1uj+IgRrBz6JJdWMr96AShr0U W/QwbYDm3cr1hmk5c4aoapXMcS9gbMMJ2uXKPSE= X-Google-Smtp-Source: AGHT+IGCQbT+dqODAOLe8ctv34rQdYgKp8FqD7QcNRkzTr95gTpbHFIddBdq7hpmH55QDGgh+m6U8A== X-Received: by 2002:a17:902:ce88:b0:1ca:92a:df0 with SMTP id f8-20020a170902ce8800b001ca092a0df0mr18705046plg.59.1698279589218; Wed, 25 Oct 2023 17:19:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 50/94] target/sparc: Split out ldst functions with asi pre-computed Date: Wed, 25 Oct 2023 17:14:58 -0700 Message-Id: <20231026001542.1141412-80-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279828673100003 Content-Type: text/plain; charset="utf-8" As an intermediate step in decodetree conversion, create new functions passing in DisasASI and not insn. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 215 ++++++++++++++++++++++----------------- 1 file changed, 123 insertions(+), 92 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 09b01ccf77..e24945e50e 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2162,25 +2162,21 @@ static void gen_helper_st_asi(TCGv_env e, TCGv a, T= CGv_i64 r, } #endif =20 -static void __attribute__((unused)) -gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop) +static void gen_ld_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv add= r) { - DisasASI da =3D get_asi(dc, insn, memop); - - switch (da.type) { + switch (da->type) { case GET_ASI_EXCP: break; case GET_ASI_DTWINX: /* Reserved for ldda. */ gen_exception(dc, TT_ILL_INSN); break; case GET_ASI_DIRECT: - gen_address_mask(dc, addr); - tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop | MO_ALIGN); + tcg_gen_qemu_ld_tl(dst, addr, da->mem_idx, da->memop | MO_ALIGN); break; default: { - TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); - TCGv_i32 r_mop =3D tcg_constant_i32(memop | MO_ALIGN); + TCGv_i32 r_asi =3D tcg_constant_i32(da->asi); + TCGv_i32 r_mop =3D tcg_constant_i32(da->memop | MO_ALIGN); =20 save_state(dc); #ifdef TARGET_SPARC64 @@ -2198,33 +2194,38 @@ gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, i= nt insn, MemOp memop) } =20 static void __attribute__((unused)) -gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop) +gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop) { DisasASI da =3D get_asi(dc, insn, memop); =20 - switch (da.type) { + gen_address_mask(dc, addr); + gen_ld_asi0(dc, &da, dst, addr); +} + +static void gen_st_asi0(DisasContext *dc, DisasASI *da, TCGv src, TCGv add= r) +{ + switch (da->type) { case GET_ASI_EXCP: break; + case GET_ASI_DTWINX: /* Reserved for stda. */ -#ifndef TARGET_SPARC64 - gen_exception(dc, TT_ILL_INSN); - break; -#else - if (!(dc->def->features & CPU_FEATURE_HYPV)) { + if (TARGET_LONG_BITS =3D=3D 32) { + gen_exception(dc, TT_ILL_INSN); + break; + } else if (!(dc->def->features & CPU_FEATURE_HYPV)) { /* Pre OpenSPARC CPUs don't have these */ gen_exception(dc, TT_ILL_INSN); - return; + break; } - /* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions - * are ST_BLKINIT_ ASIs */ -#endif + /* In OpenSPARC T1+ CPUs TWINX ASIs in store are ST_BLKINIT_ ASIs = */ /* fall through */ + case GET_ASI_DIRECT: - gen_address_mask(dc, addr); - tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop | MO_ALIGN); + tcg_gen_qemu_st_tl(src, addr, da->mem_idx, da->memop | MO_ALIGN); break; -#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) + case GET_ASI_BCOPY: + assert(TARGET_LONG_BITS =3D=3D 32); /* Copy 32 bytes from the address in SRC to ADDR. */ /* ??? The original qemu code suggests 4-byte alignment, dropping the low bits, but the only place I can see this used is in the @@ -2242,18 +2243,18 @@ gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, i= nt insn, MemOp memop) for (i =3D 0; i < 32; i +=3D 4) { /* Since the loads and stores are paired, allow the copy to happen in the host endianness. */ - tcg_gen_qemu_ld_i32(tmp, saddr, da.mem_idx, MO_UL); - tcg_gen_qemu_st_i32(tmp, daddr, da.mem_idx, MO_UL); + tcg_gen_qemu_ld_i32(tmp, saddr, da->mem_idx, MO_UL); + tcg_gen_qemu_st_i32(tmp, daddr, da->mem_idx, MO_UL); tcg_gen_add_tl(saddr, saddr, four); tcg_gen_add_tl(daddr, daddr, four); } } break; -#endif + default: { - TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); - TCGv_i32 r_mop =3D tcg_constant_i32(memop | MO_ALIGN); + TCGv_i32 r_asi =3D tcg_constant_i32(da->asi); + TCGv_i32 r_mop =3D tcg_constant_i32(da->memop | MO_ALIGN); =20 save_state(dc); #ifdef TARGET_SPARC64 @@ -2273,16 +2274,49 @@ gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, i= nt insn, MemOp memop) } } =20 +static void __attribute__((unused)) +gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop) +{ + DisasASI da =3D get_asi(dc, insn, memop); + + gen_address_mask(dc, addr); + gen_st_asi0(dc, &da, src, addr); +} + +static void gen_swap_asi0(DisasContext *dc, DisasASI *da, + TCGv dst, TCGv src, TCGv addr) +{ + switch (da->type) { + case GET_ASI_EXCP: + break; + case GET_ASI_DIRECT: + gen_swap(dc, dst, src, addr, da->mem_idx, da->memop); + break; + default: + /* ??? Should be DAE_invalid_asi. */ + gen_exception(dc, TT_DATA_ACCESS); + break; + } +} + static void __attribute__((unused)) gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, TCGv addr, int insn) { DisasASI da =3D get_asi(dc, insn, MO_TEUL); =20 - switch (da.type) { + gen_address_mask(dc, addr); + gen_swap_asi0(dc, &da, dst, src, addr); +} + +static void gen_cas_asi0(DisasContext *dc, DisasASI *da, + TCGv oldv, TCGv newv, TCGv cmpv, TCGv addr) +{ + switch (da->type) { case GET_ASI_EXCP: - break; + return; case GET_ASI_DIRECT: - gen_swap(dc, dst, src, addr, da.mem_idx, da.memop); + tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, newv, + da->mem_idx, da->memop | MO_ALIGN); break; default: /* ??? Should be DAE_invalid_asi. */ @@ -2295,34 +2329,33 @@ static void __attribute__((unused)) gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) { DisasASI da =3D get_asi(dc, insn, MO_TEUL); - TCGv oldv; + TCGv oldv =3D gen_dest_gpr(dc, rd); + TCGv newv =3D gen_load_gpr(dc, rd); =20 - switch (da.type) { - case GET_ASI_EXCP: - return; - case GET_ASI_DIRECT: - oldv =3D tcg_temp_new(); - tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd), - da.mem_idx, da.memop | MO_ALIGN); - gen_store_gpr(dc, rd, oldv); - break; - default: - /* ??? Should be DAE_invalid_asi. */ - gen_exception(dc, TT_DATA_ACCESS); - break; - } + gen_address_mask(dc, addr); + gen_cas_asi0(dc, &da, oldv, newv, cmpv, addr); + gen_store_gpr(dc, rd, oldv); } =20 static void __attribute__((unused)) -gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) +gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) { - DisasASI da =3D get_asi(dc, insn, MO_UB); + DisasASI da =3D get_asi(dc, insn, MO_TEUQ); + TCGv oldv =3D gen_dest_gpr(dc, rd); + TCGv newv =3D gen_load_gpr(dc, rd); =20 - switch (da.type) { + gen_address_mask(dc, addr); + gen_cas_asi0(dc, &da, oldv, newv, cmpv, addr); + gen_store_gpr(dc, rd, oldv); +} + +static void gen_ldstub_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv= addr) +{ + switch (da->type) { case GET_ASI_EXCP: break; case GET_ASI_DIRECT: - gen_ldstub(dc, dst, addr, da.mem_idx); + gen_ldstub(dc, dst, addr, da->mem_idx); break; default: /* ??? In theory, this should be raise DAE_invalid_asi. @@ -2330,7 +2363,7 @@ gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr,= int insn) if (tb_cflags(dc->base.tb) & CF_PARALLEL) { gen_helper_exit_atomic(tcg_env); } else { - TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); + TCGv_i32 r_asi =3D tcg_constant_i32(da->asi); TCGv_i32 r_mop =3D tcg_constant_i32(MO_UB); TCGv_i64 s64, t64; =20 @@ -2350,6 +2383,15 @@ gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr= , int insn) } } =20 +static void __attribute__((unused)) +gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) +{ + DisasASI da =3D get_asi(dc, insn, MO_UB); + + gen_address_mask(dc, addr); + gen_ldstub_asi0(dc, &da, dst, addr); +} + static void __attribute__((unused)) gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) { @@ -2542,36 +2584,32 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, = int size, int rd) } } =20 -static void __attribute__((unused)) -gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) +static void gen_ldda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int r= d) { - DisasASI da =3D get_asi(dc, insn, MO_TEUQ); TCGv hi =3D gen_dest_gpr(dc, rd); TCGv lo =3D gen_dest_gpr(dc, rd + 1); =20 - switch (da.type) { + switch (da->type) { case GET_ASI_EXCP: return; =20 case GET_ASI_DTWINX: assert(TARGET_LONG_BITS =3D=3D 64); - gen_address_mask(dc, addr); - tcg_gen_qemu_ld_tl(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); + tcg_gen_qemu_ld_tl(hi, addr, da->mem_idx, da->memop | MO_ALIGN_16); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_ld_tl(lo, addr, da.mem_idx, da.memop); + tcg_gen_qemu_ld_tl(lo, addr, da->mem_idx, da->memop); break; =20 case GET_ASI_DIRECT: { TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 - gen_address_mask(dc, addr); - tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop | MO_ALIGN= ); + tcg_gen_qemu_ld_i64(tmp, addr, da->mem_idx, da->memop | MO_ALI= GN); =20 /* Note that LE ldda acts as if each 32-bit register result is byte swapped. Having just performed one 64-bit bswap, we need now to swap the writebacks. */ - if ((da.memop & MO_BSWAP) =3D=3D MO_TE) { + if ((da->memop & MO_BSWAP) =3D=3D MO_TE) { tcg_gen_extr_i64_tl(lo, hi, tmp); } else { tcg_gen_extr_i64_tl(hi, lo, tmp); @@ -2585,15 +2623,15 @@ gen_ldda_asi(DisasContext *dc, TCGv addr, int insn,= int rd) real hardware allows others. This can be seen with e.g. FreeBSD 10.3 wrt ASI_IC_TAG. */ { - TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); - TCGv_i32 r_mop =3D tcg_constant_i32(da.memop); + TCGv_i32 r_asi =3D tcg_constant_i32(da->asi); + TCGv_i32 r_mop =3D tcg_constant_i32(da->memop); TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 save_state(dc); gen_helper_ld_asi(tmp, tcg_env, addr, r_asi, r_mop); =20 /* See above. */ - if ((da.memop & MO_BSWAP) =3D=3D MO_TE) { + if ((da->memop & MO_BSWAP) =3D=3D MO_TE) { tcg_gen_extr_i64_tl(lo, hi, tmp); } else { tcg_gen_extr_i64_tl(hi, lo, tmp); @@ -2607,21 +2645,28 @@ gen_ldda_asi(DisasContext *dc, TCGv addr, int insn,= int rd) } =20 static void __attribute__((unused)) -gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd) +gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) { DisasASI da =3D get_asi(dc, insn, MO_TEUQ); + + gen_address_mask(dc, addr); + gen_ldda_asi0(dc, &da, addr, rd); +} + +static void gen_stda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int r= d) +{ + TCGv hi =3D gen_load_gpr(dc, rd); TCGv lo =3D gen_load_gpr(dc, rd + 1); =20 - switch (da.type) { + switch (da->type) { case GET_ASI_EXCP: break; =20 case GET_ASI_DTWINX: assert(TARGET_LONG_BITS =3D=3D 64); - gen_address_mask(dc, addr); - tcg_gen_qemu_st_tl(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); + tcg_gen_qemu_st_tl(hi, addr, da->mem_idx, da->memop | MO_ALIGN_16); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_st_tl(lo, addr, da.mem_idx, da.memop); + tcg_gen_qemu_st_tl(lo, addr, da->mem_idx, da->memop); break; =20 case GET_ASI_DIRECT: @@ -2631,13 +2676,12 @@ gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, = int insn, int rd) /* Note that LE stda acts as if each 32-bit register result is byte swapped. We will perform one 64-bit LE store, so now we must swap the order of the construction. */ - if ((da.memop & MO_BSWAP) =3D=3D MO_TE) { + if ((da->memop & MO_BSWAP) =3D=3D MO_TE) { tcg_gen_concat_tl_i64(t64, lo, hi); } else { tcg_gen_concat_tl_i64(t64, hi, lo); } - gen_address_mask(dc, addr); - tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN= ); + tcg_gen_qemu_st_i64(t64, addr, da->mem_idx, da->memop | MO_ALI= GN); } break; =20 @@ -2657,7 +2701,7 @@ gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, in= t insn, int rd) tcg_gen_concat_tl_i64(t64, lo, hi); tcg_gen_andi_tl(d_addr, addr, -8); for (i =3D 0; i < 32; i +=3D 8) { - tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop); + tcg_gen_qemu_st_i64(t64, d_addr, da->mem_idx, da->memop); tcg_gen_add_tl(d_addr, d_addr, eight); } } @@ -2667,12 +2711,12 @@ gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, = int insn, int rd) /* ??? In theory we've handled all of the ASIs that are valid for stda, and this should raise DAE_invalid_asi. */ { - TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); - TCGv_i32 r_mop =3D tcg_constant_i32(da.memop); + TCGv_i32 r_asi =3D tcg_constant_i32(da->asi); + TCGv_i32 r_mop =3D tcg_constant_i32(da->memop); TCGv_i64 t64 =3D tcg_temp_new_i64(); =20 /* See above. */ - if ((da.memop & MO_BSWAP) =3D=3D MO_TE) { + if ((da->memop & MO_BSWAP) =3D=3D MO_TE) { tcg_gen_concat_tl_i64(t64, lo, hi); } else { tcg_gen_concat_tl_i64(t64, hi, lo); @@ -2686,25 +2730,12 @@ gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, = int insn, int rd) } =20 static void __attribute__((unused)) -gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) +gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd) { DisasASI da =3D get_asi(dc, insn, MO_TEUQ); - TCGv oldv; =20 - switch (da.type) { - case GET_ASI_EXCP: - return; - case GET_ASI_DIRECT: - oldv =3D tcg_temp_new(); - tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd), - da.mem_idx, da.memop | MO_ALIGN); - gen_store_gpr(dc, rd, oldv); - break; - default: - /* ??? Should be DAE_invalid_asi. */ - gen_exception(dc, TT_DATA_ACCESS); - break; - } + gen_address_mask(dc, addr); + gen_stda_asi0(dc, &da, addr, rd); } =20 static TCGv get_src1(DisasContext *dc, unsigned int insn) --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698280281369297.2666077669562; Wed, 25 Oct 2023 17:31:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo9Q-0000zN-LQ; Wed, 25 Oct 2023 20:23:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo9I-0008Se-CN for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:22:58 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo9E-0008AN-IS for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:22:55 -0400 Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-565e54cb93aso302053a12.3 for ; Wed, 25 Oct 2023 17:22:51 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.22.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:22:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279770; x=1698884570; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tug4Ye+ri5yZyV+52Sfq/q/Jg8MaYnVtboKHbVUVRBc=; b=yfpkQYwD5jONLqy3Kn/qYAi4ubnQIHrSiPYdIyMWF8SnER6xi34QAFIpYT+tj8kasf 2Y+hG3JnOAJXeytET9cTdXEt7ZcTiEvadDIxVn/6S4/RY5RxKUw2bJ++4i4316FmMze9 5UWoNhElTz1Z8pJDhJZbu1elAT3pTT0+8rEmU3JZvIizgHgUG13Ifym8WA+XSPiaxGFM WOT+8VYAaijdZy5dezeCllVOkTRzNIMBeOcfx1jmMByGsIngAw7wWf/wUC049ttadGQq IMbK27JvwQYal7MIeESd80PCyx6J9Cy2e3LE+Ed2JlI8G9qbLq25wrUiokOHuheU195i q0xA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279770; x=1698884570; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tug4Ye+ri5yZyV+52Sfq/q/Jg8MaYnVtboKHbVUVRBc=; b=jfnj+aZKH+54n17n+lO2k1uLR0qaxfvqBOHinMfYDxiVa9p40CJfn9gC8E6/UB0OvJ LdQ6j1E9L/h+R5VTJBUxQ/Ls+Vr9ejUEAO5KCdKWJmQSwoa3+qFBLSItdcOqG9BCY0Wp C8qoRmQ2lwQqR5kK9kHLFVobFzPHpKhkvW/cpXoBPZfQ7ZtonH0/7j5remw4+Ek2F4q7 3vgUqe0eIyT4UZTpPW9QJ445u3fWOtZa85mtSEufhBEQKeWc03YyN8O53qgpqwvgApHT szHaAFQgNk3nEjtLIi/CK1Mus2HD3YCRY5OXhNHkraFsCc3NC5sdPRInPhw2ajQT7EV3 p5Aw== X-Gm-Message-State: AOJu0YyGd50kfb7YGf7/zfZIBPmTF8KL8dZa0iRSKosY2T4BN8fOtzIn pma8YRHc1lH7b7ze3z2t24Elviq1BX0LvCX9b+U= X-Google-Smtp-Source: AGHT+IEyI1ZAC5xTUehm1hdRWSoeXC2ufT8fXYTsUPlOmHQ4DYn11bSGyVWV+jigm/qia6z6jTD4nA== X-Received: by 2002:a17:90b:4a8f:b0:27d:b885:17f2 with SMTP id lp15-20020a17090b4a8f00b0027db88517f2mr13526115pjb.30.1698279770446; Wed, 25 Oct 2023 17:22:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 51/94] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX Date: Wed, 25 Oct 2023 17:14:59 -0700 Message-Id: <20231026001542.1141412-81-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1698280281940100010 Content-Type: text/plain; charset="utf-8" Perform one atomic 16-byte operation. The atomicity is required for the LDTXA instructions. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 48 +++++++++++++++++++++++++++++++++------- 1 file changed, 40 insertions(+), 8 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index e24945e50e..7ce9ab66c6 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2594,11 +2594,27 @@ static void gen_ldda_asi0(DisasContext *dc, DisasAS= I *da, TCGv addr, int rd) return; =20 case GET_ASI_DTWINX: - assert(TARGET_LONG_BITS =3D=3D 64); - tcg_gen_qemu_ld_tl(hi, addr, da->mem_idx, da->memop | MO_ALIGN_16); - tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_ld_tl(lo, addr, da->mem_idx, da->memop); +#ifdef TARGET_SPARC64 + { + MemOp mop =3D (da->memop & MO_BSWAP) | MO_128 | MO_ALIGN_16; + TCGv_i128 t =3D tcg_temp_new_i128(); + + tcg_gen_qemu_ld_i128(t, addr, da->mem_idx, mop); + /* + * Note that LE twinx acts as if each 64-bit register result is + * byte swapped. We perform one 128-bit LE load, so must swap + * the order of the writebacks. + */ + if ((mop & MO_BSWAP) =3D=3D MO_TE) { + tcg_gen_extr_i128_i64(lo, hi, t); + } else { + tcg_gen_extr_i128_i64(hi, lo, t); + } + } break; +#else + g_assert_not_reached(); +#endif =20 case GET_ASI_DIRECT: { @@ -2663,11 +2679,27 @@ static void gen_stda_asi0(DisasContext *dc, DisasAS= I *da, TCGv addr, int rd) break; =20 case GET_ASI_DTWINX: - assert(TARGET_LONG_BITS =3D=3D 64); - tcg_gen_qemu_st_tl(hi, addr, da->mem_idx, da->memop | MO_ALIGN_16); - tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_st_tl(lo, addr, da->mem_idx, da->memop); +#ifdef TARGET_SPARC64 + { + MemOp mop =3D (da->memop & MO_BSWAP) | MO_128 | MO_ALIGN_16; + TCGv_i128 t =3D tcg_temp_new_i128(); + + /* + * Note that LE twinx acts as if each 64-bit register result is + * byte swapped. We perform one 128-bit LE store, so must swap + * the order of the construction. + */ + if ((mop & MO_BSWAP) =3D=3D MO_TE) { + tcg_gen_concat_i64_i128(t, lo, hi); + } else { + tcg_gen_concat_i64_i128(t, hi, lo); + } + tcg_gen_qemu_st_i128(t, addr, da->mem_idx, mop); + } break; +#else + g_assert_not_reached(); +#endif =20 case GET_ASI_DIRECT: { --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279882; cv=none; d=zohomail.com; s=zohoarc; b=NmEb3vqTpONMBiYZr6m7RE4BktELCsgmon3NOpvzl9kyhM5AGJQfmmhQogpsVc20TCoI+G95kpFnkcooc+BTOIhcoJBhD7KWC6t/SGQ8w+aCf+K1NF1i7xCGTQFxR7sJd86kLhI4DUgidgl+pRkalDb01tdK3KaJ4dOf3yxmixA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698279882; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=10ZlbZnfTg8LnI0vemtKsGjnuIMVwA7h5DHDNssZclo=; b=UThGck2HVx6s/4skdKUiQ13rixej+HgANR8Lnlw+Vv/VqSGNW/AA1HmNt6zipO/ZVrFVVFhJbPGXYCMZqVXmBws76rkXzOz5nsTncjwWs6wKhrKRDBXqpd5l5PsDSJt/sV5aryRGMNyrItHS6bEUUIs/T3UpE9XPNrUFTME65WY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698279882800166.69064334086227; Wed, 25 Oct 2023 17:24:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo9W-0001ev-73; Wed, 25 Oct 2023 20:23:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo9I-0008WJ-Nf for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:22:58 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo9F-0008AR-NN for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:22:56 -0400 Received: by mail-pj1-x102d.google.com with SMTP id 98e67ed59e1d1-27d18475ed4so252633a91.0 for ; Wed, 25 Oct 2023 17:22:52 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:22:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279771; x=1698884571; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=10ZlbZnfTg8LnI0vemtKsGjnuIMVwA7h5DHDNssZclo=; b=OxwTXMYl3k5hd4lHcZu8RhKI5xcXN2bT+XBgjIIVaGsqvLoaJXmFPywRJ4kciIe3fT zwgPJZpU2BdZvT+Q7bv6Xeu/gnyPCpIeN+NDUQ4QAgcFENHE0AfhGkvuhPK7tQZGfwhL Y5q26ZCFKw0XUHQ35AuFroWbbwns98Q7IXVmEviff1uZffoHLvcyKBKaDWw33yEHlVyg gT5I+icpoLMUujk3w5xP8j7yLCiMxa7rZGkoQiqzU370w05NhtIaerJzc5J4MfRwq65t jbu3pIUJezdnTgZDPZhgjsYh/uIeU1DteJjsXD6CVZzWMPsYfqiK272QzpeFjEGufSFp xMVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279771; x=1698884571; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=10ZlbZnfTg8LnI0vemtKsGjnuIMVwA7h5DHDNssZclo=; b=LSzd51usgBZYTv84I/3rlovmr03753qUJf8H4uVVTwt9gzDRyuSuEdp5lYYhIlkUGV CRFdFVXQ/Vf8mPbxueOxg7FSHAumHusq06BEb5o7eTi3YGIGKKLIZdHc9s6ReyBvoYFT hHOuQ376d5blj6BIkdqIUos9kHCrMiNm0hpIVP+I2qpleofzBXhaL5mSFHa3CsECqlUs iWuaMEoPwa7zIV9drWiGhzlg7diAOjCPl15llIRDUNZkT6a6PloGDF6r/UFZqCqws+OA SsrpBnB/pAl3eG71+StUVyqt0rHFqCvQtlpI6KVmuD2bD4QkzvNZslxRrwQcSXbaNzsk fx5Q== X-Gm-Message-State: AOJu0YzRvCNS8AnsmCcfhBiPJfwU3FKw5O57PjOvMC5eB6U7hWYUZLHz RwOrtoy3QigQpmoCOn4w39hDo4WJFMdC8vEJMcU= X-Google-Smtp-Source: AGHT+IEL6RJ1Q2eLwKS6nu5jr0UrCTy3J/LgQ0HSt3USenk7fHYEpQpPMqnnaPMUc/SexOuLxyC3PA== X-Received: by 2002:a17:90a:fa8f:b0:268:2658:3b01 with SMTP id cu15-20020a17090afa8f00b0026826583b01mr13163836pjb.39.1698279771277; Wed, 25 Oct 2023 17:22:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 52/94] target/sparc: Move simple integer load/store to decodetree Date: Wed, 25 Oct 2023 17:15:00 -0700 Message-Id: <20231026001542.1141412-82-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279884842100003 Content-Type: text/plain; charset="utf-8" Move LDUW, LDUB, LDUH, LDD, LDSW, LDSB, LDSH, LDX, STW, STB, STH, STD, STX. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 22 +++++ target/sparc/translate.c | 196 +++++++++++++++++++++++--------------- 2 files changed, 142 insertions(+), 76 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 137b7eb3c6..6197fbdb03 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -231,6 +231,28 @@ RESTORE 10 ..... 111101 ..... . ............. = @r_r_ri DONE 10 00000 111110 00000 0 0000000000000 RETRY 10 00001 111110 00000 0 0000000000000 =20 +## +## Major Opcode 11 -- load and store instructions +## + +&r_r_ri_asi rd rs1 rs2_or_imm asi imm:bool +@r_r_ri_na .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_asi asi= =3D-1 + +LDUW 11 ..... 000000 ..... . ............. @r_r_ri_na +LDUB 11 ..... 000001 ..... . ............. @r_r_ri_na +LDUH 11 ..... 000010 ..... . ............. @r_r_ri_na +LDD 11 ..... 000011 ..... . ............. @r_r_ri_na +LDSW 11 ..... 001000 ..... . ............. @r_r_ri_na +LDSB 11 ..... 001001 ..... . ............. @r_r_ri_na +LDSH 11 ..... 001010 ..... . ............. @r_r_ri_na +LDX 11 ..... 001011 ..... . ............. @r_r_ri_na + +STW 11 ..... 000100 ..... . ............. @r_r_ri_na +STB 11 ..... 000101 ..... . ............. @r_r_ri_na +STH 11 ..... 000110 ..... . ............. @r_r_ri_na +STD 11 ..... 000111 ..... . ............. @r_r_ri_na +STX 11 ..... 001110 ..... . ............. @r_r_ri_na + NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 7ce9ab66c6..db09255854 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4536,6 +4536,117 @@ static bool do_done_retry(DisasContext *dc, bool do= ne) TRANS(DONE, 64, do_done_retry, true) TRANS(RETRY, 64, do_done_retry, false) =20 +/* + * Major opcode 11 -- load and store instructions + */ + +static TCGv gen_ldst_addr(DisasContext *dc, int rs1, bool imm, int rs2_or_= imm) +{ + TCGv addr, tmp =3D NULL; + + /* For simplicity, we under-decoded the rs2 form. */ + if (!imm && rs2_or_imm & ~0x1f) { + return NULL; + } + + addr =3D gen_load_gpr(dc, rs1); + if (rs2_or_imm) { + tmp =3D tcg_temp_new(); + if (imm) { + tcg_gen_addi_tl(tmp, addr, rs2_or_imm); + } else { + tcg_gen_add_tl(tmp, addr, cpu_regs[rs2_or_imm]); + } + addr =3D tmp; + } + if (AM_CHECK(dc)) { + if (!tmp) { + tmp =3D tcg_temp_new(); + } + tcg_gen_ext32u_tl(tmp, addr); + addr =3D tmp; + } + return addr; +} + +static bool do_ld_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) +{ + TCGv reg, addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + DisasASI da; + + if (addr =3D=3D NULL) { + return false; + } + da =3D resolve_asi(dc, a->asi, mop); + + reg =3D gen_dest_gpr(dc, a->rd); + gen_ld_asi0(dc, &da, reg, addr); + gen_store_gpr(dc, a->rd, reg); + return advance_pc(dc); +} + +TRANS(LDUW, ALL, do_ld_gpr, a, MO_TEUL) +TRANS(LDUB, ALL, do_ld_gpr, a, MO_UB) +TRANS(LDUH, ALL, do_ld_gpr, a, MO_TEUW) +TRANS(LDSB, ALL, do_ld_gpr, a, MO_SB) +TRANS(LDSH, ALL, do_ld_gpr, a, MO_TESW) +TRANS(LDSW, 64, do_ld_gpr, a, MO_TESL) +TRANS(LDX, 64, do_ld_gpr, a, MO_TEUQ) + +static bool do_st_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) +{ + TCGv reg, addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + DisasASI da; + + if (addr =3D=3D NULL) { + return false; + } + da =3D resolve_asi(dc, a->asi, mop); + + reg =3D gen_load_gpr(dc, a->rd); + gen_st_asi0(dc, &da, reg, addr); + return advance_pc(dc); +} + +TRANS(STW, ALL, do_st_gpr, a, MO_TEUL) +TRANS(STB, ALL, do_st_gpr, a, MO_UB) +TRANS(STH, ALL, do_st_gpr, a, MO_TEUW) +TRANS(STX, 64, do_st_gpr, a, MO_TEUQ) + +static bool trans_LDD(DisasContext *dc, arg_r_r_ri_asi *a) +{ + TCGv addr; + DisasASI da; + + if (a->rd & 1) { + return false; + } + addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + if (addr =3D=3D NULL) { + return false; + } + da =3D resolve_asi(dc, a->asi, MO_TEUQ); + gen_ldda_asi0(dc, &da, addr, a->rd); + return advance_pc(dc); +} + +static bool trans_STD(DisasContext *dc, arg_r_r_ri_asi *a) +{ + TCGv addr; + DisasASI da; + + if (a->rd & 1) { + return false; + } + addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + if (addr =3D=3D NULL) { + return false; + } + da =3D resolve_asi(dc, a->asi, MO_TEUQ); + gen_stda_asi0(dc, &da, addr, a->rd); + return advance_pc(dc); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5359,47 +5470,15 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) =20 switch (xop) { case 0x0: /* ld, V9 lduw, load unsigned word */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUL | MO_ALIGN); - break; case 0x1: /* ldub, load unsigned byte */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_UB); - break; case 0x2: /* lduh, load unsigned halfword */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUW | MO_ALIGN); - break; case 0x3: /* ldd, load double word */ - if (rd & 1) - goto illegal_insn; - else { - TCGv_i64 t64; - - gen_address_mask(dc, cpu_addr); - t64 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t64, cpu_addr, - dc->mem_idx, MO_TEUQ | MO_ALIG= N); - tcg_gen_trunc_i64_tl(cpu_val, t64); - tcg_gen_ext32u_tl(cpu_val, cpu_val); - gen_store_gpr(dc, rd + 1, cpu_val); - tcg_gen_shri_i64(t64, t64, 32); - tcg_gen_trunc_i64_tl(cpu_val, t64); - tcg_gen_ext32u_tl(cpu_val, cpu_val); - } - break; case 0x9: /* ldsb, load signed byte */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, dc->mem_idx, MO_= SB); - break; case 0xa: /* ldsh, load signed halfword */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TESW | MO_ALIGN); - break; + g_assert_not_reached(); /* in decodetree */ + case 0x08: /* V9 ldsw */ + case 0x0b: /* V9 ldx */ + goto illegal_insn; /* in decodetree */ case 0xd: /* ldstub */ gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx); break; @@ -5441,16 +5520,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) break; #endif #ifdef TARGET_SPARC64 - case 0x08: /* V9 ldsw */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TESL | MO_ALIGN); - break; - case 0x0b: /* V9 ldx */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUQ | MO_ALIGN); - break; case 0x18: /* V9 ldswa */ gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL); break; @@ -5543,38 +5612,18 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) } } else if (xop < 8 || (xop >=3D 0x14 && xop < 0x18) || xop =3D=3D 0xe || xop =3D=3D 0x1e) { +#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) TCGv cpu_val =3D gen_load_gpr(dc, rd); +#endif =20 switch (xop) { case 0x4: /* st, store word */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_st_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUL | MO_ALIGN); - break; case 0x5: /* stb, store byte */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_st_tl(cpu_val, cpu_addr, dc->mem_idx, MO_= UB); - break; case 0x6: /* sth, store halfword */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_st_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUW | MO_ALIGN); - break; case 0x7: /* std, store double word */ - if (rd & 1) - goto illegal_insn; - else { - TCGv_i64 t64; - TCGv lo; - - gen_address_mask(dc, cpu_addr); - lo =3D gen_load_gpr(dc, rd + 1); - t64 =3D tcg_temp_new_i64(); - tcg_gen_concat_tl_i64(t64, lo, cpu_val); - tcg_gen_qemu_st_i64(t64, cpu_addr, - dc->mem_idx, MO_TEUQ | MO_ALIG= N); - } - break; + g_assert_not_reached(); /* in decodetree */ + case 0x0e: /* V9 stx */ + goto illegal_insn; /* in decodetree */ #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x14: /* sta, V9 stwa, store word alternate */ gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL); @@ -5593,11 +5642,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) break; #endif #ifdef TARGET_SPARC64 - case 0x0e: /* V9 stx */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_st_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUQ | MO_ALIGN); - break; case 0x1e: /* V9 stxa */ gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ); break; --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.22.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:22:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279772; x=1698884572; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jZBbjchxW1tHrNN5v0YkGnZIiPMEUx8oDtYFBFTOGuQ=; b=n1AyPk7kp2Cdh3G1FlMsXyqbcRDtsarjxZs5iZqI43FGzj0JWCUq+0Ky6ewqNxVeD6 eWU7koCtwUnw6VqjDixNmvDp9ajf233i6YLtfPNRFc9pxxDjYH1ptOAoT0MyxtH08I0s +z2d/IQ4I2ittE7o6Zqv9jGbVCyOzIxQXyzcUFF/aiMOivPL8RMuQiIiNSG9hT1+L+oM sy+GQSvyeifq/pKO/AeoqY8VOriPpcUE79rPdqD6nXkx+v2ZZKRAfvQn9hVPsMSrYamB ekno/ax8IhBjBUW3medjr9MDl72ERu0zEYrl1pJgIL7yXBmq4pyV4cMgy078Lycz0iCe bkVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279772; x=1698884572; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jZBbjchxW1tHrNN5v0YkGnZIiPMEUx8oDtYFBFTOGuQ=; b=mmkBn3JOhBoGSvymbzi6OHjaR+xu68/nT6EvOWitbN+2UyEzql4KiGvJGb/RzPnzLZ kql/segrvxAI1lfGE1kEXeaVIfJPIcwtsVg4zNCGu4ficWoWLhUqjEMQdr6fB40PCx06 daG1VRM8TUpKTBr3JzngeZQfH4LHySoB0r0jebTAooy6IBPJpomypw9QdEnMCxIcZW+8 J1NxFwV1bnJb2wUJ2T0o8yx4dmfSwBTLJNvrThxjQGwfu/XGRZii4fPbLqHHo9msoKdG 8W+nbkRlqzLGYJjRDV3mnvoCnOlLcTuwLClnlrPTIvX6g+zRr7fdlnEpTIVEAfgpU8Al ntTg== X-Gm-Message-State: AOJu0YyCOeUU7MG2+n6pXOvur0+caezvM8Kny1bgrgiQnKo/2Hq90Q96 PprjANr0+acCOSoz2KBnW1yF/R/bF9NhQ4VUByc= X-Google-Smtp-Source: AGHT+IHfI9yJruwdJdeJynHVEAieaX/vzZhRkk4e8IEe8ix0EILLXnnEj2bZl/RtW4KrsUYH1u3cnQ== X-Received: by 2002:a17:90a:7442:b0:27d:9b67:7fa6 with SMTP id o2-20020a17090a744200b0027d9b677fa6mr14984972pjk.3.1698279771997; Wed, 25 Oct 2023 17:22:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 53/94] target/sparc: Move asi integer load/store to decodetree Date: Wed, 25 Oct 2023 17:15:01 -0700 Message-Id: <20231026001542.1141412-83-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280360972100003 Content-Type: text/plain; charset="utf-8" Move LDDA, LDSBA, LDSHA, LDSWA, LDUBA, LDUHA, LDUWA, LDXA, STBA, STDA, STHA, STWA, STXA. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 31 +++++++++ target/sparc/translate.c | 128 +++++--------------------------------- 2 files changed, 48 insertions(+), 111 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 6197fbdb03..280b19f033 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -237,6 +237,9 @@ RETRY 10 00001 111110 00000 0 0000000000000 =20 &r_r_ri_asi rd rs1 rs2_or_imm asi imm:bool @r_r_ri_na .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_asi asi= =3D-1 +@r_r_r_asi .. rd:5 ...... rs1:5 0 asi:8 rs2_or_imm:5 &r_r_ri_asi imm= =3D0 +@r_r_i_asi .. rd:5 ...... rs1:5 1 rs2_or_imm:s13 \ + &r_r_ri_asi imm=3D1 asi=3D-2 =20 LDUW 11 ..... 000000 ..... . ............. @r_r_ri_na LDUB 11 ..... 000001 ..... . ............. @r_r_ri_na @@ -253,6 +256,34 @@ STH 11 ..... 000110 ..... . ............. = @r_r_ri_na STD 11 ..... 000111 ..... . ............. @r_r_ri_na STX 11 ..... 001110 ..... . ............. @r_r_ri_na =20 +LDUW 11 ..... 010000 ..... . ............. @r_r_r_asi # LD= UWA +LDUW 11 ..... 010000 ..... . ............. @r_r_i_asi # LD= UWA +LDUB 11 ..... 010001 ..... . ............. @r_r_r_asi # LD= UBA +LDUB 11 ..... 010001 ..... . ............. @r_r_i_asi # LD= UBA +LDUH 11 ..... 010010 ..... . ............. @r_r_r_asi # LD= UHA +LDUH 11 ..... 010010 ..... . ............. @r_r_i_asi # LD= UHA +LDD 11 ..... 010011 ..... . ............. @r_r_r_asi # LD= DA +LDD 11 ..... 010011 ..... . ............. @r_r_i_asi # LD= DA +LDX 11 ..... 011011 ..... . ............. @r_r_r_asi # LD= XA +LDX 11 ..... 011011 ..... . ............. @r_r_i_asi # LD= XA +LDSB 11 ..... 011001 ..... . ............. @r_r_r_asi # LD= SBA +LDSB 11 ..... 011001 ..... . ............. @r_r_i_asi # LD= SBA +LDSH 11 ..... 011010 ..... . ............. @r_r_r_asi # LD= SHA +LDSH 11 ..... 011010 ..... . ............. @r_r_i_asi # LD= SHA +LDSW 11 ..... 011000 ..... . ............. @r_r_r_asi # LD= SWA +LDSW 11 ..... 011000 ..... . ............. @r_r_i_asi # LD= SWA + +STW 11 ..... 010100 ..... . ............. @r_r_r_asi # ST= WA +STW 11 ..... 010100 ..... . ............. @r_r_i_asi # ST= WA +STB 11 ..... 010101 ..... . ............. @r_r_r_asi # ST= BA +STB 11 ..... 010101 ..... . ............. @r_r_i_asi # ST= BA +STH 11 ..... 010110 ..... . ............. @r_r_r_asi # ST= HA +STH 11 ..... 010110 ..... . ............. @r_r_i_asi # ST= HA +STD 11 ..... 010111 ..... . ............. @r_r_r_asi # ST= DA +STD 11 ..... 010111 ..... . ............. @r_r_i_asi # ST= DA +STX 11 ..... 011110 ..... . ............. @r_r_r_asi # ST= XA +STX 11 ..... 011110 ..... . ............. @r_r_i_asi # ST= XA + NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index db09255854..74cf3105f0 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2162,7 +2162,7 @@ static void gen_helper_st_asi(TCGv_env e, TCGv a, TCG= v_i64 r, } #endif =20 -static void gen_ld_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv add= r) +static void gen_ld_asi(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr) { switch (da->type) { case GET_ASI_EXCP: @@ -2193,16 +2193,7 @@ static void gen_ld_asi0(DisasContext *dc, DisasASI *= da, TCGv dst, TCGv addr) } } =20 -static void __attribute__((unused)) -gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop) -{ - DisasASI da =3D get_asi(dc, insn, memop); - - gen_address_mask(dc, addr); - gen_ld_asi0(dc, &da, dst, addr); -} - -static void gen_st_asi0(DisasContext *dc, DisasASI *da, TCGv src, TCGv add= r) +static void gen_st_asi(DisasContext *dc, DisasASI *da, TCGv src, TCGv addr) { switch (da->type) { case GET_ASI_EXCP: @@ -2274,15 +2265,6 @@ static void gen_st_asi0(DisasContext *dc, DisasASI *= da, TCGv src, TCGv addr) } } =20 -static void __attribute__((unused)) -gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop) -{ - DisasASI da =3D get_asi(dc, insn, memop); - - gen_address_mask(dc, addr); - gen_st_asi0(dc, &da, src, addr); -} - static void gen_swap_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv src, TCGv addr) { @@ -2584,7 +2566,7 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, in= t size, int rd) } } =20 -static void gen_ldda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int r= d) +static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) { TCGv hi =3D gen_dest_gpr(dc, rd); TCGv lo =3D gen_dest_gpr(dc, rd + 1); @@ -2660,16 +2642,7 @@ static void gen_ldda_asi0(DisasContext *dc, DisasASI= *da, TCGv addr, int rd) gen_store_gpr(dc, rd + 1, lo); } =20 -static void __attribute__((unused)) -gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) -{ - DisasASI da =3D get_asi(dc, insn, MO_TEUQ); - - gen_address_mask(dc, addr); - gen_ldda_asi0(dc, &da, addr, rd); -} - -static void gen_stda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int r= d) +static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) { TCGv hi =3D gen_load_gpr(dc, rd); TCGv lo =3D gen_load_gpr(dc, rd + 1); @@ -2761,15 +2734,6 @@ static void gen_stda_asi0(DisasContext *dc, DisasASI= *da, TCGv addr, int rd) } } =20 -static void __attribute__((unused)) -gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd) -{ - DisasASI da =3D get_asi(dc, insn, MO_TEUQ); - - gen_address_mask(dc, addr); - gen_stda_asi0(dc, &da, addr, rd); -} - static TCGv get_src1(DisasContext *dc, unsigned int insn) { unsigned int rs1 =3D GET_FIELD(insn, 13, 17); @@ -4580,7 +4544,7 @@ static bool do_ld_gpr(DisasContext *dc, arg_r_r_ri_as= i *a, MemOp mop) da =3D resolve_asi(dc, a->asi, mop); =20 reg =3D gen_dest_gpr(dc, a->rd); - gen_ld_asi0(dc, &da, reg, addr); + gen_ld_asi(dc, &da, reg, addr); gen_store_gpr(dc, a->rd, reg); return advance_pc(dc); } @@ -4604,7 +4568,7 @@ static bool do_st_gpr(DisasContext *dc, arg_r_r_ri_as= i *a, MemOp mop) da =3D resolve_asi(dc, a->asi, mop); =20 reg =3D gen_load_gpr(dc, a->rd); - gen_st_asi0(dc, &da, reg, addr); + gen_st_asi(dc, &da, reg, addr); return advance_pc(dc); } =20 @@ -4626,7 +4590,7 @@ static bool trans_LDD(DisasContext *dc, arg_r_r_ri_as= i *a) return false; } da =3D resolve_asi(dc, a->asi, MO_TEUQ); - gen_ldda_asi0(dc, &da, addr, a->rd); + gen_ldda_asi(dc, &da, addr, a->rd); return advance_pc(dc); } =20 @@ -4643,7 +4607,7 @@ static bool trans_STD(DisasContext *dc, arg_r_r_ri_as= i *a) return false; } da =3D resolve_asi(dc, a->asi, MO_TEUQ); - gen_stda_asi0(dc, &da, addr, a->rd); + gen_stda_asi(dc, &da, addr, a->rd); return advance_pc(dc); } =20 @@ -5475,9 +5439,17 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) case 0x3: /* ldd, load double word */ case 0x9: /* ldsb, load signed byte */ case 0xa: /* ldsh, load signed halfword */ + case 0x10: /* lda, V9 lduwa, load word alternate */ + case 0x11: /* lduba, load unsigned byte alternate */ + case 0x12: /* lduha, load unsigned halfword alternate= */ + case 0x13: /* ldda, load double word alternate */ + case 0x19: /* ldsba, load signed byte alternate */ + case 0x1a: /* ldsha, load signed halfword alternate */ g_assert_not_reached(); /* in decodetree */ case 0x08: /* V9 ldsw */ case 0x0b: /* V9 ldx */ + case 0x18: /* V9 ldswa */ + case 0x1b: /* V9 ldxa */ goto illegal_insn; /* in decodetree */ case 0xd: /* ldstub */ gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx); @@ -5489,27 +5461,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) dc->mem_idx, MO_TEUL); break; #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) - case 0x10: /* lda, V9 lduwa, load word alternate */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL); - break; - case 0x11: /* lduba, load unsigned byte alternate */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_UB); - break; - case 0x12: /* lduha, load unsigned halfword alternate= */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW); - break; - case 0x13: /* ldda, load double word alternate */ - if (rd & 1) { - goto illegal_insn; - } - gen_ldda_asi(dc, cpu_addr, insn, rd); - goto skip_move; - case 0x19: /* ldsba, load signed byte alternate */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_SB); - break; - case 0x1a: /* ldsha, load signed halfword alternate */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESW); - break; case 0x1d: /* ldstuba -- XXX: should be atomically */ gen_ldstub_asi(dc, cpu_val, cpu_addr, insn); break; @@ -5520,12 +5471,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) break; #endif #ifdef TARGET_SPARC64 - case 0x18: /* V9 ldswa */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL); - break; - case 0x1b: /* V9 ldxa */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ); - break; case 0x2d: /* V9 prefetch, no effect */ goto skip_move; case 0x30: /* V9 ldfa */ @@ -5557,7 +5502,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) goto illegal_insn; } gen_store_gpr(dc, rd, cpu_val); -#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) +#if defined(TARGET_SPARC64) skip_move: ; #endif } else if (xop >=3D 0x20 && xop < 0x24) { @@ -5610,45 +5555,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) default: goto illegal_insn; } - } else if (xop < 8 || (xop >=3D 0x14 && xop < 0x18) || - xop =3D=3D 0xe || xop =3D=3D 0x1e) { -#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) - TCGv cpu_val =3D gen_load_gpr(dc, rd); -#endif - - switch (xop) { - case 0x4: /* st, store word */ - case 0x5: /* stb, store byte */ - case 0x6: /* sth, store halfword */ - case 0x7: /* std, store double word */ - g_assert_not_reached(); /* in decodetree */ - case 0x0e: /* V9 stx */ - goto illegal_insn; /* in decodetree */ -#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) - case 0x14: /* sta, V9 stwa, store word alternate */ - gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL); - break; - case 0x15: /* stba, store byte alternate */ - gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_UB); - break; - case 0x16: /* stha, store halfword alternate */ - gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW); - break; - case 0x17: /* stda, store double word alternate */ - if (rd & 1) { - goto illegal_insn; - } - gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd); - break; -#endif -#ifdef TARGET_SPARC64 - case 0x1e: /* V9 stxa */ - gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ); - break; -#endif - default: - goto illegal_insn; - } } else if (xop > 0x23 && xop < 0x28) { if (gen_trap_ifnofpu(dc)) { goto jmp_insn; --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280745; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.22.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:22:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279773; x=1698884573; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nqsLsbZVjs5bsqoicc0u3zyho9ONy37FphIeA4eEfCQ=; b=tfxCLzm1fIWtzRf4/Acfgx+RKwWjjBDj5tET08Xas5ou/UfNIGoFks2T2RT5sLfltK 7KBH3BexSIeXIfoIEjTymaKnwh3h9lHn5Q2BnBc39VVHABL+Y7TKEiBiVmLboVfzUt/i uqLxfidZf3QliXWVi8LdhgdC8by280e679S3HLtEG+iRG9OzUirwrU6Ly9qr/3I+3WSP VW7cvcwO7Sh3I2Q/3+MfMFy0oJjkIJ1LrOJUcvbqiBfYo4AWPJXobtV4Y088D9xpoccM imamLYlzOo0r9mFQzHNdTPmecDw5xTXIVoeYx/cMfh41AQn8vo/i4C1caNsvxrF/uu4d wrdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279773; x=1698884573; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nqsLsbZVjs5bsqoicc0u3zyho9ONy37FphIeA4eEfCQ=; b=WnGeDXBZKD3g2ifeYus0s34VeIVThq25VBl4hEOma9luP2nZDzcBhHKHZ2AEigp3Vr 13/vhjiVmlnUysmyEvmE1+Xy1JRyZoWFBpqRgzs/TDnJRiBl6jNWCuOu7AZ00MhbuYOq 2JEnJNKJtlNQAtUHlwszSPEr5Lpu+PRyfZ8A+YJ4NKm9VMk2Lx+8tXgtntvwgTi6sbml crHtyb5Hxbfyc1GjC85ogshQBVAcBQJ8foL9sL2phgqOpm1S1SlS6TlrrM9O7Z55M0z1 oSiJ9iLaFU9aoPP0CvjGpMdlmTestJtWW9DOGw5hPSYpMr+r0koNAupMNvNfpgtv8clU 5sRQ== X-Gm-Message-State: AOJu0YwISHPVpXiNRvnvHFYB/dETsO/9uBHrSKut3zF/hW4KtkUC8EcS OWDLjS7lseF5j1kKmi1/e5sFCy0N/vF4uMrNPpg= X-Google-Smtp-Source: AGHT+IGu7BKgUgPJ36kjma5DB762KjSXaM6IU+mgidUwr0XNVn4dc+MOYaMnzCL3ks3mrDIyODDjzg== X-Received: by 2002:a17:90a:1c8:b0:27d:6dd:fb7d with SMTP id 8-20020a17090a01c800b0027d06ddfb7dmr17544975pjd.17.1698279772817; Wed, 25 Oct 2023 17:22:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 54/94] target/sparc: Move LDSTUB, LDSTUBA to decodetree Date: Wed, 25 Oct 2023 17:15:02 -0700 Message-Id: <20231026001542.1141412-84-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280746474100003 Content-Type: text/plain; charset="utf-8" Remove gen_ldstub_asi. Rename gen_ldstub_asi0 to gen_ldstub_asi. Merge gen_ldstub into gen_ldstub_asi. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++++ target/sparc/translate.c | 46 +++++++++++++++++++-------------------- 2 files changed, 26 insertions(+), 24 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 280b19f033..2f950000b5 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -284,6 +284,10 @@ STD 11 ..... 010111 ..... . ............. = @r_r_i_asi # STDA STX 11 ..... 011110 ..... . ............. @r_r_r_asi # ST= XA STX 11 ..... 011110 ..... . ............. @r_r_i_asi # ST= XA =20 +LDSTUB 11 ..... 001101 ..... . ............. @r_r_ri_na +LDSTUB 11 ..... 011101 ..... . ............. @r_r_r_asi # LD= STUBA +LDSTUB 11 ..... 011101 ..... . ............. @r_r_i_asi # LD= STUBA + NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 74cf3105f0..ddfb76af68 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1892,13 +1892,6 @@ static void gen_swap(DisasContext *dc, TCGv dst, TCG= v src, tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop | MO_ALIGN); } =20 -static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx) -{ - TCGv m1 =3D tcg_constant_tl(0xff); - gen_address_mask(dc, addr); - tcg_gen_atomic_xchg_tl(dst, addr, m1, mmu_idx, MO_UB); -} - /* asi moves */ typedef enum { GET_ASI_HELPER, @@ -2331,13 +2324,14 @@ gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv= , int insn, int rd) gen_store_gpr(dc, rd, oldv); } =20 -static void gen_ldstub_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv= addr) +static void gen_ldstub_asi(DisasContext *dc, DisasASI *da, TCGv dst, TCGv = addr) { switch (da->type) { case GET_ASI_EXCP: break; case GET_ASI_DIRECT: - gen_ldstub(dc, dst, addr, da->mem_idx); + tcg_gen_atomic_xchg_tl(dst, addr, tcg_constant_tl(0xff), + da->mem_idx, MO_UB); break; default: /* ??? In theory, this should be raise DAE_invalid_asi. @@ -2365,15 +2359,6 @@ static void gen_ldstub_asi0(DisasContext *dc, DisasA= SI *da, TCGv dst, TCGv addr) } } =20 -static void __attribute__((unused)) -gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) -{ - DisasASI da =3D get_asi(dc, insn, MO_UB); - - gen_address_mask(dc, addr); - gen_ldstub_asi0(dc, &da, dst, addr); -} - static void __attribute__((unused)) gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) { @@ -4611,6 +4596,23 @@ static bool trans_STD(DisasContext *dc, arg_r_r_ri_a= si *a) return advance_pc(dc); } =20 +static bool trans_LDSTUB(DisasContext *dc, arg_r_r_ri_asi *a) +{ + TCGv addr, reg; + DisasASI da; + + addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + if (addr =3D=3D NULL) { + return false; + } + da =3D resolve_asi(dc, a->asi, MO_UB); + + reg =3D gen_dest_gpr(dc, a->rd); + gen_ldstub_asi(dc, &da, reg, addr); + gen_store_gpr(dc, a->rd, reg); + return advance_pc(dc); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5439,21 +5441,20 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 0x3: /* ldd, load double word */ case 0x9: /* ldsb, load signed byte */ case 0xa: /* ldsh, load signed halfword */ + case 0xd: /* ldstub */ case 0x10: /* lda, V9 lduwa, load word alternate */ case 0x11: /* lduba, load unsigned byte alternate */ case 0x12: /* lduha, load unsigned halfword alternate= */ case 0x13: /* ldda, load double word alternate */ case 0x19: /* ldsba, load signed byte alternate */ case 0x1a: /* ldsha, load signed halfword alternate */ + case 0x1d: /* ldstuba */ g_assert_not_reached(); /* in decodetree */ case 0x08: /* V9 ldsw */ case 0x0b: /* V9 ldx */ case 0x18: /* V9 ldswa */ case 0x1b: /* V9 ldxa */ goto illegal_insn; /* in decodetree */ - case 0xd: /* ldstub */ - gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx); - break; case 0x0f: /* swap, swap register with memory. Also atomically */ cpu_src1 =3D gen_load_gpr(dc, rd); @@ -5461,9 +5462,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) dc->mem_idx, MO_TEUL); break; #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) - case 0x1d: /* ldstuba -- XXX: should be atomically */ - gen_ldstub_asi(dc, cpu_val, cpu_addr, insn); - break; case 0x1f: /* swapa, swap reg with alt. memory. Also atomically */ cpu_src1 =3D gen_load_gpr(dc, rd); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280544; cv=none; d=zohomail.com; s=zohoarc; b=SeQYa3gZiJTYZ7g6fL3MBiv7s9GD/Q72dOw4wt43Xbg5ZBW9/9CwxkYrpaF6RTHICI9kefoJYziId5mLVYgOjAqAnXK3WVNZMSeEUUOPJicu4ULlaL2dvooUg5udEzkaozomS0LCIPmjx4IIdNskg5i4p0ElBJDMLjktZzUab2Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280544; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1RBMEZdckkbOemPC0F9coR5p32iULbwwkWkdlHi6JSU=; b=PoK4sAERg7tKz07pdoIv+auXjQNBMDKHo3dXXGVk7uarcKT4Js4YAuCBUzSF3lA82eoThuqyZQKX5QhoLUdgYgqZdQTEUIq99Qm/+KSE+bf/e6O/RJthm5GU8Zeg486qUEWp47xR9s+C44rAFyN0+TbT8BQrksimUygyfCkGFRQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169828054482461.006267006041526; Wed, 25 Oct 2023 17:35:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo9Y-00028r-Tz; Wed, 25 Oct 2023 20:23:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo9K-000089-Md for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:22:58 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo9H-0008Aq-1a for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:22:58 -0400 Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-5b8c39a2dceso289862a12.2 for ; Wed, 25 Oct 2023 17:22:54 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.22.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:22:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279774; x=1698884574; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1RBMEZdckkbOemPC0F9coR5p32iULbwwkWkdlHi6JSU=; b=hCcH9BPOgSeQTwnClbaqyRCUKu1OseqLLd8elqSw/71hX3zIMZZt8bnIQxJCroKqxM jQkVZ3Fe7jmmpWKPZJvq9y0Byt+Ra9JFNb8uRPFyqQq490UgF6sLwIWEYy6WzbmXMzrC FBW3hMEFD6h+DpwaKRrrLKXRW5rVqfURSC6+8bA6AEJ2NzCH0UmBO4bviUmov1juq9VL a/ZvWjfUgX10G5ALQtPvIw4Nn/VjEY5oYECrYrEkgna+pjDogHwoel2GcdfRaN0gmsW1 EX8NINatqyPXXXHnN8VTwZKJpzMuPfC0mJTAkgYVGe5tot7O3+XfKTZblSXwkhIpWjoO efKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279774; x=1698884574; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1RBMEZdckkbOemPC0F9coR5p32iULbwwkWkdlHi6JSU=; b=tV/H+3lHFvlcU/lEHrx/rQRAqW6C5otXRLqo1uFZC2SdzkK+KbH4CDzb3BVazVfpl2 6zRBGXaojkltJ6vvzOioORHw4n2qMIPxo0KBq+RVQZle1rHhet3OtMVWQMc3GlrK7QBo kd/HpRpjjQ2VVClRz02uwq4/6lBC+oYkpy8fY++mys3xJ4v6vsHyspHf+2L7fVlxszEl 6c8hZG7Z9f5II1SKyvDa33lnJcY5YFd8AbedaWV4zMPur+cNaIN+CC3VQXBeBCxeypkz 2Qzy0oAdlE0rDjlVcRCR3YfKSEzgnmv/wRkl5aFG4hFRjzzHEOMekwXxax+8uatqeMSd prsQ== X-Gm-Message-State: AOJu0YyM7LIW0Zrz0DtwK0BwHFKJVb83ufSl40MN9rkost+YCtiuafa0 1m696cq1JSa78BhCVH10FhpO+4epbMtAQPxei0M= X-Google-Smtp-Source: AGHT+IG4zjA0HMJFhngQT5J4wGcfuiidkoNXh2E2MnCcfqInBxWYfZ7TZo6JWiTIe7qRo95CfXw0XQ== X-Received: by 2002:a17:90a:1996:b0:27c:fa10:fc82 with SMTP id 22-20020a17090a199600b0027cfa10fc82mr14254516pji.28.1698279773734; Wed, 25 Oct 2023 17:22:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 55/94] target/sparc: Move SWAP, SWAPA to decodetree Date: Wed, 25 Oct 2023 17:15:03 -0700 Message-Id: <20231026001542.1141412-85-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280545845100003 Content-Type: text/plain; charset="utf-8" Remove gen_swap_asi. Rename gen_swap_asi0 to gen_swap_asi. Merge gen_swap into gen_swap_asi. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 58 +++++++++++++++++---------------------- 2 files changed, 29 insertions(+), 33 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 2f950000b5..9c4597317c 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -288,6 +288,10 @@ LDSTUB 11 ..... 001101 ..... . ............. = @r_r_ri_na LDSTUB 11 ..... 011101 ..... . ............. @r_r_r_asi # LD= STUBA LDSTUB 11 ..... 011101 ..... . ............. @r_r_i_asi # LD= STUBA =20 +SWAP 11 ..... 001111 ..... . ............. @r_r_ri_na +SWAP 11 ..... 011111 ..... . ............. @r_r_r_asi # SW= APA +SWAP 11 ..... 011111 ..... . ............. @r_r_i_asi # SW= APA + NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ddfb76af68..29bfc98522 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1885,13 +1885,6 @@ static void gen_ne_fop_QD(DisasContext *dc, int rd, = int rs, gen_update_fprs_dirty(dc, QFPREG(rd)); } =20 -static void gen_swap(DisasContext *dc, TCGv dst, TCGv src, - TCGv addr, int mmu_idx, MemOp memop) -{ - gen_address_mask(dc, addr); - tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop | MO_ALIGN); -} - /* asi moves */ typedef enum { GET_ASI_HELPER, @@ -2258,14 +2251,15 @@ static void gen_st_asi(DisasContext *dc, DisasASI *= da, TCGv src, TCGv addr) } } =20 -static void gen_swap_asi0(DisasContext *dc, DisasASI *da, - TCGv dst, TCGv src, TCGv addr) +static void gen_swap_asi(DisasContext *dc, DisasASI *da, + TCGv dst, TCGv src, TCGv addr) { switch (da->type) { case GET_ASI_EXCP: break; case GET_ASI_DIRECT: - gen_swap(dc, dst, src, addr, da->mem_idx, da->memop); + tcg_gen_atomic_xchg_tl(dst, addr, src, + da->mem_idx, da->memop | MO_ALIGN); break; default: /* ??? Should be DAE_invalid_asi. */ @@ -2274,15 +2268,6 @@ static void gen_swap_asi0(DisasContext *dc, DisasASI= *da, } } =20 -static void __attribute__((unused)) -gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, TCGv addr, int insn) -{ - DisasASI da =3D get_asi(dc, insn, MO_TEUL); - - gen_address_mask(dc, addr); - gen_swap_asi0(dc, &da, dst, src, addr); -} - static void gen_cas_asi0(DisasContext *dc, DisasASI *da, TCGv oldv, TCGv newv, TCGv cmpv, TCGv addr) { @@ -4613,6 +4598,24 @@ static bool trans_LDSTUB(DisasContext *dc, arg_r_r_r= i_asi *a) return advance_pc(dc); } =20 +static bool trans_SWAP(DisasContext *dc, arg_r_r_ri_asi *a) +{ + TCGv addr, dst, src; + DisasASI da; + + addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + if (addr =3D=3D NULL) { + return false; + } + da =3D resolve_asi(dc, a->asi, MO_TEUL); + + dst =3D gen_dest_gpr(dc, a->rd); + src =3D gen_load_gpr(dc, a->rd); + gen_swap_asi(dc, &da, dst, src, addr); + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4624,7 +4627,7 @@ static bool trans_LDSTUB(DisasContext *dc, arg_r_r_ri= _asi *a) static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) { unsigned int opc, rs1, rs2, rd; - TCGv cpu_src1; + TCGv cpu_src1 __attribute__((unused)); TCGv cpu_src2 __attribute__((unused)); TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32; TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64; @@ -5442,6 +5445,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) case 0x9: /* ldsb, load signed byte */ case 0xa: /* ldsh, load signed halfword */ case 0xd: /* ldstub */ + case 0x0f: /* swap */ case 0x10: /* lda, V9 lduwa, load word alternate */ case 0x11: /* lduba, load unsigned byte alternate */ case 0x12: /* lduha, load unsigned halfword alternate= */ @@ -5449,25 +5453,13 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 0x19: /* ldsba, load signed byte alternate */ case 0x1a: /* ldsha, load signed halfword alternate */ case 0x1d: /* ldstuba */ + case 0x1f: /* swapa */ g_assert_not_reached(); /* in decodetree */ case 0x08: /* V9 ldsw */ case 0x0b: /* V9 ldx */ case 0x18: /* V9 ldswa */ case 0x1b: /* V9 ldxa */ goto illegal_insn; /* in decodetree */ - case 0x0f: - /* swap, swap register with memory. Also atomically */ - cpu_src1 =3D gen_load_gpr(dc, rd); - gen_swap(dc, cpu_val, cpu_src1, cpu_addr, - dc->mem_idx, MO_TEUL); - break; -#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) - case 0x1f: /* swapa, swap reg with alt. memory. Also - atomically */ - cpu_src1 =3D gen_load_gpr(dc, rd); - gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn); - break; -#endif #ifdef TARGET_SPARC64 case 0x2d: /* V9 prefetch, no effect */ goto skip_move; --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280700; cv=none; d=zohomail.com; s=zohoarc; b=Ho9MZBYfMQaoxs1mBjjzInNTpf+yZu2BuZR/UTYF7QUiA7nOso5DhNpXjZU5QZOYRCyyFyZjjuG0vEDfLYMYahChGNQNiSTwTjuJoU7zCXZlGvg2eM48GUGBGHryNw7t0BGTano01bLXx6GrhV/avxtw2mMilvZa71aZLykqVK8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280700; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=BibC+DRs59nbFE1Ls41U4uh2VUfxNEDa0ycsD8PCaHk=; b=ahE6uBKrRwitAjdmWrako8lxAmr/+TqgYb1bpMDT1BWqaGSogmgTvfFdaDzo/N+RvSIKlOrw1MZfxiDb+0O4allGYgB0WQM006qQixcJwwxlhTq/vHvjxWr2jrPj0QBlr0mpRoPkXwIOqM9yzqQSr0T/8AnwWDmKRKth1cKNk0I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698280700051320.1182203536348; Wed, 25 Oct 2023 17:38:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo9N-0000bG-M4; Wed, 25 Oct 2023 20:23:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo9L-0000Db-4B for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:22:59 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo9I-0008BF-2I for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:22:58 -0400 Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-27d1a03f540so242336a91.1 for ; Wed, 25 Oct 2023 17:22:55 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.22.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:22:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279774; x=1698884574; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BibC+DRs59nbFE1Ls41U4uh2VUfxNEDa0ycsD8PCaHk=; b=kVlnxQXrX/1PUJZ1ScHRxpW5gu1qlG3lxCNp6v1lFMp2Zfm54FvcpSErCRnrFAwQuD gtZnB6xLJsxA2PNHAwBucPp77sm+h+cvoHF8I5BbBO352Tpgca7lLPaoTPqxqfc+FRTh ep5aISm00WEaptsSWKD0W1C3jVlPC5nFCMRX1UPfsEP27l8m8fa5pC+4+PTMhSmirIzA d/hqo/xmXbGW5Obw4+iB2fpJp7Xlv2sWdBJB+mxrs6SqLgunNBkqX3B2mWg+TkKS/FEX fVLYKOH4fvo+0DNE+08bQ1ZUvN1MYxqSF3lHewdSGOa0vKwWqwIo0f5m1o2bB041zRos 13iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279774; x=1698884574; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BibC+DRs59nbFE1Ls41U4uh2VUfxNEDa0ycsD8PCaHk=; b=RBd2+YXTAwczY1D+tgsoxFEwMUcGZa2jRRM9fKItWQiDu5SoxksOu7OUL1zJLEhihz 9mpX5y51kNKl6H60a8uWK9Won+Vck/4XRmsnzG4zfsIecLS6zWAiV243RLkDmdCk2nyN Sjno05BLqxo8+oxlHmhZRnUA+DIdNr2PK5WWXHgtD6+jab9ebH4L/xv+rWAfK1fhvJM4 rOW06rmVuvbtJDaBA+Rj2z7waUgRCdWRoQ7ACh3R7ufGQfgvnGUGiOghXaKj7/TIOnh3 u3qn9Yyl5/2yz0iTQ7IeFHTqygjYoKb4SgWrvR6r8WLilvuJ5VtbeO6OAmBDdSGSSr82 dcTg== X-Gm-Message-State: AOJu0YxjAuhT/hQZqLZ5lTda+yiXJ1L7+WrVJSRuBXRsQhOMW2hC8J7n irInrgXczwww+0PJ0lO/Z1/bYJ/a4NSipOvlxOE= X-Google-Smtp-Source: AGHT+IEDdYqqF/FHIb87lEISdqFdjL9FeXa4EFeruW0kpzrWlzTyETEpRwH6Yld34mDvILwXTS3Zdg== X-Received: by 2002:a17:90b:1016:b0:27d:23f1:ddf5 with SMTP id gm22-20020a17090b101600b0027d23f1ddf5mr13425605pjb.30.1698279774430; Wed, 25 Oct 2023 17:22:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 56/94] target/sparc: Move CASA, CASXA to decodetree Date: Wed, 25 Oct 2023 17:15:04 -0700 Message-Id: <20231026001542.1141412-86-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280700233100005 Content-Type: text/plain; charset="utf-8" Remove gen_cas_asi, gen_casx_asi. Rename gen_cas_asi0 to gen_cas_asi. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 7 ++++ target/sparc/translate.c | 72 ++++++++++++++++----------------------- 2 files changed, 36 insertions(+), 43 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 9c4597317c..82c484fbc7 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -240,6 +240,8 @@ RETRY 10 00001 111110 00000 0 0000000000000 @r_r_r_asi .. rd:5 ...... rs1:5 0 asi:8 rs2_or_imm:5 &r_r_ri_asi imm= =3D0 @r_r_i_asi .. rd:5 ...... rs1:5 1 rs2_or_imm:s13 \ &r_r_ri_asi imm=3D1 asi=3D-2 +@casa_imm .. rd:5 ...... rs1:5 1 00000000 rs2_or_imm:5 \ + &r_r_ri_asi imm=3D1 asi=3D-2 =20 LDUW 11 ..... 000000 ..... . ............. @r_r_ri_na LDUB 11 ..... 000001 ..... . ............. @r_r_ri_na @@ -292,6 +294,11 @@ SWAP 11 ..... 001111 ..... . ............. = @r_r_ri_na SWAP 11 ..... 011111 ..... . ............. @r_r_r_asi # SW= APA SWAP 11 ..... 011111 ..... . ............. @r_r_i_asi # SW= APA =20 +CASA 11 ..... 111100 ..... . ............. @r_r_r_asi +CASA 11 ..... 111100 ..... . ............. @casa_imm +CASXA 11 ..... 111110 ..... . ............. @r_r_r_asi +CASXA 11 ..... 111110 ..... . ............. @casa_imm + NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 29bfc98522..2175c00ded 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2268,8 +2268,8 @@ static void gen_swap_asi(DisasContext *dc, DisasASI *= da, } } =20 -static void gen_cas_asi0(DisasContext *dc, DisasASI *da, - TCGv oldv, TCGv newv, TCGv cmpv, TCGv addr) +static void gen_cas_asi(DisasContext *dc, DisasASI *da, + TCGv oldv, TCGv newv, TCGv cmpv, TCGv addr) { switch (da->type) { case GET_ASI_EXCP: @@ -2285,30 +2285,6 @@ static void gen_cas_asi0(DisasContext *dc, DisasASI = *da, } } =20 -static void __attribute__((unused)) -gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) -{ - DisasASI da =3D get_asi(dc, insn, MO_TEUL); - TCGv oldv =3D gen_dest_gpr(dc, rd); - TCGv newv =3D gen_load_gpr(dc, rd); - - gen_address_mask(dc, addr); - gen_cas_asi0(dc, &da, oldv, newv, cmpv, addr); - gen_store_gpr(dc, rd, oldv); -} - -static void __attribute__((unused)) -gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) -{ - DisasASI da =3D get_asi(dc, insn, MO_TEUQ); - TCGv oldv =3D gen_dest_gpr(dc, rd); - TCGv newv =3D gen_load_gpr(dc, rd); - - gen_address_mask(dc, addr); - gen_cas_asi0(dc, &da, oldv, newv, cmpv, addr); - gen_store_gpr(dc, rd, oldv); -} - static void gen_ldstub_asi(DisasContext *dc, DisasASI *da, TCGv dst, TCGv = addr) { switch (da->type) { @@ -2913,6 +2889,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s= 1, TCGv s2) #ifdef TARGET_SPARC64 # define avail_32(C) false # define avail_ASR17(C) false +# define avail_CASA(C) true # define avail_DIV(C) true # define avail_MUL(C) true # define avail_POWERDOWN(C) false @@ -2922,6 +2899,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s= 1, TCGv s2) #else # define avail_32(C) true # define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17) +# define avail_CASA(C) ((C)->def->features & CPU_FEATURE_CASA) # define avail_DIV(C) ((C)->def->features & CPU_FEATURE_DIV) # define avail_MUL(C) ((C)->def->features & CPU_FEATURE_MUL) # define avail_POWERDOWN(C) ((C)->def->features & CPU_FEATURE_POWERDOWN) @@ -4616,6 +4594,28 @@ static bool trans_SWAP(DisasContext *dc, arg_r_r_ri_= asi *a) return advance_pc(dc); } =20 +static bool do_casa(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) +{ + TCGv addr, o, n, c; + DisasASI da; + + addr =3D gen_ldst_addr(dc, a->rs1, true, 0); + if (addr =3D=3D NULL) { + return false; + } + da =3D resolve_asi(dc, a->asi, mop); + + o =3D gen_dest_gpr(dc, a->rd); + n =3D gen_load_gpr(dc, a->rd); + c =3D gen_load_gpr(dc, a->rs2_or_imm); + gen_cas_asi(dc, &da, o, n, c, addr); + gen_store_gpr(dc, a->rd, o); + return advance_pc(dc); +} + +TRANS(CASA, CASA, do_casa, a, MO_TEUL) +TRANS(CASXA, 64, do_casa, a, MO_TEUQ) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5419,9 +5419,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) TCGv cpu_addr =3D tcg_temp_new(); =20 tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn)); - if (xop =3D=3D 0x3c || xop =3D=3D 0x3e) { - /* V9 casa/casxa : no offset */ - } else if (IS_IMM) { /* immediate */ + if (IS_IMM) { /* immediate */ simm =3D GET_FIELDs(insn, 19, 31); if (simm !=3D 0) { tcg_gen_addi_tl(cpu_addr, cpu_addr, simm); @@ -5634,22 +5632,10 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) } gen_stf_asi(dc, cpu_addr, insn, 8, DFPREG(rd)); break; +#endif case 0x3e: /* V9 casxa */ - rs2 =3D GET_FIELD(insn, 27, 31); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd); - break; -#endif -#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x3c: /* V9 or LEON3 casa */ -#ifndef TARGET_SPARC64 - CHECK_IU_FEATURE(dc, CASA); -#endif - rs2 =3D GET_FIELD(insn, 27, 31); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd); - break; -#endif + goto illegal_insn; /* in decodetree */ default: goto illegal_insn; } --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280175717100008 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 8 ++++++-- target/sparc/translate.c | 23 ++++++++--------------- 2 files changed, 14 insertions(+), 17 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 82c484fbc7..aa452f1d00 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -231,6 +231,9 @@ RESTORE 10 ..... 111101 ..... . ............. = @r_r_ri DONE 10 00000 111110 00000 0 0000000000000 RETRY 10 00001 111110 00000 0 0000000000000 =20 +NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 +NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 + ## ## Major Opcode 11 -- load and store instructions ## @@ -299,8 +302,9 @@ CASA 11 ..... 111100 ..... . ............. = @casa_imm CASXA 11 ..... 111110 ..... . ............. @r_r_r_asi CASXA 11 ..... 111110 ..... . ............. @casa_imm =20 -NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 -NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 +NOP_v9 11 ----- 101101 ----- 0 00000000 ----- # PREFETCH +NOP_v9 11 ----- 101101 ----- 1 ------------- # PREFETCH +NOP_v9 11 ----- 111101 ----- - ------------- # PREFETCHA =20 NCP 11 ----- 110000 ----- --------- ----- # v8 LDC NCP 11 ----- 110001 ----- --------- ----- # v8 LDCSR diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 2175c00ded..363d8b7fc8 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4031,17 +4031,12 @@ static bool trans_NOP(DisasContext *dc, arg_NOP *a) return advance_pc(dc); } =20 -static bool trans_NOP_v7(DisasContext *dc, arg_NOP_v7 *a) -{ - /* - * TODO: Need a feature bit for sparcv8. - * In the meantime, treat all 32-bit cpus like sparcv7. - */ - if (avail_32(dc)) { - return advance_pc(dc); - } - return false; -} +/* + * TODO: Need a feature bit for sparcv8. + * In the meantime, treat all 32-bit cpus like sparcv7. + */ +TRANS(NOP_v7, 32, trans_NOP, a) +TRANS(NOP_v9, 64, trans_NOP, a) =20 static bool do_arith_int(DisasContext *dc, arg_r_r_ri_cc *a, int cc_op, void (*func)(TCGv, TCGv, TCGv), @@ -5457,10 +5452,10 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 0x0b: /* V9 ldx */ case 0x18: /* V9 ldswa */ case 0x1b: /* V9 ldxa */ + case 0x2d: /* V9 prefetch */ + case 0x3d: /* V9 prefetcha */ goto illegal_insn; /* in decodetree */ #ifdef TARGET_SPARC64 - case 0x2d: /* V9 prefetch, no effect */ - goto skip_move; case 0x30: /* V9 ldfa */ if (gen_trap_ifnofpu(dc)) { goto jmp_insn; @@ -5475,8 +5470,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd)); gen_update_fprs_dirty(dc, DFPREG(rd)); goto skip_move; - case 0x3d: /* V9 prefetcha, no effect */ - goto skip_move; case 0x32: /* V9 ldqfa */ CHECK_FPU_FEATURE(dc, FLOAT128); if (gen_trap_ifnofpu(dc)) { --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280279; cv=none; d=zohomail.com; s=zohoarc; b=NF7nI2HhLtxiRPXibi7qBEP058wS7WwnPwZORvQPCZhDfwpaY4mDierd0MbECKCFzGQhT0n9T86G5mIAlPHVyRJopeaqRTHrMnp+Jy3oV/bJpb9HcJLnUBC2gG0VL9se9Qcypwo65NsDPuUd962uKK0Q8pf8aw20xaQn1btBiZY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280279; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:22:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279776; x=1698884576; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MS8CtSutyWAJAksCJoGHPpSo/oeGceEkhH07ubL3sMY=; b=BygX+Jj9NP+IVqkgQagfv+J67MDHAtp6KEeb+RNQfDj0OXEKauQtg/QaFHkIPh6f7M rgM4f1mT+c37T3gEduVYzLuu0xlB1RaXFLvjPY87mlhHLlUsmz7ozt79KvXVf2uWVNFk /zTnOCtIDU5EMKhP1VD0Wr1yk0PQzFlLNBM05UIg6xfQI2XOvHQoYr6HxCdKVG1HJOfw uA45yGmZK+pDLpukjqOoMiuLSBDdUPg7HkaBlAwGdNYlDVmfM0BGDhGY9qmbFHUmDG29 QLpYIyDGmJV+uJxdwQ4JUfjEuFDTjCeLOkOeTJpYyUBfoQWRdZGS5fHejq1Ld6ERYjyr 58nA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279776; x=1698884576; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MS8CtSutyWAJAksCJoGHPpSo/oeGceEkhH07ubL3sMY=; b=htAxAL9rnWA/LSQplEvByUnlz3RMdsuXHNapksK+sFFlhTusssobbV75shmh9hTDW6 +RfoMrVII+92dRp7U/IHYmO9jx8iNWuEgZzD+SG9r9Ash+m8MqIIffc/lCDX0vzvAw/I uliekMx5+l/EvyiIUH8GG/ZeXsPm3wL1Wot9At9limPR1g+iUTRcG6pnjuVOvTWaeOC1 rQq8qiyvtNOqvEw8z71w2fCo/PFYwkm8tArKYvRmvF2VyytzLl8Rm4tCXX9ymDQj81zu LyP+F5uAD525lcDhhV+ouMwsA+ajMoGY8+zxl9JhJ8LBen5l7S5nXuw5n2VZXv1rnsAQ pnZg== X-Gm-Message-State: AOJu0YxRiKrP6hAxumU//O0lvtXRGeiZDlgeun2wMD/emgTAZelJTwSu rPss/opH3Y+iBDrzbgCHqcxplFxRtvvKSmxEnbE= X-Google-Smtp-Source: AGHT+IFDacrXp5DWghQ2gKumDQebG2jRrcGn2iZGQMydEZAYRgTZo08L0COJaIOkuc4ZLg17rhnVGg== X-Received: by 2002:a17:90b:1093:b0:27d:2c3c:7e25 with SMTP id gj19-20020a17090b109300b0027d2c3c7e25mr14823515pjb.46.1698279776085; Wed, 25 Oct 2023 17:22:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 58/94] target/sparc: Split out fp ldst functions with asi precomputed Date: Wed, 25 Oct 2023 17:15:06 -0700 Message-Id: <20231026001542.1141412-88-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280279935100001 Content-Type: text/plain; charset="utf-8" Take the operation size from the MemOp instead of a separate parameter. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 138 +++++++++++++++++++++++---------------- 1 file changed, 80 insertions(+), 58 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 363d8b7fc8..55d6f83736 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2320,35 +2320,41 @@ static void gen_ldstub_asi(DisasContext *dc, DisasA= SI *da, TCGv dst, TCGv addr) } } =20 -static void __attribute__((unused)) -gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) +static void gen_ldf_asi0(DisasContext *dc, DisasASI *da, MemOp orig_size, + TCGv addr, int rd) { - DisasASI da =3D get_asi(dc, insn, (size =3D=3D 4 ? MO_TEUL : MO_TEUQ)); + MemOp memop =3D da->memop; + MemOp size =3D memop & MO_SIZE; TCGv_i32 d32; TCGv_i64 d64; =20 - switch (da.type) { + /* TODO: Use 128-bit load/store below. */ + if (size =3D=3D MO_128) { + memop =3D (memop & ~MO_SIZE) | MO_64; + } + + switch (da->type) { case GET_ASI_EXCP: break; =20 case GET_ASI_DIRECT: - gen_address_mask(dc, addr); + memop |=3D MO_ALIGN_4; switch (size) { - case 4: + case MO_32: d32 =3D gen_dest_fpr_F(dc); - tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN= ); + tcg_gen_qemu_ld_i32(d32, addr, da->mem_idx, memop); gen_store_fpr_F(dc, rd, d32); break; - case 8: - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, - da.memop | MO_ALIGN_4); + + case MO_64: + tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da->mem_idx, memop); break; - case 16: + + case MO_128: d64 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(d64, addr, da.mem_idx, da.memop | MO_ALIGN= _4); + tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, - da.memop | MO_ALIGN_4); + tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + 1], addr, da->mem_idx, me= mop); tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); break; default: @@ -2358,24 +2364,19 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, = int size, int rd) =20 case GET_ASI_BLOCK: /* Valid for lddfa on aligned registers only. */ - if (size =3D=3D 8 && (rd & 7) =3D=3D 0) { - MemOp memop; + if (orig_size =3D=3D MO_64 && (rd & 7) =3D=3D 0) { TCGv eight; int i; =20 - gen_address_mask(dc, addr); - /* The first operation checks required alignment. */ - memop =3D da.memop | MO_ALIGN_64; eight =3D tcg_constant_tl(8); for (i =3D 0; ; ++i) { - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, - da.mem_idx, memop); + tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx, + memop | (i =3D=3D 0 ? MO_ALIGN_64 : 0)= ); if (i =3D=3D 7) { break; } tcg_gen_add_tl(addr, addr, eight); - memop =3D da.memop; } } else { gen_exception(dc, TT_ILL_INSN); @@ -2384,10 +2385,9 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, i= nt size, int rd) =20 case GET_ASI_SHORT: /* Valid for lddfa only. */ - if (size =3D=3D 8) { - gen_address_mask(dc, addr); - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, - da.memop | MO_ALIGN); + if (orig_size =3D=3D MO_64) { + tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da->mem_idx, + memop | MO_ALIGN); } else { gen_exception(dc, TT_ILL_INSN); } @@ -2395,8 +2395,8 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, in= t size, int rd) =20 default: { - TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); - TCGv_i32 r_mop =3D tcg_constant_i32(da.memop | MO_ALIGN); + TCGv_i32 r_asi =3D tcg_constant_i32(da->asi); + TCGv_i32 r_mop =3D tcg_constant_i32(memop | MO_ALIGN); =20 save_state(dc); /* According to the table in the UA2011 manual, the only @@ -2404,21 +2404,23 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, = int size, int rd) the NO_FAULT asis. We still need a helper for these, but we can just use the integer asi helper for them. */ switch (size) { - case 4: + case MO_32: d64 =3D tcg_temp_new_i64(); gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop); d32 =3D gen_dest_fpr_F(dc); tcg_gen_extrl_i64_i32(d32, d64); gen_store_fpr_F(dc, rd, d32); break; - case 8: - gen_helper_ld_asi(cpu_fpr[rd / 2], tcg_env, addr, r_asi, r= _mop); + case MO_64: + gen_helper_ld_asi(cpu_fpr[rd / 2], tcg_env, addr, + r_asi, r_mop); break; - case 16: + case MO_128: d64 =3D tcg_temp_new_i64(); gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop); tcg_gen_addi_tl(addr, addr, 8); - gen_helper_ld_asi(cpu_fpr[rd/2+1], tcg_env, addr, r_asi, r= _mop); + gen_helper_ld_asi(cpu_fpr[rd / 2 + 1], tcg_env, addr, + r_asi, r_mop); tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); break; default: @@ -2430,36 +2432,52 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, = int size, int rd) } =20 static void __attribute__((unused)) -gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) +gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) { - DisasASI da =3D get_asi(dc, insn, (size =3D=3D 4 ? MO_TEUL : MO_TEUQ)); + MemOp sz =3D ctz32(size); + DisasASI da =3D get_asi(dc, insn, MO_TE | sz); + + gen_address_mask(dc, addr); + gen_ldf_asi0(dc, &da, sz, addr, rd); +} + +static void gen_stf_asi0(DisasContext *dc, DisasASI *da, MemOp orig_size, + TCGv addr, int rd) +{ + MemOp memop =3D da->memop; + MemOp size =3D memop & MO_SIZE; TCGv_i32 d32; =20 - switch (da.type) { + /* TODO: Use 128-bit load/store below. */ + if (size =3D=3D MO_128) { + memop =3D (memop & ~MO_SIZE) | MO_64; + } + + switch (da->type) { case GET_ASI_EXCP: break; =20 case GET_ASI_DIRECT: - gen_address_mask(dc, addr); + memop |=3D MO_ALIGN_4; switch (size) { - case 4: + case MO_32: d32 =3D gen_load_fpr_F(dc, rd); - tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN= ); + tcg_gen_qemu_st_i32(d32, addr, da->mem_idx, memop | MO_ALIGN); break; - case 8: - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, - da.memop | MO_ALIGN_4); + case MO_64: + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx, + memop | MO_ALIGN_4); break; - case 16: + case MO_128: /* Only 4-byte alignment required. However, it is legal for t= he cpu to signal the alignment fault, and the OS trap handler = is required to fix it up. Requiring 16-byte alignment here av= oids having to probe the second page before performing the first write. */ - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, - da.memop | MO_ALIGN_16); + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx, + memop | MO_ALIGN_16); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_st_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, da.memo= p); + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + 1], addr, da->mem_idx, me= mop); break; default: g_assert_not_reached(); @@ -2468,24 +2486,19 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, = int size, int rd) =20 case GET_ASI_BLOCK: /* Valid for stdfa on aligned registers only. */ - if (size =3D=3D 8 && (rd & 7) =3D=3D 0) { - MemOp memop; + if (orig_size =3D=3D MO_64 && (rd & 7) =3D=3D 0) { TCGv eight; int i; =20 - gen_address_mask(dc, addr); - /* The first operation checks required alignment. */ - memop =3D da.memop | MO_ALIGN_64; eight =3D tcg_constant_tl(8); for (i =3D 0; ; ++i) { - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, - da.mem_idx, memop); + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx, + memop | (i =3D=3D 0 ? MO_ALIGN_64 : 0)= ); if (i =3D=3D 7) { break; } tcg_gen_add_tl(addr, addr, eight); - memop =3D da.memop; } } else { gen_exception(dc, TT_ILL_INSN); @@ -2494,10 +2507,9 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, i= nt size, int rd) =20 case GET_ASI_SHORT: /* Valid for stdfa only. */ - if (size =3D=3D 8) { - gen_address_mask(dc, addr); - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, - da.memop | MO_ALIGN); + if (orig_size =3D=3D MO_64) { + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx, + memop | MO_ALIGN); } else { gen_exception(dc, TT_ILL_INSN); } @@ -2512,6 +2524,16 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, i= nt size, int rd) } } =20 +static void __attribute__((unused)) +gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) +{ + MemOp sz =3D ctz32(size); + DisasASI da =3D get_asi(dc, insn, MO_TE | sz); + + gen_address_mask(dc, addr); + gen_stf_asi0(dc, &da, sz, addr, rd); +} + static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) { TCGv hi =3D gen_dest_gpr(dc, rd); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280524; cv=none; d=zohomail.com; s=zohoarc; b=mMdwE1j60rq2QMPoH1RXbai5/eI520K7/I/F/BTam9O3cUDm8N+FOxeUUn6FmEIINHbSFQ2EEnqjK5BSYwHKs67g6xGWxPXLCN69dYTNhumLxisDNYH2bCTgJiCKsnMbhxlQvU+C/d59D+u86Ll33g8qHHNfps0gQgCuy27I2Pg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280524; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=b+HQpe9L5M9mn0a2A+T0Xl3xxidoAXsFEfrMksqu35Y=; b=g7Vlpt+zUUViWItFe4KMr6zVa5kdTCFdj1hJsZ8lLzz6itMtZHFD+5JbyhJY3oKBZuid1rVjKakgRehLhXSmKpxyeo3NOSfeN3zZhFZr5b8somjEHAbM+tTcpGLvcd1fOlbfDhxN/l9/Ddl2VOKt90j2tHurzVZCjLDZRVQteT8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698280524414823.2926090948663; Wed, 25 Oct 2023 17:35:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo9v-0003au-4T; Wed, 25 Oct 2023 20:23:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo9b-0002o1-GU for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:23:16 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo9K-0008Bo-B1 for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:23:15 -0400 Received: by mail-pj1-x102d.google.com with SMTP id 98e67ed59e1d1-27d0a173e61so248347a91.0 for ; Wed, 25 Oct 2023 17:22:57 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280525757100003 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 19 ++++ target/sparc/translate.c | 194 ++++++++++++++++++-------------------- 2 files changed, 113 insertions(+), 100 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index aa452f1d00..1150890e44 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -238,8 +238,16 @@ NCP 10 ----- 110111 ----- --------- ----- = # v8 CPop2 ## Major Opcode 11 -- load and store instructions ## =20 +%dfp_rd 25:5 !function=3Dextract_dfpreg +%qfp_rd 25:5 !function=3Dextract_qfpreg + &r_r_ri_asi rd rs1 rs2_or_imm asi imm:bool @r_r_ri_na .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_asi asi= =3D-1 +@d_r_ri_na .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 \ + &r_r_ri_asi rd=3D%dfp_rd asi=3D-1 +@q_r_ri_na .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 \ + &r_r_ri_asi rd=3D%qfp_rd asi=3D-1 + @r_r_r_asi .. rd:5 ...... rs1:5 0 asi:8 rs2_or_imm:5 &r_r_ri_asi imm= =3D0 @r_r_i_asi .. rd:5 ...... rs1:5 1 rs2_or_imm:s13 \ &r_r_ri_asi imm=3D1 asi=3D-2 @@ -289,6 +297,17 @@ STD 11 ..... 010111 ..... . ............. = @r_r_i_asi # STDA STX 11 ..... 011110 ..... . ............. @r_r_r_asi # ST= XA STX 11 ..... 011110 ..... . ............. @r_r_i_asi # ST= XA =20 +LDF 11 ..... 100000 ..... . ............. @r_r_ri_na +LDQF 11 ..... 100010 ..... . ............. @q_r_ri_na +LDDF 11 ..... 100011 ..... . ............. @d_r_ri_na + +STF 11 ..... 100100 ..... . ............. @r_r_ri_na +{ + STQF 11 ..... 100110 ..... . ............. @q_r_ri_na + STDFQ 11 ----- 100110 ----- - ------------- +} +STDF 11 ..... 100111 ..... . ............. @d_r_ri_na + LDSTUB 11 ..... 001101 ..... . ............. @r_r_ri_na LDSTUB 11 ..... 011101 ..... . ............. @r_r_r_asi # LD= STUBA LDSTUB 11 ..... 011101 ..... . ............. @r_r_i_asi # LD= STUBA diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 55d6f83736..dab3dfd09c 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -254,29 +254,7 @@ static void gen_op_store_QT0_fpr(unsigned int dst) offsetof(CPU_QuadU, ll.lower)); } =20 -static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst, - TCGv_i64 v1, TCGv_i64 v2) -{ - dst =3D QFPREG(dst); - - tcg_gen_mov_i64(cpu_fpr[dst / 2], v1); - tcg_gen_mov_i64(cpu_fpr[dst / 2 + 1], v2); - gen_update_fprs_dirty(dc, dst); -} - #ifdef TARGET_SPARC64 -static TCGv_i64 gen_load_fpr_Q0(DisasContext *dc, unsigned int src) -{ - src =3D QFPREG(src); - return cpu_fpr[src / 2]; -} - -static TCGv_i64 gen_load_fpr_Q1(DisasContext *dc, unsigned int src) -{ - src =3D QFPREG(src); - return cpu_fpr[src / 2 + 1]; -} - static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs) { rd =3D QFPREG(rd); @@ -2900,6 +2878,16 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv = s1, TCGv s2) } #endif =20 +static int extract_dfpreg(DisasContext *dc, int x) +{ + return DFPREG(x); +} + +static int extract_qfpreg(DisasContext *dc, int x) +{ + return QFPREG(x); +} + /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" =20 @@ -3035,6 +3023,20 @@ static bool raise_priv(DisasContext *dc) return true; } =20 +static bool raise_unimpfpop(DisasContext *dc) +{ + gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP); + return true; +} + +static bool gen_trap_float128(DisasContext *dc) +{ + if (dc->def->features & CPU_FEATURE_FLOAT128) { + return false; + } + return raise_unimpfpop(dc); +} + static bool do_bpcc(DisasContext *dc, arg_bcc *a) { target_long target =3D address_mask_i(dc, dc->pc + a->i * 4); @@ -4633,6 +4635,68 @@ static bool do_casa(DisasContext *dc, arg_r_r_ri_asi= *a, MemOp mop) TRANS(CASA, CASA, do_casa, a, MO_TEUL) TRANS(CASXA, 64, do_casa, a, MO_TEUQ) =20 +static bool do_ld_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz) +{ + TCGv addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + DisasASI da; + + if (addr =3D=3D NULL) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (sz =3D=3D MO_128 && gen_trap_float128(dc)) { + return true; + } + da =3D resolve_asi(dc, a->asi, MO_TE | sz); + gen_ldf_asi0(dc, &da, sz, addr, a->rd); + gen_update_fprs_dirty(dc, a->rd); + return advance_pc(dc); +} + +TRANS(LDF, ALL, do_ld_fpr, a, MO_32) +TRANS(LDDF, ALL, do_ld_fpr, a, MO_64) +TRANS(LDQF, ALL, do_ld_fpr, a, MO_128) + +static bool do_st_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz) +{ + TCGv addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + DisasASI da; + + if (addr =3D=3D NULL) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (sz =3D=3D MO_128 && gen_trap_float128(dc)) { + return true; + } + da =3D resolve_asi(dc, a->asi, MO_TE | sz); + gen_stf_asi0(dc, &da, sz, addr, a->rd); + return advance_pc(dc); +} + +TRANS(STF, ALL, do_st_fpr, a, MO_32) +TRANS(STDF, ALL, do_st_fpr, a, MO_64) +TRANS(STQF, ALL, do_st_fpr, a, MO_128) + +static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a) +{ + if (!avail_32(dc)) { + return false; + } + if (!supervisor(dc)) { + return raise_priv(dc); + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR); + return true; +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4647,7 +4711,8 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) TCGv cpu_src1 __attribute__((unused)); TCGv cpu_src2 __attribute__((unused)); TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32; - TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64; + TCGv_i64 cpu_src1_64, cpu_src2_64; + TCGv_i64 cpu_dst_64 __attribute__((unused)); target_long simm; =20 opc =3D GET_FIELD(insn, 0, 1); @@ -5514,12 +5579,9 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) } switch (xop) { case 0x20: /* ldf, load fpreg */ - gen_address_mask(dc, cpu_addr); - cpu_dst_32 =3D gen_dest_fpr_F(dc); - tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr, - dc->mem_idx, MO_TEUL | MO_ALIGN); - gen_store_fpr_F(dc, rd, cpu_dst_32); - break; + case 0x22: /* ldqf, load quad fpreg */ + case 0x23: /* lddf, load double fpreg */ + g_assert_not_reached(); /* in decodetree */ case 0x21: /* ldfsr, V9 ldxfsr */ #ifdef TARGET_SPARC64 gen_address_mask(dc, cpu_addr); @@ -5536,25 +5598,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) dc->mem_idx, MO_TEUL | MO_ALIGN); gen_helper_ldfsr(cpu_fsr, tcg_env, cpu_fsr, cpu_dst_32= ); break; - case 0x22: /* ldqf, load quad fpreg */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_address_mask(dc, cpu_addr); - cpu_src1_64 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(cpu_src1_64, cpu_addr, dc->mem_idx, - MO_TEUQ | MO_ALIGN_4); - tcg_gen_addi_tl(cpu_addr, cpu_addr, 8); - cpu_src2_64 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(cpu_src2_64, cpu_addr, dc->mem_idx, - MO_TEUQ | MO_ALIGN_4); - gen_store_fpr_Q(dc, rd, cpu_src1_64, cpu_src2_64); - break; - case 0x23: /* lddf, load double fpreg */ - gen_address_mask(dc, cpu_addr); - cpu_dst_64 =3D gen_dest_fpr_D(dc, rd); - tcg_gen_qemu_ld_i64(cpu_dst_64, cpu_addr, dc->mem_idx, - MO_TEUQ | MO_ALIGN_4); - gen_store_fpr_D(dc, rd, cpu_dst_64); - break; default: goto illegal_insn; } @@ -5564,11 +5607,9 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) } switch (xop) { case 0x24: /* stf, store fpreg */ - gen_address_mask(dc, cpu_addr); - cpu_src1_32 =3D gen_load_fpr_F(dc, rd); - tcg_gen_qemu_st_i32(cpu_src1_32, cpu_addr, - dc->mem_idx, MO_TEUL | MO_ALIGN); - break; + case 0x26: /* v9 stqf, v8 stdfq */ + case 0x27: /* stdf, store double fpreg */ + g_assert_not_reached(); case 0x25: /* stfsr, V9 stxfsr */ { #ifdef TARGET_SPARC64 @@ -5583,43 +5624,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) dc->mem_idx, MO_TEUL | MO_ALIGN= ); } break; - case 0x26: -#ifdef TARGET_SPARC64 - /* V9 stqf, store quad fpreg */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_address_mask(dc, cpu_addr); - /* ??? While stqf only requires 4-byte alignment, it is - legal for the cpu to signal the unaligned exception. - The OS trap handler is then required to fix it up. - For qemu, this avoids having to probe the second pa= ge - before performing the first write. */ - cpu_src1_64 =3D gen_load_fpr_Q0(dc, rd); - tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, - dc->mem_idx, MO_TEUQ | MO_ALIGN_16= ); - tcg_gen_addi_tl(cpu_addr, cpu_addr, 8); - cpu_src2_64 =3D gen_load_fpr_Q1(dc, rd); - tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, - dc->mem_idx, MO_TEUQ); - break; -#else /* !TARGET_SPARC64 */ - /* stdfq, store floating point queue */ -#if defined(CONFIG_USER_ONLY) - goto illegal_insn; -#else - if (!supervisor(dc)) - goto priv_insn; - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - goto nfq_insn; -#endif -#endif - case 0x27: /* stdf, store double fpreg */ - gen_address_mask(dc, cpu_addr); - cpu_src1_64 =3D gen_load_fpr_D(dc, rd); - tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, dc->mem_idx, - MO_TEUQ | MO_ALIGN_4); - break; default: goto illegal_insn; } @@ -5666,19 +5670,9 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) illegal_insn: gen_exception(dc, TT_ILL_INSN); return; -#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) - priv_insn: - gen_exception(dc, TT_PRIV_INSN); - return; -#endif nfpu_insn: gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP); return; -#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) - nfq_insn: - gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR); - return; -#endif } =20 static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280090; cv=none; d=zohomail.com; s=zohoarc; b=O3eqfP5W7I70pTrtA7/hsUCR3N7wtTt1u2FLfNXM/05fDEU0mdLGEIZTU8T+b3Iw0WmPAlr/QbBYLmmwriAO40JrQKMPFBJVykqJdaBPPf1Joc0ZEX4yGRWxZdmIRaXiuqifOGi5DdfQ07ZBG0s/KWEqAeePBuVlOwvAabcwMM4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280090; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=K8YU64Za2EkWkchsAfoy1+WnYH0eMyiNHsii8BGP13U=; b=ZKQlPAzxlcsFlFJYRa8nD7nSwPxu6uc9QV7zDjmnNKtt2kwBahRuDp3WFl43JxUZrp0OxKCYEulTILXHKeif/wctWq6zDlfrY1aNYyI46fqhWUGev+cnuU9gk7mZxm34d99+3oWd+fGWgU9C7evUxycVkCAloAfl/BC89+y0nuY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698280090789906.3878059694921; Wed, 25 Oct 2023 17:28:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo9w-0003bw-3Z; Wed, 25 Oct 2023 20:23:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo9Q-0000zD-8C for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:23:04 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo9L-0008Bu-E3 for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:23:03 -0400 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-27d23f1e3b8so241814a91.1 for ; Wed, 25 Oct 2023 17:22:58 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280091455100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 51 +++++++++-- target/sparc/translate.c | 173 ++++++++------------------------------ 2 files changed, 81 insertions(+), 143 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 1150890e44..45eb6a967f 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -251,6 +251,14 @@ NCP 10 ----- 110111 ----- --------- ----- = # v8 CPop2 @r_r_r_asi .. rd:5 ...... rs1:5 0 asi:8 rs2_or_imm:5 &r_r_ri_asi imm= =3D0 @r_r_i_asi .. rd:5 ...... rs1:5 1 rs2_or_imm:s13 \ &r_r_ri_asi imm=3D1 asi=3D-2 +@d_r_r_asi .. ..... ...... rs1:5 0 asi:8 rs2_or_imm:5 \ + &r_r_ri_asi rd=3D%dfp_rd imm=3D0 +@d_r_i_asi .. ..... ...... rs1:5 1 rs2_or_imm:s13 \ + &r_r_ri_asi rd=3D%dfp_rd imm=3D1 asi=3D-2 +@q_r_r_asi .. ..... ...... rs1:5 0 asi:8 rs2_or_imm:5 \ + &r_r_ri_asi rd=3D%qfp_rd imm=3D0 +@q_r_i_asi .. ..... ...... rs1:5 1 rs2_or_imm:s13 \ + &r_r_ri_asi rd=3D%qfp_rd imm=3D1 asi=3D-2 @casa_imm .. rd:5 ...... rs1:5 1 00000000 rs2_or_imm:5 \ &r_r_ri_asi imm=3D1 asi=3D-2 =20 @@ -325,10 +333,43 @@ NOP_v9 11 ----- 101101 ----- 0 00000000 ----- = # PREFETCH NOP_v9 11 ----- 101101 ----- 1 ------------- # PREFETCH NOP_v9 11 ----- 111101 ----- - ------------- # PREFETCHA =20 -NCP 11 ----- 110000 ----- --------- ----- # v8 LDC +{ + [ + LDFA 11 ..... 110000 ..... . ............. @r_r_r_asi + LDFA 11 ..... 110000 ..... . ............. @r_r_i_asi + ] + NCP 11 ----- 110000 ----- --------- ----- # v8 LDC +} NCP 11 ----- 110001 ----- --------- ----- # v8 LDCSR -NCP 11 ----- 110011 ----- --------- ----- # v8 LDDC -NCP 11 ----- 110100 ----- --------- ----- # v8 STC +LDQFA 11 ..... 110010 ..... . ............. @q_r_r_asi +LDQFA 11 ..... 110010 ..... . ............. @q_r_i_asi +{ + [ + LDDFA 11 ..... 110011 ..... . ............. @d_r_r_asi + LDDFA 11 ..... 110011 ..... . ............. @d_r_i_asi + ] + NCP 11 ----- 110011 ----- --------- ----- # v8 LDDC +} + +{ + [ + STFA 11 ..... 110100 ..... . ............. @r_r_r_asi + STFA 11 ..... 110100 ..... . ............. @r_r_i_asi + ] + NCP 11 ----- 110100 ----- --------- ----- # v8 STC +} NCP 11 ----- 110101 ----- --------- ----- # v8 STCSR -NCP 11 ----- 110110 ----- --------- ----- # v8 STDCQ -NCP 11 ----- 110111 ----- --------- ----- # v8 STDC +{ + [ + STQFA 11 ..... 110110 ..... . ............. @q_r_r_asi + STQFA 11 ..... 110110 ..... . ............. @q_r_i_asi + ] + NCP 11 ----- 110110 ----- --------- ----- # v8 STDCQ +} +{ + [ + STDFA 11 ..... 110111 ..... . ............. @d_r_r_asi + STDFA 11 ..... 110111 ..... . ............. @d_r_i_asi + ] + NCP 11 ----- 110111 ----- --------- ----- # v8 STDC +} diff --git a/target/sparc/translate.c b/target/sparc/translate.c index dab3dfd09c..ebffcd7393 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2106,12 +2106,6 @@ static DisasASI resolve_asi(DisasContext *dc, int as= i, MemOp memop) return (DisasASI){ type, asi, mem_idx, memop }; } =20 -static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop) -{ - int asi =3D IS_IMM ? -2 : GET_FIELD(insn, 19, 26); - return resolve_asi(dc, asi, memop); -} - #if defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) static void gen_helper_ld_asi(TCGv_i64 r, TCGv_env e, TCGv a, TCGv_i32 asi, TCGv_i32 mop) @@ -2298,13 +2292,14 @@ static void gen_ldstub_asi(DisasContext *dc, DisasA= SI *da, TCGv dst, TCGv addr) } } =20 -static void gen_ldf_asi0(DisasContext *dc, DisasASI *da, MemOp orig_size, - TCGv addr, int rd) +static void gen_ldf_asi(DisasContext *dc, DisasASI *da, MemOp orig_size, + TCGv addr, int rd) { MemOp memop =3D da->memop; MemOp size =3D memop & MO_SIZE; TCGv_i32 d32; TCGv_i64 d64; + TCGv addr_tmp; =20 /* TODO: Use 128-bit load/store below. */ if (size =3D=3D MO_128) { @@ -2331,8 +2326,9 @@ static void gen_ldf_asi0(DisasContext *dc, DisasASI *= da, MemOp orig_size, case MO_128: d64 =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop); - tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + 1], addr, da->mem_idx, me= mop); + addr_tmp =3D tcg_temp_new(); + tcg_gen_addi_tl(addr_tmp, addr, 8); + tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + 1], addr_tmp, da->mem_idx= , memop); tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); break; default: @@ -2343,18 +2339,16 @@ static void gen_ldf_asi0(DisasContext *dc, DisasASI= *da, MemOp orig_size, case GET_ASI_BLOCK: /* Valid for lddfa on aligned registers only. */ if (orig_size =3D=3D MO_64 && (rd & 7) =3D=3D 0) { - TCGv eight; - int i; - /* The first operation checks required alignment. */ - eight =3D tcg_constant_tl(8); - for (i =3D 0; ; ++i) { + addr_tmp =3D tcg_temp_new(); + for (int i =3D 0; ; ++i) { tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx, memop | (i =3D=3D 0 ? MO_ALIGN_64 : 0)= ); if (i =3D=3D 7) { break; } - tcg_gen_add_tl(addr, addr, eight); + tcg_gen_addi_tl(addr_tmp, addr, 8); + addr =3D addr_tmp; } } else { gen_exception(dc, TT_ILL_INSN); @@ -2396,8 +2390,9 @@ static void gen_ldf_asi0(DisasContext *dc, DisasASI *= da, MemOp orig_size, case MO_128: d64 =3D tcg_temp_new_i64(); gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop); - tcg_gen_addi_tl(addr, addr, 8); - gen_helper_ld_asi(cpu_fpr[rd / 2 + 1], tcg_env, addr, + addr_tmp =3D tcg_temp_new(); + tcg_gen_addi_tl(addr_tmp, addr, 8); + gen_helper_ld_asi(cpu_fpr[rd / 2 + 1], tcg_env, addr_tmp, r_asi, r_mop); tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); break; @@ -2409,22 +2404,13 @@ static void gen_ldf_asi0(DisasContext *dc, DisasASI= *da, MemOp orig_size, } } =20 -static void __attribute__((unused)) -gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) -{ - MemOp sz =3D ctz32(size); - DisasASI da =3D get_asi(dc, insn, MO_TE | sz); - - gen_address_mask(dc, addr); - gen_ldf_asi0(dc, &da, sz, addr, rd); -} - -static void gen_stf_asi0(DisasContext *dc, DisasASI *da, MemOp orig_size, - TCGv addr, int rd) +static void gen_stf_asi(DisasContext *dc, DisasASI *da, MemOp orig_size, + TCGv addr, int rd) { MemOp memop =3D da->memop; MemOp size =3D memop & MO_SIZE; TCGv_i32 d32; + TCGv addr_tmp; =20 /* TODO: Use 128-bit load/store below. */ if (size =3D=3D MO_128) { @@ -2454,8 +2440,9 @@ static void gen_stf_asi0(DisasContext *dc, DisasASI *= da, MemOp orig_size, write. */ tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx, memop | MO_ALIGN_16); - tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + 1], addr, da->mem_idx, me= mop); + addr_tmp =3D tcg_temp_new(); + tcg_gen_addi_tl(addr_tmp, addr, 8); + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + 1], addr_tmp, da->mem_idx= , memop); break; default: g_assert_not_reached(); @@ -2465,18 +2452,16 @@ static void gen_stf_asi0(DisasContext *dc, DisasASI= *da, MemOp orig_size, case GET_ASI_BLOCK: /* Valid for stdfa on aligned registers only. */ if (orig_size =3D=3D MO_64 && (rd & 7) =3D=3D 0) { - TCGv eight; - int i; - /* The first operation checks required alignment. */ - eight =3D tcg_constant_tl(8); - for (i =3D 0; ; ++i) { + addr_tmp =3D tcg_temp_new(); + for (int i =3D 0; ; ++i) { tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx, memop | (i =3D=3D 0 ? MO_ALIGN_64 : 0)= ); if (i =3D=3D 7) { break; } - tcg_gen_add_tl(addr, addr, eight); + tcg_gen_addi_tl(addr_tmp, addr, 8); + addr =3D addr_tmp; } } else { gen_exception(dc, TT_ILL_INSN); @@ -2502,16 +2487,6 @@ static void gen_stf_asi0(DisasContext *dc, DisasASI = *da, MemOp orig_size, } } =20 -static void __attribute__((unused)) -gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) -{ - MemOp sz =3D ctz32(size); - DisasASI da =3D get_asi(dc, insn, MO_TE | sz); - - gen_address_mask(dc, addr); - gen_stf_asi0(dc, &da, sz, addr, rd); -} - static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) { TCGv hi =3D gen_dest_gpr(dc, rd); @@ -4650,7 +4625,7 @@ static bool do_ld_fpr(DisasContext *dc, arg_r_r_ri_as= i *a, MemOp sz) return true; } da =3D resolve_asi(dc, a->asi, MO_TE | sz); - gen_ldf_asi0(dc, &da, sz, addr, a->rd); + gen_ldf_asi(dc, &da, sz, addr, a->rd); gen_update_fprs_dirty(dc, a->rd); return advance_pc(dc); } @@ -4659,6 +4634,10 @@ TRANS(LDF, ALL, do_ld_fpr, a, MO_32) TRANS(LDDF, ALL, do_ld_fpr, a, MO_64) TRANS(LDQF, ALL, do_ld_fpr, a, MO_128) =20 +TRANS(LDFA, 64, do_ld_fpr, a, MO_32) +TRANS(LDDFA, 64, do_ld_fpr, a, MO_64) +TRANS(LDQFA, 64, do_ld_fpr, a, MO_128) + static bool do_st_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz) { TCGv addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); @@ -4674,7 +4653,7 @@ static bool do_st_fpr(DisasContext *dc, arg_r_r_ri_as= i *a, MemOp sz) return true; } da =3D resolve_asi(dc, a->asi, MO_TE | sz); - gen_stf_asi0(dc, &da, sz, addr, a->rd); + gen_stf_asi(dc, &da, sz, addr, a->rd); return advance_pc(dc); } =20 @@ -4682,6 +4661,10 @@ TRANS(STF, ALL, do_st_fpr, a, MO_32) TRANS(STDF, ALL, do_st_fpr, a, MO_64) TRANS(STQF, ALL, do_st_fpr, a, MO_128) =20 +TRANS(STFA, 64, do_st_fpr, a, MO_32) +TRANS(STDFA, 64, do_st_fpr, a, MO_64) +TRANS(STQFA, 64, do_st_fpr, a, MO_128) + static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a) { if (!avail_32(dc)) { @@ -5515,64 +5498,7 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) if (xop < 4 || (xop > 7 && xop < 0x14 && xop !=3D 0x0e) || (xop > 0x17 && xop <=3D 0x1d ) || (xop > 0x2c && xop <=3D 0x33) || xop =3D=3D 0x1f || xop = =3D=3D 0x3d) { - TCGv cpu_val =3D gen_dest_gpr(dc, rd); - - switch (xop) { - case 0x0: /* ld, V9 lduw, load unsigned word */ - case 0x1: /* ldub, load unsigned byte */ - case 0x2: /* lduh, load unsigned halfword */ - case 0x3: /* ldd, load double word */ - case 0x9: /* ldsb, load signed byte */ - case 0xa: /* ldsh, load signed halfword */ - case 0xd: /* ldstub */ - case 0x0f: /* swap */ - case 0x10: /* lda, V9 lduwa, load word alternate */ - case 0x11: /* lduba, load unsigned byte alternate */ - case 0x12: /* lduha, load unsigned halfword alternate= */ - case 0x13: /* ldda, load double word alternate */ - case 0x19: /* ldsba, load signed byte alternate */ - case 0x1a: /* ldsha, load signed halfword alternate */ - case 0x1d: /* ldstuba */ - case 0x1f: /* swapa */ - g_assert_not_reached(); /* in decodetree */ - case 0x08: /* V9 ldsw */ - case 0x0b: /* V9 ldx */ - case 0x18: /* V9 ldswa */ - case 0x1b: /* V9 ldxa */ - case 0x2d: /* V9 prefetch */ - case 0x3d: /* V9 prefetcha */ - goto illegal_insn; /* in decodetree */ -#ifdef TARGET_SPARC64 - case 0x30: /* V9 ldfa */ - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - gen_ldf_asi(dc, cpu_addr, insn, 4, rd); - gen_update_fprs_dirty(dc, rd); - goto skip_move; - case 0x33: /* V9 lddfa */ - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd)); - gen_update_fprs_dirty(dc, DFPREG(rd)); - goto skip_move; - case 0x32: /* V9 ldqfa */ - CHECK_FPU_FEATURE(dc, FLOAT128); - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - gen_ldf_asi(dc, cpu_addr, insn, 16, QFPREG(rd)); - gen_update_fprs_dirty(dc, QFPREG(rd)); - goto skip_move; -#endif - default: - goto illegal_insn; - } - gen_store_gpr(dc, rd, cpu_val); -#if defined(TARGET_SPARC64) - skip_move: ; -#endif + goto illegal_insn; /* in decodetree */ } else if (xop >=3D 0x20 && xop < 0x24) { if (gen_trap_ifnofpu(dc)) { goto jmp_insn; @@ -5628,36 +5554,7 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) goto illegal_insn; } } else if (xop > 0x33 && xop < 0x3f) { - switch (xop) { -#ifdef TARGET_SPARC64 - case 0x34: /* V9 stfa */ - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - gen_stf_asi(dc, cpu_addr, insn, 4, rd); - break; - case 0x36: /* V9 stqfa */ - { - CHECK_FPU_FEATURE(dc, FLOAT128); - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd)); - } - break; - case 0x37: /* V9 stdfa */ - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - gen_stf_asi(dc, cpu_addr, insn, 8, DFPREG(rd)); - break; -#endif - case 0x3e: /* V9 casxa */ - case 0x3c: /* V9 or LEON3 casa */ - goto illegal_insn; /* in decodetree */ - default: - goto illegal_insn; - } + goto illegal_insn; /* in decodetree */ } else { goto illegal_insn; } --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280175734100009 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 + target/sparc/translate.c | 152 +++++++++++++++----------------------- 2 files changed, 64 insertions(+), 92 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 45eb6a967f..5df3b1add4 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -306,10 +306,14 @@ STX 11 ..... 011110 ..... . ............. = @r_r_r_asi # STXA STX 11 ..... 011110 ..... . ............. @r_r_i_asi # ST= XA =20 LDF 11 ..... 100000 ..... . ............. @r_r_ri_na +LDFSR 11 00000 100001 ..... . ............. @n_r_ri +LDXFSR 11 00001 100001 ..... . ............. @n_r_ri LDQF 11 ..... 100010 ..... . ............. @q_r_ri_na LDDF 11 ..... 100011 ..... . ............. @d_r_ri_na =20 STF 11 ..... 100100 ..... . ............. @r_r_ri_na +STFSR 11 00000 100101 ..... . ............. @n_r_ri +STXFSR 11 00001 100101 ..... . ............. @n_r_ri { STQF 11 ..... 100110 ..... . ............. @q_r_ri_na STDFQ 11 ----- 100110 ----- - ------------- diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ebffcd7393..4c0e7cde4a 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -45,6 +45,7 @@ # define gen_helper_clear_softint(E, S) qemu_build_not_reached() # define gen_helper_done(E) qemu_build_not_reached() # define gen_helper_flushw(E) qemu_build_not_reached() +# define gen_helper_ldxfsr(D, E, A, B) qemu_build_not_reached() # define gen_helper_rdccr(D, E) qemu_build_not_reached() # define gen_helper_rdcwp(D, E) qemu_build_not_reached() # define gen_helper_restored(E) qemu_build_not_reached() @@ -164,12 +165,6 @@ typedef struct { #define UA2005_HTRAP_MASK 0xff #define V8_TRAP_MASK 0x7f =20 -static int sign_extend(int x, int len) -{ - len =3D 32 - len; - return (x << len) >> len; -} - #define IS_IMM (insn & (1<<13)) =20 static void gen_update_fprs_dirty(DisasContext *dc, int rd) @@ -2655,13 +2650,13 @@ static void gen_stda_asi(DisasContext *dc, DisasASI= *da, TCGv addr, int rd) } } =20 +#ifdef TARGET_SPARC64 static TCGv get_src1(DisasContext *dc, unsigned int insn) { unsigned int rs1 =3D GET_FIELD(insn, 13, 17); return gen_load_gpr(dc, rs1); } =20 -#ifdef TARGET_SPARC64 static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs) { TCGv_i32 c32, zero, dst, s1, s2; @@ -4680,6 +4675,61 @@ static bool trans_STDFQ(DisasContext *dc, arg_STDFQ = *a) return true; } =20 +static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri *a) +{ + TCGv addr; + TCGv_i32 tmp; + + addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + if (addr =3D=3D NULL) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + tmp =3D tcg_temp_new_i32(); + tcg_gen_qemu_ld_i32(tmp, addr, dc->mem_idx, MO_TEUL | MO_ALIGN); + gen_helper_ldfsr(cpu_fsr, tcg_env, cpu_fsr, tmp); + return advance_pc(dc); +} + +static bool trans_LDXFSR(DisasContext *dc, arg_r_r_ri *a) +{ + TCGv addr; + TCGv_i64 tmp; + + if (!avail_64(dc)) { + return false; + } + addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + if (addr =3D=3D NULL) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + tmp =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(tmp, addr, dc->mem_idx, MO_TEUQ | MO_ALIGN); + gen_helper_ldxfsr(cpu_fsr, tcg_env, cpu_fsr, tmp); + return advance_pc(dc); +} + +static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop) +{ + TCGv addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + if (addr =3D=3D NULL) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + tcg_gen_qemu_st_tl(cpu_fsr, addr, dc->mem_idx, mop | MO_ALIGN); + return advance_pc(dc); +} + +TRANS(STFSR, ALL, do_stfsr, a, MO_TEUL) +TRANS(STXFSR, 64, do_stfsr, a, MO_TEUQ) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4693,10 +4743,10 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) unsigned int opc, rs1, rs2, rd; TCGv cpu_src1 __attribute__((unused)); TCGv cpu_src2 __attribute__((unused)); - TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32; + TCGv_i32 cpu_src1_32, cpu_src2_32; TCGv_i64 cpu_src1_64, cpu_src2_64; + TCGv_i32 cpu_dst_32 __attribute__((unused)); TCGv_i64 cpu_dst_64 __attribute__((unused)); - target_long simm; =20 opc =3D GET_FIELD(insn, 0, 1); rd =3D GET_FIELD(insn, 2, 6); @@ -5477,89 +5527,7 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) } break; case 3: /* load/store instructions */ - { - unsigned int xop =3D GET_FIELD(insn, 7, 12); - /* ??? gen_address_mask prevents us from using a source - register directly. Always generate a temporary. */ - TCGv cpu_addr =3D tcg_temp_new(); - - tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn)); - if (IS_IMM) { /* immediate */ - simm =3D GET_FIELDs(insn, 19, 31); - if (simm !=3D 0) { - tcg_gen_addi_tl(cpu_addr, cpu_addr, simm); - } - } else { /* register */ - rs2 =3D GET_FIELD(insn, 27, 31); - if (rs2 !=3D 0) { - tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs= 2)); - } - } - if (xop < 4 || (xop > 7 && xop < 0x14 && xop !=3D 0x0e) || - (xop > 0x17 && xop <=3D 0x1d ) || - (xop > 0x2c && xop <=3D 0x33) || xop =3D=3D 0x1f || xop = =3D=3D 0x3d) { - goto illegal_insn; /* in decodetree */ - } else if (xop >=3D 0x20 && xop < 0x24) { - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - switch (xop) { - case 0x20: /* ldf, load fpreg */ - case 0x22: /* ldqf, load quad fpreg */ - case 0x23: /* lddf, load double fpreg */ - g_assert_not_reached(); /* in decodetree */ - case 0x21: /* ldfsr, V9 ldxfsr */ -#ifdef TARGET_SPARC64 - gen_address_mask(dc, cpu_addr); - if (rd =3D=3D 1) { - TCGv_i64 t64 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t64, cpu_addr, - dc->mem_idx, MO_TEUQ | MO_ALIG= N); - gen_helper_ldxfsr(cpu_fsr, tcg_env, cpu_fsr, t64); - break; - } -#endif - cpu_dst_32 =3D tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr, - dc->mem_idx, MO_TEUL | MO_ALIGN); - gen_helper_ldfsr(cpu_fsr, tcg_env, cpu_fsr, cpu_dst_32= ); - break; - default: - goto illegal_insn; - } - } else if (xop > 0x23 && xop < 0x28) { - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - switch (xop) { - case 0x24: /* stf, store fpreg */ - case 0x26: /* v9 stqf, v8 stdfq */ - case 0x27: /* stdf, store double fpreg */ - g_assert_not_reached(); - case 0x25: /* stfsr, V9 stxfsr */ - { -#ifdef TARGET_SPARC64 - gen_address_mask(dc, cpu_addr); - if (rd =3D=3D 1) { - tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr, - dc->mem_idx, MO_TEUQ | MO_A= LIGN); - break; - } -#endif - tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr, - dc->mem_idx, MO_TEUL | MO_ALIGN= ); - } - break; - default: - goto illegal_insn; - } - } else if (xop > 0x33 && xop < 0x3f) { - goto illegal_insn; /* in decodetree */ - } else { - goto illegal_insn; - } - } - break; + goto illegal_insn; /* in decodetree */ } advance_pc(dc); jmp_insn: --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280028; cv=none; d=zohomail.com; s=zohoarc; b=El4+e18xZ/SZaAToyUWkoFe1u1v4DrzQmxVxlvK767ENNwXWO2WwGyjeQkVo/o6MmCOaPRB7Qro/pS82rNTpvd7j1wIpVonENLZqNWxwL8MAH9/a0bTuZdyI87aBkl7JNE1HSRmImUbuvInxyclhVjXxauUVKULFOQ5BVrg8lsw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280028; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=XwblM3qYHhgk/BSbqYTN8K2nRmzxfzwTe7jRYcOw49o=; b=cJtFTWhA5/x9emtr0hGS2CJTwoffIZCM0nCKqoM6FYr8Lgw6YLfZIwn5eduEQdDAmU98aywf5RRq3pV3LlIc4mfja0/oxch26/1TDd+3p3sc9b/wBJhPQPDGdObLlnJNoPbSath5kVtUNyGOpw8qkEBcvML846Ol4kDOZYz+rQg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698280028286936.8148087538069; Wed, 25 Oct 2023 17:27:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo9i-0002tv-1P; Wed, 25 Oct 2023 20:23:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo9T-0001QP-0Z for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:23:07 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo9O-0008CP-5W for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:23:06 -0400 Received: by mail-pj1-x102c.google.com with SMTP id 98e67ed59e1d1-27d292d38c0so243709a91.1 for ; Wed, 25 Oct 2023 17:23:01 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.22.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:22:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279779; x=1698884579; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XwblM3qYHhgk/BSbqYTN8K2nRmzxfzwTe7jRYcOw49o=; b=siYacVCUOgF3CAT2tuXgx68dIpTpF5VA2069tcX3Dlf83rN4sXazeu2JgO14PceC/Z aF8blQZr+M2OwOWoejORTOBiUku2A76WNcOa7B7T3Wb72cXm4cvvWO/JTZB+EC1LvrGM r4aq0NeiJo69qTxrY9awGoX1wCnQ5EdZlyZiDoh123Hio+KijxCpW34uOAyPCfjZfQ0u 9pjGTqZY6moVTI7+gIY4kFsowxC9A2r+Ci4Zg5dEZR47y6hWdaH/h0IsQoIDMf7oOnoa aO0D8mqduL2r1TjGZIZP+LZhkOOKZDyjkMiXhzSqGokB/OweFtYGJ1mYevHi/tJrvCmm RR/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279779; x=1698884579; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XwblM3qYHhgk/BSbqYTN8K2nRmzxfzwTe7jRYcOw49o=; b=YZU6dhl5uWiHQTKCtz4FAkhqRledptgzfMfPH2SlR/8kIJmnj7EAv3FHWo+bOWGbRF yiBIP+T4lIEjrkvhdsYX9ANTyiFvEEn5Vble1SQBECT7ngKeLWK75LPl5MyrDgWcfef5 OjeB6+jGlbmZcrXe7Vi6ReXkg+eh2bCuwFKDsaEFP1PJdn7VV9SsG8/0LdNUX6Hu8Kyu VikFJgMHI7eGcAuEeLyptuZRQ+wS/lCZggJwvcxxEQO674iI/95WTkjiu+dlLhg/1oSq AOUkKizNQxctMBJnQiW+CqnrJXncQkuZw54ltYsOKo/mIC1WgpgRYRotsUtzVQf5qLWO PJ/w== X-Gm-Message-State: AOJu0YyhbLBwZwVjxQVV8twVPDIDLEd9uM7pnyd5o6uods35OxDsWWnQ YY9VYRHNr32araonRhDfwvDj6pkZGEFUce/1ePk= X-Google-Smtp-Source: AGHT+IG9zHcRR+OT8n35bz+h6/YfnAyHdrnQrIWNEfDeqw/i3AUf66Dmd6PBsibzqiKbpUrVh2/PbA== X-Received: by 2002:a17:90a:56:b0:27d:1ec3:4367 with SMTP id 22-20020a17090a005600b0027d1ec34367mr14292477pjb.0.1698279779037; Wed, 25 Oct 2023 17:22:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 62/94] target/sparc: Merge LDFSR, LDXFSR implementations Date: Wed, 25 Oct 2023 17:15:10 -0700 Message-Id: <20231026001542.1141412-92-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280029229100005 Content-Type: text/plain; charset="utf-8" Combine the helper to a single set_fsr(). Perform the mask and merge inline. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/helper.h | 3 +-- target/sparc/fop_helper.c | 17 ++-------------- target/sparc/translate.c | 42 ++++++++++++--------------------------- 3 files changed, 16 insertions(+), 46 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index b116ddcb29..790752467f 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -42,7 +42,7 @@ DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, = int, i32) DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32) #endif DEF_HELPER_FLAGS_1(check_ieee_exceptions, TCG_CALL_NO_WG, tl, env) -DEF_HELPER_FLAGS_3(ldfsr, TCG_CALL_NO_RWG, tl, env, tl, i32) +DEF_HELPER_FLAGS_2(set_fsr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_1(fabss, TCG_CALL_NO_RWG_SE, f32, f32) DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_RWG, f32, env, f32) DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_RWG, f64, env, f64) @@ -54,7 +54,6 @@ DEF_HELPER_FLAGS_1(fsqrtq, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_1(fcmpq, TCG_CALL_NO_WG, tl, env) DEF_HELPER_FLAGS_1(fcmpeq, TCG_CALL_NO_WG, tl, env) #ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_3(ldxfsr, TCG_CALL_NO_RWG, tl, env, tl, i64) DEF_HELPER_FLAGS_1(fabsd, TCG_CALL_NO_RWG_SE, f64, f64) DEF_HELPER_FLAGS_3(fcmps_fcc1, TCG_CALL_NO_WG, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmps_fcc2, TCG_CALL_NO_WG, tl, env, f32, f32) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index f54fa9b959..0f8aa3abcd 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -382,20 +382,7 @@ static void set_fsr(CPUSPARCState *env, target_ulong f= sr) set_float_rounding_mode(rnd_mode, &env->fp_status); } =20 -target_ulong helper_ldfsr(CPUSPARCState *env, target_ulong old_fsr, - uint32_t new_fsr) +void helper_set_fsr(CPUSPARCState *env, target_ulong fsr) { - old_fsr =3D (new_fsr & FSR_LDFSR_MASK) | (old_fsr & FSR_LDFSR_OLDMASK); - set_fsr(env, old_fsr); - return old_fsr; + set_fsr(env, fsr); } - -#ifdef TARGET_SPARC64 -target_ulong helper_ldxfsr(CPUSPARCState *env, target_ulong old_fsr, - uint64_t new_fsr) -{ - old_fsr =3D (new_fsr & FSR_LDXFSR_MASK) | (old_fsr & FSR_LDXFSR_OLDMAS= K); - set_fsr(env, old_fsr); - return old_fsr; -} -#endif diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 4c0e7cde4a..bf8c5a16b6 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -45,7 +45,6 @@ # define gen_helper_clear_softint(E, S) qemu_build_not_reached() # define gen_helper_done(E) qemu_build_not_reached() # define gen_helper_flushw(E) qemu_build_not_reached() -# define gen_helper_ldxfsr(D, E, A, B) qemu_build_not_reached() # define gen_helper_rdccr(D, E) qemu_build_not_reached() # define gen_helper_rdcwp(D, E) qemu_build_not_reached() # define gen_helper_restored(E) qemu_build_not_reached() @@ -63,6 +62,8 @@ # define gen_helper_write_softint(E, S) qemu_build_not_reached() # define gen_helper_wrpil(E, S) qemu_build_not_reached() # define gen_helper_wrpstate(E, S) qemu_build_not_reached() +# define FSR_LDXFSR_MASK 0 +# define FSR_LDXFSR_OLDMASK 0 # define MAXTL_MASK 0 #endif =20 @@ -4675,44 +4676,27 @@ static bool trans_STDFQ(DisasContext *dc, arg_STDFQ= *a) return true; } =20 -static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri *a) +static bool do_ldfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop, + target_ulong new_mask, target_ulong old_mask) { - TCGv addr; - TCGv_i32 tmp; - - addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + TCGv tmp, addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); if (addr =3D=3D NULL) { return false; } if (gen_trap_ifnofpu(dc)) { return true; } - tmp =3D tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp, addr, dc->mem_idx, MO_TEUL | MO_ALIGN); - gen_helper_ldfsr(cpu_fsr, tcg_env, cpu_fsr, tmp); + tmp =3D tcg_temp_new(); + tcg_gen_qemu_ld_tl(tmp, addr, dc->mem_idx, mop | MO_ALIGN); + tcg_gen_andi_tl(tmp, tmp, new_mask); + tcg_gen_andi_tl(cpu_fsr, cpu_fsr, old_mask); + tcg_gen_or_tl(cpu_fsr, cpu_fsr, tmp); + gen_helper_set_fsr(tcg_env, cpu_fsr); return advance_pc(dc); } =20 -static bool trans_LDXFSR(DisasContext *dc, arg_r_r_ri *a) -{ - TCGv addr; - TCGv_i64 tmp; - - if (!avail_64(dc)) { - return false; - } - addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); - if (addr =3D=3D NULL) { - return false; - } - if (gen_trap_ifnofpu(dc)) { - return true; - } - tmp =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(tmp, addr, dc->mem_idx, MO_TEUQ | MO_ALIGN); - gen_helper_ldxfsr(cpu_fsr, tcg_env, cpu_fsr, tmp); - return advance_pc(dc); -} +TRANS(LDFSR, ALL, do_ldfsr, a, MO_TEUL, FSR_LDFSR_MASK, FSR_LDFSR_OLDMASK) +TRANS(LDXFSR, 64, do_ldfsr, a, MO_TEUQ, FSR_LDXFSR_MASK, FSR_LDXFSR_OLDMAS= K) =20 static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop) { --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280875; cv=none; d=zohomail.com; s=zohoarc; b=lhSUiMe2bbt1vepu5+mWF/UhwLefiBgrfxOktAD01vEZGj+zSV0VvDNddI0SuWkX87cIfz/Vqq7DcRWMREkqdIqnjzm9AWadmqbMdq8YHBMyRpI6Ut0SCbXssEWsjRoZ6qoo+8VW4LKYqzOcXlRekZOo56NS1aMnoF5WtunRGKs= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280876873100006 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 22 +++- target/sparc/translate.c | 271 ++++++++++++++++---------------------- 2 files changed, 133 insertions(+), 160 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 5df3b1add4..a9630509bd 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -35,6 +35,9 @@ CALL 01 i:s30 @r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc = cc=3D0 @r_r_ri_cc1 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc = cc=3D1 =20 +&r_r_r rd rs1 rs2 +@r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r + { [ STBAR 10 00000 101000 01111 0 0000000000000 @@ -231,7 +234,24 @@ RESTORE 10 ..... 111101 ..... . ............. = @r_r_ri DONE 10 00000 111110 00000 0 0000000000000 RETRY 10 00001 111110 00000 0 0000000000000 =20 -NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 +{ + [ + EDGE8cc 10 ..... 110110 ..... 0 0000 0000 ..... @r_r_r + EDGE8N 10 ..... 110110 ..... 0 0000 0001 ..... @r_r_r + EDGE8Lcc 10 ..... 110110 ..... 0 0000 0010 ..... @r_r_r + EDGE8LN 10 ..... 110110 ..... 0 0000 0011 ..... @r_r_r + EDGE16cc 10 ..... 110110 ..... 0 0000 0100 ..... @r_r_r + EDGE16N 10 ..... 110110 ..... 0 0000 0101 ..... @r_r_r + EDGE16Lcc 10 ..... 110110 ..... 0 0000 0110 ..... @r_r_r + EDGE16LN 10 ..... 110110 ..... 0 0000 0111 ..... @r_r_r + EDGE32cc 10 ..... 110110 ..... 0 0000 1000 ..... @r_r_r + EDGE32N 10 ..... 110110 ..... 0 0000 1001 ..... @r_r_r + EDGE32Lcc 10 ..... 110110 ..... 0 0000 1010 ..... @r_r_r + EDGE32LN 10 ..... 110110 ..... 0 0000 1011 ..... @r_r_r + ] + NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 +} + NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 =20 ## diff --git a/target/sparc/translate.c b/target/sparc/translate.c index bf8c5a16b6..2f38453dc6 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2728,93 +2728,6 @@ static void gen_load_trap_state_at_tl(TCGv_ptr r_tsp= tr) } } =20 -static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, - int width, bool cc, bool left) -{ - TCGv lo1, lo2; - uint64_t amask, tabl, tabr; - int shift, imask, omask; - - if (cc) { - tcg_gen_mov_tl(cpu_cc_src, s1); - tcg_gen_mov_tl(cpu_cc_src2, s2); - tcg_gen_sub_tl(cpu_cc_dst, s1, s2); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); - dc->cc_op =3D CC_OP_SUB; - } - - /* Theory of operation: there are two tables, left and right (not to - be confused with the left and right versions of the opcode). These - are indexed by the low 3 bits of the inputs. To make things "easy", - these tables are loaded into two constants, TABL and TABR below. - The operation index =3D (input & imask) << shift calculates the ind= ex - into the constant, while val =3D (table >> index) & omask calculates - the value we're looking for. */ - switch (width) { - case 8: - imask =3D 0x7; - shift =3D 3; - omask =3D 0xff; - if (left) { - tabl =3D 0x80c0e0f0f8fcfeffULL; - tabr =3D 0xff7f3f1f0f070301ULL; - } else { - tabl =3D 0x0103070f1f3f7fffULL; - tabr =3D 0xfffefcf8f0e0c080ULL; - } - break; - case 16: - imask =3D 0x6; - shift =3D 1; - omask =3D 0xf; - if (left) { - tabl =3D 0x8cef; - tabr =3D 0xf731; - } else { - tabl =3D 0x137f; - tabr =3D 0xfec8; - } - break; - case 32: - imask =3D 0x4; - shift =3D 0; - omask =3D 0x3; - if (left) { - tabl =3D (2 << 2) | 3; - tabr =3D (3 << 2) | 1; - } else { - tabl =3D (1 << 2) | 3; - tabr =3D (3 << 2) | 2; - } - break; - default: - abort(); - } - - lo1 =3D tcg_temp_new(); - lo2 =3D tcg_temp_new(); - tcg_gen_andi_tl(lo1, s1, imask); - tcg_gen_andi_tl(lo2, s2, imask); - tcg_gen_shli_tl(lo1, lo1, shift); - tcg_gen_shli_tl(lo2, lo2, shift); - - tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1); - tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2); - tcg_gen_andi_tl(lo1, lo1, omask); - tcg_gen_andi_tl(lo2, lo2, omask); - - amask =3D -8; - if (AM_CHECK(dc)) { - amask &=3D 0xffffffffULL; - } - tcg_gen_andi_tl(s1, s1, amask); - tcg_gen_andi_tl(s2, s2, amask); - - /* Compute dst =3D (s1 =3D=3D s2 ? lo1 : lo1 & lo2). */ - tcg_gen_and_tl(lo2, lo2, lo1); - tcg_gen_movcond_tl(TCG_COND_EQ, dst, s1, s2, lo1, lo2); -} - static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left) { TCGv tmp =3D tcg_temp_new(); @@ -2877,6 +2790,8 @@ static int extract_qfpreg(DisasContext *dc, int x) # define avail_64(C) true # define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL) # define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV) +# define avail_VIS1(C) ((C)->def->features & CPU_FEATURE_VIS1) +# define avail_VIS2(C) ((C)->def->features & CPU_FEATURE_VIS2) #else # define avail_32(C) true # define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17) @@ -2887,6 +2802,8 @@ static int extract_qfpreg(DisasContext *dc, int x) # define avail_64(C) false # define avail_GL(C) false # define avail_HYPV(C) false +# define avail_VIS1(C) false +# define avail_VIS2(C) false #endif =20 /* Default case for non jump instructions. */ @@ -4187,6 +4104,113 @@ static bool trans_MULScc(DisasContext *dc, arg_r_r_= ri_cc *a) return do_arith(dc, a, CC_OP_ADD, NULL, NULL, gen_op_mulscc); } =20 +static bool gen_edge(DisasContext *dc, arg_r_r_r *a, + int width, bool cc, bool left) +{ + TCGv dst, s1, s2, lo1, lo2; + uint64_t amask, tabl, tabr; + int shift, imask, omask; + + dst =3D gen_dest_gpr(dc, a->rd); + s1 =3D gen_load_gpr(dc, a->rs1); + s2 =3D gen_load_gpr(dc, a->rs2); + + if (cc) { + tcg_gen_mov_tl(cpu_cc_src, s1); + tcg_gen_mov_tl(cpu_cc_src2, s2); + tcg_gen_sub_tl(cpu_cc_dst, s1, s2); + tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); + dc->cc_op =3D CC_OP_SUB; + } + + /* + * Theory of operation: there are two tables, left and right (not to + * be confused with the left and right versions of the opcode). These + * are indexed by the low 3 bits of the inputs. To make things "easy", + * these tables are loaded into two constants, TABL and TABR below. + * The operation index =3D (input & imask) << shift calculates the ind= ex + * into the constant, while val =3D (table >> index) & omask calculates + * the value we're looking for. + */ + switch (width) { + case 8: + imask =3D 0x7; + shift =3D 3; + omask =3D 0xff; + if (left) { + tabl =3D 0x80c0e0f0f8fcfeffULL; + tabr =3D 0xff7f3f1f0f070301ULL; + } else { + tabl =3D 0x0103070f1f3f7fffULL; + tabr =3D 0xfffefcf8f0e0c080ULL; + } + break; + case 16: + imask =3D 0x6; + shift =3D 1; + omask =3D 0xf; + if (left) { + tabl =3D 0x8cef; + tabr =3D 0xf731; + } else { + tabl =3D 0x137f; + tabr =3D 0xfec8; + } + break; + case 32: + imask =3D 0x4; + shift =3D 0; + omask =3D 0x3; + if (left) { + tabl =3D (2 << 2) | 3; + tabr =3D (3 << 2) | 1; + } else { + tabl =3D (1 << 2) | 3; + tabr =3D (3 << 2) | 2; + } + break; + default: + abort(); + } + + lo1 =3D tcg_temp_new(); + lo2 =3D tcg_temp_new(); + tcg_gen_andi_tl(lo1, s1, imask); + tcg_gen_andi_tl(lo2, s2, imask); + tcg_gen_shli_tl(lo1, lo1, shift); + tcg_gen_shli_tl(lo2, lo2, shift); + + tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1); + tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2); + tcg_gen_andi_tl(lo1, lo1, omask); + tcg_gen_andi_tl(lo2, lo2, omask); + + amask =3D address_mask_i(dc, -8); + tcg_gen_andi_tl(s1, s1, amask); + tcg_gen_andi_tl(s2, s2, amask); + + /* Compute dst =3D (s1 =3D=3D s2 ? lo1 : lo1 & lo2). */ + tcg_gen_and_tl(lo2, lo2, lo1); + tcg_gen_movcond_tl(TCG_COND_EQ, dst, s1, s2, lo1, lo2); + + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(EDGE8cc, VIS1, gen_edge, a, 8, 1, 0) +TRANS(EDGE8Lcc, VIS1, gen_edge, a, 8, 1, 1) +TRANS(EDGE16cc, VIS1, gen_edge, a, 16, 1, 0) +TRANS(EDGE16Lcc, VIS1, gen_edge, a, 16, 1, 1) +TRANS(EDGE32cc, VIS1, gen_edge, a, 32, 1, 0) +TRANS(EDGE32Lcc, VIS1, gen_edge, a, 32, 1, 1) + +TRANS(EDGE8N, VIS2, gen_edge, a, 8, 0, 0) +TRANS(EDGE8LN, VIS2, gen_edge, a, 8, 0, 1) +TRANS(EDGE16N, VIS2, gen_edge, a, 16, 0, 0) +TRANS(EDGE16LN, VIS2, gen_edge, a, 16, 0, 1) +TRANS(EDGE32N, VIS2, gen_edge, a, 32, 0, 0) +TRANS(EDGE32LN, VIS2, gen_edge, a, 32, 0, 1) + static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u) { TCGv dst, src1, src2; @@ -5075,89 +5099,18 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) =20 switch (opf) { case 0x000: /* VIS I edge8cc */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 =3D gen_load_gpr(dc, rs1); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x001: /* VIS II edge8n */ - CHECK_FPU_FEATURE(dc, VIS2); - cpu_src1 =3D gen_load_gpr(dc, rs1); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x002: /* VIS I edge8lcc */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 =3D gen_load_gpr(dc, rs1); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x003: /* VIS II edge8ln */ - CHECK_FPU_FEATURE(dc, VIS2); - cpu_src1 =3D gen_load_gpr(dc, rs1); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x004: /* VIS I edge16cc */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 =3D gen_load_gpr(dc, rs1); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x005: /* VIS II edge16n */ - CHECK_FPU_FEATURE(dc, VIS2); - cpu_src1 =3D gen_load_gpr(dc, rs1); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x006: /* VIS I edge16lcc */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 =3D gen_load_gpr(dc, rs1); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x007: /* VIS II edge16ln */ - CHECK_FPU_FEATURE(dc, VIS2); - cpu_src1 =3D gen_load_gpr(dc, rs1); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x008: /* VIS I edge32cc */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 =3D gen_load_gpr(dc, rs1); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x009: /* VIS II edge32n */ - CHECK_FPU_FEATURE(dc, VIS2); - cpu_src1 =3D gen_load_gpr(dc, rs1); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x00a: /* VIS I edge32lcc */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 =3D gen_load_gpr(dc, rs1); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x00b: /* VIS II edge32ln */ - CHECK_FPU_FEATURE(dc, VIS2); - cpu_src1 =3D gen_load_gpr(dc, rs1); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1); - gen_store_gpr(dc, rd, cpu_dst); - break; + g_assert_not_reached(); /* in decodetree */ case 0x010: /* VIS I array8 */ CHECK_FPU_FEATURE(dc, VIS1); cpu_src1 =3D gen_load_gpr(dc, rs1); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280628072100007 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 57 ++++++++++++++++++++++++--------------- 2 files changed, 40 insertions(+), 21 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a9630509bd..b15ede5fd4 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -248,6 +248,10 @@ RETRY 10 00001 111110 00000 0 0000000000000 EDGE32N 10 ..... 110110 ..... 0 0000 1001 ..... @r_r_r EDGE32Lcc 10 ..... 110110 ..... 0 0000 1010 ..... @r_r_r EDGE32LN 10 ..... 110110 ..... 0 0000 1011 ..... @r_r_r + + ARRAY8 10 ..... 110110 ..... 0 0001 0000 ..... @r_r_r + ARRAY16 10 ..... 110110 ..... 0 0001 0010 ..... @r_r_r + ARRAY32 10 ..... 110110 ..... 0 0001 0100 ..... @r_r_r ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 2f38453dc6..d40d664f16 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -722,6 +722,25 @@ static void gen_op_popc(TCGv dst, TCGv src1, TCGv src2) tcg_gen_ctpop_tl(dst, src2); } =20 +#ifndef TARGET_SPARC64 +static void gen_helper_array8(TCGv dst, TCGv src1, TCGv src2) +{ + g_assert_not_reached(); +} +#endif + +static void gen_op_array16(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_array8(dst, src1, src2); + tcg_gen_shli_tl(dst, dst, 1); +} + +static void gen_op_array32(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_array8(dst, src1, src2); + tcg_gen_shli_tl(dst, dst, 2); +} + // 1 static void gen_op_eval_ba(TCGv dst) { @@ -4211,6 +4230,22 @@ TRANS(EDGE16LN, VIS2, gen_edge, a, 16, 0, 1) TRANS(EDGE32N, VIS2, gen_edge, a, 32, 0, 0) TRANS(EDGE32LN, VIS2, gen_edge, a, 32, 0, 1) =20 +static bool do_rrr(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv, TCGv, TCGv)) +{ + TCGv dst =3D gen_dest_gpr(dc, a->rd); + TCGv src1 =3D gen_load_gpr(dc, a->rs1); + TCGv src2 =3D gen_load_gpr(dc, a->rs2); + + func(dst, src1, src2); + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(ARRAY8, VIS1, do_rrr, a, gen_helper_array8) +TRANS(ARRAY16, VIS1, do_rrr, a, gen_op_array16) +TRANS(ARRAY32, VIS1, do_rrr, a, gen_op_array32) + static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u) { TCGv dst, src1, src2; @@ -5110,30 +5145,10 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 0x009: /* VIS II edge32n */ case 0x00a: /* VIS I edge32lcc */ case 0x00b: /* VIS II edge32ln */ - g_assert_not_reached(); /* in decodetree */ case 0x010: /* VIS I array8 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 =3D gen_load_gpr(dc, rs1); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x012: /* VIS I array16 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 =3D gen_load_gpr(dc, rs1); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); - tcg_gen_shli_i64(cpu_dst, cpu_dst, 1); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x014: /* VIS I array32 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 =3D gen_load_gpr(dc, rs1); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); - tcg_gen_shli_i64(cpu_dst, cpu_dst, 2); - gen_store_gpr(dc, rd, cpu_dst); - break; + g_assert_not_reached(); /* in decodetree */ case 0x018: /* VIS I alignaddr */ CHECK_FPU_FEATURE(dc, VIS1); cpu_src1 =3D gen_load_gpr(dc, rs1); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280360; cv=none; d=zohomail.com; s=zohoarc; b=g2P7VVXryZmZ2AuJBeGpn8Re0TAmtGqEjjhbWRacWsqRIw25crUBJBFpEE7VYBONfqa9xYsYruiXS/5c2RiK+R5M5sfFWICAHNPdiNdwHvs0ubEmyGRcMNrlQFkDCavl/5PwHDk8W23muvl8PcWA0yyFeteyMIOdKDTS6fQe+V4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280360; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280362964100007 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 56 ++++++++++++++++++++++----------------- 2 files changed, 34 insertions(+), 25 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index b15ede5fd4..f70423895e 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -252,6 +252,9 @@ RETRY 10 00001 111110 00000 0 0000000000000 ARRAY8 10 ..... 110110 ..... 0 0001 0000 ..... @r_r_r ARRAY16 10 ..... 110110 ..... 0 0001 0010 ..... @r_r_r ARRAY32 10 ..... 110110 ..... 0 0001 0100 ..... @r_r_r + + ALIGNADDR 10 ..... 110110 ..... 0 0001 1000 ..... @r_r_r + ALIGNADDRL 10 ..... 110110 ..... 0 0001 1010 ..... @r_r_r ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d40d664f16..5d2be34135 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2747,18 +2747,6 @@ static void gen_load_trap_state_at_tl(TCGv_ptr r_tsp= tr) } } =20 -static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left) -{ - TCGv tmp =3D tcg_temp_new(); - - tcg_gen_add_tl(tmp, s1, s2); - tcg_gen_andi_tl(dst, tmp, -8); - if (left) { - tcg_gen_neg_tl(tmp, tmp); - } - tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3); -} - static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) { TCGv t1, t2, shift; @@ -4246,6 +4234,36 @@ TRANS(ARRAY8, VIS1, do_rrr, a, gen_helper_array8) TRANS(ARRAY16, VIS1, do_rrr, a, gen_op_array16) TRANS(ARRAY32, VIS1, do_rrr, a, gen_op_array32) =20 +static void gen_op_alignaddr(TCGv dst, TCGv s1, TCGv s2) +{ +#ifdef TARGET_SPARC64 + TCGv tmp =3D tcg_temp_new(); + + tcg_gen_add_tl(tmp, s1, s2); + tcg_gen_andi_tl(dst, tmp, -8); + tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3); +#else + g_assert_not_reached(); +#endif +} + +static void gen_op_alignaddrl(TCGv dst, TCGv s1, TCGv s2) +{ +#ifdef TARGET_SPARC64 + TCGv tmp =3D tcg_temp_new(); + + tcg_gen_add_tl(tmp, s1, s2); + tcg_gen_andi_tl(dst, tmp, -8); + tcg_gen_neg_tl(tmp, tmp); + tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3); +#else + g_assert_not_reached(); +#endif +} + +TRANS(ALIGNADDR, VIS1, do_rrr, a, gen_op_alignaddr) +TRANS(ALIGNADDRL, VIS1, do_rrr, a, gen_op_alignaddrl) + static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u) { TCGv dst, src1, src2; @@ -5148,21 +5166,9 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) case 0x010: /* VIS I array8 */ case 0x012: /* VIS I array16 */ case 0x014: /* VIS I array32 */ - g_assert_not_reached(); /* in decodetree */ case 0x018: /* VIS I alignaddr */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 =3D gen_load_gpr(dc, rs1); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x01a: /* VIS I alignaddrl */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 =3D gen_load_gpr(dc, rs1); - cpu_src2 =3D gen_load_gpr(dc, rs2); - gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1); - gen_store_gpr(dc, rd, cpu_dst); - break; + g_assert_not_reached(); /* in decodetree */ case 0x019: /* VIS II bmask */ CHECK_FPU_FEATURE(dc, VIS2); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280794610100008 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 22 +++++++++++++--------- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index f70423895e..db372573a2 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -255,6 +255,8 @@ RETRY 10 00001 111110 00000 0 0000000000000 =20 ALIGNADDR 10 ..... 110110 ..... 0 0001 1000 ..... @r_r_r ALIGNADDRL 10 ..... 110110 ..... 0 0001 1010 ..... @r_r_r + + BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 5d2be34135..ee0c263a99 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4264,6 +4264,18 @@ static void gen_op_alignaddrl(TCGv dst, TCGv s1, TCG= v s2) TRANS(ALIGNADDR, VIS1, do_rrr, a, gen_op_alignaddr) TRANS(ALIGNADDRL, VIS1, do_rrr, a, gen_op_alignaddrl) =20 +static void gen_op_bmask(TCGv dst, TCGv s1, TCGv s2) +{ +#ifdef TARGET_SPARC64 + tcg_gen_add_tl(dst, s1, s2); + tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, dst, 32, 32); +#else + g_assert_not_reached(); +#endif +} + +TRANS(BMASK, VIS2, do_rrr, a, gen_op_bmask) + static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u) { TCGv dst, src1, src2; @@ -4803,7 +4815,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) { unsigned int opc, rs1, rs2, rd; TCGv cpu_src1 __attribute__((unused)); - TCGv cpu_src2 __attribute__((unused)); TCGv_i32 cpu_src1_32, cpu_src2_32; TCGv_i64 cpu_src1_64, cpu_src2_64; TCGv_i32 cpu_dst_32 __attribute__((unused)); @@ -5168,15 +5179,8 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) case 0x014: /* VIS I array32 */ case 0x018: /* VIS I alignaddr */ case 0x01a: /* VIS I alignaddrl */ - g_assert_not_reached(); /* in decodetree */ case 0x019: /* VIS II bmask */ - CHECK_FPU_FEATURE(dc, VIS2); - cpu_src1 =3D gen_load_gpr(dc, rs1); - cpu_src2 =3D gen_load_gpr(dc, rs2); - tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); - tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32); - gen_store_gpr(dc, rd, cpu_dst); - break; + g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); cpu_src1_64 =3D gen_load_fpr_D(dc, rs1); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280798; cv=none; d=zohomail.com; s=zohoarc; b=aLSWhNDGFnDfn/oEr1/jCIofmww4BptXJaAdG7l72N4Of7gP6s/QGpQE80+oJjH3y2moBy/bPYsSh54TM1J+hfa7psAlyA0Wt8lC5caheRY+TAz9ntqVG4itG6hXgei3acn2fJJCSU6DnOb+PsFtw57WFXJeSJvPLzlxfnaTW5M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280798; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280798613100007 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 13 ++++++ target/sparc/translate.c | 92 +++++++++++++++++++++------------------ 2 files changed, 62 insertions(+), 43 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index db372573a2..669a54e297 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -38,6 +38,10 @@ CALL 01 i:s30 &r_r_r rd rs1 rs2 @r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r =20 +&r_r rd rs +@r_r1 .. rd:5 ...... rs:5 . ........ ..... &r_r +@r_r2 .. rd:5 ...... ..... . ........ rs:5 &r_r + { [ STBAR 10 00000 101000 01111 0 0000000000000 @@ -234,6 +238,10 @@ RESTORE 10 ..... 111101 ..... . ............. = @r_r_ri DONE 10 00000 111110 00000 0 0000000000000 RETRY 10 00001 111110 00000 0 0000000000000 =20 +FMOVs 10 ..... 110100 00000 0 0000 0001 ..... @r_r2 +FNEGs 10 ..... 110100 00000 0 0000 0101 ..... @r_r2 +FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2 + { [ EDGE8cc 10 ..... 110110 ..... 0 0000 0000 ..... @r_r_r @@ -257,6 +265,11 @@ RETRY 10 00001 111110 00000 0 0000000000000 ALIGNADDRL 10 ..... 110110 ..... 0 0001 1010 ..... @r_r_r =20 BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r + + FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s + FSRCs 10 ..... 110110 00000 0 0111 1001 ..... @r_r2 # FSRC2s + FNOTs 10 ..... 110110 ..... 0 0110 1011 00000 @r_r1 # FNOT1s + FNOTs 10 ..... 110110 00000 0 0110 0111 ..... @r_r2 # FNOT2s ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ee0c263a99..eb0aa2020f 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1397,6 +1397,29 @@ static void gen_compare_reg(DisasCompare *cmp, int c= ond, TCGv r_src) cmp->c2 =3D tcg_constant_tl(0); } =20 +static void gen_op_clear_ieee_excp_and_FTT(void) +{ + tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); +} + +static void gen_op_fmovs(TCGv_i32 dst, TCGv_i32 src) +{ + gen_op_clear_ieee_excp_and_FTT(); + tcg_gen_mov_i32(dst, src); +} + +static void gen_op_fnegs(TCGv_i32 dst, TCGv_i32 src) +{ + gen_op_clear_ieee_excp_and_FTT(); + gen_helper_fnegs(dst, src); +} + +static void gen_op_fabss(TCGv_i32 dst, TCGv_i32 src) +{ + gen_op_clear_ieee_excp_and_FTT(); + gen_helper_fabss(dst, src); +} + #ifdef TARGET_SPARC64 static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) { @@ -1557,11 +1580,6 @@ static int gen_trap_ifnofpu(DisasContext *dc) return 0; } =20 -static void gen_op_clear_ieee_excp_and_FTT(void) -{ - tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); -} - static void gen_fop_FF(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32)) { @@ -1576,19 +1594,6 @@ static void gen_fop_FF(DisasContext *dc, int rd, int= rs, gen_store_fpr_F(dc, rd, dst); } =20 -static void gen_ne_fop_FF(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i32, TCGv_i32)) -{ - TCGv_i32 dst, src; - - src =3D gen_load_fpr_F(dc, rs); - dst =3D gen_dest_fpr_F(dc); - - gen(dst, src); - - gen_store_fpr_F(dc, rd, dst); -} - static void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32= )) { @@ -4803,6 +4808,27 @@ static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a= , MemOp mop) TRANS(STFSR, ALL, do_stfsr, a, MO_TEUL) TRANS(STXFSR, 64, do_stfsr, a, MO_TEUQ) =20 +static bool do_ff(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + tmp =3D gen_load_fpr_F(dc, a->rs); + func(tmp, tmp); + gen_store_fpr_F(dc, a->rd, tmp); + return advance_pc(dc); +} + +TRANS(FMOVs, ALL, do_ff, a, gen_op_fmovs) +TRANS(FNEGs, ALL, do_ff, a, gen_op_fnegs) +TRANS(FABSs, ALL, do_ff, a, gen_op_fabss) +TRANS(FSRCs, VIS1, do_ff, a, tcg_gen_mov_i32) +TRANS(FNOTs, VIS1, do_ff, a, tcg_gen_not_i32) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4844,15 +4870,9 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) =20 switch (xop) { case 0x1: /* fmovs */ - cpu_src1_32 =3D gen_load_fpr_F(dc, rs2); - gen_store_fpr_F(dc, rd, cpu_src1_32); - break; case 0x5: /* fnegs */ - gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs); - break; case 0x9: /* fabss */ - gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss); - break; + g_assert_not_reached(); /* in decodetree */ case 0x29: /* fsqrts */ gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts); break; @@ -5180,6 +5200,10 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) case 0x018: /* VIS I alignaddr */ case 0x01a: /* VIS I alignaddrl */ case 0x019: /* VIS II bmask */ + case 0x067: /* VIS I fnot2s */ + case 0x06b: /* VIS I fnot1s */ + case 0x075: /* VIS I fsrc1s */ + case 0x079: /* VIS I fsrc2s */ g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -5367,10 +5391,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64); break; - case 0x067: /* VIS I fnot2s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32); - break; case 0x068: /* VIS I fandnot1 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64); @@ -5383,10 +5403,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64); break; - case 0x06b: /* VIS I fnot1s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32); - break; case 0x06c: /* VIS I fxor */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64); @@ -5424,11 +5440,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) cpu_src1_64 =3D gen_load_fpr_D(dc, rs1); gen_store_fpr_D(dc, rd, cpu_src1_64); break; - case 0x075: /* VIS I fsrc1s */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_32 =3D gen_load_fpr_F(dc, rs1); - gen_store_fpr_F(dc, rd, cpu_src1_32); - break; case 0x076: /* VIS I fornot2 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64); @@ -5442,11 +5453,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) cpu_src1_64 =3D gen_load_fpr_D(dc, rs2); gen_store_fpr_D(dc, rd, cpu_src1_64); break; - case 0x079: /* VIS I fsrc2s */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_32 =3D gen_load_fpr_F(dc, rs2); - gen_store_fpr_F(dc, rd, cpu_src1_32); - break; case 0x07a: /* VIS I fornot1 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280659; cv=none; d=zohomail.com; s=zohoarc; b=P1ATdgHDYcJU23GE1QeodIR43TmLNoO2B8033XpMedud/SxezY78CkHpHHFhzloCKB3iVGjIBEkrLofAUNaKzWTsRJPfNYaUNszsP/0/XWMfO3tDDwxFuC3GAj/noEDh8t+PcMFJ+2UyDM+GF0CXAEn5tWdTU7yKWyyflLjljUc= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280660115100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 7 +++ target/sparc/translate.c | 91 +++++++++++++++++++++------------------ 2 files changed, 56 insertions(+), 42 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 669a54e297..23a21f2c20 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -239,8 +239,11 @@ DONE 10 00000 111110 00000 0 0000000000000 RETRY 10 00001 111110 00000 0 0000000000000 =20 FMOVs 10 ..... 110100 00000 0 0000 0001 ..... @r_r2 +FMOVd 10 ..... 110100 00000 0 0000 0010 ..... @r_r2 FNEGs 10 ..... 110100 00000 0 0000 0101 ..... @r_r2 +FNEGd 10 ..... 110100 00000 0 0000 0110 ..... @r_r2 FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2 +FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 =20 { [ @@ -266,9 +269,13 @@ FABSs 10 ..... 110100 00000 0 0000 1001 ..... = @r_r2 =20 BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r =20 + FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @r_r1 # FSRC1d FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s + FSRCd 10 ..... 110110 00000 0 0111 1000 ..... @r_r2 # FSRC2d FSRCs 10 ..... 110110 00000 0 0111 1001 ..... @r_r2 # FSRC2s + FNOTd 10 ..... 110110 ..... 0 0110 1010 00000 @r_r1 # FNOT1d FNOTs 10 ..... 110110 ..... 0 0110 1011 00000 @r_r1 # FNOT1s + FNOTd 10 ..... 110110 00000 0 0110 0110 ..... @r_r2 # FNOT2d FNOTs 10 ..... 110110 00000 0 0110 0111 ..... @r_r2 # FNOT2s ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index eb0aa2020f..572de4ef14 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -44,7 +44,9 @@ #else # define gen_helper_clear_softint(E, S) qemu_build_not_reached() # define gen_helper_done(E) qemu_build_not_reached() +# define gen_helper_fabsd(D, S) qemu_build_not_reached() # define gen_helper_flushw(E) qemu_build_not_reached() +# define gen_helper_fnegd(D, S) qemu_build_not_reached() # define gen_helper_rdccr(D, E) qemu_build_not_reached() # define gen_helper_rdcwp(D, E) qemu_build_not_reached() # define gen_helper_restored(E) qemu_build_not_reached() @@ -1420,6 +1422,24 @@ static void gen_op_fabss(TCGv_i32 dst, TCGv_i32 src) gen_helper_fabss(dst, src); } =20 +static void gen_op_fmovd(TCGv_i64 dst, TCGv_i64 src) +{ + gen_op_clear_ieee_excp_and_FTT(); + tcg_gen_mov_i64(dst, src); +} + +static void gen_op_fnegd(TCGv_i64 dst, TCGv_i64 src) +{ + gen_op_clear_ieee_excp_and_FTT(); + gen_helper_fnegd(dst, src); +} + +static void gen_op_fabsd(TCGv_i64 dst, TCGv_i64 src) +{ + gen_op_clear_ieee_excp_and_FTT(); + gen_helper_fabsd(dst, src); +} + #ifdef TARGET_SPARC64 static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) { @@ -1639,21 +1659,6 @@ static void gen_fop_DD(DisasContext *dc, int rd, int= rs, gen_store_fpr_D(dc, rd, dst); } =20 -#ifdef TARGET_SPARC64 -static void gen_ne_fop_DD(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i64, TCGv_i64)) -{ - TCGv_i64 dst, src; - - src =3D gen_load_fpr_D(dc, rs); - dst =3D gen_dest_fpr_D(dc, rd); - - gen(dst, src); - - gen_store_fpr_D(dc, rd, dst); -} -#endif - static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64= )) { @@ -4829,6 +4834,28 @@ TRANS(FABSs, ALL, do_ff, a, gen_op_fabss) TRANS(FSRCs, VIS1, do_ff, a, tcg_gen_mov_i32) TRANS(FNOTs, VIS1, do_ff, a, tcg_gen_not_i32) =20 +static bool do_dd(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i64, TCGv_i64)) +{ + TCGv_i64 dst, src; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + dst =3D gen_dest_fpr_D(dc, a->rd); + src =3D gen_load_fpr_D(dc, a->rs); + func(dst, src); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FMOVd, 64, do_dd, a, gen_op_fmovd) +TRANS(FNEGd, 64, do_dd, a, gen_op_fnegd) +TRANS(FABSd, 64, do_dd, a, gen_op_fabsd) +TRANS(FSRCd, VIS1, do_dd, a, tcg_gen_mov_i64) +TRANS(FNOTd, VIS1, do_dd, a, tcg_gen_not_i64) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4872,6 +4899,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) case 0x1: /* fmovs */ case 0x5: /* fnegs */ case 0x9: /* fabss */ + case 0x2: /* V9 fmovd */ + case 0x6: /* V9 fnegd */ + case 0xa: /* V9 fabsd */ g_assert_not_reached(); /* in decodetree */ case 0x29: /* fsqrts */ gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts); @@ -4974,24 +5004,14 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi); break; #ifdef TARGET_SPARC64 - case 0x2: /* V9 fmovd */ - cpu_src1_64 =3D gen_load_fpr_D(dc, rs2); - gen_store_fpr_D(dc, rd, cpu_src1_64); - break; case 0x3: /* V9 fmovq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_move_Q(dc, rd, rs2); break; - case 0x6: /* V9 fnegd */ - gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd); - break; case 0x7: /* V9 fnegq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq); break; - case 0xa: /* V9 fabsd */ - gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd); - break; case 0xb: /* V9 fabsq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq); @@ -5204,6 +5224,10 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) case 0x06b: /* VIS I fnot1s */ case 0x075: /* VIS I fsrc1s */ case 0x079: /* VIS I fsrc2s */ + case 0x066: /* VIS I fnot2 */ + case 0x06a: /* VIS I fnot1 */ + case 0x074: /* VIS I fsrc1 */ + case 0x078: /* VIS I fsrc2 */ g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -5387,10 +5411,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32); break; - case 0x066: /* VIS I fnot2 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64); - break; case 0x068: /* VIS I fandnot1 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64); @@ -5399,10 +5419,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32); break; - case 0x06a: /* VIS I fnot1 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64); - break; case 0x06c: /* VIS I fxor */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64); @@ -5435,10 +5451,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32); break; - case 0x074: /* VIS I fsrc1 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 =3D gen_load_fpr_D(dc, rs1); - gen_store_fpr_D(dc, rd, cpu_src1_64); break; case 0x076: /* VIS I fornot2 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -5448,11 +5460,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32); break; - case 0x078: /* VIS I fsrc2 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 =3D gen_load_fpr_D(dc, rs2); - gen_store_fpr_D(dc, rd, cpu_src1_64); - break; case 0x07a: /* VIS I fornot1 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.23.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:23:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279784; x=1698884584; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mf1oJrduPCBqL7ZJPmcmrJhpPRE8uXn/4De5kKhDPeY=; b=ZnGzBBODna+PKMReZ3IEqpU40rrUXy7CRbozznbBh4xgpTvl1ZOr8pc6itDBgy/gMg qQAvHECRUvfMK0cL+rGsfNWsvSZ23c7sUSvqE6nZp8RCpsRNmVFaPLbzJQFNuc4EVGl4 Opkz2/R1BnlVtWHVPvkrJrxNvIsc0WeWdYNG0nEm7D1YmK1SuCRtMdA/zrhyVhPW4GcE gDo716PSgWVEa59CgHpvT/hCElbb3UoCSmfNoulVpq5eHp2O0vhBXTjsDXEP/gY3WDQQ YC1csOUgtChMo7+YnWtLf+6BzRvqJJV8U1xs3ppFSSef/E5Vu28v9FFSXdGt4RVr/Bgc u42g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279784; x=1698884584; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mf1oJrduPCBqL7ZJPmcmrJhpPRE8uXn/4De5kKhDPeY=; b=cMKuT6KQqx0V8W48iZiVfMuwgtgA/6FGNAZmQ+7xkLrMQuftVzzKzQZna7ValuFfda iMAITtL3hDlPZ7xUBzcuhoR7IACNgSjKn3IM79LP/MoWm+Do3WTpLtAmbvtjxGWHfdUk ENWhy0rPzrRRniG9YCyjEQSv1SzyxGglHTLvSk0PCJZQl6Aeueu6JQAXW+z3QnIkztJK 88WbTkVoEn5pEw7aJ2OWVnux10TDMzdeKUOIq1ulc9yRm+YUrmzrLNEMuSg+NHQarvb2 zIfgGPkzTuCfK8RmrzFtKyB+H3AYQx1TOhOrjZltfU6yG8TBnuSouNFs+X7rbhH3R6yk XsQg== X-Gm-Message-State: AOJu0Ywemxk0mCllOLUM24Rw6/R7aQmvh4xSF84AgXISwRHh1Ij2Wu5D qHSvw0ng2CNXndNZG81ryb2KXzf9VO46JxFJ5xg= X-Google-Smtp-Source: AGHT+IErZlCcYAjQaXTfsUlxiW7cHzAMkXv7NTmiXzUgArFc+LPvfAYs84CK3RJFqxBRXrjnGvwlXQ== X-Received: by 2002:a05:6a20:7f86:b0:174:2d20:5414 with SMTP id d6-20020a056a207f8600b001742d205414mr9593997pzj.49.1698279784366; Wed, 25 Oct 2023 17:23:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 69/94] target/sparc: Use tcg_gen_vec_{add,sub}* Date: Wed, 25 Oct 2023 17:15:17 -0700 Message-Id: <20231026001542.1141412-99-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280565917100001 Content-Type: text/plain; charset="utf-8" Replace the local helpers for the same integer operations. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/helper.h | 12 -------- target/sparc/translate.c | 15 +++++----- target/sparc/vis_helper.c | 59 --------------------------------------- 3 files changed, 7 insertions(+), 79 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 790752467f..dd1721a340 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -137,18 +137,6 @@ DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_NO_RWG_SE, i32, i= 64, i64) DEF_HELPER_FLAGS_3(fpack32, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) DEF_HELPER_FLAGS_2(fpackfix, TCG_CALL_NO_RWG_SE, i32, i64, i64) DEF_HELPER_FLAGS_3(bshuffle, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) -#define VIS_HELPER(name) \ - DEF_HELPER_FLAGS_2(f ## name ## 16, TCG_CALL_NO_RWG_SE, \ - i64, i64, i64) \ - DEF_HELPER_FLAGS_2(f ## name ## 16s, TCG_CALL_NO_RWG_SE, \ - i32, i32, i32) \ - DEF_HELPER_FLAGS_2(f ## name ## 32, TCG_CALL_NO_RWG_SE, \ - i64, i64, i64) \ - DEF_HELPER_FLAGS_2(f ## name ## 32s, TCG_CALL_NO_RWG_SE, \ - i32, i32, i32) - -VIS_HELPER(padd) -VIS_HELPER(psub) #define VIS_CMPHELPER(name) \ DEF_HELPER_FLAGS_2(f##name##16, TCG_CALL_NO_RWG_SE, \ i64, i64, i64) \ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 572de4ef14..09ca9c51bd 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -25,9 +25,8 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" - +#include "tcg/tcg-op-gvec.h" #include "exec/helper-gen.h" - #include "exec/translator.h" #include "exec/log.h" #include "asi.h" @@ -5353,15 +5352,15 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) break; case 0x050: /* VIS I fpadd16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16); + gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add16_i64= ); break; case 0x051: /* VIS I fpadd16s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s); + gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_vec_add16_i32= ); break; case 0x052: /* VIS I fpadd32 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32); + gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64= ); break; case 0x053: /* VIS I fpadd32s */ CHECK_FPU_FEATURE(dc, VIS1); @@ -5369,15 +5368,15 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) break; case 0x054: /* VIS I fpsub16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16); + gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_sub16_i64= ); break; case 0x055: /* VIS I fpsub16s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s); + gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_vec_sub16_i32= ); break; case 0x056: /* VIS I fpsub32 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32); + gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64= ); break; case 0x057: /* VIS I fpsub32s */ CHECK_FPU_FEATURE(dc, VIS1); diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index 3afdc6975c..7763b16c24 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -275,65 +275,6 @@ uint64_t helper_fexpand(uint64_t src1, uint64_t src2) return d.ll; } =20 -#define VIS_HELPER(name, F) \ - uint64_t name##16(uint64_t src1, uint64_t src2) \ - { \ - VIS64 s, d; \ - \ - s.ll =3D src1; \ - d.ll =3D src2; \ - \ - d.VIS_W64(0) =3D F(d.VIS_W64(0), s.VIS_W64(0)); \ - d.VIS_W64(1) =3D F(d.VIS_W64(1), s.VIS_W64(1)); \ - d.VIS_W64(2) =3D F(d.VIS_W64(2), s.VIS_W64(2)); \ - d.VIS_W64(3) =3D F(d.VIS_W64(3), s.VIS_W64(3)); \ - \ - return d.ll; \ - } \ - \ - uint32_t name##16s(uint32_t src1, uint32_t src2) \ - { \ - VIS32 s, d; \ - \ - s.l =3D src1; \ - d.l =3D src2; \ - \ - d.VIS_W32(0) =3D F(d.VIS_W32(0), s.VIS_W32(0)); \ - d.VIS_W32(1) =3D F(d.VIS_W32(1), s.VIS_W32(1)); \ - \ - return d.l; \ - } \ - \ - uint64_t name##32(uint64_t src1, uint64_t src2) \ - { \ - VIS64 s, d; \ - \ - s.ll =3D src1; \ - d.ll =3D src2; \ - \ - d.VIS_L64(0) =3D F(d.VIS_L64(0), s.VIS_L64(0)); \ - d.VIS_L64(1) =3D F(d.VIS_L64(1), s.VIS_L64(1)); \ - \ - return d.ll; \ - } \ - \ - uint32_t name##32s(uint32_t src1, uint32_t src2) \ - { \ - VIS32 s, d; \ - \ - s.l =3D src1; \ - d.l =3D src2; \ - \ - d.l =3D F(d.l, s.l); \ - \ - return d.l; \ - } - -#define FADD(a, b) ((a) + (b)) -#define FSUB(a, b) ((a) - (b)) -VIS_HELPER(helper_fpadd, FADD) -VIS_HELPER(helper_fpsub, FSUB) - #define VIS_CMPHELPER(name, F) \ uint64_t name##16(uint64_t src1, uint64_t src2) \ { \ --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.23.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:23:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279785; x=1698884585; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bk59M1JI+E4cyB0CQ9rgcLwL2YU9APHWN+wZfRVduds=; b=OStBVrJE9kNGAQ6mc1jAacHy6OCQOWpAwm2ZsdZAUgLAUGmMpBYSbpe5oNNXnEA9EQ mUrQATaUILyb+CMdg0oM9ELxI9cDaqz+YDoEJ6V59CZn5+8EhYSqpk2J2hMReRpttRfR kfgBvBQYAO2VIZIOm9fdRMuYjKjh3Qi0rxQLHWdZlEfTK5by9gbQnbbOeXwRf0iXRafq JojLMmHGz/FNeN+pQJRNuatR1H9jnIiaTgyJVyQYLXUCiavul34Pmg5IUkf7y9qnPMf5 lubsi0YFPcKdyawbs24K+fYNqSwGsGjwVxNiCHYCfwXgH6VOkmT5mGDkZAynxUer03oN kg9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279785; x=1698884585; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bk59M1JI+E4cyB0CQ9rgcLwL2YU9APHWN+wZfRVduds=; b=QTZ4pZRCm2iHOwJqjb2hvszUdQrNWXPHEVK91ikeOWXtHJiMq14X02rlF0H/I5xg1H MxCHeLyNmMlZ5q1qUibhES75SiMqHpkc8xI5A4UJpU7tKkOYK1bAt+nYGvHC7IraC2Gj 3H0Hhu80e5BN4e6voHeyN9U9r51kWNtQFZuKxg45dS7XDn5A3DMx3VEQM7qmMEOtOeqH XGbZqY5ExHuE2F56drLtJZBbs7tMURdJOwHkHpW9YSPeWgy4lz7TOe1EjY3xbPNiFBnf dWAgW/fdfHBl7OREvhqWEL4cENaaGDseUwBtkktUbq1vVUlC26Bel8zEdUvX8xFE7MP5 5+Qw== X-Gm-Message-State: AOJu0YythxVSvCIFi+qHB+/nR05JOYuM5EVyudCRjI3zxv/ezK+FcfmZ I90NbqxX2PyGhmuhErUtDDzJp92Gjwa/GBVCQHY= X-Google-Smtp-Source: AGHT+IHKiDN31fWCb7lBGMVGzUJ2Rj8ft8Gl3XwMWohW2t7lDSi6S3E7hRJeJoVOCXyfK9uroQzipg== X-Received: by 2002:a17:90a:6e05:b0:27c:edf3:d045 with SMTP id b5-20020a17090a6e0500b0027cedf3d045mr16250718pjk.40.1698279785096; Wed, 25 Oct 2023 17:23:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 70/94] target/sparc: Move gen_ne_fop_FFF insns to decodetree Date: Wed, 25 Oct 2023 17:15:18 -0700 Message-Id: <20231026001542.1141412-100-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280328086100001 Content-Type: text/plain; charset="utf-8" Move FANDNOT1s, FANDNOT2s, FANDs, FNANDs, FNORs, FORNOT1s, FORNOT2s, FORs, FPADD16s, FPADD32s, FPSUB16s, FPSUB32s, FXNORs, FXORs. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 16 ++++++ target/sparc/translate.c | 116 ++++++++++++++------------------------ 2 files changed, 59 insertions(+), 73 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 23a21f2c20..0290f2aefb 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -37,6 +37,7 @@ CALL 01 i:s30 =20 &r_r_r rd rs1 rs2 @r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r +@r_r_r_swap .. rd:5 ...... rs2:5 . ........ rs1:5 &r_r_r =20 &r_r rd rs @r_r1 .. rd:5 ...... rs:5 . ........ ..... &r_r @@ -277,6 +278,21 @@ FABSd 10 ..... 110100 00000 0 0000 1010 ..... = @r_r2 FNOTs 10 ..... 110110 ..... 0 0110 1011 00000 @r_r1 # FNOT1s FNOTd 10 ..... 110110 00000 0 0110 0110 ..... @r_r2 # FNOT2d FNOTs 10 ..... 110110 00000 0 0110 0111 ..... @r_r2 # FNOT2s + + FPADD16s 10 ..... 110110 ..... 0 0101 0001 ..... @r_r_r + FPADD32s 10 ..... 110110 ..... 0 0101 0011 ..... @r_r_r + FPSUB16s 10 ..... 110110 ..... 0 0101 0101 ..... @r_r_r + FPSUB32s 10 ..... 110110 ..... 0 0101 0111 ..... @r_r_r + FNORs 10 ..... 110110 ..... 0 0110 0011 ..... @r_r_r + FANDNOTs 10 ..... 110110 ..... 0 0110 0101 ..... @r_r_r # FAND= NOT2s + FANDNOTs 10 ..... 110110 ..... 0 0110 1001 ..... @r_r_r_swap # .= .. 1s + FXORs 10 ..... 110110 ..... 0 0110 1101 ..... @r_r_r + FNANDs 10 ..... 110110 ..... 0 0110 1111 ..... @r_r_r + FANDs 10 ..... 110110 ..... 0 0111 0001 ..... @r_r_r + FXNORs 10 ..... 110110 ..... 0 0111 0011 ..... @r_r_r + FORNOTs 10 ..... 110110 ..... 0 0111 0111 ..... @r_r_r # FOR= NOT2s + FORNOTs 10 ..... 110110 ..... 0 0111 1011 ..... @r_r_r_swap # .= .. 1s + FORs 10 ..... 110110 ..... 0 0111 1101 ..... @r_r_r ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 09ca9c51bd..949d1954a4 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1628,22 +1628,6 @@ static void gen_fop_FFF(DisasContext *dc, int rd, in= t rs1, int rs2, gen_store_fpr_F(dc, rd, dst); } =20 -#ifdef TARGET_SPARC64 -static void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) -{ - TCGv_i32 dst, src1, src2; - - src1 =3D gen_load_fpr_F(dc, rs1); - src2 =3D gen_load_fpr_F(dc, rs2); - dst =3D gen_dest_fpr_F(dc); - - gen(dst, src1, src2); - - gen_store_fpr_F(dc, rd, dst); -} -#endif - static void gen_fop_DD(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64)) { @@ -4855,6 +4839,35 @@ TRANS(FABSd, 64, do_dd, a, gen_op_fabsd) TRANS(FSRCd, VIS1, do_dd, a, tcg_gen_mov_i64) TRANS(FNOTd, VIS1, do_dd, a, tcg_gen_not_i64) =20 +static bool do_fff(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + src1 =3D gen_load_fpr_F(dc, a->rs1); + src2 =3D gen_load_fpr_F(dc, a->rs2); + func(src1, src1, src2); + gen_store_fpr_F(dc, a->rd, src1); + return advance_pc(dc); +} + +TRANS(FPADD16s, VIS1, do_fff, a, tcg_gen_vec_add16_i32) +TRANS(FPADD32s, VIS1, do_fff, a, tcg_gen_add_i32) +TRANS(FPSUB16s, VIS1, do_fff, a, tcg_gen_vec_sub16_i32) +TRANS(FPSUB32s, VIS1, do_fff, a, tcg_gen_sub_i32) +TRANS(FNORs, VIS1, do_fff, a, tcg_gen_nor_i32) +TRANS(FANDNOTs, VIS1, do_fff, a, tcg_gen_andc_i32) +TRANS(FXORs, VIS1, do_fff, a, tcg_gen_xor_i32) +TRANS(FNANDs, VIS1, do_fff, a, tcg_gen_nand_i32) +TRANS(FANDs, VIS1, do_fff, a, tcg_gen_and_i32) +TRANS(FXNORs, VIS1, do_fff, a, tcg_gen_eqv_i32) +TRANS(FORNOTs, VIS1, do_fff, a, tcg_gen_orc_i32) +TRANS(FORs, VIS1, do_fff, a, tcg_gen_or_i32) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5227,6 +5240,20 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) case 0x06a: /* VIS I fnot1 */ case 0x074: /* VIS I fsrc1 */ case 0x078: /* VIS I fsrc2 */ + case 0x051: /* VIS I fpadd16s */ + case 0x053: /* VIS I fpadd32s */ + case 0x055: /* VIS I fpsub16s */ + case 0x057: /* VIS I fpsub32s */ + case 0x063: /* VIS I fnors */ + case 0x065: /* VIS I fandnot2s */ + case 0x069: /* VIS I fandnot1s */ + case 0x06d: /* VIS I fxors */ + case 0x06f: /* VIS I fnands */ + case 0x071: /* VIS I fands */ + case 0x073: /* VIS I fxnors */ + case 0x077: /* VIS I fornot2s */ + case 0x07b: /* VIS I fornot1s */ + case 0x07d: /* VIS I fors */ g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -5354,34 +5381,18 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add16_i64= ); break; - case 0x051: /* VIS I fpadd16s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_vec_add16_i32= ); - break; case 0x052: /* VIS I fpadd32 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64= ); break; - case 0x053: /* VIS I fpadd32s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32); - break; case 0x054: /* VIS I fpsub16 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_sub16_i64= ); break; - case 0x055: /* VIS I fpsub16s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_vec_sub16_i32= ); - break; case 0x056: /* VIS I fpsub32 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64= ); break; - case 0x057: /* VIS I fpsub32s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32); - break; case 0x060: /* VIS I fzero */ CHECK_FPU_FEATURE(dc, VIS1); cpu_dst_64 =3D gen_dest_fpr_D(dc, rd); @@ -5398,83 +5409,42 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64); break; - case 0x063: /* VIS I fnors */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32); - break; case 0x064: /* VIS I fandnot2 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64); break; - case 0x065: /* VIS I fandnot2s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32); - break; case 0x068: /* VIS I fandnot1 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64); break; - case 0x069: /* VIS I fandnot1s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32); - break; case 0x06c: /* VIS I fxor */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64); break; - case 0x06d: /* VIS I fxors */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32); - break; case 0x06e: /* VIS I fnand */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64); break; - case 0x06f: /* VIS I fnands */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32); - break; case 0x070: /* VIS I fand */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64); break; - case 0x071: /* VIS I fands */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32); - break; case 0x072: /* VIS I fxnor */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64); break; - case 0x073: /* VIS I fxnors */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32); - break; - break; case 0x076: /* VIS I fornot2 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64); break; - case 0x077: /* VIS I fornot2s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32); - break; case 0x07a: /* VIS I fornot1 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64); break; - case 0x07b: /* VIS I fornot1s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32); - break; case 0x07c: /* VIS I for */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64); break; - case 0x07d: /* VIS I fors */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32); - break; case 0x07e: /* VIS I fone */ CHECK_FPU_FEATURE(dc, VIS1); cpu_dst_64 =3D gen_dest_fpr_D(dc, rd); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698279998; cv=none; d=zohomail.com; s=zohoarc; b=I1NziMfwh4HWaewGxtnVVhLwSGBFfFrnDUVeu+3U7Ysk/g/qGOPBYG9X/D6j8ljySP9dHa1wpPTbbJ4b+MyNLN1umIKVSUpTBzoodMJRp+m3PqjjJLcEB+JGjE9LheEwkof+JGBoDeuVJa5zLWzs1+KA1KNFm7WLbsjtO4ELv8M= ARC-Message-Signature: i=1; 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Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 26 ++++++ target/sparc/translate.c | 178 +++++++++++++++----------------------- 2 files changed, 98 insertions(+), 106 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 0290f2aefb..0e29629b5c 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -270,6 +270,17 @@ FABSd 10 ..... 110100 00000 0 0000 1010 ..... = @r_r2 =20 BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r =20 + FMUL8x16 10 ..... 110110 ..... 0 0011 0001 ..... @r_r_r + FMUL8x16AU 10 ..... 110110 ..... 0 0011 0011 ..... @r_r_r + FMUL8x16AL 10 ..... 110110 ..... 0 0011 0101 ..... @r_r_r + FMUL8SUx16 10 ..... 110110 ..... 0 0011 0110 ..... @r_r_r + FMUL8ULx16 10 ..... 110110 ..... 0 0011 0111 ..... @r_r_r + FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @r_r_r + FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @r_r_r + + FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @r_r_r + FEXPAND 10 ..... 110110 ..... 0 0100 1101 ..... @r_r_r + FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @r_r1 # FSRC1d FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s FSRCd 10 ..... 110110 00000 0 0111 1000 ..... @r_r2 # FSRC2d @@ -279,19 +290,34 @@ FABSd 10 ..... 110100 00000 0 0000 1010 ..... = @r_r2 FNOTd 10 ..... 110110 00000 0 0110 0110 ..... @r_r2 # FNOT2d FNOTs 10 ..... 110110 00000 0 0110 0111 ..... @r_r2 # FNOT2s =20 + FPADD16 10 ..... 110110 ..... 0 0101 0000 ..... @r_r_r FPADD16s 10 ..... 110110 ..... 0 0101 0001 ..... @r_r_r + FPADD32 10 ..... 110110 ..... 0 0101 0010 ..... @r_r_r FPADD32s 10 ..... 110110 ..... 0 0101 0011 ..... @r_r_r + FPSUB16 10 ..... 110110 ..... 0 0101 0100 ..... @r_r_r FPSUB16s 10 ..... 110110 ..... 0 0101 0101 ..... @r_r_r + FPSUB32 10 ..... 110110 ..... 0 0101 0110 ..... @r_r_r FPSUB32s 10 ..... 110110 ..... 0 0101 0111 ..... @r_r_r + + FNORd 10 ..... 110110 ..... 0 0110 0010 ..... @r_r_r FNORs 10 ..... 110110 ..... 0 0110 0011 ..... @r_r_r + FANDNOTd 10 ..... 110110 ..... 0 0110 0100 ..... @r_r_r # FAND= NOT2d FANDNOTs 10 ..... 110110 ..... 0 0110 0101 ..... @r_r_r # FAND= NOT2s + FANDNOTd 10 ..... 110110 ..... 0 0110 1000 ..... @r_r_r_swap # .= .. 1d FANDNOTs 10 ..... 110110 ..... 0 0110 1001 ..... @r_r_r_swap # .= .. 1s + FXORd 10 ..... 110110 ..... 0 0110 1100 ..... @r_r_r FXORs 10 ..... 110110 ..... 0 0110 1101 ..... @r_r_r + FNANDd 10 ..... 110110 ..... 0 0110 1110 ..... @r_r_r FNANDs 10 ..... 110110 ..... 0 0110 1111 ..... @r_r_r + FANDd 10 ..... 110110 ..... 0 0111 0000 ..... @r_r_r FANDs 10 ..... 110110 ..... 0 0111 0001 ..... @r_r_r + FXNORd 10 ..... 110110 ..... 0 0111 0010 ..... @r_r_r FXNORs 10 ..... 110110 ..... 0 0111 0011 ..... @r_r_r + FORNOTd 10 ..... 110110 ..... 0 0111 0110 ..... @r_r_r # FOR= NOT2d FORNOTs 10 ..... 110110 ..... 0 0111 0111 ..... @r_r_r # FOR= NOT2s + FORNOTd 10 ..... 110110 ..... 0 0111 1010 ..... @r_r_r_swap # .= .. 1d FORNOTs 10 ..... 110110 ..... 0 0111 1011 ..... @r_r_r_swap # .= .. 1s + FORd 10 ..... 110110 ..... 0 0111 1100 ..... @r_r_r FORs 10 ..... 110110 ..... 0 0111 1101 ..... @r_r_r ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 949d1954a4..35fdcfe4c1 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -63,6 +63,15 @@ # define gen_helper_write_softint(E, S) qemu_build_not_reached() # define gen_helper_wrpil(E, S) qemu_build_not_reached() # define gen_helper_wrpstate(E, S) qemu_build_not_reached() +# define gen_helper_fexpand ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fmul8sux16 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fmul8ulx16 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fmul8x16al ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fmul8x16au ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fmul8x16 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fmuld8sux16 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fmuld8ulx16 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fpmerge ({ qemu_build_not_reached(); NULL= ; }) # define FSR_LDXFSR_MASK 0 # define FSR_LDXFSR_OLDMASK 0 # define MAXTL_MASK 0 @@ -1658,20 +1667,6 @@ static void gen_fop_DDD(DisasContext *dc, int rd, in= t rs1, int rs2, } =20 #ifdef TARGET_SPARC64 -static void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64)) -{ - TCGv_i64 dst, src1, src2; - - src1 =3D gen_load_fpr_D(dc, rs1); - src2 =3D gen_load_fpr_D(dc, rs2); - dst =3D gen_dest_fpr_D(dc, rd); - - gen(dst, src1, src2); - - gen_store_fpr_D(dc, rd, dst); -} - static void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv= _i64)) { @@ -4868,6 +4863,46 @@ TRANS(FXNORs, VIS1, do_fff, a, tcg_gen_eqv_i32) TRANS(FORNOTs, VIS1, do_fff, a, tcg_gen_orc_i32) TRANS(FORs, VIS1, do_fff, a, tcg_gen_or_i32) =20 +static bool do_ddd(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_i64, TCGv_i64, TCGv_i64)) +{ + TCGv_i64 dst, src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + dst =3D gen_dest_fpr_D(dc, a->rd); + src1 =3D gen_load_fpr_D(dc, a->rs1); + src2 =3D gen_load_fpr_D(dc, a->rs2); + func(dst, src1, src2); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FMUL8x16, VIS1, do_ddd, a, gen_helper_fmul8x16) +TRANS(FMUL8x16AU, VIS1, do_ddd, a, gen_helper_fmul8x16au) +TRANS(FMUL8x16AL, VIS1, do_ddd, a, gen_helper_fmul8x16al) +TRANS(FMUL8SUx16, VIS1, do_ddd, a, gen_helper_fmul8sux16) +TRANS(FMUL8ULx16, VIS1, do_ddd, a, gen_helper_fmul8ulx16) +TRANS(FMULD8SUx16, VIS1, do_ddd, a, gen_helper_fmuld8sux16) +TRANS(FMULD8ULx16, VIS1, do_ddd, a, gen_helper_fmuld8ulx16) +TRANS(FPMERGE, VIS1, do_ddd, a, gen_helper_fpmerge) +TRANS(FEXPAND, VIS1, do_ddd, a, gen_helper_fexpand) + +TRANS(FPADD16, VIS1, do_ddd, a, tcg_gen_vec_add16_i64) +TRANS(FPADD32, VIS1, do_ddd, a, tcg_gen_vec_add32_i64) +TRANS(FPSUB16, VIS1, do_ddd, a, tcg_gen_vec_sub16_i64) +TRANS(FPSUB32, VIS1, do_ddd, a, tcg_gen_vec_sub32_i64) +TRANS(FNORd, VIS1, do_ddd, a, tcg_gen_nor_i64) +TRANS(FANDNOTd, VIS1, do_ddd, a, tcg_gen_andc_i64) +TRANS(FXORd, VIS1, do_ddd, a, tcg_gen_xor_i64) +TRANS(FNANDd, VIS1, do_ddd, a, tcg_gen_nand_i64) +TRANS(FANDd, VIS1, do_ddd, a, tcg_gen_and_i64) +TRANS(FXNORd, VIS1, do_ddd, a, tcg_gen_eqv_i64) +TRANS(FORNOTd, VIS1, do_ddd, a, tcg_gen_orc_i64) +TRANS(FORd, VIS1, do_ddd, a, tcg_gen_or_i64) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5254,6 +5289,29 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) case 0x077: /* VIS I fornot2s */ case 0x07b: /* VIS I fornot1s */ case 0x07d: /* VIS I fors */ + case 0x050: /* VIS I fpadd16 */ + case 0x052: /* VIS I fpadd32 */ + case 0x054: /* VIS I fpsub16 */ + case 0x056: /* VIS I fpsub32 */ + case 0x062: /* VIS I fnor */ + case 0x064: /* VIS I fandnot2 */ + case 0x068: /* VIS I fandnot1 */ + case 0x06c: /* VIS I fxor */ + case 0x06e: /* VIS I fnand */ + case 0x070: /* VIS I fand */ + case 0x072: /* VIS I fxnor */ + case 0x076: /* VIS I fornot2 */ + case 0x07a: /* VIS I fornot1 */ + case 0x07c: /* VIS I for */ + case 0x031: /* VIS I fmul8x16 */ + case 0x033: /* VIS I fmul8x16au */ + case 0x035: /* VIS I fmul8x16al */ + case 0x036: /* VIS I fmul8sux16 */ + case 0x037: /* VIS I fmul8ulx16 */ + case 0x038: /* VIS I fmuld8sux16 */ + case 0x039: /* VIS I fmuld8ulx16 */ + case 0x04b: /* VIS I fpmerge */ + case 0x04d: /* VIS I fexpand */ g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -5311,34 +5369,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64); gen_store_gpr(dc, rd, cpu_dst); break; - case 0x031: /* VIS I fmul8x16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16); - break; - case 0x033: /* VIS I fmul8x16au */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au= ); - break; - case 0x035: /* VIS I fmul8x16al */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al= ); - break; - case 0x036: /* VIS I fmul8sux16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16= ); - break; - case 0x037: /* VIS I fmul8ulx16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16= ); - break; - case 0x038: /* VIS I fmuld8sux16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux1= 6); - break; - case 0x039: /* VIS I fmuld8ulx16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx1= 6); - break; case 0x03a: /* VIS I fpack32 */ CHECK_FPU_FEATURE(dc, VIS1); gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32); @@ -5365,34 +5395,10 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) CHECK_FPU_FEATURE(dc, VIS1); gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata); break; - case 0x04b: /* VIS I fpmerge */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge); - break; case 0x04c: /* VIS II bshuffle */ CHECK_FPU_FEATURE(dc, VIS2); gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle); break; - case 0x04d: /* VIS I fexpand */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand); - break; - case 0x050: /* VIS I fpadd16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add16_i64= ); - break; - case 0x052: /* VIS I fpadd32 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64= ); - break; - case 0x054: /* VIS I fpsub16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_sub16_i64= ); - break; - case 0x056: /* VIS I fpsub32 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64= ); - break; case 0x060: /* VIS I fzero */ CHECK_FPU_FEATURE(dc, VIS1); cpu_dst_64 =3D gen_dest_fpr_D(dc, rd); @@ -5405,46 +5411,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) tcg_gen_movi_i32(cpu_dst_32, 0); gen_store_fpr_F(dc, rd, cpu_dst_32); break; - case 0x062: /* VIS I fnor */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64); - break; - case 0x064: /* VIS I fandnot2 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64); - break; - case 0x068: /* VIS I fandnot1 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64); - break; - case 0x06c: /* VIS I fxor */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64); - break; - case 0x06e: /* VIS I fnand */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64); - break; - case 0x070: /* VIS I fand */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64); - break; - case 0x072: /* VIS I fxnor */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64); - break; - case 0x076: /* VIS I fornot2 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64); - break; - case 0x07a: /* VIS I fornot1 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64); - break; - case 0x07c: /* VIS I for */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64); - break; case 0x07e: /* VIS I fone */ CHECK_FPU_FEATURE(dc, VIS1); cpu_dst_64 =3D gen_dest_fpr_D(dc, rd); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280798609100006 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 41 +++++++++++++++++++++------------------ 2 files changed, 23 insertions(+), 19 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 0e29629b5c..42d740ad44 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -277,6 +277,7 @@ FABSd 10 ..... 110100 00000 0 0000 1010 ..... = @r_r2 FMUL8ULx16 10 ..... 110110 ..... 0 0011 0111 ..... @r_r_r FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @r_r_r FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @r_r_r + PDIST 10 ..... 110110 ..... 0 0011 1110 ..... @r_r_r =20 FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @r_r_r FEXPAND 10 ..... 110110 ..... 0 0100 1101 ..... @r_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 35fdcfe4c1..40ef395d14 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -72,6 +72,7 @@ # define gen_helper_fmuld8sux16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fmuld8ulx16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fpmerge ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_pdist ({ qemu_build_not_reached(); NULL= ; }) # define FSR_LDXFSR_MASK 0 # define FSR_LDXFSR_OLDMASK 0 # define MAXTL_MASK 0 @@ -1680,21 +1681,6 @@ static void gen_gsr_fop_DDD(DisasContext *dc, int rd= , int rs1, int rs2, =20 gen_store_fpr_D(dc, rd, dst); } - -static void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv= _i64)) -{ - TCGv_i64 dst, src0, src1, src2; - - src1 =3D gen_load_fpr_D(dc, rs1); - src2 =3D gen_load_fpr_D(dc, rs2); - src0 =3D gen_load_fpr_D(dc, rd); - dst =3D gen_dest_fpr_D(dc, rd); - - gen(dst, src0, src1, src2); - - gen_store_fpr_D(dc, rd, dst); -} #endif =20 static void gen_fop_QQ(DisasContext *dc, int rd, int rs, @@ -4903,6 +4889,26 @@ TRANS(FXNORd, VIS1, do_ddd, a, tcg_gen_eqv_i64) TRANS(FORNOTd, VIS1, do_ddd, a, tcg_gen_orc_i64) TRANS(FORd, VIS1, do_ddd, a, tcg_gen_or_i64) =20 +static bool do_dddd(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) +{ + TCGv_i64 dst, src0, src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + dst =3D gen_dest_fpr_D(dc, a->rd); + src0 =3D gen_load_fpr_D(dc, a->rd); + src1 =3D gen_load_fpr_D(dc, a->rs1); + src2 =3D gen_load_fpr_D(dc, a->rs2); + func(dst, src0, src1, src2); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(PDIST, VIS1, do_dddd, a, gen_helper_pdist) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5312,6 +5318,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) case 0x039: /* VIS I fmuld8ulx16 */ case 0x04b: /* VIS I fpmerge */ case 0x04d: /* VIS I fexpand */ + case 0x03e: /* VIS I pdist */ g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -5387,10 +5394,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64); gen_store_fpr_F(dc, rd, cpu_dst_32); break; - case 0x03e: /* VIS I pdist */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist); - break; case 0x048: /* VIS I faligndata */ CHECK_FPU_FEATURE(dc, VIS1); gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280056; cv=none; d=zohomail.com; s=zohoarc; b=hPkKv0MmWRQGIausXhwO4ifICWw9dxEb5kuPR32XqiPBVI0SejOF5z61MMd1h6y5qtJKmufUF3Yl4cJUXytfBwUi2T1wxzTDCsDmjnIN6jGqNDKdMqQk9EnrzSBcWnj+o28Ccaruh2hq0t0rdAbXHwG6TFhJ2DGZmEMTF8XPhs4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280056; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.23.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:23:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279787; x=1698884587; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mOv2aXvy/cTQRcQjfdy8YMCe5wBIO8HMxVf+QakBJKM=; b=gxsVK33zrqz50Hie0achCX8XpJCLt0SuPEXNo4wvrGyx8d2F0SSPYurTmfwSFpDD7U RUtpfQ3Nfaq4hewb1neC4kRwfxSNrgW7VVzl75hNbtsj00Yp9krKN2x03rV0G5lfDvme NQ0Xx3zvImMYX77b92Z1B9JWaqCrzu1QJcb7AOTFRaXxpnvYkxRgaIHWBHHYcYH2jJXx 0ZbBrCr8a7jWGipCzg2Vqqg6/RzHPNlPc96cLgtLbko1pWQzzvsN/9bC5HZmY3IbqkT8 gcfuj71W4sCBNiRBUjgg2kE+uBJPlyzpejBk8nx/p5VkVPWoR3+aN2nXjE0sGJeYmtLj cNBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279787; x=1698884587; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mOv2aXvy/cTQRcQjfdy8YMCe5wBIO8HMxVf+QakBJKM=; b=VSJDAJKgbtTCUyHslnarcKOrBmvQnanrasT8AT/7DeY9wDjgZytmxIDOi1pHhC4HtY 6fMtyYpk1eN5PQagmf36sG6IV4gQiJnaX2kulYjrLTocS7c0JYtRWuy6ehLeeVsIBA9X 319JESlKEuTfwCzzV1lNkmKFVjni31gNDf/+iJuxZIHeubmrcfFO1aTq3aOflQz7M67F f8Sde1fEMGSy95Yq0eMck6UJYWvKoFik+0kEtAQtJg8Z9ZZV1mAY7/5K2LeIpxPWrQOz JXZpTinPEQR1fKb2BBGQg991q/PucIGJCErg/ueeQ+PjiV2W1NzgkwGAzkiTXvxYmiTi 2y8Q== X-Gm-Message-State: AOJu0YyEEZEkLWmPsOtknjjRRUpl10ktKQT99vbqHc5fbCR3qwOLCNEL GPA4Mp6Riu6jI0XmljD9HV2lACAePt+D/Qzu9aA= X-Google-Smtp-Source: AGHT+IGwqkFNa1Sd9OY6+TGxrP4TIHHlc9gecYxzAu79Vxvk3ihbpgWWsMGwXyRlRyuaHxRNRi5IuQ== X-Received: by 2002:a17:90a:1a52:b0:27f:bd9e:5a10 with SMTP id 18-20020a17090a1a5200b0027fbd9e5a10mr8285510pjl.20.1698279787354; Wed, 25 Oct 2023 17:23:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 73/94] target/sparc: Move gen_gsr_fop_DDD insns to decodetree Date: Wed, 25 Oct 2023 17:15:21 -0700 Message-Id: <20231026001542.1141412-103-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280057304100001 Content-Type: text/plain; charset="utf-8" Move FPACK32, FALIGNDATA, BSHUFFLE. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 ++ target/sparc/translate.c | 101 ++++++++++++++++++++------------------ 2 files changed, 55 insertions(+), 49 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 42d740ad44..bc449023dd 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -277,9 +277,12 @@ FABSd 10 ..... 110100 00000 0 0000 1010 ..... = @r_r2 FMUL8ULx16 10 ..... 110110 ..... 0 0011 0111 ..... @r_r_r FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @r_r_r FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @r_r_r + FPACK32 10 ..... 110110 ..... 0 0011 1010 ..... @r_r_r PDIST 10 ..... 110110 ..... 0 0011 1110 ..... @r_r_r =20 + FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @r_r_r FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @r_r_r + BSHUFFLE 10 ..... 110110 ..... 0 0100 1100 ..... @r_r_r FEXPAND 10 ..... 110110 ..... 0 0100 1101 ..... @r_r_r =20 FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @r_r1 # FSRC1d diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 40ef395d14..197c0bea54 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -752,6 +752,51 @@ static void gen_op_array32(TCGv dst, TCGv src1, TCGv s= rc2) tcg_gen_shli_tl(dst, dst, 2); } =20 +static void gen_op_fpack32(TCGv_i64 dst, TCGv_i64 src1, TCGv_i64 src2) +{ +#ifdef TARGET_SPARC64 + gen_helper_fpack32(dst, cpu_gsr, src1, src2); +#else + g_assert_not_reached(); +#endif +} + +static void gen_op_faligndata(TCGv_i64 dst, TCGv_i64 s1, TCGv_i64 s2) +{ +#ifdef TARGET_SPARC64 + TCGv t1, t2, shift; + + t1 =3D tcg_temp_new(); + t2 =3D tcg_temp_new(); + shift =3D tcg_temp_new(); + + tcg_gen_andi_tl(shift, cpu_gsr, 7); + tcg_gen_shli_tl(shift, shift, 3); + tcg_gen_shl_tl(t1, s1, shift); + + /* + * A shift of 64 does not produce 0 in TCG. Divide this into a + * shift of (up to 63) followed by a constant shift of 1. + */ + tcg_gen_xori_tl(shift, shift, 63); + tcg_gen_shr_tl(t2, s2, shift); + tcg_gen_shri_tl(t2, t2, 1); + + tcg_gen_or_tl(dst, t1, t2); +#else + g_assert_not_reached(); +#endif +} + +static void gen_op_bshuffle(TCGv_i64 dst, TCGv_i64 src1, TCGv_i64 src2) +{ +#ifdef TARGET_SPARC64 + gen_helper_bshuffle(dst, cpu_gsr, src1, src2); +#else + g_assert_not_reached(); +#endif +} + // 1 static void gen_op_eval_ba(TCGv dst) { @@ -1667,22 +1712,6 @@ static void gen_fop_DDD(DisasContext *dc, int rd, in= t rs1, int rs2, gen_store_fpr_D(dc, rd, dst); } =20 -#ifdef TARGET_SPARC64 -static void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv= _i64)) -{ - TCGv_i64 dst, src1, src2; - - src1 =3D gen_load_fpr_D(dc, rs1); - src2 =3D gen_load_fpr_D(dc, rs2); - dst =3D gen_dest_fpr_D(dc, rd); - - gen(dst, cpu_gsr, src1, src2); - - gen_store_fpr_D(dc, rd, dst); -} -#endif - static void gen_fop_QQ(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_ptr)) { @@ -2720,27 +2749,6 @@ static void gen_load_trap_state_at_tl(TCGv_ptr r_tsp= tr) tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp); } } - -static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) -{ - TCGv t1, t2, shift; - - t1 =3D tcg_temp_new(); - t2 =3D tcg_temp_new(); - shift =3D tcg_temp_new(); - - tcg_gen_andi_tl(shift, gsr, 7); - tcg_gen_shli_tl(shift, shift, 3); - tcg_gen_shl_tl(t1, s1, shift); - - /* A shift of 64 does not produce 0 in TCG. Divide this into a - shift of (up to 63) followed by a constant shift of 1. */ - tcg_gen_xori_tl(shift, shift, 63); - tcg_gen_shr_tl(t2, s2, shift); - tcg_gen_shri_tl(t2, t2, 1); - - tcg_gen_or_tl(dst, t1, t2); -} #endif =20 static int extract_dfpreg(DisasContext *dc, int x) @@ -4889,6 +4897,10 @@ TRANS(FXNORd, VIS1, do_ddd, a, tcg_gen_eqv_i64) TRANS(FORNOTd, VIS1, do_ddd, a, tcg_gen_orc_i64) TRANS(FORd, VIS1, do_ddd, a, tcg_gen_or_i64) =20 +TRANS(FPACK32, VIS1, do_ddd, a, gen_op_fpack32) +TRANS(FALIGNDATAg, VIS1, do_ddd, a, gen_op_faligndata) +TRANS(BSHUFFLE, VIS2, do_ddd, a, gen_op_bshuffle) + static bool do_dddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) { @@ -5319,6 +5331,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) case 0x04b: /* VIS I fpmerge */ case 0x04d: /* VIS I fexpand */ case 0x03e: /* VIS I pdist */ + case 0x03a: /* VIS I fpack32 */ + case 0x048: /* VIS I faligndata */ + case 0x04c: /* VIS II bshuffle */ g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -5376,10 +5391,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64); gen_store_gpr(dc, rd, cpu_dst); break; - case 0x03a: /* VIS I fpack32 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32); - break; case 0x03b: /* VIS I fpack16 */ CHECK_FPU_FEATURE(dc, VIS1); cpu_src1_64 =3D gen_load_fpr_D(dc, rs2); @@ -5394,14 +5405,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64); gen_store_fpr_F(dc, rd, cpu_dst_32); break; - case 0x048: /* VIS I faligndata */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata); - break; - case 0x04c: /* VIS II bshuffle */ - CHECK_FPU_FEATURE(dc, VIS2); - gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle); - break; case 0x060: /* VIS I fzero */ CHECK_FPU_FEATURE(dc, VIS1); cpu_dst_64 =3D gen_dest_fpr_D(dc, rd); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280721; cv=none; d=zohomail.com; s=zohoarc; b=iVPVaWREPIZpHQ5RHitPpqaz7R1uPW4GuKqseGkjydowaiKbJLqP1anKCMklI80bOnlFnIW7m1s/8/DyKodCp09KBybclhrjBm3tMtyDa8BW/itcbbPuQLOxEFlO1zc+12LtyPrHfIm6bFzS+aU2HyldShDiSZCJ87vAghQU0WY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280721; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=aiKlYh0ZSQ4q5RqF1EsnIe40ZaI3W0/mpHtSrRjKKnM=; b=lK2OG0OH2PJNzt3NononHlsXWvyor3gPBBzOJglofYAO7WS2//GhF/ADv6yxbmBSL0zY2SsWAhGXgfgaa95Ai3Ct9XawoVU35E9gsa4gVz7eaxkxT88dBtO3AZTzalV9coUV+2Ir6+ywuGrqYu9NmGZagADRlooZr/oGgE59kqE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698280721433801.0236492543103; Wed, 25 Oct 2023 17:38:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvoAQ-0006FM-78; Wed, 25 Oct 2023 20:24:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo9k-0003EF-3X for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:23:25 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo9X-0008EZ-6d for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:23:22 -0400 Received: by mail-pj1-x102b.google.com with SMTP id 98e67ed59e1d1-27e1eea2f0dso225771a91.1 for ; Wed, 25 Oct 2023 17:23:10 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.23.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:23:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279788; x=1698884588; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aiKlYh0ZSQ4q5RqF1EsnIe40ZaI3W0/mpHtSrRjKKnM=; b=dzcAlT3l5QTav52QML6cL6OS2kYcUBvXT53gZnqEA3bdEKozs/RHKDjXAB9gTVv8M3 u+nXl29Ve2CLSpr/LdPtuorJggQRI1+jqZ1JeKXPT6wqywQho0W1MZh7f2YJy4H4E5to LNEcqHfsXiobnQT1okVF5cvz/oyxJkBfqOoAgfFwLoIvEs7jaNnSjQaLaX9DU0Y63oV3 Eq9WvaIS7M2L05ExDvhqbLl2SDDnuQFDMKy0glQ1SuU8kvkQpybuRM4na7KizCKPVAIM txQBtUpDCTdBnSk0xSX7gLrFBoEsa1UeVrtsgrArUcCrGYffBvk4NUTtATK5O/TBu1/l Rs8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279788; x=1698884588; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aiKlYh0ZSQ4q5RqF1EsnIe40ZaI3W0/mpHtSrRjKKnM=; b=s2C2Xw/R4QiNGT+QZunLWSdyPAQm+AOcm/yhP+eA0OpMnkvvPgLCXyD+SYQzjmbaHq w9YNc0hsmZGxpJqLyezxcODem0IrCOlU/GmrympJLkB1YBthTYeB1V93WzFncHwxdnbA cbmGX+bSQtqjOdIIhn7JNj/qzWrZLHodEXiVIG/b88zNrU1Vt3Zxt47tKqZjE3bLQd6o Fb0YBvKOpkFWMfs/+pJjZj61g3JiLt40jt2YMDE7gxbIFYuwZdxMrEVbWSDvs1MHQ7YG mBy1tDi3jTmJREwuU9qDlb6VJz0Ig7MeWevUD/QIJ4TxLqbmj3X8OlKRj6+G7vZq0PQ8 n48g== X-Gm-Message-State: AOJu0Ywz18T0p0KQ5dezeuKuS8rqCzhJZlXpnnFtfP91TtPpPiUamgHX FSp4SYbHq1TwxlIlPvXjOJRDUTI52rK2TXAQ4ts= X-Google-Smtp-Source: AGHT+IGtO9kYFTsQWvneLGVn9T8qsRavJ7QQuhEPExiubxZG1ctORGRhRqsFkllpnvLLXHhDsiTZxQ== X-Received: by 2002:a17:90b:3654:b0:27d:22ed:8e9e with SMTP id nh20-20020a17090b365400b0027d22ed8e9emr13691032pjb.6.1698279788161; Wed, 25 Oct 2023 17:23:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 74/94] target/sparc: Move gen_fop_FF insns to decodetree Date: Wed, 25 Oct 2023 17:15:22 -0700 Message-Id: <20231026001542.1141412-104-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280722363100001 Content-Type: text/plain; charset="utf-8" Move FSQRTs, FiTOs, FsTOi. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 47 ++++++++++++++++++++------------------- 2 files changed, 27 insertions(+), 23 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index bc449023dd..85464285b7 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -245,6 +245,9 @@ FNEGs 10 ..... 110100 00000 0 0000 0101 ..... = @r_r2 FNEGd 10 ..... 110100 00000 0 0000 0110 ..... @r_r2 FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2 FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 +FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2 +FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 +FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 =20 { [ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 197c0bea54..13932e087d 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1654,20 +1654,6 @@ static int gen_trap_ifnofpu(DisasContext *dc) return 0; } =20 -static void gen_fop_FF(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32)) -{ - TCGv_i32 dst, src; - - src =3D gen_load_fpr_F(dc, rs); - dst =3D gen_dest_fpr_F(dc); - - gen(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_F(dc, rd, dst); -} - static void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32= )) { @@ -4806,6 +4792,27 @@ TRANS(FABSs, ALL, do_ff, a, gen_op_fabss) TRANS(FSRCs, VIS1, do_ff, a, tcg_gen_mov_i32) TRANS(FNOTs, VIS1, do_ff, a, tcg_gen_not_i32) =20 +static bool do_env_ff(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i32, TCGv_env, TCGv_i32)) +{ + TCGv_i32 tmp; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + tmp =3D gen_load_fpr_F(dc, a->rs); + func(tmp, tcg_env, tmp); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_F(dc, a->rd, tmp); + return advance_pc(dc); +} + +TRANS(FSQRTs, ALL, do_env_ff, a, gen_helper_fsqrts) +TRANS(FiTOs, ALL, do_env_ff, a, gen_helper_fitos) +TRANS(FsTOi, ALL, do_env_ff, a, gen_helper_fstoi) + static bool do_dd(DisasContext *dc, arg_r_r *a, void (*func)(TCGv_i64, TCGv_i64)) { @@ -4967,10 +4974,10 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 0x2: /* V9 fmovd */ case 0x6: /* V9 fnegd */ case 0xa: /* V9 fabsd */ - g_assert_not_reached(); /* in decodetree */ case 0x29: /* fsqrts */ - gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts); - break; + case 0xc4: /* fitos */ + case 0xd1: /* fstoi */ + g_assert_not_reached(); /* in decodetree */ case 0x2a: /* fsqrtd */ gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd); break; @@ -5026,9 +5033,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq); break; - case 0xc4: /* fitos */ - gen_fop_FF(dc, rd, rs2, gen_helper_fitos); - break; case 0xc6: /* fdtos */ gen_fop_FD(dc, rd, rs2, gen_helper_fdtos); break; @@ -5058,9 +5062,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq); break; - case 0xd1: /* fstoi */ - gen_fop_FF(dc, rd, rs2, gen_helper_fstoi); - break; case 0xd2: /* fdtoi */ gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi); break; --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.23.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:23:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279789; x=1698884589; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zFG3LVvfi+A5uqJYCl0wfU1RjeC2BCq05T39q27kqdA=; b=RuVv6tB4dFE8dAvArjZKVjcUg6b8aa6PMJ6c5I6vLpLUUcZoHVcTEb68VDDSoAC9pY jmGGJnGP66o5kOsG6FxBPHAnu0l1YyawvKjyew24o0soDF0hCimr9Zj3Dlr4zk7nIZhM O+IpqstwNkESDpCPhZgEssV0ufPlAip05wWLwXbc7ArpnlGmCB9G4pSkrTfs7ckFlSEQ 0epDhX+8EPNmywyE40s+2QX9gRF70AYmnAJyOtgwAUh+ux3HiOb4ckhQUrKvknLvpKss 6bHyXebYTmV9g2EuDOlTfknI746EvGawWRn8c0FU29NchZgkcnvrymX0Vm+OwAnb1GUN LobQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279789; x=1698884589; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zFG3LVvfi+A5uqJYCl0wfU1RjeC2BCq05T39q27kqdA=; b=QbBvKnoUemCxbK3jD7BVwXY5uydAeB7BsC/iITwNGhlxy1LTLqWwJElIjWsvlhMD74 YpOSJGA1p67oyxamVZXqBAKtkZ1I46EBlF1Vc/iphwkva7y4QwxjIFXHE+0LBX0JhHAa E+uGNiXxGUlBhDZlioAuxqfuyyEC8AxSFfHhK4wz8CoIDnTzJU0i/D/dOhTCrpHcRD4W NlkxOwvG9CbT06zXX6MEgqYyTbhtFTi9qzXx+eC+gqNoEJr396IcSNh95NdGXAJ7kpVI yJfirLnXhdWrKRiE5FwtWqmT4Ra9U2OVHXa9U0qcNdqf9edsWRz6dAHfirrSmIj8p1+Z K/QA== X-Gm-Message-State: AOJu0YyaM1d6G+oL/zuNiaznBmX47lEqyszZztM6dUMl7VvJpyyAXahw OcZk5FUNubhXdxSXB5SGfEQ03UhhJeSTt/QG2aQ= X-Google-Smtp-Source: AGHT+IHD07ATmDS6YFyNjlsRo7PBN8mw+xFycJjHINTMYBEoiFxBu66E1SX7iJALlRY2TlJwlc4asg== X-Received: by 2002:a17:90b:2d8d:b0:27d:4ab9:fccb with SMTP id sj13-20020a17090b2d8d00b0027d4ab9fccbmr14930344pjb.5.1698279788983; Wed, 25 Oct 2023 17:23:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 75/94] target/sparc: Move gen_fop_DD insns to decodetree Date: Wed, 25 Oct 2023 17:15:23 -0700 Message-Id: <20231026001542.1141412-105-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280790608100003 Content-Type: text/plain; charset="utf-8" Move FSQRTd, FxTOd, FdTOx. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 50 +++++++++++++++++++++------------------ 2 files changed, 30 insertions(+), 23 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 85464285b7..1d766fab21 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -246,6 +246,9 @@ FNEGd 10 ..... 110100 00000 0 0000 0110 ..... = @r_r2 FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2 FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2 +FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2 +FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 +FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 13932e087d..307fbc4628 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -63,6 +63,7 @@ # define gen_helper_write_softint(E, S) qemu_build_not_reached() # define gen_helper_wrpil(E, S) qemu_build_not_reached() # define gen_helper_wrpstate(E, S) qemu_build_not_reached() +# define gen_helper_fdtox ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fexpand ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fmul8sux16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fmul8ulx16 ({ qemu_build_not_reached(); NULL= ; }) @@ -72,6 +73,7 @@ # define gen_helper_fmuld8sux16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fmuld8ulx16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fpmerge ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fxtod ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_pdist ({ qemu_build_not_reached(); NULL= ; }) # define FSR_LDXFSR_MASK 0 # define FSR_LDXFSR_OLDMASK 0 @@ -1669,20 +1671,6 @@ static void gen_fop_FFF(DisasContext *dc, int rd, in= t rs1, int rs2, gen_store_fpr_F(dc, rd, dst); } =20 -static void gen_fop_DD(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64)) -{ - TCGv_i64 dst, src; - - src =3D gen_load_fpr_D(dc, rs); - dst =3D gen_dest_fpr_D(dc, rd); - - gen(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_D(dc, rd, dst); -} - static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64= )) { @@ -4835,6 +4823,28 @@ TRANS(FABSd, 64, do_dd, a, gen_op_fabsd) TRANS(FSRCd, VIS1, do_dd, a, tcg_gen_mov_i64) TRANS(FNOTd, VIS1, do_dd, a, tcg_gen_not_i64) =20 +static bool do_env_dd(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i64, TCGv_env, TCGv_i64)) +{ + TCGv_i64 dst, src; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + dst =3D gen_dest_fpr_D(dc, a->rd); + src =3D gen_load_fpr_D(dc, a->rs); + func(dst, tcg_env, src); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FSQRTd, ALL, do_env_dd, a, gen_helper_fsqrtd) +TRANS(FxTOd, 64, do_env_dd, a, gen_helper_fxtod) +TRANS(FdTOx, 64, do_env_dd, a, gen_helper_fdtox) + static bool do_fff(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i32, TCGv_i32, TCGv_i32)) { @@ -4977,10 +4987,10 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 0x29: /* fsqrts */ case 0xc4: /* fitos */ case 0xd1: /* fstoi */ - g_assert_not_reached(); /* in decodetree */ case 0x2a: /* fsqrtd */ - gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd); - break; + case 0x82: /* V9 fdtox */ + case 0x88: /* V9 fxtod */ + g_assert_not_reached(); /* in decodetree */ case 0x2b: /* fsqrtq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq); @@ -5085,9 +5095,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) case 0x81: /* V9 fstox */ gen_fop_DF(dc, rd, rs2, gen_helper_fstox); break; - case 0x82: /* V9 fdtox */ - gen_fop_DD(dc, rd, rs2, gen_helper_fdtox); - break; case 0x83: /* V9 fqtox */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox); @@ -5095,9 +5102,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) case 0x84: /* V9 fxtos */ gen_fop_FD(dc, rd, rs2, gen_helper_fxtos); break; - case 0x88: /* V9 fxtod */ - gen_fop_DD(dc, rd, rs2, gen_helper_fxtod); - break; case 0x8c: /* V9 fxtoq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280963124100002 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 38 ++++++++++++++++++++++---------------- 2 files changed, 23 insertions(+), 16 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 1d766fab21..4cb250265d 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -247,6 +247,7 @@ FABSs 10 ..... 110100 00000 0 0000 1001 ..... = @r_r2 FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2 FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2 +FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2 FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 307fbc4628..93efdf3383 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1686,18 +1686,6 @@ static void gen_fop_DDD(DisasContext *dc, int rd, in= t rs1, int rs2, gen_store_fpr_D(dc, rd, dst); } =20 -static void gen_fop_QQ(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_ptr)) -{ - gen_op_load_fpr_QT1(QFPREG(rs)); - - gen(tcg_env); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(dc, QFPREG(rd)); -} - #ifdef TARGET_SPARC64 static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_ptr)) @@ -4845,6 +4833,27 @@ TRANS(FSQRTd, ALL, do_env_dd, a, gen_helper_fsqrtd) TRANS(FxTOd, 64, do_env_dd, a, gen_helper_fxtod) TRANS(FdTOx, 64, do_env_dd, a, gen_helper_fdtox) =20 +static bool do_env_qq(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_env)) +{ + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + gen_op_load_fpr_QT1(QFPREG(a->rs)); + func(tcg_env); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_op_store_QT0_fpr(QFPREG(a->rd)); + gen_update_fprs_dirty(dc, QFPREG(a->rd)); + return advance_pc(dc); +} + +TRANS(FSQRTq, ALL, do_env_qq, a, gen_helper_fsqrtq) + static bool do_fff(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i32, TCGv_i32, TCGv_i32)) { @@ -4990,11 +4999,8 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) case 0x2a: /* fsqrtd */ case 0x82: /* V9 fdtox */ case 0x88: /* V9 fxtod */ - g_assert_not_reached(); /* in decodetree */ case 0x2b: /* fsqrtq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq); - break; + g_assert_not_reached(); /* in decodetree */ case 0x41: /* fadds */ gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds); break; --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280723; cv=none; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.23.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:23:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279790; x=1698884590; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2Vu8uE4u91cXAtlNEMc67KwdFgVsES8vkFmIj+yngHw=; b=iFbAkQmYiTlvqNfnQCGrSTy8wkXUqpb/oPDad81H8CTUs/2mbT1vAnkuoCNfjZwzdZ 4ZTFFJVJ8gU6hPoj5IfyZ3hq1DjHw7nRUMR/hnMwfNmpYEwXMVm+dre/fpovFqta0jCi 5FcN4wd8dSpchBNXYVyQ55jyPQJ4HDfpHQHg5Ugxg+x0PdbOXUJ0JUwI2O10nbVoefrO yX1lm3k7ntWo8OmvSEK647tFuoJV6kOuKIT+LYHRSdSN2vAYgzzLHg2LdJuYocdocWo/ 2fiME/CSn5l6MeC6kcqKHLC/iJlZl03qjuLFEl6jPayziJe0R4yMPAsKGsF7ONZqaOnC +SXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279790; x=1698884590; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2Vu8uE4u91cXAtlNEMc67KwdFgVsES8vkFmIj+yngHw=; b=o2xzNJrflODygXigyY85Qe0D5mZ+CSHqyBgr+XcgjKq6Yb5JiIUp5wfegSgAN3DLJa HKUbHKH2cauqz+VzVLwq7pOG8FMxVnwPPWSPJ9kmNlsDs9di51NPiQWQEaCds0nXgvST dY44KpKZin9gjSQXitFaVZlF6slANqlqw/R98VA3ZLdfQbez+kbvjByYEJf4JiN9HBjO 9zz2Tx6tJpl3bDU4Ebolo24YN8USvDWUoqxes8sTTorn7z2IxFdtoRCVdnxtIuHOL2ds Cvll/U/SS7qbYqDgNEplBIYbJPJBa0IuMNgLWWlxIo92usle3vGXKg+pwU9xmWF5D0rY ZHkg== X-Gm-Message-State: AOJu0YwRIIUbRe2zNWLFmeUg8O+FO2eVT1lXOPMnjJi2LKtVHD6B6qUP JzpYlVlwvD5JzgcrzF4fuJfLUlMhB5+BynWDOr0= X-Google-Smtp-Source: AGHT+IFDiz/Z8fv3mNGqD7hqziXcayVBA6p1CAu4AYVSky66jsv5ICbBl+OjhA6IMqTqKHrE24nJKQ== X-Received: by 2002:a17:90a:194b:b0:27d:1ea0:bc84 with SMTP id 11-20020a17090a194b00b0027d1ea0bc84mr13636473pjh.34.1698279790409; Wed, 25 Oct 2023 17:23:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 77/94] target/sparc: Move gen_fop_FFF insns to decodetree Date: Wed, 25 Oct 2023 17:15:25 -0700 Message-Id: <20231026001542.1141412-107-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280724346100005 Content-Type: text/plain; charset="utf-8" Move FADDs, FSUBs, FMULs, FDIVs. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 54 +++++++++++++++++++-------------------- 2 files changed, 31 insertions(+), 27 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 4cb250265d..09444e313f 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -248,6 +248,10 @@ FABSd 10 ..... 110100 00000 0 0000 1010 ..... = @r_r2 FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2 FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2 FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2 +FADDs 10 ..... 110100 ..... 0 0100 0001 ..... @r_r_r +FSUBs 10 ..... 110100 ..... 0 0100 0101 ..... @r_r_r +FMULs 10 ..... 110100 ..... 0 0100 1001 ..... @r_r_r +FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 93efdf3383..d2205f7e7d 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1656,21 +1656,6 @@ static int gen_trap_ifnofpu(DisasContext *dc) return 0; } =20 -static void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32= )) -{ - TCGv_i32 dst, src1, src2; - - src1 =3D gen_load_fpr_F(dc, rs1); - src2 =3D gen_load_fpr_F(dc, rs2); - dst =3D gen_dest_fpr_F(dc); - - gen(dst, tcg_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_F(dc, rd, dst); -} - static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64= )) { @@ -4883,6 +4868,29 @@ TRANS(FXNORs, VIS1, do_fff, a, tcg_gen_eqv_i32) TRANS(FORNOTs, VIS1, do_fff, a, tcg_gen_orc_i32) TRANS(FORs, VIS1, do_fff, a, tcg_gen_or_i32) =20 +static bool do_env_fff(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32= )) +{ + TCGv_i32 src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + src1 =3D gen_load_fpr_F(dc, a->rs1); + src2 =3D gen_load_fpr_F(dc, a->rs2); + func(src1, tcg_env, src1, src2); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_F(dc, a->rd, src1); + return advance_pc(dc); +} + +TRANS(FADDs, ALL, do_env_fff, a, gen_helper_fadds) +TRANS(FSUBs, ALL, do_env_fff, a, gen_helper_fsubs) +TRANS(FMULs, ALL, do_env_fff, a, gen_helper_fmuls) +TRANS(FDIVs, ALL, do_env_fff, a, gen_helper_fdivs) + static bool do_ddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i64, TCGv_i64)) { @@ -5000,10 +5008,11 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 0x82: /* V9 fdtox */ case 0x88: /* V9 fxtod */ case 0x2b: /* fsqrtq */ - g_assert_not_reached(); /* in decodetree */ case 0x41: /* fadds */ - gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds); - break; + case 0x45: /* fsubs */ + case 0x49: /* fmuls */ + case 0x4d: /* fdivs */ + g_assert_not_reached(); /* in decodetree */ case 0x42: /* faddd */ gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd); break; @@ -5011,9 +5020,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq); break; - case 0x45: /* fsubs */ - gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs); - break; case 0x46: /* fsubd */ gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd); break; @@ -5021,9 +5027,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq); break; - case 0x49: /* fmuls */ - gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls); - break; case 0x4a: /* fmuld */ gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld); break; @@ -5031,9 +5034,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq); break; - case 0x4d: /* fdivs */ - gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs); - break; case 0x4e: /* fdivd */ gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd); break; --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.23.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:23:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279791; x=1698884591; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=llQJzbUwM11Tola+ykfL4GeM3KHqjJx/kOe5B4gTN/o=; b=VlTYy12WC47e+z9K/+Fwn1TP665jxWaUUIU/PcwdsxXi6yqmpL6WpDnSsjiJ/47xxf H3zFKeoEsE6pWO28OF6H9cRhnhfxbakWsog2JAEn4msgxswwX5EPqsfCp2jkjROIHUxd dpuRzBnZliL0sCpRLhlj+gX0b6xDxCTIlc5V8AFhRW3P8Mlr5+21kNXIg4T896PRAV4d eOeIg1md0uks3NY0Pn6pT5dZUkXQHNmFSWSKh8PWj2tdhdGg5vyO/q+Df4wTAeS+rWEQ o95IYwN2DJF/JGISikGvbPaiIey4AEOSrj21Pwc5OqnkxMbU9VcShyUE78HxLdPir4cR iOeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279791; x=1698884591; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=llQJzbUwM11Tola+ykfL4GeM3KHqjJx/kOe5B4gTN/o=; b=kRVFUjHS8k34+BbF25GI4kBZU+YQ8ZRIQCrcJnLx2pZ0LPVX1sSEQrfUiYhPqUyuCV k4o/KNC732mxpG+UYiNyzgCY/rxinER4tQlttosDcQWZZuKbceSgXwAVm2pqW0Bnvz7M BgGkgOqV4krwQf2AOohSOpXfXA3242x2S+ayHgFtNpHjoia6UsaNBrIVeZ8AXehB4K9h jquxfB8zyUQMM5dAoJWTuSgXlIrkKbzN9T7aylkKJSOhboKIMh+T9262xqFhaZi7IhrW Pk4O1L103QZs5YvUWry537LA3GfJEUmdT1DRknHStORsNUr4//UN5xFgibal7rvCsDQy vQ+g== X-Gm-Message-State: AOJu0YzyCzOeYWBmreu5QAMwhNbNlzRp2gz74lyuMzylJTE21la7xv3d tgcjmc1RRIlCGOMLXprof7UJaPrelHLgNCcZy3U= X-Google-Smtp-Source: AGHT+IEQ7MMagzWEmxtdEP0KRRwG7pjit8T6tNOJrK1wzQCmwq6ltkFuJYC2aV9DdcZEYASGaJmgAg== X-Received: by 2002:a17:90b:1c82:b0:27f:df1e:198e with SMTP id oo2-20020a17090b1c8200b0027fdf1e198emr3162634pjb.26.1698279791336; Wed, 25 Oct 2023 17:23:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 78/94] target/sparc: Move gen_fop_DDD insns to decodetree Date: Wed, 25 Oct 2023 17:15:26 -0700 Message-Id: <20231026001542.1141412-108-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280083396100001 Content-Type: text/plain; charset="utf-8" Move FADDd, FSUBd, FMULd, FDIVd. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 55 ++++++++++++++++++++------------------- 2 files changed, 32 insertions(+), 27 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 09444e313f..a429c04980 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -249,9 +249,13 @@ FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... = @r_r2 FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2 FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2 FADDs 10 ..... 110100 ..... 0 0100 0001 ..... @r_r_r +FADDd 10 ..... 110100 ..... 0 0100 0010 ..... @r_r_r FSUBs 10 ..... 110100 ..... 0 0100 0101 ..... @r_r_r +FSUBd 10 ..... 110100 ..... 0 0100 0110 ..... @r_r_r FMULs 10 ..... 110100 ..... 0 0100 1001 ..... @r_r_r +FMULd 10 ..... 110100 ..... 0 0100 1010 ..... @r_r_r FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r +FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @r_r_r FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d2205f7e7d..e2bcb3c7b1 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1656,21 +1656,6 @@ static int gen_trap_ifnofpu(DisasContext *dc) return 0; } =20 -static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64= )) -{ - TCGv_i64 dst, src1, src2; - - src1 =3D gen_load_fpr_D(dc, rs1); - src2 =3D gen_load_fpr_D(dc, rs2); - dst =3D gen_dest_fpr_D(dc, rd); - - gen(dst, tcg_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_D(dc, rd, dst); -} - #ifdef TARGET_SPARC64 static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_ptr)) @@ -4935,6 +4920,30 @@ TRANS(FPACK32, VIS1, do_ddd, a, gen_op_fpack32) TRANS(FALIGNDATAg, VIS1, do_ddd, a, gen_op_faligndata) TRANS(BSHUFFLE, VIS2, do_ddd, a, gen_op_bshuffle) =20 +static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64= )) +{ + TCGv_i64 dst, src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + dst =3D gen_dest_fpr_D(dc, a->rd); + src1 =3D gen_load_fpr_D(dc, a->rs1); + src2 =3D gen_load_fpr_D(dc, a->rs2); + func(dst, tcg_env, src1, src2); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FADDd, ALL, do_env_ddd, a, gen_helper_faddd) +TRANS(FSUBd, ALL, do_env_ddd, a, gen_helper_fsubd) +TRANS(FMULd, ALL, do_env_ddd, a, gen_helper_fmuld) +TRANS(FDIVd, ALL, do_env_ddd, a, gen_helper_fdivd) + static bool do_dddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) { @@ -5012,31 +5021,23 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 0x45: /* fsubs */ case 0x49: /* fmuls */ case 0x4d: /* fdivs */ - g_assert_not_reached(); /* in decodetree */ case 0x42: /* faddd */ - gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd); - break; + case 0x46: /* fsubd */ + case 0x4a: /* fmuld */ + case 0x4e: /* fdivd */ + g_assert_not_reached(); /* in decodetree */ case 0x43: /* faddq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq); break; - case 0x46: /* fsubd */ - gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd); - break; case 0x47: /* fsubq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq); break; - case 0x4a: /* fmuld */ - gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld); - break; case 0x4b: /* fmulq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq); break; - case 0x4e: /* fdivd */ - gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd); - break; case 0x4f: /* fdivq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280961; cv=none; d=zohomail.com; s=zohoarc; b=V1d+2LSA4MmCiCTBX8FtmBOhvdzTjJfCVy+B7KTV39Ifu3tE/HXAqM7opbZvqSqYJ6i3U0IS+JcYBej0XNpY3DTPvoy4whhUYKFEcJvWZOmvxRvRqhohRIIQAOkpRwH21q6m9g7UnEa/e5Y42+/Y+UDWdr7yC5hvaT02aPd9BsM= ARC-Message-Signature: i=1; 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Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 52 +++++++++++++++++++-------------------- 2 files changed, 30 insertions(+), 26 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a429c04980..f18fd99476 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -250,12 +250,16 @@ FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... = @r_r2 FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2 FADDs 10 ..... 110100 ..... 0 0100 0001 ..... @r_r_r FADDd 10 ..... 110100 ..... 0 0100 0010 ..... @r_r_r +FADDq 10 ..... 110100 ..... 0 0100 0011 ..... @r_r_r FSUBs 10 ..... 110100 ..... 0 0100 0101 ..... @r_r_r FSUBd 10 ..... 110100 ..... 0 0100 0110 ..... @r_r_r +FSUBq 10 ..... 110100 ..... 0 0100 0111 ..... @r_r_r FMULs 10 ..... 110100 ..... 0 0100 1001 ..... @r_r_r FMULd 10 ..... 110100 ..... 0 0100 1010 ..... @r_r_r +FMULq 10 ..... 110100 ..... 0 0100 1011 ..... @r_r_r FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @r_r_r +FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @r_r_r FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index e2bcb3c7b1..94ad75b897 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1669,19 +1669,6 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, = int rs, } #endif =20 -static void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_ptr)) -{ - gen_op_load_fpr_QT0(QFPREG(rs1)); - gen_op_load_fpr_QT1(QFPREG(rs2)); - - gen(tcg_env); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(dc, QFPREG(rd)); -} - static void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32= )) { @@ -4964,6 +4951,31 @@ static bool do_dddd(DisasContext *dc, arg_r_r_r *a, =20 TRANS(PDIST, VIS1, do_dddd, a, gen_helper_pdist) =20 +static bool do_env_qqq(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_env)) +{ + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + gen_op_load_fpr_QT0(QFPREG(a->rs1)); + gen_op_load_fpr_QT1(QFPREG(a->rs2)); + func(tcg_env); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_op_store_QT0_fpr(QFPREG(a->rd)); + gen_update_fprs_dirty(dc, QFPREG(a->rd)); + return advance_pc(dc); +} + +TRANS(FADDq, ALL, do_env_qqq, a, gen_helper_faddq) +TRANS(FSUBq, ALL, do_env_qqq, a, gen_helper_fsubq) +TRANS(FMULq, ALL, do_env_qqq, a, gen_helper_fmulq) +TRANS(FDIVq, ALL, do_env_qqq, a, gen_helper_fdivq) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5025,23 +5037,11 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 0x46: /* fsubd */ case 0x4a: /* fmuld */ case 0x4e: /* fdivd */ - g_assert_not_reached(); /* in decodetree */ case 0x43: /* faddq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq); - break; case 0x47: /* fsubq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq); - break; case 0x4b: /* fmulq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq); - break; case 0x4f: /* fdivq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq); - break; + g_assert_not_reached(); /* in decodetree */ case 0x69: /* fsmuld */ CHECK_FPU_FEATURE(dc, FSMULD); gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698279973037100002 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 43 +++++++++++++++++++++------------------ 2 files changed, 24 insertions(+), 20 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index f18fd99476..6817d52ca2 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -260,6 +260,7 @@ FMULq 10 ..... 110100 ..... 0 0100 1011 ..... = @r_r_r FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @r_r_r FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @r_r_r +FsMULd 10 ..... 110100 ..... 0 0110 1001 ..... @r_r_r FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 94ad75b897..6626042776 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1669,22 +1669,6 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, = int rs, } #endif =20 -static void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32= )) -{ - TCGv_i64 dst; - TCGv_i32 src1, src2; - - src1 =3D gen_load_fpr_F(dc, rs1); - src2 =3D gen_load_fpr_F(dc, rs2); - dst =3D gen_dest_fpr_D(dc, rd); - - gen(dst, tcg_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_D(dc, rd, dst); -} - static void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64)) { @@ -4931,6 +4915,28 @@ TRANS(FSUBd, ALL, do_env_ddd, a, gen_helper_fsubd) TRANS(FMULd, ALL, do_env_ddd, a, gen_helper_fmuld) TRANS(FDIVd, ALL, do_env_ddd, a, gen_helper_fdivd) =20 +static bool trans_FsMULd(DisasContext *dc, arg_r_r_r *a) +{ + TCGv_i64 dst; + TCGv_i32 src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (!(dc->def->features & CPU_FEATURE_FSMULD)) { + return raise_unimpfpop(dc); + } + + gen_op_clear_ieee_excp_and_FTT(); + dst =3D gen_dest_fpr_D(dc, a->rd); + src1 =3D gen_load_fpr_F(dc, a->rs1); + src2 =3D gen_load_fpr_F(dc, a->rs2); + gen_helper_fsmuld(dst, tcg_env, src1, src2); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + static bool do_dddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) { @@ -5041,11 +5047,8 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) case 0x47: /* fsubq */ case 0x4b: /* fmulq */ case 0x4f: /* fdivq */ - g_assert_not_reached(); /* in decodetree */ case 0x69: /* fsmuld */ - CHECK_FPU_FEATURE(dc, FSMULD); - gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld); - break; + g_assert_not_reached(); /* in decodetree */ case 0x6e: /* fdmulq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280776514100005 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 41 +++++++++++++++++++++------------------ 2 files changed, 23 insertions(+), 19 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 6817d52ca2..a19d191603 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -261,6 +261,7 @@ FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... = @r_r_r FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @r_r_r FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @r_r_r FsMULd 10 ..... 110100 ..... 0 0110 1001 ..... @r_r_r +FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @r_r_r FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 6626042776..29643768e1 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1669,21 +1669,6 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, = int rs, } #endif =20 -static void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64)) -{ - TCGv_i64 src1, src2; - - src1 =3D gen_load_fpr_D(dc, rs1); - src2 =3D gen_load_fpr_D(dc, rs2); - - gen(tcg_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(dc, QFPREG(rd)); -} - #ifdef TARGET_SPARC64 static void gen_fop_DF(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32)) @@ -4982,6 +4967,27 @@ TRANS(FSUBq, ALL, do_env_qqq, a, gen_helper_fsubq) TRANS(FMULq, ALL, do_env_qqq, a, gen_helper_fmulq) TRANS(FDIVq, ALL, do_env_qqq, a, gen_helper_fdivq) =20 +static bool trans_FdMULq(DisasContext *dc, arg_r_r_r *a) +{ + TCGv_i64 src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + src1 =3D gen_load_fpr_D(dc, a->rs1); + src2 =3D gen_load_fpr_D(dc, a->rs2); + gen_helper_fdmulq(tcg_env, src1, src2); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_op_store_QT0_fpr(QFPREG(a->rd)); + gen_update_fprs_dirty(dc, QFPREG(a->rd)); + return advance_pc(dc); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5048,11 +5054,8 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) case 0x4b: /* fmulq */ case 0x4f: /* fdivq */ case 0x69: /* fsmuld */ - g_assert_not_reached(); /* in decodetree */ case 0x6e: /* fdmulq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq); - break; + g_assert_not_reached(); /* in decodetree */ case 0xc6: /* fdtos */ gen_fop_FD(dc, rd, rs2, gen_helper_fdtos); break; --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280968; cv=none; d=zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.23.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:23:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279794; x=1698884594; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tFnSxDeK3rdSz9x4fev82AZ34W6M8VZ9rvoNIcYwmXE=; b=L1R4JiZLtpaycJYn1EdrgX/ite72R0Wk2Y2zPT9O2dErHzIX4NOO1WGkQb0XT9TVCU UFvyWA6Saw2+zF8C909MvBrPnxgh/H/IFfjUYzeIaXUaD3jIZZ4Zg/G5iB3oznRLWEFE TdckOoigZv8xJgEDXQre3+PMUqk35EptP6qpSLb09p/QWREhX2+Pz15G3tfWfvGBgQaJ mSdX3Aj1yke7dL9P4d7cB514joMBm5ToBU/cDPGGq0K2i5UVrWcz4TYkVpmgM/tOB+sN JKjkHAt8EePMkcCvok0O/s0Mb0sT39D1xo622RsHq7I/knMpz0geAnQ8dj/dyWxkxbVp CEEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279794; x=1698884594; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tFnSxDeK3rdSz9x4fev82AZ34W6M8VZ9rvoNIcYwmXE=; b=Exb37oqLK4hA68LNKob8F+BYvTnrW/6qbNcc5ODEvJsT3NrN7CIZh4JJtBQmJcD7ex uyCCn/flUi0NO8zR9klGMm1OUzAQld6rmncXNvswpiiN2KoUwIB68OwFAc0vKCbZih9r n6zBl4co9FTAM4BsOTJVa8bdYe0SQ7OF/HlEXdXk1cjRkqxHhc77K6htjPDk3tRaWzWy QkRhnfiNtITYaJ0rdYknl6u38Y2kIhjhD9vhJ5BXPEULtqFzLhINOfcSU1SRl7a8U25J eDbN0iBrftNGi/qqR9U3vu0Z649PXFTqzi/SJg7tCjYmmaDtU4mKgcELgv9LzOD5dVPL Gwpg== X-Gm-Message-State: AOJu0YwwavgilnL82PHOhjcjl5I/XEakcOSs2rs+U0jaKuLODAQLOccQ ghaQeD9xzFd5z/6RykZGJcMwh1NfmlNth8lKSbo= X-Google-Smtp-Source: AGHT+IFuPytdW3kOS2I6ngaFh1pw8DdFFnq4oacRfFcfuKU7qHL96lS5qLS8xLKVkxMDU8JccO6pFQ== X-Received: by 2002:a17:90b:4f4a:b0:27d:1862:a494 with SMTP id pj10-20020a17090b4f4a00b0027d1862a494mr14172731pjb.11.1698279794150; Wed, 25 Oct 2023 17:23:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 82/94] target/sparc: Move gen_fop_FD insns to decodetree Date: Wed, 25 Oct 2023 17:15:30 -0700 Message-Id: <20231026001542.1141412-112-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280969078100001 Content-Type: text/plain; charset="utf-8" Move FdTOs, FdTOi, FxTOs. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 51 +++++++++++++++++++++------------------ 2 files changed, 30 insertions(+), 24 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a19d191603..faf2bcef83 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -263,9 +263,12 @@ FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... = @r_r_r FsMULd 10 ..... 110100 ..... 0 0110 1001 ..... @r_r_r FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @r_r_r FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 +FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 +FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_r2 FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 +FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2 =20 { [ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 29643768e1..6c1dcf6472 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -74,6 +74,7 @@ # define gen_helper_fmuld8ulx16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fpmerge ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fxtod ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fxtos ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_pdist ({ qemu_build_not_reached(); NULL= ; }) # define FSR_LDXFSR_MASK 0 # define FSR_LDXFSR_OLDMASK 0 @@ -1700,21 +1701,6 @@ static void gen_ne_fop_DF(DisasContext *dc, int rd, = int rs, gen_store_fpr_D(dc, rd, dst); } =20 -static void gen_fop_FD(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64)) -{ - TCGv_i32 dst; - TCGv_i64 src; - - src =3D gen_load_fpr_D(dc, rs); - dst =3D gen_dest_fpr_F(dc); - - gen(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_F(dc, rd, dst); -} - static void gen_fop_FQ(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_i32, TCGv_ptr)) { @@ -4715,6 +4701,29 @@ TRANS(FSQRTs, ALL, do_env_ff, a, gen_helper_fsqrts) TRANS(FiTOs, ALL, do_env_ff, a, gen_helper_fitos) TRANS(FsTOi, ALL, do_env_ff, a, gen_helper_fstoi) =20 +static bool do_env_fd(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i32, TCGv_env, TCGv_i64)) +{ + TCGv_i32 dst; + TCGv_i64 src; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + dst =3D gen_dest_fpr_F(dc); + src =3D gen_load_fpr_D(dc, a->rs); + func(dst, tcg_env, src); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_F(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FdTOs, ALL, do_env_fd, a, gen_helper_fdtos) +TRANS(FdTOi, ALL, do_env_fd, a, gen_helper_fdtoi) +TRANS(FxTOs, 64, do_env_fd, a, gen_helper_fxtos) + static bool do_dd(DisasContext *dc, arg_r_r *a, void (*func)(TCGv_i64, TCGv_i64)) { @@ -5055,10 +5064,10 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 0x4f: /* fdivq */ case 0x69: /* fsmuld */ case 0x6e: /* fdmulq */ - g_assert_not_reached(); /* in decodetree */ case 0xc6: /* fdtos */ - gen_fop_FD(dc, rd, rs2, gen_helper_fdtos); - break; + case 0xd2: /* fdtoi */ + case 0x84: /* V9 fxtos */ + g_assert_not_reached(); /* in decodetree */ case 0xc7: /* fqtos */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos); @@ -5085,9 +5094,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq); break; - case 0xd2: /* fdtoi */ - gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi); - break; case 0xd3: /* fqtoi */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi); @@ -5112,9 +5118,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox); break; - case 0x84: /* V9 fxtos */ - gen_fop_FD(dc, rd, rs2, gen_helper_fxtos); - break; case 0x8c: /* V9 fxtoq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 9-20020a17090a0cc900b0027463889e72sm499870pjt.55.2023.10.25.17.23.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:23:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279795; x=1698884595; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W5ov1/Ws58A6tJgu37c7vPdUN8+EpdwR2VU2PLSJwVY=; b=lJWzDqDiEl6UH27RJfec5tLuDYg/zPLqerdX3WmG3rrsOCH0vCdHERBKPwtPkARiRB SH7ORi8uYnQgpmmkVrlsWD5V/RdePaRXawh4jMwMi5Hb/ot2gdbhQsJdhlBsdoRcWDbD LAij+nbCoCw/hrPyC6GG0W4PGWrsAS5GS6wfVwvAmlWUsQNpSqvn0+ou7+37wEAPb2dN slWNfUBvfAa8RBKuGz9FnuZ3oVjD6RMk9NtKTknRaaSj9ym+3xNCGvpVse+Oh+uIF7Cd llZB6R4kEZiPafM/vyHvO4LBUCjSQ367TA+XC/vv0rmcyugiKHnH09KNMcBR/8A8eiGX Yw3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279795; x=1698884595; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W5ov1/Ws58A6tJgu37c7vPdUN8+EpdwR2VU2PLSJwVY=; b=DZlGyl6Q4j9sUXAdoeJyNRfPnv3C4GWsS1EaJLNb8dFrPowKZhad72jkCvr8m4dEVB dnfyr9KoVmIUL6xAfKRyrsc1Kv3z0iDRpWrK4Q2IT2dgJpCmSsQb7f46AOSdqz1/4a2T A4Pj+wxwLMY3VwAWnwiWYqFvPxA+M0xtRqavDjTpBXe9RkKTrEwydcomL82QwOywDYwI 2u2eueMYKG/1pxpAkkimj1gHoKyJTaVs4vDKDKNlS9WKvxk1oo3x7FkjqJutMqnjdJ3c Rd99xj9gRWu+Ovo9ZU9VySzEF+bxUjExzUnwN5UGdojUxttmUq9i2GCUhupcFCNMBrQl kHFg== X-Gm-Message-State: AOJu0YwnKj9B6l8Q+eBK8gA88N1rRnk0rJlvRXlAe8EYerhO2xU/bKaa 6QRK7GcD/UwvkXoAOkM8he6UbDh9KCVd0LGSMTA= X-Google-Smtp-Source: AGHT+IEAFzW2o6TE6yRNHYk3MXUOmqMqHokyaWXLkulVOERxMY0gIvR3pKFb7IdJhabh/gonrh4skA== X-Received: by 2002:a17:90a:7543:b0:268:1355:b03e with SMTP id q61-20020a17090a754300b002681355b03emr14570195pjk.38.1698279794915; Wed, 25 Oct 2023 17:23:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 83/94] target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree Date: Wed, 25 Oct 2023 17:15:31 -0700 Message-Id: <20231026001542.1141412-113-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280357015100001 Content-Type: text/plain; charset="utf-8" Note that gen_ne_fop_DF was incorrectly named and does pass env. The two sets of helpers should have been unified. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 ++ target/sparc/translate.c | 67 ++++++++++++++++----------------------- 2 files changed, 30 insertions(+), 40 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index faf2bcef83..ee9262061b 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -262,11 +262,14 @@ FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... = @r_r_r FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @r_r_r FsMULd 10 ..... 110100 ..... 0 0110 1001 ..... @r_r_r FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @r_r_r +FsTOx 10 ..... 110100 00000 0 1000 0001 ..... @r_r2 FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_r2 +FiTOd 10 ..... 110100 00000 0 1100 1000 ..... @r_r2 +FsTOd 10 ..... 110100 00000 0 1100 1001 ..... @r_r2 FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2 =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 6c1dcf6472..e71b41e196 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -73,6 +73,7 @@ # define gen_helper_fmuld8sux16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fmuld8ulx16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fpmerge ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fstox ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fxtod ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fxtos ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_pdist ({ qemu_build_not_reached(); NULL= ; }) @@ -1670,37 +1671,6 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, = int rs, } #endif =20 -#ifdef TARGET_SPARC64 -static void gen_fop_DF(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32)) -{ - TCGv_i64 dst; - TCGv_i32 src; - - src =3D gen_load_fpr_F(dc, rs); - dst =3D gen_dest_fpr_D(dc, rd); - - gen(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_D(dc, rd, dst); -} -#endif - -static void gen_ne_fop_DF(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32)) -{ - TCGv_i64 dst; - TCGv_i32 src; - - src =3D gen_load_fpr_F(dc, rs); - dst =3D gen_dest_fpr_D(dc, rd); - - gen(dst, tcg_env, src); - - gen_store_fpr_D(dc, rd, dst); -} - static void gen_fop_FQ(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_i32, TCGv_ptr)) { @@ -4768,6 +4738,29 @@ TRANS(FSQRTd, ALL, do_env_dd, a, gen_helper_fsqrtd) TRANS(FxTOd, 64, do_env_dd, a, gen_helper_fxtod) TRANS(FdTOx, 64, do_env_dd, a, gen_helper_fdtox) =20 +static bool do_env_df(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i64, TCGv_env, TCGv_i32)) +{ + TCGv_i64 dst; + TCGv_i32 src; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + dst =3D gen_dest_fpr_D(dc, a->rd); + src =3D gen_load_fpr_F(dc, a->rs); + func(dst, tcg_env, src); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FiTOd, ALL, do_env_df, a, gen_helper_fitod) +TRANS(FsTOd, ALL, do_env_df, a, gen_helper_fstod) +TRANS(FsTOx, 64, do_env_df, a, gen_helper_fstox) + static bool do_env_qq(DisasContext *dc, arg_r_r *a, void (*func)(TCGv_env)) { @@ -5067,17 +5060,14 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 0xc6: /* fdtos */ case 0xd2: /* fdtoi */ case 0x84: /* V9 fxtos */ + case 0xc8: /* fitod */ + case 0xc9: /* fstod */ + case 0x81: /* V9 fstox */ g_assert_not_reached(); /* in decodetree */ case 0xc7: /* fqtos */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos); break; - case 0xc8: /* fitod */ - gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod); - break; - case 0xc9: /* fstod */ - gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod); - break; case 0xcb: /* fqtod */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod); @@ -5111,9 +5101,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq); break; - case 0x81: /* V9 fstox */ - gen_fop_DF(dc, rd, rs2, gen_helper_fstox); - break; case 0x83: /* V9 fqtox */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280971074100007 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 48 +++++++++++++++++++++------------------ 2 files changed, 28 insertions(+), 22 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index ee9262061b..33f0c738e6 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -268,10 +268,12 @@ FxTOs 10 ..... 110100 00000 0 1000 0100 ..... = @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_r2 +FqTOs 10 ..... 110100 00000 0 1100 0111 ..... @r_r2 FiTOd 10 ..... 110100 00000 0 1100 1000 ..... @r_r2 FsTOd 10 ..... 110100 00000 0 1100 1001 ..... @r_r2 FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2 +FqTOi 10 ..... 110100 00000 0 1101 0011 ..... @r_r2 =20 { [ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index e71b41e196..37405df926 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1671,20 +1671,6 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, = int rs, } #endif =20 -static void gen_fop_FQ(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i32, TCGv_ptr)) -{ - TCGv_i32 dst; - - gen_op_load_fpr_QT1(QFPREG(rs)); - dst =3D gen_dest_fpr_F(dc); - - gen(dst, tcg_env); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_F(dc, rd, dst); -} - static void gen_fop_DQ(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_i64, TCGv_ptr)) { @@ -4782,6 +4768,30 @@ static bool do_env_qq(DisasContext *dc, arg_r_r *a, =20 TRANS(FSQRTq, ALL, do_env_qq, a, gen_helper_fsqrtq) =20 +static bool do_env_fq(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i32, TCGv_env)) +{ + TCGv_i32 dst; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + gen_op_load_fpr_QT1(QFPREG(a->rs)); + dst =3D gen_dest_fpr_F(dc); + func(dst, tcg_env); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_F(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FqTOs, ALL, do_env_fq, a, gen_helper_fqtos) +TRANS(FqTOi, ALL, do_env_fq, a, gen_helper_fqtoi) + static bool do_fff(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i32, TCGv_i32, TCGv_i32)) { @@ -5063,11 +5073,9 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) case 0xc8: /* fitod */ case 0xc9: /* fstod */ case 0x81: /* V9 fstox */ - g_assert_not_reached(); /* in decodetree */ case 0xc7: /* fqtos */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos); - break; + case 0xd3: /* fqtoi */ + g_assert_not_reached(); /* in decodetree */ case 0xcb: /* fqtod */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod); @@ -5084,10 +5092,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq); break; - case 0xd3: /* fqtoi */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi); - break; #ifdef TARGET_SPARC64 case 0x3: /* V9 fmovq */ CHECK_FPU_FEATURE(dc, FLOAT128); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280399272100007 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 49 +++++++++++++++++++++------------------ 2 files changed, 29 insertions(+), 22 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 33f0c738e6..7b65b31f89 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -264,6 +264,7 @@ FsMULd 10 ..... 110100 ..... 0 0110 1001 ..... = @r_r_r FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @r_r_r FsTOx 10 ..... 110100 00000 0 1000 0001 ..... @r_r2 FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 +FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @r_r2 FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 @@ -271,6 +272,7 @@ FdTOs 10 ..... 110100 00000 0 1100 0110 ..... = @r_r2 FqTOs 10 ..... 110100 00000 0 1100 0111 ..... @r_r2 FiTOd 10 ..... 110100 00000 0 1100 1000 ..... @r_r2 FsTOd 10 ..... 110100 00000 0 1100 1001 ..... @r_r2 +FqTOd 10 ..... 110100 00000 0 1100 1011 ..... @r_r2 FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2 FqTOi 10 ..... 110100 00000 0 1101 0011 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 37405df926..39da3f1705 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -73,6 +73,7 @@ # define gen_helper_fmuld8sux16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fmuld8ulx16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fpmerge ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fqtox ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fstox ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fxtod ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fxtos ({ qemu_build_not_reached(); NULL= ; }) @@ -1671,20 +1672,6 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, = int rs, } #endif =20 -static void gen_fop_DQ(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i64, TCGv_ptr)) -{ - TCGv_i64 dst; - - gen_op_load_fpr_QT1(QFPREG(rs)); - dst =3D gen_dest_fpr_D(dc, rd); - - gen(dst, tcg_env); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_D(dc, rd, dst); -} - static void gen_ne_fop_QF(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_ptr, TCGv_i32)) { @@ -4792,6 +4779,30 @@ static bool do_env_fq(DisasContext *dc, arg_r_r *a, TRANS(FqTOs, ALL, do_env_fq, a, gen_helper_fqtos) TRANS(FqTOi, ALL, do_env_fq, a, gen_helper_fqtoi) =20 +static bool do_env_dq(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i64, TCGv_env)) +{ + TCGv_i64 dst; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + gen_op_load_fpr_QT1(QFPREG(a->rs)); + dst =3D gen_dest_fpr_D(dc, a->rd); + func(dst, tcg_env); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FqTOd, ALL, do_env_dq, a, gen_helper_fqtod) +TRANS(FqTOx, 64, do_env_dq, a, gen_helper_fqtox) + static bool do_fff(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i32, TCGv_i32, TCGv_i32)) { @@ -5075,11 +5086,9 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) case 0x81: /* V9 fstox */ case 0xc7: /* fqtos */ case 0xd3: /* fqtoi */ - g_assert_not_reached(); /* in decodetree */ case 0xcb: /* fqtod */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod); - break; + case 0x83: /* V9 fqtox */ + g_assert_not_reached(); /* in decodetree */ case 0xcc: /* fitoq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq); @@ -5105,10 +5114,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq); break; - case 0x83: /* V9 fqtox */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox); - break; case 0x8c: /* V9 fxtoq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280428; cv=none; d=zohomail.com; s=zohoarc; b=K+Kxn6OledeVYal8ylq4pcUuhllf3yIPul/7cWdyvGJmec/jvsO5sX3JiqgtuZhBiQpQ4JfhpK0a0PHg1ffnLMt4ZDe55jKiHeilF2TWasqAedJLM/5K5RlMjXE77UCk0O/7grrXuKh7f3gxdaa8f0m4xIpb4/B667wxr0BqvSg= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280429427100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 44 +++++++++++++++++++++------------------ 2 files changed, 26 insertions(+), 20 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 7b65b31f89..c76e603f2d 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -273,6 +273,8 @@ FqTOs 10 ..... 110100 00000 0 1100 0111 ..... = @r_r2 FiTOd 10 ..... 110100 00000 0 1100 1000 ..... @r_r2 FsTOd 10 ..... 110100 00000 0 1100 1001 ..... @r_r2 FqTOd 10 ..... 110100 00000 0 1100 1011 ..... @r_r2 +FiTOq 10 ..... 110100 00000 0 1100 1100 ..... @r_r2 +FsTOq 10 ..... 110100 00000 0 1100 1101 ..... @r_r2 FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2 FqTOi 10 ..... 110100 00000 0 1101 0011 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 39da3f1705..ad2d794b3d 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1672,19 +1672,6 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, = int rs, } #endif =20 -static void gen_ne_fop_QF(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_ptr, TCGv_i32)) -{ - TCGv_i32 src; - - src =3D gen_load_fpr_F(dc, rs); - - gen(tcg_env, src); - - gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(dc, QFPREG(rd)); -} - static void gen_ne_fop_QD(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_ptr, TCGv_i64)) { @@ -4803,6 +4790,29 @@ static bool do_env_dq(DisasContext *dc, arg_r_r *a, TRANS(FqTOd, ALL, do_env_dq, a, gen_helper_fqtod) TRANS(FqTOx, 64, do_env_dq, a, gen_helper_fqtox) =20 +static bool do_env_qf(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_env, TCGv_i32)) +{ + TCGv_i32 src; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + src =3D gen_load_fpr_F(dc, a->rs); + func(tcg_env, src); + gen_op_store_QT0_fpr(QFPREG(a->rd)); + gen_update_fprs_dirty(dc, QFPREG(a->rd)); + return advance_pc(dc); +} + +TRANS(FiTOq, ALL, do_env_qf, a, gen_helper_fitoq) +TRANS(FsTOq, ALL, do_env_qf, a, gen_helper_fstoq) + static bool do_fff(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i32, TCGv_i32, TCGv_i32)) { @@ -5088,15 +5098,9 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) case 0xd3: /* fqtoi */ case 0xcb: /* fqtod */ case 0x83: /* V9 fqtox */ - g_assert_not_reached(); /* in decodetree */ case 0xcc: /* fitoq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq); - break; case 0xcd: /* fstoq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq); - break; + g_assert_not_reached(); /* in decodetree */ case 0xce: /* fdtoq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280775; cv=none; d=zohomail.com; s=zohoarc; b=JH9nQxvVTNHqKAwAh9S+rVX2nJZE8pjenLIGRPMJjzSotse1ebOckAuZTvnWZxlW+ARYm2A4Fh6Mc3XiMEk8PjwnfbMrf+P8yRRxkSrsDmyy6SOAe8dSQvLwf1l8LwPHVLv1/nU3bJ7LV6QfCZbBJxet3ewUdh2paB3lQzV+pbM= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280776537100006 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 47 ++++++++++++++++++++++----------------- 2 files changed, 28 insertions(+), 21 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index c76e603f2d..e1f5394d17 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -267,6 +267,7 @@ FdTOx 10 ..... 110100 00000 0 1000 0010 ..... = @r_r2 FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @r_r2 FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 +FxTOq 10 ..... 110100 00000 0 1000 1100 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_r2 FqTOs 10 ..... 110100 00000 0 1100 0111 ..... @r_r2 @@ -275,6 +276,7 @@ FsTOd 10 ..... 110100 00000 0 1100 1001 ..... = @r_r2 FqTOd 10 ..... 110100 00000 0 1100 1011 ..... @r_r2 FiTOq 10 ..... 110100 00000 0 1100 1100 ..... @r_r2 FsTOq 10 ..... 110100 00000 0 1100 1101 ..... @r_r2 +FdTOq 10 ..... 110100 00000 0 1100 1110 ..... @r_r2 FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2 FqTOi 10 ..... 110100 00000 0 1101 0011 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ad2d794b3d..40823f1325 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -77,6 +77,7 @@ # define gen_helper_fstox ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fxtod ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fxtos ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fxtoq ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_pdist ({ qemu_build_not_reached(); NULL= ; }) # define FSR_LDXFSR_MASK 0 # define FSR_LDXFSR_OLDMASK 0 @@ -1672,19 +1673,6 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, = int rs, } #endif =20 -static void gen_ne_fop_QD(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_ptr, TCGv_i64)) -{ - TCGv_i64 src; - - src =3D gen_load_fpr_D(dc, rs); - - gen(tcg_env, src); - - gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(dc, QFPREG(rd)); -} - /* asi moves */ typedef enum { GET_ASI_HELPER, @@ -4813,6 +4801,29 @@ static bool do_env_qf(DisasContext *dc, arg_r_r *a, TRANS(FiTOq, ALL, do_env_qf, a, gen_helper_fitoq) TRANS(FsTOq, ALL, do_env_qf, a, gen_helper_fstoq) =20 +static bool do_env_qd(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_env, TCGv_i64)) +{ + TCGv_i64 src; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + src =3D gen_load_fpr_D(dc, a->rs); + func(tcg_env, src); + gen_op_store_QT0_fpr(QFPREG(a->rd)); + gen_update_fprs_dirty(dc, QFPREG(a->rd)); + return advance_pc(dc); +} + +TRANS(FdTOq, ALL, do_env_qd, a, gen_helper_fdtoq) +TRANS(FxTOq, 64, do_env_qd, a, gen_helper_fxtoq) + static bool do_fff(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i32, TCGv_i32, TCGv_i32)) { @@ -5100,11 +5111,9 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) case 0x83: /* V9 fqtox */ case 0xcc: /* fitoq */ case 0xcd: /* fstoq */ - g_assert_not_reached(); /* in decodetree */ case 0xce: /* fdtoq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq); - break; + case 0x8c: /* V9 fxtoq */ + g_assert_not_reached(); /* in decodetree */ #ifdef TARGET_SPARC64 case 0x3: /* V9 fmovq */ CHECK_FPU_FEATURE(dc, FLOAT128); @@ -5118,10 +5127,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq); break; - case 0x8c: /* V9 fxtoq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq); - break; #endif default: goto illegal_insn; --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280707; cv=none; d=zohomail.com; s=zohoarc; b=acYl+YMkRvtUIqLDJ7ltighiOAK48k3YLZsWF6xjkvzEkB7ybTKFvnalMsw3qVbIu+58Krb90N0eWGXeAtqKbUAFUnbpMdzbUIbZPN0hcROPBTdWgwh/f/H+QNcCAw1sNs9T8hHMp3rYPzsdVF62Cb7r4c6ZWutievrnQ6/r1eU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698280707; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280708412100011 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 + target/sparc/translate.c | 142 +++++++++++++------------------------- 2 files changed, 51 insertions(+), 94 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index e1f5394d17..807ed3f66f 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -241,10 +241,13 @@ RETRY 10 00001 111110 00000 0 0000000000000 =20 FMOVs 10 ..... 110100 00000 0 0000 0001 ..... @r_r2 FMOVd 10 ..... 110100 00000 0 0000 0010 ..... @r_r2 +FMOVq 10 ..... 110100 00000 0 0000 0011 ..... @r_r2 FNEGs 10 ..... 110100 00000 0 0000 0101 ..... @r_r2 FNEGd 10 ..... 110100 00000 0 0000 0110 ..... @r_r2 +FNEGq 10 ..... 110100 00000 0 0000 0111 ..... @r_r2 FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2 FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 +FABSq 10 ..... 110100 00000 0 0000 1011 ..... @r_r2 FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2 FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2 FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 40823f1325..e6451f3950 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -63,6 +63,7 @@ # define gen_helper_write_softint(E, S) qemu_build_not_reached() # define gen_helper_wrpil(E, S) qemu_build_not_reached() # define gen_helper_wrpstate(E, S) qemu_build_not_reached() +# define gen_helper_fabsq ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fdtox ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fexpand ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fmul8sux16 ({ qemu_build_not_reached(); NULL= ; }) @@ -72,12 +73,13 @@ # define gen_helper_fmul8x16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fmuld8sux16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fmuld8ulx16 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fnegq ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fpmerge ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fqtox ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fstox ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fxtod ({ qemu_build_not_reached(); NULL= ; }) -# define gen_helper_fxtos ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fxtoq ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fxtos ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_pdist ({ qemu_build_not_reached(); NULL= ; }) # define FSR_LDXFSR_MASK 0 # define FSR_LDXFSR_OLDMASK 0 @@ -267,18 +269,6 @@ static void gen_op_store_QT0_fpr(unsigned int dst) offsetof(CPU_QuadU, ll.lower)); } =20 -#ifdef TARGET_SPARC64 -static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs) -{ - rd =3D QFPREG(rd); - rs =3D QFPREG(rs); - - tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]); - tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]); - gen_update_fprs_dirty(dc, rd); -} -#endif - /* moves */ #ifdef CONFIG_USER_ONLY #define supervisor(dc) 0 @@ -1660,19 +1650,6 @@ static int gen_trap_ifnofpu(DisasContext *dc) return 0; } =20 -#ifdef TARGET_SPARC64 -static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_ptr)) -{ - gen_op_load_fpr_QT1(QFPREG(rs)); - - gen(tcg_env); - - gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(dc, QFPREG(rd)); -} -#endif - /* asi moves */ typedef enum { GET_ASI_HELPER, @@ -4709,6 +4686,50 @@ TRANS(FiTOd, ALL, do_env_df, a, gen_helper_fitod) TRANS(FsTOd, ALL, do_env_df, a, gen_helper_fstod) TRANS(FsTOx, 64, do_env_df, a, gen_helper_fstox) =20 +static bool trans_FMOVq(DisasContext *dc, arg_FMOVq *a) +{ + int rd, rs; + + if (!avail_64(dc)) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + rd =3D QFPREG(a->rd); + rs =3D QFPREG(a->rs); + tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]); + tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]); + gen_update_fprs_dirty(dc, rd); + return advance_pc(dc); +} + +static bool do_qq(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_env)) +{ + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + gen_op_load_fpr_QT1(QFPREG(a->rs)); + func(tcg_env); + gen_op_store_QT0_fpr(QFPREG(a->rd)); + gen_update_fprs_dirty(dc, QFPREG(a->rd)); + return advance_pc(dc); +} + +TRANS(FNEGq, 64, do_qq, a, gen_helper_fnegq) +TRANS(FABSq, 64, do_qq, a, gen_helper_fabsq) + static bool do_env_qq(DisasContext *dc, arg_r_r *a, void (*func)(TCGv_env)) { @@ -5063,74 +5084,7 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) TCGv cpu_dst __attribute__((unused)) =3D tcg_temp_new(); =20 if (xop =3D=3D 0x34) { /* FPU Operations */ - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - gen_op_clear_ieee_excp_and_FTT(); - rs1 =3D GET_FIELD(insn, 13, 17); - rs2 =3D GET_FIELD(insn, 27, 31); - xop =3D GET_FIELD(insn, 18, 26); - - switch (xop) { - case 0x1: /* fmovs */ - case 0x5: /* fnegs */ - case 0x9: /* fabss */ - case 0x2: /* V9 fmovd */ - case 0x6: /* V9 fnegd */ - case 0xa: /* V9 fabsd */ - case 0x29: /* fsqrts */ - case 0xc4: /* fitos */ - case 0xd1: /* fstoi */ - case 0x2a: /* fsqrtd */ - case 0x82: /* V9 fdtox */ - case 0x88: /* V9 fxtod */ - case 0x2b: /* fsqrtq */ - case 0x41: /* fadds */ - case 0x45: /* fsubs */ - case 0x49: /* fmuls */ - case 0x4d: /* fdivs */ - case 0x42: /* faddd */ - case 0x46: /* fsubd */ - case 0x4a: /* fmuld */ - case 0x4e: /* fdivd */ - case 0x43: /* faddq */ - case 0x47: /* fsubq */ - case 0x4b: /* fmulq */ - case 0x4f: /* fdivq */ - case 0x69: /* fsmuld */ - case 0x6e: /* fdmulq */ - case 0xc6: /* fdtos */ - case 0xd2: /* fdtoi */ - case 0x84: /* V9 fxtos */ - case 0xc8: /* fitod */ - case 0xc9: /* fstod */ - case 0x81: /* V9 fstox */ - case 0xc7: /* fqtos */ - case 0xd3: /* fqtoi */ - case 0xcb: /* fqtod */ - case 0x83: /* V9 fqtox */ - case 0xcc: /* fitoq */ - case 0xcd: /* fstoq */ - case 0xce: /* fdtoq */ - case 0x8c: /* V9 fxtoq */ - g_assert_not_reached(); /* in decodetree */ -#ifdef TARGET_SPARC64 - case 0x3: /* V9 fmovq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_move_Q(dc, rd, rs2); - break; - case 0x7: /* V9 fnegq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq); - break; - case 0xb: /* V9 fabsq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq); - break; -#endif - default: - goto illegal_insn; - } + goto illegal_insn; /* in decodetree */ } else if (xop =3D=3D 0x35) { /* FPU Operations */ #ifdef TARGET_SPARC64 int cond; --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280758; cv=none; d=zohomail.com; s=zohoarc; b=KjlxXk2O0pD87Nju1FI1q3sOoutuJpPtWtvhuk5fqDB7aEJR3yi4+wjM2dpS5yluaILo+jzN8Aceu/epZ8+5p34ZGewjjnMfnfgGgeKDkwGot//wp+YA705r142V+efPI+yk2R7OO8YFY5ibMsaV6sYwY/tjONSanXuN/9o0D2E= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280758482100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 12 +++ target/sparc/translate.c | 192 ++++++++++++++++---------------------- 2 files changed, 91 insertions(+), 113 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 807ed3f66f..d4487e326a 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -284,6 +284,18 @@ FsTOi 10 ..... 110100 00000 0 1101 0001 ..... = @r_r2 FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2 FqTOi 10 ..... 110100 00000 0 1101 0011 ..... @r_r2 =20 +FMOVscc 10 rd:5 110101 0 cond:4 1 cc:1 0 000001 rs2:5 +FMOVdcc 10 rd:5 110101 0 cond:4 1 cc:1 0 000010 rs2:5 +FMOVqcc 10 rd:5 110101 0 cond:4 1 cc:1 0 000011 rs2:5 + +FMOVsfcc 10 rd:5 110101 0 cond:4 0 cc:2 000001 rs2:5 +FMOVdfcc 10 rd:5 110101 0 cond:4 0 cc:2 000010 rs2:5 +FMOVqfcc 10 rd:5 110101 0 cond:4 0 cc:2 000011 rs2:5 + +FMOVRs 10 rd:5 110101 rs1:5 0 cond:3 00101 rs2:5 +FMOVRd 10 rd:5 110101 rs1:5 0 cond:3 00110 rs2:5 +FMOVRq 10 rd:5 110101 rs1:5 0 cond:3 00111 rs2:5 + { [ EDGE8cc 10 ..... 110110 ..... 0 0000 0000 ..... @r_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index e6451f3950..ff18dc0482 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2442,15 +2442,9 @@ static void gen_stda_asi(DisasContext *dc, DisasASI = *da, TCGv addr, int rd) } } =20 -#ifdef TARGET_SPARC64 -static TCGv get_src1(DisasContext *dc, unsigned int insn) -{ - unsigned int rs1 =3D GET_FIELD(insn, 13, 17); - return gen_load_gpr(dc, rs1); -} - static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs) { +#ifdef TARGET_SPARC64 TCGv_i32 c32, zero, dst, s1, s2; =20 /* We have two choices here: extend the 32 bit data and use movcond_i6= 4, @@ -2473,19 +2467,27 @@ static void gen_fmovs(DisasContext *dc, DisasCompar= e *cmp, int rd, int rs) tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2); =20 gen_store_fpr_F(dc, rd, dst); +#else + qemu_build_not_reached(); +#endif } =20 static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs) { +#ifdef TARGET_SPARC64 TCGv_i64 dst =3D gen_dest_fpr_D(dc, rd); tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2, gen_load_fpr_D(dc, rs), gen_load_fpr_D(dc, rd)); gen_store_fpr_D(dc, rd, dst); +#else + qemu_build_not_reached(); +#endif } =20 static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs) { +#ifdef TARGET_SPARC64 int qd =3D QFPREG(rd); int qs =3D QFPREG(rs); =20 @@ -2495,8 +2497,12 @@ static void gen_fmovq(DisasContext *dc, DisasCompare= *cmp, int rd, int rs) cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]); =20 gen_update_fprs_dirty(dc, qd); +#else + qemu_build_not_reached(); +#endif } =20 +#ifdef TARGET_SPARC64 static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr) { TCGv_i32 r_tl =3D tcg_temp_new_i32(); @@ -5053,6 +5059,72 @@ static bool trans_FdMULq(DisasContext *dc, arg_r_r_r= *a) return advance_pc(dc); } =20 +static bool do_fmovr(DisasContext *dc, arg_FMOVRs *a, bool is_128, + void (*func)(DisasContext *, DisasCompare *, int, int= )) +{ + DisasCompare cmp; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (is_128 && gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1)); + func(dc, &cmp, a->rd, a->rs2); + return advance_pc(dc); +} + +TRANS(FMOVRs, 64, do_fmovr, a, false, gen_fmovs) +TRANS(FMOVRd, 64, do_fmovr, a, false, gen_fmovd) +TRANS(FMOVRq, 64, do_fmovr, a, true, gen_fmovq) + +static bool do_fmovcc(DisasContext *dc, arg_FMOVscc *a, bool is_128, + void (*func)(DisasContext *, DisasCompare *, int, in= t)) +{ + DisasCompare cmp; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (is_128 && gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + gen_compare(&cmp, a->cc, a->cond, dc); + func(dc, &cmp, a->rd, a->rs2); + return advance_pc(dc); +} + +TRANS(FMOVscc, 64, do_fmovcc, a, false, gen_fmovs) +TRANS(FMOVdcc, 64, do_fmovcc, a, false, gen_fmovd) +TRANS(FMOVqcc, 64, do_fmovcc, a, true, gen_fmovq) + +static bool do_fmovfcc(DisasContext *dc, arg_FMOVsfcc *a, bool is_128, + void (*func)(DisasContext *, DisasCompare *, int, i= nt)) +{ + DisasCompare cmp; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (is_128 && gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + gen_fcompare(&cmp, a->cc, a->cond); + func(dc, &cmp, a->rd, a->rs2); + return advance_pc(dc); +} + +TRANS(FMOVsfcc, 64, do_fmovfcc, a, false, gen_fmovs) +TRANS(FMOVdfcc, 64, do_fmovfcc, a, false, gen_fmovd) +TRANS(FMOVqfcc, 64, do_fmovfcc, a, true, gen_fmovq) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5086,9 +5158,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsi= gned int insn) if (xop =3D=3D 0x34) { /* FPU Operations */ goto illegal_insn; /* in decodetree */ } else if (xop =3D=3D 0x35) { /* FPU Operations */ -#ifdef TARGET_SPARC64 - int cond; -#endif if (gen_trap_ifnofpu(dc)) { goto jmp_insn; } @@ -5097,110 +5166,7 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) rs2 =3D GET_FIELD(insn, 27, 31); xop =3D GET_FIELD(insn, 18, 26); =20 -#ifdef TARGET_SPARC64 -#define FMOVR(sz) \ - do { \ - DisasCompare cmp; \ - cond =3D GET_FIELD_SP(insn, 10, 12); \ - cpu_src1 =3D get_src1(dc, insn); \ - gen_compare_reg(&cmp, cond, cpu_src1); \ - gen_fmov##sz(dc, &cmp, rd, rs2); \ - } while (0) - - if ((xop & 0x11f) =3D=3D 0x005) { /* V9 fmovsr */ - FMOVR(s); - break; - } else if ((xop & 0x11f) =3D=3D 0x006) { // V9 fmovdr - FMOVR(d); - break; - } else if ((xop & 0x11f) =3D=3D 0x007) { // V9 fmovqr - CHECK_FPU_FEATURE(dc, FLOAT128); - FMOVR(q); - break; - } -#undef FMOVR -#endif switch (xop) { -#ifdef TARGET_SPARC64 -#define FMOVCC(fcc, sz) \ - do { \ - DisasCompare cmp; \ - cond =3D GET_FIELD_SP(insn, 14, 17); \ - gen_fcompare(&cmp, fcc, cond); \ - gen_fmov##sz(dc, &cmp, rd, rs2); \ - } while (0) - - case 0x001: /* V9 fmovscc %fcc0 */ - FMOVCC(0, s); - break; - case 0x002: /* V9 fmovdcc %fcc0 */ - FMOVCC(0, d); - break; - case 0x003: /* V9 fmovqcc %fcc0 */ - CHECK_FPU_FEATURE(dc, FLOAT128); - FMOVCC(0, q); - break; - case 0x041: /* V9 fmovscc %fcc1 */ - FMOVCC(1, s); - break; - case 0x042: /* V9 fmovdcc %fcc1 */ - FMOVCC(1, d); - break; - case 0x043: /* V9 fmovqcc %fcc1 */ - CHECK_FPU_FEATURE(dc, FLOAT128); - FMOVCC(1, q); - break; - case 0x081: /* V9 fmovscc %fcc2 */ - FMOVCC(2, s); - break; - case 0x082: /* V9 fmovdcc %fcc2 */ - FMOVCC(2, d); - break; - case 0x083: /* V9 fmovqcc %fcc2 */ - CHECK_FPU_FEATURE(dc, FLOAT128); - FMOVCC(2, q); - break; - case 0x0c1: /* V9 fmovscc %fcc3 */ - FMOVCC(3, s); - break; - case 0x0c2: /* V9 fmovdcc %fcc3 */ - FMOVCC(3, d); - break; - case 0x0c3: /* V9 fmovqcc %fcc3 */ - CHECK_FPU_FEATURE(dc, FLOAT128); - FMOVCC(3, q); - break; -#undef FMOVCC -#define FMOVCC(xcc, sz) \ - do { \ - DisasCompare cmp; \ - cond =3D GET_FIELD_SP(insn, 14, 17); \ - gen_compare(&cmp, xcc, cond, dc); \ - gen_fmov##sz(dc, &cmp, rd, rs2); \ - } while (0) - - case 0x101: /* V9 fmovscc %icc */ - FMOVCC(0, s); - break; - case 0x102: /* V9 fmovdcc %icc */ - FMOVCC(0, d); - break; - case 0x103: /* V9 fmovqcc %icc */ - CHECK_FPU_FEATURE(dc, FLOAT128); - FMOVCC(0, q); - break; - case 0x181: /* V9 fmovscc %xcc */ - FMOVCC(1, s); - break; - case 0x182: /* V9 fmovdcc %xcc */ - FMOVCC(1, d); - break; - case 0x183: /* V9 fmovqcc %xcc */ - CHECK_FPU_FEATURE(dc, FLOAT128); - FMOVCC(1, q); - break; -#undef FMOVCC -#endif case 0x51: /* fcmps, V9 %fcc */ cpu_src1_32 =3D gen_load_fpr_F(dc, rs1); cpu_src2_32 =3D gen_load_fpr_F(dc, rs2); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280902915100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 7 ++ target/sparc/translate.c | 145 +++++++++++++++++++++++--------------- 2 files changed, 96 insertions(+), 56 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index d4487e326a..f197bb0b36 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -296,6 +296,13 @@ FMOVRs 10 rd:5 110101 rs1:5 0 cond:3 00101 r= s2:5 FMOVRd 10 rd:5 110101 rs1:5 0 cond:3 00110 rs2:5 FMOVRq 10 rd:5 110101 rs1:5 0 cond:3 00111 rs2:5 =20 +FCMPs 10 000 cc:2 110101 rs1:5 0 0101 0001 rs2:5 +FCMPd 10 000 cc:2 110101 rs1:5 0 0101 0010 rs2:5 +FCMPq 10 000 cc:2 110101 rs1:5 0 0101 0011 rs2:5 +FCMPEs 10 000 cc:2 110101 rs1:5 0 0101 0101 rs2:5 +FCMPEd 10 000 cc:2 110101 rs1:5 0 0101 0110 rs2:5 +FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5 + { [ EDGE8cc 10 ..... 110110 ..... 0 0000 0000 ..... @r_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ff18dc0482..ddde64dfb4 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5125,6 +5125,82 @@ TRANS(FMOVsfcc, 64, do_fmovfcc, a, false, gen_fmovs) TRANS(FMOVdfcc, 64, do_fmovfcc, a, false, gen_fmovd) TRANS(FMOVqfcc, 64, do_fmovfcc, a, true, gen_fmovq) =20 +static bool do_fcmps(DisasContext *dc, arg_FCMPs *a, bool e) +{ + TCGv_i32 src1, src2; + + if (avail_32(dc) && a->cc !=3D 0) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + src1 =3D gen_load_fpr_F(dc, a->rs1); + src2 =3D gen_load_fpr_F(dc, a->rs2); + if (e) { + gen_op_fcmpes(a->cc, src1, src2); + } else { + gen_op_fcmps(a->cc, src1, src2); + } + return advance_pc(dc); +} + +TRANS(FCMPs, ALL, do_fcmps, a, false) +TRANS(FCMPEs, ALL, do_fcmps, a, true) + +static bool do_fcmpd(DisasContext *dc, arg_FCMPd *a, bool e) +{ + TCGv_i64 src1, src2; + + if (avail_32(dc) && a->cc !=3D 0) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + src1 =3D gen_load_fpr_D(dc, a->rs1); + src2 =3D gen_load_fpr_D(dc, a->rs2); + if (e) { + gen_op_fcmped(a->cc, src1, src2); + } else { + gen_op_fcmpd(a->cc, src1, src2); + } + return advance_pc(dc); +} + +TRANS(FCMPd, ALL, do_fcmpd, a, false) +TRANS(FCMPEd, ALL, do_fcmpd, a, true) + +static bool do_fcmpq(DisasContext *dc, arg_FCMPq *a, bool e) +{ + if (avail_32(dc) && a->cc !=3D 0) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + gen_op_load_fpr_QT0(QFPREG(a->rs1)); + gen_op_load_fpr_QT1(QFPREG(a->rs2)); + if (e) { + gen_op_fcmpeq(a->cc); + } else { + gen_op_fcmpq(a->cc); + } + return advance_pc(dc); +} + +TRANS(FCMPq, ALL, do_fcmpq, a, false) +TRANS(FCMPEq, ALL, do_fcmpq, a, true) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5135,15 +5211,7 @@ TRANS(FMOVqfcc, 64, do_fmovfcc, a, true, gen_fmovq) /* before an instruction, dc->pc must be static */ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) { - unsigned int opc, rs1, rs2, rd; - TCGv cpu_src1 __attribute__((unused)); - TCGv_i32 cpu_src1_32, cpu_src2_32; - TCGv_i64 cpu_src1_64, cpu_src2_64; - TCGv_i32 cpu_dst_32 __attribute__((unused)); - TCGv_i64 cpu_dst_64 __attribute__((unused)); - - opc =3D GET_FIELD(insn, 0, 1); - rd =3D GET_FIELD(insn, 2, 6); + unsigned int opc =3D GET_FIELD(insn, 0, 1); =20 switch (opc) { case 0: @@ -5153,61 +5221,22 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 2: /* FPU & Logical Operations */ { unsigned int xop =3D GET_FIELD(insn, 7, 12); - TCGv cpu_dst __attribute__((unused)) =3D tcg_temp_new(); =20 if (xop =3D=3D 0x34) { /* FPU Operations */ goto illegal_insn; /* in decodetree */ } else if (xop =3D=3D 0x35) { /* FPU Operations */ - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - gen_op_clear_ieee_excp_and_FTT(); - rs1 =3D GET_FIELD(insn, 13, 17); - rs2 =3D GET_FIELD(insn, 27, 31); - xop =3D GET_FIELD(insn, 18, 26); - - switch (xop) { - case 0x51: /* fcmps, V9 %fcc */ - cpu_src1_32 =3D gen_load_fpr_F(dc, rs1); - cpu_src2_32 =3D gen_load_fpr_F(dc, rs2); - gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32); - break; - case 0x52: /* fcmpd, V9 %fcc */ - cpu_src1_64 =3D gen_load_fpr_D(dc, rs1); - cpu_src2_64 =3D gen_load_fpr_D(dc, rs2); - gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64); - break; - case 0x53: /* fcmpq, V9 %fcc */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_op_load_fpr_QT0(QFPREG(rs1)); - gen_op_load_fpr_QT1(QFPREG(rs2)); - gen_op_fcmpq(rd & 3); - break; - case 0x55: /* fcmpes, V9 %fcc */ - cpu_src1_32 =3D gen_load_fpr_F(dc, rs1); - cpu_src2_32 =3D gen_load_fpr_F(dc, rs2); - gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32); - break; - case 0x56: /* fcmped, V9 %fcc */ - cpu_src1_64 =3D gen_load_fpr_D(dc, rs1); - cpu_src2_64 =3D gen_load_fpr_D(dc, rs2); - gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64); - break; - case 0x57: /* fcmpeq, V9 %fcc */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_op_load_fpr_QT0(QFPREG(rs1)); - gen_op_load_fpr_QT1(QFPREG(rs2)); - gen_op_fcmpeq(rd & 3); - break; - default: - goto illegal_insn; - } + goto illegal_insn; /* in decodetree */ } else if (xop =3D=3D 0x36) { #ifdef TARGET_SPARC64 /* VIS */ + TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64; + TCGv_i32 cpu_dst_32; + TCGv cpu_dst =3D tcg_temp_new(); int opf =3D GET_FIELD_SP(insn, 5, 13); - rs1 =3D GET_FIELD(insn, 13, 17); - rs2 =3D GET_FIELD(insn, 27, 31); + int rs1 =3D GET_FIELD(insn, 13, 17); + int rs2 =3D GET_FIELD(insn, 27, 31); + int rd =3D GET_FIELD(insn, 2, 6); + if (gen_trap_ifnofpu(dc)) { goto jmp_insn; } @@ -5392,14 +5421,18 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) goto illegal_insn; /* in decodetree */ } advance_pc(dc); +#ifdef TARGET_SPARC64 jmp_insn: +#endif return; illegal_insn: gen_exception(dc, TT_ILL_INSN); return; +#ifdef TARGET_SPARC64 nfpu_insn: gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP); return; +#endif } =20 static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280349137100001 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 9 ++++ target/sparc/translate.c | 90 +++++++++++++++++---------------------- 2 files changed, 47 insertions(+), 52 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index f197bb0b36..781c3cd7f7 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -327,6 +327,15 @@ FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5 =20 BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r =20 + FPCMPLE16 10 ..... 110110 ..... 0 0010 0000 ..... @r_r_r + FPCMPNE16 10 ..... 110110 ..... 0 0010 0010 ..... @r_r_r + FPCMPGT16 10 ..... 110110 ..... 0 0010 1000 ..... @r_r_r + FPCMPEQ16 10 ..... 110110 ..... 0 0010 1010 ..... @r_r_r + FPCMPLE32 10 ..... 110110 ..... 0 0010 0100 ..... @r_r_r + FPCMPNE32 10 ..... 110110 ..... 0 0010 0110 ..... @r_r_r + FPCMPGT32 10 ..... 110110 ..... 0 0010 1100 ..... @r_r_r + FPCMPEQ32 10 ..... 110110 ..... 0 0010 1110 ..... @r_r_r + FMUL8x16 10 ..... 110110 ..... 0 0011 0001 ..... @r_r_r FMUL8x16AU 10 ..... 110110 ..... 0 0011 0011 ..... @r_r_r FMUL8x16AL 10 ..... 110110 ..... 0 0011 0101 ..... @r_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ddde64dfb4..3ee1015cc4 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -64,6 +64,14 @@ # define gen_helper_wrpil(E, S) qemu_build_not_reached() # define gen_helper_wrpstate(E, S) qemu_build_not_reached() # define gen_helper_fabsq ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fcmpeq16 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fcmpeq32 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fcmpgt16 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fcmpgt32 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fcmple16 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fcmple32 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fcmpne16 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fcmpne32 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fdtox ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fexpand ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fmul8sux16 ({ qemu_build_not_reached(); NULL= ; }) @@ -4947,6 +4955,34 @@ TRANS(FPACK32, VIS1, do_ddd, a, gen_op_fpack32) TRANS(FALIGNDATAg, VIS1, do_ddd, a, gen_op_faligndata) TRANS(BSHUFFLE, VIS2, do_ddd, a, gen_op_bshuffle) =20 +static bool do_rdd(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv, TCGv_i64, TCGv_i64)) +{ + TCGv_i64 src1, src2; + TCGv dst; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + dst =3D gen_dest_gpr(dc, a->rd); + src1 =3D gen_load_fpr_D(dc, a->rs1); + src2 =3D gen_load_fpr_D(dc, a->rs2); + func(dst, src1, src2); + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FPCMPLE16, VIS1, do_rdd, a, gen_helper_fcmple16) +TRANS(FPCMPNE16, VIS1, do_rdd, a, gen_helper_fcmpne16) +TRANS(FPCMPGT16, VIS1, do_rdd, a, gen_helper_fcmpgt16) +TRANS(FPCMPEQ16, VIS1, do_rdd, a, gen_helper_fcmpeq16) + +TRANS(FPCMPLE32, VIS1, do_rdd, a, gen_helper_fcmple32) +TRANS(FPCMPNE32, VIS1, do_rdd, a, gen_helper_fcmpne32) +TRANS(FPCMPGT32, VIS1, do_rdd, a, gen_helper_fcmpgt32) +TRANS(FPCMPEQ32, VIS1, do_rdd, a, gen_helper_fcmpeq32) + static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64= )) { @@ -5229,11 +5265,9 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) } else if (xop =3D=3D 0x36) { #ifdef TARGET_SPARC64 /* VIS */ - TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64; + TCGv_i64 cpu_src1_64, cpu_dst_64; TCGv_i32 cpu_dst_32; - TCGv cpu_dst =3D tcg_temp_new(); int opf =3D GET_FIELD_SP(insn, 5, 13); - int rs1 =3D GET_FIELD(insn, 13, 17); int rs2 =3D GET_FIELD(insn, 27, 31); int rd =3D GET_FIELD(insn, 2, 6); =20 @@ -5309,63 +5343,15 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 0x03a: /* VIS I fpack32 */ case 0x048: /* VIS I faligndata */ case 0x04c: /* VIS II bshuffle */ - g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 =3D gen_load_fpr_D(dc, rs1); - cpu_src2_64 =3D gen_load_fpr_D(dc, rs2); - gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x022: /* VIS I fcmpne16 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 =3D gen_load_fpr_D(dc, rs1); - cpu_src2_64 =3D gen_load_fpr_D(dc, rs2); - gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x024: /* VIS I fcmple32 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 =3D gen_load_fpr_D(dc, rs1); - cpu_src2_64 =3D gen_load_fpr_D(dc, rs2); - gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x026: /* VIS I fcmpne32 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 =3D gen_load_fpr_D(dc, rs1); - cpu_src2_64 =3D gen_load_fpr_D(dc, rs2); - gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x028: /* VIS I fcmpgt16 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 =3D gen_load_fpr_D(dc, rs1); - cpu_src2_64 =3D gen_load_fpr_D(dc, rs2); - gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x02a: /* VIS I fcmpeq16 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 =3D gen_load_fpr_D(dc, rs1); - cpu_src2_64 =3D gen_load_fpr_D(dc, rs2); - gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x02c: /* VIS I fcmpgt32 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 =3D gen_load_fpr_D(dc, rs1); - cpu_src2_64 =3D gen_load_fpr_D(dc, rs2); - gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x02e: /* VIS I fcmpeq32 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 =3D gen_load_fpr_D(dc, rs1); - cpu_src2_64 =3D gen_load_fpr_D(dc, rs2); - gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; + g_assert_not_reached(); /* in decodetree */ case 0x03b: /* VIS I fpack16 */ CHECK_FPU_FEATURE(dc, VIS1); cpu_src1_64 =3D gen_load_fpr_D(dc, rs2); --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280409; cv=none; d=zohomail.com; s=zohoarc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280411320100003 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 55 ++++++++++++++++++++++++++++----------- 2 files changed, 42 insertions(+), 15 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 781c3cd7f7..18a840709f 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -344,6 +344,8 @@ FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5 FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @r_r_r FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @r_r_r FPACK32 10 ..... 110110 ..... 0 0011 1010 ..... @r_r_r + FPACK16 10 ..... 110110 00000 0 0011 1011 ..... @r_r2 + FPACKFIX 10 ..... 110110 00000 0 0011 1101 ..... @r_r2 PDIST 10 ..... 110110 ..... 0 0011 1110 ..... @r_r_r =20 FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @r_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 3ee1015cc4..15c91c6caa 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -756,6 +756,24 @@ static void gen_op_array32(TCGv dst, TCGv src1, TCGv s= rc2) tcg_gen_shli_tl(dst, dst, 2); } =20 +static void gen_op_fpack16(TCGv_i32 dst, TCGv_i64 src) +{ +#ifdef TARGET_SPARC64 + gen_helper_fpack16(dst, cpu_gsr, src); +#else + g_assert_not_reached(); +#endif +} + +static void gen_op_fpackfix(TCGv_i32 dst, TCGv_i64 src) +{ +#ifdef TARGET_SPARC64 + gen_helper_fpackfix(dst, cpu_gsr, src); +#else + g_assert_not_reached(); +#endif +} + static void gen_op_fpack32(TCGv_i64 dst, TCGv_i64 src1, TCGv_i64 src2) { #ifdef TARGET_SPARC64 @@ -4589,6 +4607,26 @@ TRANS(FABSs, ALL, do_ff, a, gen_op_fabss) TRANS(FSRCs, VIS1, do_ff, a, tcg_gen_mov_i32) TRANS(FNOTs, VIS1, do_ff, a, tcg_gen_not_i32) =20 +static bool do_fd(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i32, TCGv_i64)) +{ + TCGv_i32 dst; + TCGv_i64 src; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + dst =3D gen_dest_fpr_F(dc); + src =3D gen_load_fpr_D(dc, a->rs); + func(dst, src); + gen_store_fpr_F(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FPACK16, VIS1, do_fd, a, gen_op_fpack16) +TRANS(FPACKFIX, VIS1, do_fd, a, gen_op_fpackfix) + static bool do_env_ff(DisasContext *dc, arg_r_r *a, void (*func)(TCGv_i32, TCGv_env, TCGv_i32)) { @@ -5265,10 +5303,9 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) } else if (xop =3D=3D 0x36) { #ifdef TARGET_SPARC64 /* VIS */ - TCGv_i64 cpu_src1_64, cpu_dst_64; + TCGv_i64 cpu_dst_64; TCGv_i32 cpu_dst_32; int opf =3D GET_FIELD_SP(insn, 5, 13); - int rs2 =3D GET_FIELD(insn, 27, 31); int rd =3D GET_FIELD(insn, 2, 6); =20 if (gen_trap_ifnofpu(dc)) { @@ -5351,21 +5388,9 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) case 0x02a: /* VIS I fcmpeq16 */ case 0x02c: /* VIS I fcmpgt32 */ case 0x02e: /* VIS I fcmpeq32 */ - g_assert_not_reached(); /* in decodetree */ case 0x03b: /* VIS I fpack16 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 =3D gen_load_fpr_D(dc, rs2); - cpu_dst_32 =3D gen_dest_fpr_F(dc); - gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64); - gen_store_fpr_F(dc, rd, cpu_dst_32); - break; case 0x03d: /* VIS I fpackfix */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 =3D gen_load_fpr_D(dc, rs2); - cpu_dst_32 =3D gen_dest_fpr_F(dc); - gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64); - gen_store_fpr_F(dc, rd, cpu_dst_32); - break; + g_assert_not_reached(); /* in decodetree */ case 0x060: /* VIS I fzero */ CHECK_FPU_FEATURE(dc, VIS1); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280794627100010 Content-Type: text/plain; charset="utf-8" Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 5 +++ target/sparc/translate.c | 69 +++++++++++++++++++++++---------------- 2 files changed, 45 insertions(+), 29 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 18a840709f..0552f1447d 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -391,6 +391,11 @@ FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5 FORNOTs 10 ..... 110110 ..... 0 0111 1011 ..... @r_r_r_swap # .= .. 1s FORd 10 ..... 110110 ..... 0 0111 1100 ..... @r_r_r FORs 10 ..... 110110 ..... 0 0111 1101 ..... @r_r_r + + FZEROd 10 rd:5 110110 00000 0 0110 0000 00000 + FZEROs 10 rd:5 110110 00000 0 0110 0001 00000 + FONEd 10 rd:5 110110 00000 0 0111 1110 00000 + FONEs 10 rd:5 110110 00000 0 0111 1111 00000 ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 15c91c6caa..62c77ae5e1 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4586,6 +4586,45 @@ static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a= , MemOp mop) TRANS(STFSR, ALL, do_stfsr, a, MO_TEUL) TRANS(STXFSR, 64, do_stfsr, a, MO_TEUQ) =20 +static bool do_fc(DisasContext *dc, int rd, bool c) +{ + uint64_t mask; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + if (rd & 1) { + mask =3D MAKE_64BIT_MASK(0, 32); + } else { + mask =3D MAKE_64BIT_MASK(32, 32); + } + if (c) { + tcg_gen_ori_i64(cpu_fpr[rd / 2], cpu_fpr[rd / 2], mask); + } else { + tcg_gen_andi_i64(cpu_fpr[rd / 2], cpu_fpr[rd / 2], ~mask); + } + gen_update_fprs_dirty(dc, rd); + return advance_pc(dc); +} + +TRANS(FZEROs, VIS1, do_fc, a->rd, 0) +TRANS(FONEs, VIS1, do_fc, a->rd, 1) + +static bool do_dc(DisasContext *dc, int rd, int64_t c) +{ + if (gen_trap_ifnofpu(dc)) { + return true; + } + + tcg_gen_movi_i64(cpu_fpr[rd / 2], c); + gen_update_fprs_dirty(dc, rd); + return advance_pc(dc); +} + +TRANS(FZEROd, VIS1, do_dc, a->rd, 0) +TRANS(FONEd, VIS1, do_dc, a->rd, -1) + static bool do_ff(DisasContext *dc, arg_r_r *a, void (*func)(TCGv_i32, TCGv_i32)) { @@ -5303,10 +5342,7 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) } else if (xop =3D=3D 0x36) { #ifdef TARGET_SPARC64 /* VIS */ - TCGv_i64 cpu_dst_64; - TCGv_i32 cpu_dst_32; int opf =3D GET_FIELD_SP(insn, 5, 13); - int rd =3D GET_FIELD(insn, 2, 6); =20 if (gen_trap_ifnofpu(dc)) { goto jmp_insn; @@ -5390,31 +5426,11 @@ static void disas_sparc_legacy(DisasContext *dc, un= signed int insn) case 0x02e: /* VIS I fcmpeq32 */ case 0x03b: /* VIS I fpack16 */ case 0x03d: /* VIS I fpackfix */ - g_assert_not_reached(); /* in decodetree */ case 0x060: /* VIS I fzero */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_dst_64 =3D gen_dest_fpr_D(dc, rd); - tcg_gen_movi_i64(cpu_dst_64, 0); - gen_store_fpr_D(dc, rd, cpu_dst_64); - break; case 0x061: /* VIS I fzeros */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_dst_32 =3D gen_dest_fpr_F(dc); - tcg_gen_movi_i32(cpu_dst_32, 0); - gen_store_fpr_F(dc, rd, cpu_dst_32); - break; case 0x07e: /* VIS I fone */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_dst_64 =3D gen_dest_fpr_D(dc, rd); - tcg_gen_movi_i64(cpu_dst_64, -1); - gen_store_fpr_D(dc, rd, cpu_dst_64); - break; case 0x07f: /* VIS I fones */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_dst_32 =3D gen_dest_fpr_F(dc); - tcg_gen_movi_i32(cpu_dst_32, -1); - gen_store_fpr_F(dc, rd, cpu_dst_32); - break; + g_assert_not_reached(); /* in decodetree */ case 0x080: /* VIS I shutdown */ case 0x081: /* VIS II siam */ // XXX @@ -5439,11 +5455,6 @@ static void disas_sparc_legacy(DisasContext *dc, uns= igned int insn) illegal_insn: gen_exception(dc, TT_ILL_INSN); return; -#ifdef TARGET_SPARC64 - nfpu_insn: - gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP); - return; -#endif } =20 static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) --=20 2.34.1 From nobody Wed Nov 27 12:34:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1698280394; cv=none; d=zohomail.com; s=zohoarc; b=Cl4fzPb3vnCrZiIcKhATmwWIRCEe9PJk9copT5a80K1UH1JwKXrXaD+KoLE/CspRF4lJGnA1H+eTczal95pDF/d2ZaryjZkDhF+fOx/qGwgFmOVxt7/650cIjIdFycKS1O6BTa/ZjkPcFt4EzaxaYg3h1AI57kwmf7E5D/AWvZc= ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id gv24-20020a17090b11d800b00262ca945cecsm438134pjb.54.2023.10.25.17.26.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:26:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279984; x=1698884784; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UNlHweIcSWalX2p286xPjt52l47jSewmSDxHwGQ1o5o=; b=WpoGiTQj4BNo2uIiW2VgsbLHF6wy3/IlgonXobcdMNZmCi3kDjuuI6qd+04cwW6jGv 4w2X81sCcUnUCj85uXVw50gIsHvaYyEwqGHP+iNno/4PQH5X5mkfjVwfEj8pX4s3cI32 R9SqdJfjZmBjM74wqzD9OGMpyeYGNqeUuLzvHGcNFCiuvFQuz8FrJ0uCvu8Oj+OZ/8UO is3S0ERgpO3MygOCF6rQnD+FwyF/GJH0lY/BeBIhAvollUdozkRg0w4vMgVVOVaS2Ezo y+bcym+UNpUnbLw0frz1ncEhZ+GxK7iwM3lIqZGcmRHIP82pXH44PUvzFBEbJI4onFnE d4Ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279984; x=1698884784; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UNlHweIcSWalX2p286xPjt52l47jSewmSDxHwGQ1o5o=; b=XJNqdurxB9iaqn55/96ZU0fJQBv4WYEhWLweGJXa5KFA5l2dYeoBwLyfaIBzMWoz9+ NbEGPLkSjm2F17SZmuq1w6FyzUlcI1OGA2E7A7EzMoas3+qs6m/0YtE1PTR2ZS/OlIOj vjcQWnyypk5K3nbtM3xie1peYWUP+3Bm+gzeRQskMWjHt4ztX8rwsN15zCH7us4PnEba 7ZJSzfz1Jwh11WajLSYtUWM1AC+mipsWfN5d0vbmKimcrXN/eSWKgyRhi77vlBHIuito BPtuImHKuhwBkN0pZEfMT+MO0o6X1IW6DMfOKSxn/UF5Dz6SPtHqZf/I12Cd+YG0a4N4 NM9w== X-Gm-Message-State: AOJu0Yx+dWynJPukoaGlHkTmYenvno2oTVI8BSjI0lXuGxxrv+qTqSdy kh9zlyO6mkrl16xaAi/MLtvsaQRphkCFzpkFY14= X-Google-Smtp-Source: AGHT+IEFRhMggXoK7CGXYTHmK3AFoPMlYz3/SBqaIPhiLQOyzFmnEY+zaGdYsbyiqCcmH4O1tHaVVQ== X-Received: by 2002:a05:6a21:488b:b0:179:fac0:a89a with SMTP id av11-20020a056a21488b00b00179fac0a89amr7853967pzc.54.1698279984153; Wed, 25 Oct 2023 17:26:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 94/94] target/sparc: Remove disas_sparc_legacy Date: Wed, 25 Oct 2023 17:15:42 -0700 Message-Id: <20231026001542.1141412-124-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1698280395149100001 Content-Type: text/plain; charset="utf-8" All instructions are now converted. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 145 +-------------------------------------- 1 file changed, 1 insertion(+), 144 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 62c77ae5e1..986a88c4e1 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5314,149 +5314,6 @@ static bool do_fcmpq(DisasContext *dc, arg_FCMPq *a= , bool e) TRANS(FCMPq, ALL, do_fcmpq, a, false) TRANS(FCMPEq, ALL, do_fcmpq, a, true) =20 -#define CHECK_IU_FEATURE(dc, FEATURE) \ - if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ - goto illegal_insn; -#define CHECK_FPU_FEATURE(dc, FEATURE) \ - if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ - goto nfpu_insn; - -/* before an instruction, dc->pc must be static */ -static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) -{ - unsigned int opc =3D GET_FIELD(insn, 0, 1); - - switch (opc) { - case 0: - goto illegal_insn; /* in decodetree */ - case 1: - g_assert_not_reached(); /* in decodetree */ - case 2: /* FPU & Logical Operations */ - { - unsigned int xop =3D GET_FIELD(insn, 7, 12); - - if (xop =3D=3D 0x34) { /* FPU Operations */ - goto illegal_insn; /* in decodetree */ - } else if (xop =3D=3D 0x35) { /* FPU Operations */ - goto illegal_insn; /* in decodetree */ - } else if (xop =3D=3D 0x36) { -#ifdef TARGET_SPARC64 - /* VIS */ - int opf =3D GET_FIELD_SP(insn, 5, 13); - - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - - switch (opf) { - case 0x000: /* VIS I edge8cc */ - case 0x001: /* VIS II edge8n */ - case 0x002: /* VIS I edge8lcc */ - case 0x003: /* VIS II edge8ln */ - case 0x004: /* VIS I edge16cc */ - case 0x005: /* VIS II edge16n */ - case 0x006: /* VIS I edge16lcc */ - case 0x007: /* VIS II edge16ln */ - case 0x008: /* VIS I edge32cc */ - case 0x009: /* VIS II edge32n */ - case 0x00a: /* VIS I edge32lcc */ - case 0x00b: /* VIS II edge32ln */ - case 0x010: /* VIS I array8 */ - case 0x012: /* VIS I array16 */ - case 0x014: /* VIS I array32 */ - case 0x018: /* VIS I alignaddr */ - case 0x01a: /* VIS I alignaddrl */ - case 0x019: /* VIS II bmask */ - case 0x067: /* VIS I fnot2s */ - case 0x06b: /* VIS I fnot1s */ - case 0x075: /* VIS I fsrc1s */ - case 0x079: /* VIS I fsrc2s */ - case 0x066: /* VIS I fnot2 */ - case 0x06a: /* VIS I fnot1 */ - case 0x074: /* VIS I fsrc1 */ - case 0x078: /* VIS I fsrc2 */ - case 0x051: /* VIS I fpadd16s */ - case 0x053: /* VIS I fpadd32s */ - case 0x055: /* VIS I fpsub16s */ - case 0x057: /* VIS I fpsub32s */ - case 0x063: /* VIS I fnors */ - case 0x065: /* VIS I fandnot2s */ - case 0x069: /* VIS I fandnot1s */ - case 0x06d: /* VIS I fxors */ - case 0x06f: /* VIS I fnands */ - case 0x071: /* VIS I fands */ - case 0x073: /* VIS I fxnors */ - case 0x077: /* VIS I fornot2s */ - case 0x07b: /* VIS I fornot1s */ - case 0x07d: /* VIS I fors */ - case 0x050: /* VIS I fpadd16 */ - case 0x052: /* VIS I fpadd32 */ - case 0x054: /* VIS I fpsub16 */ - case 0x056: /* VIS I fpsub32 */ - case 0x062: /* VIS I fnor */ - case 0x064: /* VIS I fandnot2 */ - case 0x068: /* VIS I fandnot1 */ - case 0x06c: /* VIS I fxor */ - case 0x06e: /* VIS I fnand */ - case 0x070: /* VIS I fand */ - case 0x072: /* VIS I fxnor */ - case 0x076: /* VIS I fornot2 */ - case 0x07a: /* VIS I fornot1 */ - case 0x07c: /* VIS I for */ - case 0x031: /* VIS I fmul8x16 */ - case 0x033: /* VIS I fmul8x16au */ - case 0x035: /* VIS I fmul8x16al */ - case 0x036: /* VIS I fmul8sux16 */ - case 0x037: /* VIS I fmul8ulx16 */ - case 0x038: /* VIS I fmuld8sux16 */ - case 0x039: /* VIS I fmuld8ulx16 */ - case 0x04b: /* VIS I fpmerge */ - case 0x04d: /* VIS I fexpand */ - case 0x03e: /* VIS I pdist */ - case 0x03a: /* VIS I fpack32 */ - case 0x048: /* VIS I faligndata */ - case 0x04c: /* VIS II bshuffle */ - case 0x020: /* VIS I fcmple16 */ - case 0x022: /* VIS I fcmpne16 */ - case 0x024: /* VIS I fcmple32 */ - case 0x026: /* VIS I fcmpne32 */ - case 0x028: /* VIS I fcmpgt16 */ - case 0x02a: /* VIS I fcmpeq16 */ - case 0x02c: /* VIS I fcmpgt32 */ - case 0x02e: /* VIS I fcmpeq32 */ - case 0x03b: /* VIS I fpack16 */ - case 0x03d: /* VIS I fpackfix */ - case 0x060: /* VIS I fzero */ - case 0x061: /* VIS I fzeros */ - case 0x07e: /* VIS I fone */ - case 0x07f: /* VIS I fones */ - g_assert_not_reached(); /* in decodetree */ - case 0x080: /* VIS I shutdown */ - case 0x081: /* VIS II siam */ - // XXX - goto illegal_insn; - default: - goto illegal_insn; - } -#endif - } else { - goto illegal_insn; /* in decodetree */ - } - } - break; - case 3: /* load/store instructions */ - goto illegal_insn; /* in decodetree */ - } - advance_pc(dc); -#ifdef TARGET_SPARC64 - jmp_insn: -#endif - return; - illegal_insn: - gen_exception(dc, TT_ILL_INSN); - return; -} - static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -5524,7 +5381,7 @@ static void sparc_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cs) dc->base.pc_next +=3D 4; =20 if (!decode(dc, insn)) { - disas_sparc_legacy(dc, insn); + gen_exception(dc, TT_ILL_INSN); } =20 if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { --=20 2.34.1