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([191.255.2.33]) by smtp.gmail.com with ESMTPSA id w14-20020a170902e88e00b001c736746d33sm9738654plg.217.2023.10.25.16.45.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 16:45:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698277525; x=1698882325; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m+d/NJr7Lp8P9GIwbRNrTXnxAHvwrd1uro0GkYn/6g4=; b=dUMujSypOEHjv7hgV74RM/oWPfVELwrzl7RZ+aMf+dz8xSCiPnwqUIN82WB9uyrI2p GasMkrI7cPpkW4xL3AuPZZFt8WWaynyD1WBXchToTu1yI7pSbZCTDj7CDU1pKMKVafvA AmWbPpGFK/5k4VAcdMksQeXFe65MdgHaXgzGfM729g+HwJMMDSEdChp+nO/4OX5sPrDr UzsaYDWGSkYv8azH3pUjlac7RkXprlAURL5oe68hD1DxGDWKSBHJgBmp8lFMaNfFQQJv TvH/CDHSmPyd7bf4hifXoem3W6UozLkG0z4DiOofx1kNm5z2DT52mBM0JC+iIMUP8yHA EG+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698277525; x=1698882325; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m+d/NJr7Lp8P9GIwbRNrTXnxAHvwrd1uro0GkYn/6g4=; b=b9/lxw1who2n/z9qjL4mNO3x7CMpHXSs5hxguLGElVtZMYmRi5TCdo5uVmBg484CqQ J0JLo9wKpJ7zaH909CE+YfkaTQ9P7TM/Am7RFjyUPCPq8OGMhmvE4nBOUgsDj6VYQQQW l/oCZJ4MoZoA3dbVhQ8CMNqLKzcjiRKsz6++5WImA4ALtGPNN6IhvU4KQj8ITTvK5upB Wo8ZLuk5P4ZCqK1zsddXByFBQXFQdrpLx+Xf0ugUQ5X4asdiWPxKgTwjUjiY4xME7vvI Hk+rXpajoVywIkPrv/Jo6JoLsvSh9LuDxkDpTYCexhr/Ap0XBas9h0bxTAu/dId03Hfb BC9A== X-Gm-Message-State: AOJu0YzXwTPKC73YIroRbz/yiB8ZOozuZeWJ2a1In85lVhF8ucDee/hh CD06yO9h6MKgvY47LJVWUQjW9CzqVatQSTsW3VM= X-Google-Smtp-Source: AGHT+IGy1XyshTH23q31kruO8Z7gARSwtZgPgIz3WGUHf5N424Il28Dh4Pevs3HOdL9bN6wJn1yFaQ== X-Received: by 2002:a17:903:1383:b0:1ca:4681:eb37 with SMTP id jx3-20020a170903138300b001ca4681eb37mr13120875plb.14.1698277525426; Wed, 25 Oct 2023 16:45:25 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v5 05/10] target/riscv/tcg: add MISA user options hash Date: Wed, 25 Oct 2023 20:44:54 -0300 Message-ID: <20231025234459.581697-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231025234459.581697-1-dbarboza@ventanamicro.com> References: <20231025234459.581697-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1698277592305100002 Content-Type: text/plain; charset="utf-8" We already track user choice for multi-letter extensions because we needed to honor user choice when enabling/disabling extensions during realize(). We refrained from adding the same mechanism for MISA extensions since we didn't need it. Profile support requires tne need to check for user choice for MISA extensions, so let's add the corresponding hash now. It works like the existing multi-letter hash (multi_ext_user_opts) but tracking MISA bits options in the cpu_set_misa_ext_cfg() callback. Note that we can't re-use the same hash from multi-letter extensions because that hash uses cpu->cfg offsets as keys, while for MISA extensions we're using MISA bits as keys. After adding the user hash in cpu_set_misa_ext_cfg(), setting default values with object_property_set_bool() in add_misa_properties() will end up marking the user choice hash with them. Set the default value manually to avoid it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c1eddf17fd..9a0d85d6e6 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -34,6 +34,7 @@ =20 /* Hash that stores user set extensions */ static GHashTable *multi_ext_user_opts; +static GHashTable *misa_ext_user_opts; =20 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) { @@ -706,6 +707,10 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor = *v, const char *name, return; } =20 + g_hash_table_insert(misa_ext_user_opts, + GUINT_TO_POINTER(misa_bit), + (gpointer)value); + prev_val =3D env->misa_ext & misa_bit; =20 if (value =3D=3D prev_val) { @@ -769,6 +774,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { */ static void riscv_cpu_add_misa_properties(Object *cpu_obj) { + CPURISCVState *env =3D &RISCV_CPU(cpu_obj)->env; bool use_def_vals =3D riscv_cpu_is_generic(cpu_obj); int i; =20 @@ -789,7 +795,13 @@ static void riscv_cpu_add_misa_properties(Object *cpu_= obj) NULL, (void *)misa_cfg); object_property_set_description(cpu_obj, name, desc); if (use_def_vals) { - object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NUL= L); + if (misa_cfg->enabled) { + env->misa_ext |=3D bit; + env->misa_ext_mask |=3D bit; + } else { + env->misa_ext &=3D ~bit; + env->misa_ext_mask &=3D ~bit; + } } } } @@ -1021,6 +1033,7 @@ static void tcg_cpu_instance_init(CPUState *cs) RISCVCPU *cpu =3D RISCV_CPU(cs); Object *obj =3D OBJECT(cpu); =20 + misa_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); riscv_cpu_add_user_properties(obj); =20 --=20 2.41.0