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([191.255.2.33]) by smtp.gmail.com with ESMTPSA id w14-20020a170902e88e00b001c736746d33sm9738654plg.217.2023.10.25.16.45.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 16:45:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698277516; x=1698882316; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nfE3EuwF54FcNHaKLTT47crDoYBFUQZU4Scq8wPsh5A=; b=ZZ/gmcnsclPwE9CQJ4gNgWLWJuDABqCN1ONAvc01uhzOSyfapQlSwV0i1kav61dZso r3fSuOQuilG6H+Ct3Vs84y1GI0K+gR+qzdyeEKNBPUuzxkjm/LRSscDEc7KPJ/Do7ESf nPghuDEKZ7gMCc5DyUD32GQxO4aK/AGYF58sFcnkELROm2AM3raVCFDQBg8yJifJUYwN 6mkVYQpnNv9xeonrPFP9k76DeMrm3QR5DT4DuWN3iiJaOp9CahL5RYkurNlgMIco+qFb BaLowKZ+QLhBTrG4S3YmXrh3m2nPGWZwEoAc/8QUPB571glYuWOuArtZ1Oab1s9yKq9w OEUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698277516; x=1698882316; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nfE3EuwF54FcNHaKLTT47crDoYBFUQZU4Scq8wPsh5A=; b=W9ZXUC4BBIEUooB6y2J6af5nBYKBVBf0WK5L5Hl1AjEi+AFQ/AaVpwvDmebOzOhh02 2LhR+uJDd0QZuPVJRkyzfW9sa7g1ZyFkE/2C/YZULJ6rMQ7dPd7e5rXBNq86+kWMByqq TrLNaWoqbRJD/b1EYgDsa5/J2fdwi6rqnAFPENRrCo31WUmGrowjiABztDVHloTsbxLg 71BIFlGXkAF/zULAMKgLGff8Paphz1g6CTfmKSEKz6zXqMyeX6WJmcgCK0ROqrem90Fw 9CGWu0xrYtPiDUA2E/YJVnVE8WcfMO23F+h0+FWA6sp3fUPViUswkBaKx3OoyXQSxW3F eHTw== X-Gm-Message-State: AOJu0YzGAJ+Ix5dYiAl/+MQ5OZuJrRU7J1UCEZR/gLAefmeVP3weuOV7 RqRPQrlCuWI+tbCvZ9anH7zxWn7QJf9S+6c4ouE= X-Google-Smtp-Source: AGHT+IFFEsE26YqIZER6gNxsqIkgV7ex6rx1f+68hV7XAonbNXTzCus6AgPdWKwfUIS/OiGWeWJ6+A== X-Received: by 2002:a17:903:887:b0:1ca:57ff:9bfa with SMTP id kt7-20020a170903088700b001ca57ff9bfamr15170399plb.24.1698277516333; Wed, 25 Oct 2023 16:45:16 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v5 02/10] target/riscv: add rva22u64 profile definition Date: Wed, 25 Oct 2023 20:44:51 -0300 Message-ID: <20231025234459.581697-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231025234459.581697-1-dbarboza@ventanamicro.com> References: <20231025234459.581697-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1698277624375100001 Content-Type: text/plain; charset="utf-8" The rva22U64 profile, described in: https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profi= les Contains a set of CPU extensions aimed for 64-bit userspace applications. Enabling this set to be enabled via a single user flag makes it convenient to enable a predictable set of features for the CPU, giving users more predicability when running/testing their workloads. QEMU implements all possible extensions of this profile. The exception is Zicbop (Cache-Block Prefetch Operations) that is not available since QEMU RISC-V does not implement a cache model. For this same reason all the so called 'synthetic extensions' described in the profile that are cache related are ignored (Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa, Zicclsm). An abstraction called RISCVCPUProfile is created to store the profile. 'ext_offsets' contains mandatory extensions that QEMU supports. Same thing with the 'misa_ext' mask. Optional extensions must be enabled manually in the command line if desired. The design here is to use the common target/riscv/cpu.c file to store the profile declaration and export it to the accelerator files. Each accelerator is then responsible to expose it (or not) to users and how to enable the extensions. Next patches will implement the profile for TCG and KVM. Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++ target/riscv/cpu.h | 12 ++++++++++++ 2 files changed, 43 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5095f093ba..d6ba0dff34 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1437,6 +1437,37 @@ Property riscv_cpu_options[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +/* + * RVA22U64 defines some 'named features' or 'synthetic extensions' + * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa + * and Zicclsm. We do not implement caching in QEMU so we'll consider + * all these named features as always enabled. + * + * There's no riscv,isa update for them (and for zic64b) at this + * moment. + */ +static RISCVCPUProfile RVA22U64 =3D { + .name =3D "rva22u64", + .misa_ext =3D RVI | RVM | RVA | RVF | RVD | RVC, + .ext_offsets =3D { + CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause), + CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb), + CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin), + CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr), + CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom), + CPU_CFG_OFFSET(ext_zicboz), + + /* mandatory named features for this profile */ + CPU_CFG_OFFSET(zic64b), + + RISCV_PROFILE_EXT_LIST_END + } +}; + +RISCVCPUProfile *riscv_profiles[] =3D { + &RVA22U64, NULL, +}; + static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ee9abe61d6..d3d82c5a7a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -68,6 +68,18 @@ const char *riscv_get_misa_ext_description(uint32_t bit); =20 #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) =20 +typedef struct riscv_cpu_profile { + const char *name; + uint32_t misa_ext; + bool enabled; + bool user_set; + const int32_t ext_offsets[]; +} RISCVCPUProfile; + +#define RISCV_PROFILE_EXT_LIST_END -1 + +extern RISCVCPUProfile *riscv_profiles[]; + /* Privileged specification version */ enum { PRIV_VERSION_1_10_0 =3D 0, --=20 2.41.0