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([191.255.2.33]) by smtp.gmail.com with ESMTPSA id w14-20020a170902e88e00b001c736746d33sm9738654plg.217.2023.10.25.16.45.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 16:45:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698277540; x=1698882340; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N66mwe55qIwqiyZlpStxI0DDZnJyiqHeIii+NKoAya4=; b=cK/b4PSLZUq83S7vtTEsPDxxF2masnsHYPp3lFOfyVDCEe6Fy7LnwXwP7yzcIdsGo0 sI1pB8kAAqkZHt4/4Q4lkiuJxwfWZeEjmMD//9b9foUIoSvtGRJE+8M7/O8gY0peJxb9 DLqtdeyEp0d1sufRjZQJz6nHDJAHPEXCbKxDhcY/pDoOKaE4QWUmQWmPI+FCOq3/TCpf gR6JYgLxhDVelrOTH4BOfUfHahjxoB/Zk2Cdef8X+zZgcs0FUTyQJ6YTvYygm56H4FCQ Qp474iM54fukgM1xnuC3eXik8aJ4c04GG0x70Y8llBRSZZtrdtVRMNwG98GzrwGAYdsj M/XA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698277540; x=1698882340; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N66mwe55qIwqiyZlpStxI0DDZnJyiqHeIii+NKoAya4=; b=DsHG2boOK2iIDSe5igD+RhjvKh2gJwaUS04rzt4Ksan+5IeNvM6HajrZ0gWxMSy8++ RbDdPp5XKjBRxZqhUG3G5JH98cT72jJI4ov14sulmhWuRxtNxAmHvUde4g2vE8Y5N8OG NVFaAUGXEEK1W/NmWjyTDwGCdFHTDkEk/kE+L+BbVDwWGo6q9ggDiOvAUbFnZHT73cgW 0aK9ZeDEe1HULnJTPjAR6DlgP+NL6zmNngeTZoSmdpgu3UVgknOiZq4qkFmVvfhZM86F 4c6nXnI3FtgJayR+i99kyhPlXt8gVmfCBzOBtHbk9Nxro3XRGmQYnjqytnkOMQk2xVqX nPUQ== X-Gm-Message-State: AOJu0YwkJX3ZU+Ks2EQ/d/fM2fvCHFe3cxL+5tBLuUJ8J1LhwQob5e0P keHhdTkb3j5QcQ+3rSLL3mhd9ve1PpqmyRQDCL8= X-Google-Smtp-Source: AGHT+IHDwfHwMq5HfxnwFpBpVDap1BUY3VuXH9Ojj056ztPsiE7ywAa75yKw26XEbagEBCzRJ7TgIQ== X-Received: by 2002:a17:902:c411:b0:1cb:e412:c3fd with SMTP id k17-20020a170902c41100b001cbe412c3fdmr8475460plk.63.1698277540213; Wed, 25 Oct 2023 16:45:40 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v5 10/10] target/riscv/tcg: warn if profile exts are disabled Date: Wed, 25 Oct 2023 20:44:59 -0300 Message-ID: <20231025234459.581697-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231025234459.581697-1-dbarboza@ventanamicro.com> References: <20231025234459.581697-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1698277642418100011 Content-Type: text/plain; charset="utf-8" Enabling a profile and then disabling some of its mandatory extensions is a valid use. It can be useful for debugging and testing. But the common expected use of enabling a profile is to enable all its mandatory extensions. Add an user warning when mandatory extensions from an enabled profile are disabled in the command line, like we're already doing with RVG. After this patch, this will throw warnings: -cpu rv64,rva22u64=3Dtrue,zihintpause=3Dfalse,zicbom=3Dfalse,zicboz=3Dfalse qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension = zihintpause qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension = zicbom qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension = zicboz Note that the following will NOT throw warnings because the profile is being enabled last, hence all its mandatory extensions will be enabled: -cpu rv64,zihintpause=3Dfalse,zicbom=3Dfalse,zicboz=3Dfalse,rva22u64=3Dtrue Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 57 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8d24cb2e82..ac21cd5ad4 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -147,6 +147,22 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_of= fset) g_assert_not_reached(); } =20 +static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) +{ + const RISCVIsaExtData *edata; + + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (edata->ext_enable_offset !=3D ext_offset) { + continue; + } + + return edata->name; + } + + g_assert_not_reached(); +} + + static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, bool value) { @@ -644,11 +660,52 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) riscv_cpu_disable_priv_spec_isa_exts(cpu); } =20 +static void riscv_cpu_validate_profile(RISCVCPU *cpu, + RISCVCPUProfile *profile) +{ + const char *warn_msg =3D "Profile %s mandates disabled extension %s"; + int i; + + for (i =3D 0; misa_bits[i] !=3D 0; i++) { + uint32_t bit =3D misa_bits[i]; + + if (!(profile->misa_ext & bit)) { + continue; + } + + if (!riscv_has_ext(&cpu->env, bit)) { + warn_report(warn_msg, profile->name, riscv_get_misa_ext_name(b= it)); + } + } + + for (i =3D 0; profile->ext_offsets[i] !=3D RISCV_PROFILE_EXT_LIST_END;= i++) { + int ext_offset =3D profile->ext_offsets[i]; + + if (!isa_ext_is_enabled(cpu, ext_offset)) { + warn_report(warn_msg, profile->name, + cpu_cfg_ext_get_name(ext_offset)); + } + } +} + +static void riscv_cpu_validate_profiles(RISCVCPU *cpu) +{ + for (int i =3D 0; riscv_profiles[i] !=3D NULL; i++) { + RISCVCPUProfile *profile =3D riscv_profiles[i]; + + if (profile->user_set && profile->enabled) { + riscv_cpu_validate_profile(cpu, profile); + } + } +} + void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; =20 + riscv_cpu_validate_profiles(cpu); + riscv_cpu_validate_priv_spec(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.41.0