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[125.228.20.175]) by smtp.gmail.com with ESMTPSA id w14-20020a63160e000000b005b8ebef9fa0sm2677807pgl.83.2023.10.25.08.14.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 08:14:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1698246881; x=1698851681; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=npJ2K69OOSsKJtanlFl7eXChj2RfZqQfMPOCGuCNX+0=; b=HcIN8buqXPyvo7Lhc5+Ao1VjxdWA1j4tqVD1vcGDBXok2OU5hWb77nOf325QkZSGVE 9ZkIh3AeaGJBKr4xWWGc7hO4j9oMHPkXQwfAPGLk4qifj0/M0wDLQJzPec+8z2H0jYIJ QIMR2BoKmEC6is55C92s9yE3iXhnD49w2PRDBi1fCBNWAIHBgmNIJW8ACaFV4Sc080h/ OkKbsbk/k7uV0DgzSvkJE7fG6Ts1c4rlPPxid57XmJaCsG8G98f2EcG0QbPGBfGpXQoL WIhbildAi9z/+KcZU2JT14txeYoJXPixX93xBSXOYx/5/N8ZHrwLvXm8HbzODsvOn4QW 72Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698246881; x=1698851681; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=npJ2K69OOSsKJtanlFl7eXChj2RfZqQfMPOCGuCNX+0=; b=vQlanZljIhQrUp6aZEg1BoZYmmkBvDWe8R/2k550Lv3ISVkMRrRn9Zo/tZiIAm/SzY ML8F0E/JjTuUe/aXDB56qVB5TIJEhLDaNJ9h/ypz430pyHCAsy+taRCLSc09vllMX62m bUrbzz7+D3cixs3ki2Z4N1wMKVIcpfxU2qb8OaoaSmQIKOLxIGJYsLp/4ehlqjNkw0W+ 3cbxYOPLfwxYLcoZGESWR/4aD3BRPKOfHvTbxpjqTcMUW1ZwdLhpQYbKj7BH3i49TNFw dYaqw9JN6JtG+H6BeaksQvLIBfZN7ZIgKnCSaTVE/xP3ER39FncB2L3KaEEqCnfoRDVp gSTw== X-Gm-Message-State: AOJu0YwUvx8QsAo2eC/kZ6AZ6w3hxKWdDd8hcfbK4T8fm9jD8uKkJX4t nl2MX2FGU59Ci8DYNJ7KF7KNBXKgu95SdrLwdNBMJEgeLWNCRXAYw1XEeRJF5qPDxIXX3Lg3HeE 1ETL1pN5ehOr+dz9uBc+Dy1yXA+QlcuVVfOOYw3rgiZ9e1Uw4u9KuVWwTDmMBAQ38A/YJGRl5st hO X-Google-Smtp-Source: AGHT+IGxeT1XYysuWhzP+XGjVchb7sQ76Y9lFVuO/ahOs9u4ssberv2hYxI/vPlJz08p3CKKT1+D9A== X-Received: by 2002:a05:6a21:788d:b0:13a:6bca:7a84 with SMTP id bf13-20020a056a21788d00b0013a6bca7a84mr6707340pzc.44.1698246881497; Wed, 25 Oct 2023 08:14:41 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones Subject: [PATCH 08/14] target/riscv: Add cfg properties for Zvks[c|g] extensions Date: Wed, 25 Oct 2023 23:13:32 +0800 Message-Id: <20231025151341.725477-9-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025151341.725477-1-max.chou@sifive.com> References: <20231025151341.725477-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=max.chou@sifive.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1698247079148100001 Content-Type: text/plain; charset="utf-8" Vector crypto spec defines the ShangMi algorithm suite related extensions (Zvks, Zvksc, Zvksg) combined by several vector crypto extensions. Signed-off-by: Max Chou --- target/riscv/cpu_cfg.h | 3 +++ target/riscv/tcg/tcg-cpu.c | 17 +++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index fd07aa96a27..7b0ca657a6a 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -99,6 +99,9 @@ struct RISCVCPUConfig { bool ext_zvkn; bool ext_zvknc; bool ext_zvkng; + bool ext_zvks; + bool ext_zvksc; + bool ext_zvksg; bool ext_zmmul; bool ext_zvfbfmin; bool ext_zvfbfwma; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e460701a13c..f9023ca75c7 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -519,6 +519,23 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true); } =20 + if (cpu->cfg.ext_zvksc) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); + } + + if (cpu->cfg.ext_zvksg) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true); + } + + if (cpu->cfg.ext_zvks) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksed), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksh), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true); + } + if (cpu->cfg.ext_zvkt) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); --=20 2.34.1