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[125.228.20.175]) by smtp.gmail.com with ESMTPSA id w14-20020a63160e000000b005b8ebef9fa0sm2677807pgl.83.2023.10.25.08.14.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 08:14:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1698246897; x=1698851697; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uhhXgiA9ijhkCgdvzjre6qvwHLpR2uYfFwrcGxeZDYQ=; b=jBmRWAaGObUfmYDv2nPYBbK/f4OtSnKNApg1F2VPh7imCMjxE9qf42WAnQSfOqkpE+ mheFsqlZ2F7yZRUWDqDHSKlCdRa3f7HAHd29AVcFCYufaEpCaeuy085+gQudrqIwraAG ZAOtwjMhGyPOHA7P6oQQBhhngNRxUef7rfLlfZvh8PkujOEnGPhAnsKWeqAZRp81/xit Mk7yP4ZacBY25eWeQSrmb35JSlDGGmDd+c3gejGFI/KpMinCBjvZy1p+vfHXkAClN4FP ZWZgP5L4TWx55kJqvJU0AL5lFKHEY8XpnLIlMZlqMhLVWWUTUMaWGpSsZIwHYwARV00/ ut/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698246897; x=1698851697; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uhhXgiA9ijhkCgdvzjre6qvwHLpR2uYfFwrcGxeZDYQ=; b=i0DfqTz1uH9JelYKKQTJeELVA7MwTNZHTfeJplZnRrDxHUvd0YLUoByrBeQgj3IHEn BlTV6McrnEkJ/+pMzMo8S8b9TOJRWxP8FDxaekGuInyxRxO71wWMZMw50QyHl9e49nrY e1jxVlIqcD3ZnVel1r9ilDVJj9Bl8eFJ8wXmVICGigHdEbp7BKWKDxgKIVqSZdBC53eX +nxK4crlaBJotEEd72F/bkiuOh0w+WgY1N8YNeRaFG+MlI6MzHJo3XM9dGhkqaoj/k7n BLKgu6BMe+3UqydwFnJZqXcPUXfZpfC0bfZBpnAc8xd0zP5TurDLpDyTlFn+wC5nD93U +Z5A== X-Gm-Message-State: AOJu0Yy0IC/yRKPcaTOU2YnW6kmcn9cIhm0My7yhYYz6rGahLm+T1cd3 aRWQTVrhab37KQgdNXQWOssSfTan9D5K/K9AtQtKewSVMHYcTbPJZmt2GjJjKNEllVTs/0shnHz VcgQ42s49PnNWdGSrd/VbAoxyeqc7TXCVzasLEhcTXdBYj4lfBIl/a8kxyuC7E4FnkkO5AKcxZm Um X-Google-Smtp-Source: AGHT+IHiNV7l5886K5RJyRZEx4y7KbRDZ5rGOL52oOvaLUaI2tL1RGQ9R2mahd0i/u63Orc5IXa8IA== X-Received: by 2002:a05:6a00:2e97:b0:692:a727:1fdd with SMTP id fd23-20020a056a002e9700b00692a7271fddmr18972961pfb.4.1698246896595; Wed, 25 Oct 2023 08:14:56 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Palmer Dabbelt , Alistair Francis Subject: [PATCH 12/14] disas/riscv: Add rv_codec_vror_vi for vror.vi Date: Wed, 25 Oct 2023 23:13:36 +0800 Message-Id: <20231025151341.725477-13-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025151341.725477-1-max.chou@sifive.com> References: <20231025151341.725477-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=max.chou@sifive.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1698247085211100003 Content-Type: text/plain; charset="utf-8" Add rv_codec_vror_vi for the vector crypto instruction - vror.vi. The rotate amount of vror.vi is defined by combining seperated bits. Signed-off-by: Max Chou --- disas/riscv.c | 11 +++++++++++ disas/riscv.h | 1 + 2 files changed, 12 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index 8e89e1d1157..6d60033abab 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -4011,6 +4011,12 @@ static uint32_t operand_vzimm10(rv_inst inst) return (inst << 34) >> 54; } =20 +static uint32_t operand_vzimm6(rv_inst inst) +{ + return ((inst << 37) >> 63) << 5 | + ((inst << 44) >> 59); +} + static uint32_t operand_bs(rv_inst inst) { return (inst << 32) >> 62; @@ -4393,6 +4399,11 @@ static void decode_inst_operands(rv_decode *dec, rv_= isa isa) dec->imm =3D operand_vimm(inst); dec->vm =3D operand_vm(inst); break; + case rv_codec_vror_vi: + dec->rd =3D operand_rd(inst); + dec->rs2 =3D operand_rs2(inst); + dec->imm =3D operand_vzimm6(inst); + break; case rv_codec_vsetvli: dec->rd =3D operand_rd(inst); dec->rs1 =3D operand_rs1(inst); diff --git a/disas/riscv.h b/disas/riscv.h index b242d73b25e..19e5ed2ce63 100644 --- a/disas/riscv.h +++ b/disas/riscv.h @@ -152,6 +152,7 @@ typedef enum { rv_codec_v_i, rv_codec_vsetvli, rv_codec_vsetivli, + rv_codec_vror_vi, rv_codec_zcb_ext, rv_codec_zcb_mul, rv_codec_zcb_lb, --=20 2.34.1