From nobody Thu Jan 1 07:24:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=ilande.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698187370627236.62354907135864; Tue, 24 Oct 2023 15:42:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvQ5X-0002o9-Qq; Tue, 24 Oct 2023 18:41:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvQ5W-0002m6-1o; Tue, 24 Oct 2023 18:41:26 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvQ5L-0002hV-Jd; Tue, 24 Oct 2023 18:41:20 -0400 Received: from [2a00:23c4:8bb0:5400:d6f1:6571:2310:5e57] (helo=localhost.localdomain) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1qvQ59-0002va-DI; Tue, 24 Oct 2023 23:41:07 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:To:From:Sender:Reply-To:Cc: Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=KdeWY4HsoUR3dQy++Ntyu/QQaQbpZVrSZMyTuyCpghY=; b=lpOGVzdrSLiIXCCw0B5jCFgglc dT8fbA1H6nd10e25Wi1MkqJ/ctZH8a19LzXpY5BRgEtIPB0a5zV0mFWZQgpJOe7Qk5dVPiYNb+Q2j ReiEUhh8o7a0UZyYdIGBWT5WGCALpMw7AfShDhia3Nb5EYRLIZibA363Mv+f/BWF2d0G2Exfsfcn2 sJaMLL9lBrMmx3CcG5eQmL/l2eiDyppIAXQDPOywzJyTMNLcA8Q+zzMJQA0MELuRMsKoIE59FfrFs oGq8gJD1ygbyLqUlY5nUE44OUm5ACZQjcL62refLPiJMVvBZUSRaZUxgTQE6o2ba8v+8RpMHfuNhI xo3s5Ul6/3AonqR29MYNgVv2JsX3jTmtipmU/4500G9gJItTZm+YnuWagWIzcQpjo2CBki289a8kT u0DPJtinXTbm2tIEd/KJRqaELIhg1mYyltatMRx02H4biF5SU+OTibGIYKJgAL+bKsbjt3jUXe7bA mM0ijoRBzhHDH6yYomPYxQuhKn8bG2+QNDJIEFx3nBbKlr7sPXBo2iZTwzcz2Qlc+F8X0zpEEFueV /q/0uSRpCVZfBUyRIb/4ku0hchiHcZV318+WPdhAS2/Xd+3cIgIONhZN45CwJbHVnqE3ckEcTf1xc tzO8Hcjt/PIMXFeVToV3i+sOkSSvdX2cx9y2+870o=; From: Mark Cave-Ayland To: jsnow@redhat.com, qemu-block@nongnu.org, qemu-devel@nongnu.org, balaton@eik.bme.hu, philmd@linaro.org, shentey@gmail.com Date: Tue, 24 Oct 2023 23:40:54 +0100 Message-Id: <20231024224056.842607-2-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231024224056.842607-1-mark.cave-ayland@ilande.co.uk> References: <20231024224056.842607-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8bb0:5400:d6f1:6571:2310:5e57 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 1/3] ide/pci.c: introduce pci_ide_update_mode() function X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1698187371159100001 Content-Type: text/plain; charset="utf-8" This function reads the value of the PCI_CLASS_PROG register for PCI IDE controllers and configures the PCI BARs and/or IDE ioports accordingly. In the case where we switch to legacy mode, the PCI BARs are set to return = zero (as suggested in the "PCI IDE Controller" specification), the legacy IDE io= ports are enabled, and the PCI interrupt pin cleared to indicate legacy IRQ routi= ng. Conversely when we switch to native mode, the legacy IDE ioports are disabl= ed and the PCI interrupt pin set to indicate native IRQ routing. The contents = of the PCI BARs are unspecified, but this is not an issue since if a PCI IDE controller has been switched to native mode then its BARs will need to be programmed. Signed-off-by: Mark Cave-Ayland Tested-by: BALATON Zoltan Tested-by: Bernhard Beschow Reviewed-by: Bernhard Beschow --- hw/ide/pci.c | 90 ++++++++++++++++++++++++++++++++++++++++++++ include/hw/ide/pci.h | 1 + 2 files changed, 91 insertions(+) diff --git a/hw/ide/pci.c b/hw/ide/pci.c index a25b352537..5be643b460 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -104,6 +104,96 @@ const MemoryRegionOps pci_ide_data_le_ops =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 +static const MemoryRegionPortio ide_portio_list[] =3D { + { 0, 8, 1, .read =3D ide_ioport_read, .write =3D ide_ioport_write }, + { 0, 1, 2, .read =3D ide_data_readw, .write =3D ide_data_writew }, + { 0, 1, 4, .read =3D ide_data_readl, .write =3D ide_data_writel }, + PORTIO_END_OF_LIST(), +}; + +static const MemoryRegionPortio ide_portio2_list[] =3D { + { 0, 1, 1, .read =3D ide_status_read, .write =3D ide_ctrl_write }, + PORTIO_END_OF_LIST(), +}; + +void pci_ide_update_mode(PCIIDEState *s) +{ + PCIDevice *d =3D PCI_DEVICE(s); + uint8_t mode =3D d->config[PCI_CLASS_PROG]; + + switch (mode & 0xf) { + case 0xa: + /* Both channels legacy mode */ + + /* Zero BARs */ + pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x0); + pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x0); + pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x0); + pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x0); + + /* Clear interrupt pin */ + pci_config_set_interrupt_pin(d->config, 0); + + /* Add legacy IDE ports */ + if (!s->bus[0].portio_list.owner) { + portio_list_init(&s->bus[0].portio_list, OBJECT(d), + ide_portio_list, &s->bus[0], "ide"); + portio_list_add(&s->bus[0].portio_list, + pci_address_space_io(d), 0x1f0); + } + + if (!s->bus[0].portio2_list.owner) { + portio_list_init(&s->bus[0].portio2_list, OBJECT(d), + ide_portio2_list, &s->bus[0], "ide"); + portio_list_add(&s->bus[0].portio2_list, + pci_address_space_io(d), 0x3f6); + } + + if (!s->bus[1].portio_list.owner) { + portio_list_init(&s->bus[1].portio_list, OBJECT(d), + ide_portio_list, &s->bus[1], "ide"); + portio_list_add(&s->bus[1].portio_list, + pci_address_space_io(d), 0x170); + } + + if (!s->bus[1].portio2_list.owner) { + portio_list_init(&s->bus[1].portio2_list, OBJECT(d), + ide_portio2_list, &s->bus[1], "ide"); + portio_list_add(&s->bus[1].portio2_list, + pci_address_space_io(d), 0x376); + } + break; + + case 0xf: + /* Both channels native mode */ + + /* Set interrupt pin */ + pci_config_set_interrupt_pin(d->config, 1); + + /* Remove legacy IDE ports */ + if (s->bus[0].portio_list.owner) { + portio_list_del(&s->bus[0].portio_list); + portio_list_destroy(&s->bus[0].portio_list); + } + + if (s->bus[0].portio2_list.owner) { + portio_list_del(&s->bus[0].portio2_list); + portio_list_destroy(&s->bus[0].portio2_list); + } + + if (s->bus[1].portio_list.owner) { + portio_list_del(&s->bus[1].portio_list); + portio_list_destroy(&s->bus[1].portio_list); + } + + if (s->bus[1].portio2_list.owner) { + portio_list_del(&s->bus[1].portio2_list); + portio_list_destroy(&s->bus[1].portio2_list); + } + break; + } +} + static IDEState *bmdma_active_if(BMDMAState *bmdma) { assert(bmdma->bus->retry_unit !=3D (uint8_t)-1); diff --git a/include/hw/ide/pci.h b/include/hw/ide/pci.h index 1ff469de87..a814a0a7c3 100644 --- a/include/hw/ide/pci.h +++ b/include/hw/ide/pci.h @@ -61,6 +61,7 @@ void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val); void bmdma_status_writeb(BMDMAState *bm, uint32_t val); extern MemoryRegionOps bmdma_addr_ioport_ops; void pci_ide_create_devs(PCIDevice *dev); +void pci_ide_update_mode(PCIIDEState *s); =20 extern const VMStateDescription vmstate_ide_pci; extern const MemoryRegionOps pci_ide_cmd_le_ops; --=20 2.39.2 From nobody Thu Jan 1 07:24:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=ilande.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698187378206208.31880900501017; Tue, 24 Oct 2023 15:42:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvQ5a-0002pW-3n; Tue, 24 Oct 2023 18:41:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvQ5X-0002o1-BZ; Tue, 24 Oct 2023 18:41:27 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvQ5R-0002hi-8I; Tue, 24 Oct 2023 18:41:26 -0400 Received: from [2a00:23c4:8bb0:5400:d6f1:6571:2310:5e57] (helo=localhost.localdomain) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1qvQ5D-0002va-6D; Tue, 24 Oct 2023 23:41:11 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:To:From:Sender:Reply-To:Cc: Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=0iSNVIgoDqBbdYoyl+njrWXgG834i3sZNzE/xHFaVOs=; b=tW583NBWRB85+uxs0sYqszjnQn GhyvGPUoI7pFNR5g2cslx0ppt3q4E2+IiRHA/s+ps8c0+py+LbCClBacPSDH4fXHmXp9ac1yOPbuL VmbBeuuWw4lreYtBAfFAQ6PyXerS79BtaXSQegs/eKvaybZrE1VxSMARJNZnmQOhYhwumomrfbNMF gntbpSSexb2EUIVIYKjFKP9pwkNU8nxQHJHWt9NxkqtKOfrd6zqN1kImJwKd+zEzRlncntNafbtu5 uVWV+3kU2UmpvoDQGPPHNpXS9hzMOD0GUnyq7J5vyZ0SgR6oSZOGIyy1ENn9DuDPbsG83Qv+1QEvj /o0icD8fNwBdoARRRwG9D2kl4S1/0LVleVGLAKcZr5+TN9To3T2taTnBLm+Ydu76Rg+mvYQhOaTow ojly7XmXVP7CT4wU4TBWbFfH9TBgbqu7uVSFnN4u1VhacYTkznWy/wYkEIs0n6vpXblhmuwMzRhXP SPWBj21HN9ouRrgZ0Gu5J2g8hcvedqf7LkHAtx3NjpgZx2IdW25IQY/Xigr4qrEeRmwnNV5klQ1ON jCPLfNslo8SpqU3EZVxVYsJdoefwthOerJdzJ86wn2HSQY/4jpeiZHlG/xJzAgSSHCxhJOftaGjX0 R/lBmEPo+fzjIafn4otklhsf44g9eBnPpBOFd215k=; From: Mark Cave-Ayland To: jsnow@redhat.com, qemu-block@nongnu.org, qemu-devel@nongnu.org, balaton@eik.bme.hu, philmd@linaro.org, shentey@gmail.com Date: Tue, 24 Oct 2023 23:40:55 +0100 Message-Id: <20231024224056.842607-3-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231024224056.842607-1-mark.cave-ayland@ilande.co.uk> References: <20231024224056.842607-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8bb0:5400:d6f1:6571:2310:5e57 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 2/3] ide/via: don't attempt to set default BAR addresses X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1698187379220100005 Content-Type: text/plain; charset="utf-8" The via-ide device currently attempts to set the default BAR addresses to t= he values shown in the datasheet, but this doesn't work for 2 reasons: firstly BARS 1-4 do not set the bottom 2 bits to PCI_BASE_ADDRESS_SPACE_IO, and secondly the initial PCI bus reset clears the values of all PCI device BARs after the device itself has been reset. Remove the setting of the default BAR addresses from via_ide_reset() to ens= ure there is no doubt that these values are never exposed to the guest. Signed-off-by: Mark Cave-Ayland Tested-by: BALATON Zoltan Tested-by: Bernhard Beschow Reviewed-by: Bernhard Beschow Suggested-by: BALATON Zoltan --- hw/ide/via.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/hw/ide/via.c b/hw/ide/via.c index fff23803a6..87b134083a 100644 --- a/hw/ide/via.c +++ b/hw/ide/via.c @@ -132,11 +132,6 @@ static void via_ide_reset(DeviceState *dev) pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); =20 - pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0); - pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4); - pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170); - pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374); - pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-= 23h */ pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e); =20 /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/ --=20 2.39.2 From nobody Thu Jan 1 07:24:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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From: Mark Cave-Ayland To: jsnow@redhat.com, qemu-block@nongnu.org, qemu-devel@nongnu.org, balaton@eik.bme.hu, philmd@linaro.org, shentey@gmail.com Date: Tue, 24 Oct 2023 23:40:56 +0100 Message-Id: <20231024224056.842607-4-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231024224056.842607-1-mark.cave-ayland@ilande.co.uk> References: <20231024224056.842607-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8bb0:5400:d6f1:6571:2310:5e57 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 3/3] hw/ide/via: implement legacy/native mode switching X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1698187379223100006 Content-Type: text/plain; charset="utf-8" Allow the VIA IDE controller to switch between both legacy and native modes= by calling pci_ide_update_mode() to reconfigure the device whenever PCI_CLASS_= PROG is updated. This patch moves the initial setting of PCI_CLASS_PROG from via_ide_realize= () to via_ide_reset(), and removes the direct setting of PCI_INTERRUPT_PIN during= PCI bus reset since this is now managed by pci_ide_update_mode(). This ensures = that the device configuration is always consistent with respect to the currently selected mode. Signed-off-by: Mark Cave-Ayland Tested-by: BALATON Zoltan Tested-by: Bernhard Beschow Reviewed-by: Bernhard Beschow --- hw/ide/via.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/hw/ide/via.c b/hw/ide/via.c index 87b134083a..0cb65c8a3d 100644 --- a/hw/ide/via.c +++ b/hw/ide/via.c @@ -28,6 +28,7 @@ #include "hw/pci/pci.h" #include "migration/vmstate.h" #include "qemu/module.h" +#include "qemu/range.h" #include "sysemu/dma.h" #include "hw/isa/vt82c686.h" #include "hw/ide/pci.h" @@ -128,11 +129,14 @@ static void via_ide_reset(DeviceState *dev) ide_bus_reset(&d->bus[i]); } =20 + pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy mode */ + pci_ide_update_mode(d); + pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_WAIT= ); pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); =20 - pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e); + pci_set_byte(pci_conf + PCI_INTERRUPT_LINE, 0xe); =20 /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/ pci_set_long(pci_conf + 0x40, 0x0a090600); @@ -154,6 +158,18 @@ static void via_ide_reset(DeviceState *dev) pci_set_long(pci_conf + 0xc0, 0x00020001); } =20 +static void via_ide_cfg_write(PCIDevice *pd, uint32_t addr, + uint32_t val, int len) +{ + PCIIDEState *d =3D PCI_IDE(pd); + + pci_default_write_config(pd, addr, val, len); + + if (range_covers_byte(addr, len, PCI_CLASS_PROG)) { + pci_ide_update_mode(d); + } +} + static void via_ide_realize(PCIDevice *dev, Error **errp) { PCIIDEState *d =3D PCI_IDE(dev); @@ -161,7 +177,6 @@ static void via_ide_realize(PCIDevice *dev, Error **err= p) uint8_t *pci_conf =3D dev->config; int i; =20 - pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy mode */ pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); dev->wmask[PCI_INTERRUPT_LINE] =3D 0; dev->wmask[PCI_CLASS_PROG] =3D 5; @@ -216,6 +231,7 @@ static void via_ide_class_init(ObjectClass *klass, void= *data) /* Reason: only works as function of VIA southbridge */ dc->user_creatable =3D false; =20 + k->config_write =3D via_ide_cfg_write; k->realize =3D via_ide_realize; k->exit =3D via_ide_exitfn; k->vendor_id =3D PCI_VENDOR_ID_VIA; --=20 2.39.2