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Tue, 24 Oct 2023 18:12:07 +0000 (GMT) Received: from smtpav03.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BAB335803F; Tue, 24 Oct 2023 18:12:07 +0000 (GMT) Received: from mamboa4.aus.stglabs.ibm.com (unknown [9.3.84.87]) by smtpav03.dal12v.mail.ibm.com (Postfix) with ESMTP; Tue, 24 Oct 2023 18:12:07 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=8JpJ0Ocupdl2KMUp+UKGwf/vH+tk3p5CuovJ6zeSsFw=; b=HB0k+8mrpXssH0txVWKqlHZ+YJk3xLJwYhdn1Q2TkWetLx0TzT95rrELyE3KgyvDVyFj SzPt1UzwtcRv76merkC7TMeQa4BrD/g2exVOk1LcZ9X17jeU8OHjDSPx5vDuvMdPlRlD bfXZf0vi4NtlBrNXAvi4RzBbrDvQeY9KM39GO49kEDusxkWrhZi2QXK4BeB9Qyav7pZp Z0Fgy1quYQZufiD2ILq+0TUM9e8W7lOFi4K9pFDQZANh2ngZmB6b1TdCV7FAxORoPSVc k2PE6/aLyUdfnJZAVSIsmpxW1LmUvDVhtj3pXv8QWv9tg/EJzogMu2a0EnWAed4Cx+6Y xA== From: Glenn Miles To: qemu-devel@nongnu.org Cc: Glenn Miles , qemu-arm@nongnu.org, clg@kaod.org, andrew@codeconstruct.com.au, joel@jms.id.au, philmd@linaro.org Subject: [PATCH v3 1/2] misc/pca9552: Fix inverted input status Date: Tue, 24 Oct 2023 13:11:43 -0500 Message-Id: <20231024181144.4045056-2-milesg@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20231024181144.4045056-1-milesg@linux.vnet.ibm.com> References: <20231024181144.4045056-1-milesg@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: W-JXh4PluNupMa3MDqrlxnGmAHLOv08F X-Proofpoint-GUID: W-JXh4PluNupMa3MDqrlxnGmAHLOv08F X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-24_17,2023-10-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 impostorscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 spamscore=0 malwarescore=0 adultscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310170001 definitions=main-2310240156 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=148.163.158.5; envelope-from=milesg@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1698171447694100001 Content-Type: text/plain; charset="utf-8" The pca9552 INPUT0 and INPUT1 registers are supposed to hold the logical values of the LED pins. A logical 0 should be seen in the INPUT0/1 registers for a pin when its corresponding LSn bits are set to 0, which is also the state needed for turning on an LED in a typical usage scenario. Existing code was doing the opposite and setting INPUT0/1 bit to a 1 when the LSn bit was set to 0, so this commit fixes that. Reviewed-by: Andrew Jeffery Signed-off-by: Glenn Miles --- No changes from v2 hw/misc/pca9552.c | 18 +++++++++++++----- tests/qtest/pca9552-test.c | 6 +++--- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c index fff19e369a..445f56a9e8 100644 --- a/hw/misc/pca9552.c +++ b/hw/misc/pca9552.c @@ -36,7 +36,10 @@ typedef struct PCA955xClass PCA955xClass; =20 DECLARE_CLASS_CHECKERS(PCA955xClass, PCA955X, TYPE_PCA955X) - +/* + * Note: The LED_ON and LED_OFF configuration values for the PCA955X + * chips are the reverse of the PCA953X family of chips. + */ #define PCA9552_LED_ON 0x0 #define PCA9552_LED_OFF 0x1 #define PCA9552_LED_PWM0 0x2 @@ -112,13 +115,18 @@ static void pca955x_update_pin_input(PCA955xState *s) =20 switch (config) { case PCA9552_LED_ON: - qemu_set_irq(s->gpio[i], 1); - s->regs[input_reg] |=3D 1 << input_shift; - break; - case PCA9552_LED_OFF: + /* Pin is set to 0V to turn on LED */ qemu_set_irq(s->gpio[i], 0); s->regs[input_reg] &=3D ~(1 << input_shift); break; + case PCA9552_LED_OFF: + /* + * Pin is set to Hi-Z to turn off LED and + * pullup sets it to a logical 1. + */ + qemu_set_irq(s->gpio[i], 1); + s->regs[input_reg] |=3D 1 << input_shift; + break; case PCA9552_LED_PWM0: case PCA9552_LED_PWM1: /* TODO */ diff --git a/tests/qtest/pca9552-test.c b/tests/qtest/pca9552-test.c index d80ed93cd3..ccca2b3d91 100644 --- a/tests/qtest/pca9552-test.c +++ b/tests/qtest/pca9552-test.c @@ -60,7 +60,7 @@ static void send_and_receive(void *obj, void *data, QGues= tAllocator *alloc) g_assert_cmphex(value, =3D=3D, 0x55); =20 value =3D i2c_get8(i2cdev, PCA9552_INPUT0); - g_assert_cmphex(value, =3D=3D, 0x0); + g_assert_cmphex(value, =3D=3D, 0xFF); =20 pca9552_init(i2cdev); =20 @@ -68,13 +68,13 @@ static void send_and_receive(void *obj, void *data, QGu= estAllocator *alloc) g_assert_cmphex(value, =3D=3D, 0x54); =20 value =3D i2c_get8(i2cdev, PCA9552_INPUT0); - g_assert_cmphex(value, =3D=3D, 0x01); + g_assert_cmphex(value, =3D=3D, 0xFE); =20 value =3D i2c_get8(i2cdev, PCA9552_LS3); g_assert_cmphex(value, =3D=3D, 0x54); =20 value =3D i2c_get8(i2cdev, PCA9552_INPUT1); - g_assert_cmphex(value, =3D=3D, 0x10); + g_assert_cmphex(value, =3D=3D, 0xEF); } =20 static void pca9552_register_nodes(void) --=20 2.31.1