From nobody Tue Dec 16 11:42:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1698137734; cv=none; d=zohomail.com; s=zohoarc; b=LrJyBcQgIymNeT6DSrd0PQyCytvmOX68Minf5jZ6lng8rN2r49Muqx6l6CCU2dR7vy0MFqvQcqwSZNcPmZCAfhL9vEz10gaICeoUzcecT8/KUko7IogIIriA6vTn3CAr08B8p40AoDMpZ2xs+Vb8c8cgB/CMhtpTRqFhjBtTXTE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698137734; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HQ1MUJxodmGrWZ0vEYhDGyNU4Wc8Cjdrb7URsVJcK1I=; b=Kw4s8x94fbNIbU8c+fqti1dBSkIZ1yyo2yUMiFeSwCrVZ4Ws2vrGQE9AxLNIawG+ci3GnR1uqbwLolP4C7IoQIKo69K5Vn4KArZtWqCnU3Bno6CDQ5r5ul9nRs0ldkabuWc3GBlWSGg63dLRo3Gg7L9idqhm8A6gAU0l7HKZAVA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698137733879531.1093626173532; Tue, 24 Oct 2023 01:55:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvDAz-0002qz-Tu; Tue, 24 Oct 2023 04:54:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvDAr-0002fj-Nq for qemu-devel@nongnu.org; Tue, 24 Oct 2023 04:54:05 -0400 Received: from mgamail.intel.com ([134.134.136.126]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvDAp-0006Q6-Jo for qemu-devel@nongnu.org; Tue, 24 Oct 2023 04:54:05 -0400 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2023 01:54:02 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga001.jf.intel.com with ESMTP; 24 Oct 2023 01:53:58 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698137643; x=1729673643; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZH9Ks7yaXoxHhP8gjR3dGJbDILIoP4Eqh1Yeu1EGX1A=; b=HxZdAVudST5+LowC+zjR1sVvMwlXUCZBLNB55bR/QvAsOOX3we7aLqC9 63mM3SU6fYVjTC3HjwZn5gAxl0uPC/E0IVWcHfqHSVtWQfklzHvdlTx2F ZyQ5/n9UVzZDsr0hfomqdk3fpprmkmWX+Wadw5pvA3X+o5dlgP9BSBiPA LYajg9tCaGpZNtzefoqkQHTSErSdbYjlXgNCe/AEfonAGaCyqU9hKYoy5 r6FYbpS2yTOEOIVo2kwbVFoFIsPdLNcLGeALDLTOgf3vKYzUn8vhrQ5If pvkjwlfK8w7+xRC0l6kVRMqxH+ilGOpMpGL6OlHNkpv7X09TQ8owgS7Iz A==; X-IronPort-AV: E=McAfee;i="6600,9927,10872"; a="372077453" X-IronPort-AV: E=Sophos;i="6.03,247,1694761200"; d="scan'208";a="372077453" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10872"; a="793418383" X-IronPort-AV: E=Sophos;i="6.03,247,1694761200"; d="scan'208";a="793418383" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Yongwei Ma , Zhao Liu Subject: [PATCH v5 18/20] i386: Use CPUCacheInfo.share_level to encode CPUID[4] Date: Tue, 24 Oct 2023 17:03:21 +0800 Message-Id: <20231024090323.1859210-19-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231024090323.1859210-1-zhao1.liu@linux.intel.com> References: <20231024090323.1859210-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.126; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1698137735664100011 Content-Type: text/plain; charset="utf-8" From: Zhao Liu CPUID[4].EAX[bits 25:14] is used to represent the cache topology for Intel CPUs. After cache models have topology information, we can use CPUCacheInfo.share_level to decide which topology level to be encoded into CPUID[4].EAX[bits 25:14]. And since maximum_processor_id (original "num_apic_ids") is parsed based on cpu topology levels, which are verified when parsing smp, it's no need to check this value by "assert(num_apic_ids > 0)" again, so remove this assert. Additionally, wrap the encoding of CPUID[4].EAX[bits 31:26] into a helper to make the code cleaner. Signed-off-by: Zhao Liu Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin --- Changes since v1: * Use "enum CPUTopoLevel share_level" as the parameter in max_processor_ids_for_cache(). * Make cache_into_passthrough case also use max_processor_ids_for_cache() and max_core_ids_in_package() to encode CPUID[4]. (Yanan) * Rename the title of this patch (the original is "i386: Use CPUCacheInfo.share_level to encode CPUID[4].EAX[bits 25:14]"). --- target/i386/cpu.c | 70 +++++++++++++++++++++++++++++------------------ 1 file changed, 43 insertions(+), 27 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ec98bc33b0bb..90393396a0a4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -235,22 +235,53 @@ static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *= cache) ((t) =3D=3D UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 0 /* Invalid value */) =20 +static uint32_t max_processor_ids_for_cache(X86CPUTopoInfo *topo_info, + enum CPUTopoLevel share_level) +{ + uint32_t num_ids =3D 0; + + switch (share_level) { + case CPU_TOPO_LEVEL_CORE: + num_ids =3D 1 << apicid_core_offset(topo_info); + break; + case CPU_TOPO_LEVEL_DIE: + num_ids =3D 1 << apicid_die_offset(topo_info); + break; + case CPU_TOPO_LEVEL_PACKAGE: + num_ids =3D 1 << apicid_pkg_offset(topo_info); + break; + default: + /* + * Currently there is no use case for SMT and MODULE, so use + * assert directly to facilitate debugging. + */ + g_assert_not_reached(); + } + + return num_ids - 1; +} + +static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) +{ + uint32_t num_cores =3D 1 << (apicid_pkg_offset(topo_info) - + apicid_core_offset(topo_info)); + return num_cores - 1; +} =20 /* Encode cache info for CPUID[4] */ static void encode_cache_cpuid4(CPUCacheInfo *cache, - int num_apic_ids, int num_cores, + X86CPUTopoInfo *topo_info, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { assert(cache->size =3D=3D cache->line_size * cache->associativity * cache->partitions * cache->sets); =20 - assert(num_apic_ids > 0); *eax =3D CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | - ((num_cores - 1) << 26) | - ((num_apic_ids - 1) << 14); + (max_core_ids_in_package(topo_info) << 26) | + (max_processor_ids_for_cache(topo_info, cache->share_level) << = 14); =20 assert(cache->line_size > 0); assert(cache->partitions > 0); @@ -6262,56 +6293,41 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, int host_vcpus_per_cache =3D 1 + ((*eax & 0x3FFC000) >> 14= ); =20 if (cores_per_pkg > 1) { - int addressable_cores_offset =3D - apicid_pkg_offset(&topo_in= fo) - - apicid_core_offset(&topo_i= nfo); - *eax &=3D ~0xFC000000; - *eax |=3D (1 << (addressable_cores_offset - 1)) << 26; + *eax |=3D max_core_ids_in_package(&topo_info) << 26; } if (host_vcpus_per_cache > cpus_per_pkg) { - int pkg_offset =3D apicid_pkg_offset(&topo_info); - *eax &=3D ~0x3FFC000; - *eax |=3D (1 << (pkg_offset - 1)) << 14; + *eax |=3D + max_processor_ids_for_cache(&topo_info, + CPU_TOPO_LEVEL_PACKAGE) <<= 14; } } } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { *eax =3D *ebx =3D *ecx =3D *edx =3D 0; } else { *eax =3D 0; - int addressable_cores_offset =3D apicid_pkg_offset(&topo_info)= - - apicid_core_offset(&topo_info); - int core_offset, die_offset; =20 switch (count) { case 0: /* L1 dcache info */ - core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, - (1 << core_offset), - (1 << addressable_cores_offset), + &topo_info, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ - core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, - (1 << core_offset), - (1 << addressable_cores_offset), + &topo_info, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ - core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, - (1 << core_offset), - (1 << addressable_cores_offset), + &topo_info, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - die_offset =3D apicid_die_offset(&topo_info); if (cpu->enable_l3_cache) { encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, - (1 << die_offset), - (1 << addressable_cores_offset), + &topo_info, eax, ebx, ecx, edx); break; } --=20 2.34.1