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Tsirkin" , Richard Henderson , Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Yongwei Ma , Zhao Liu , Zhuocheng Ding Subject: [PATCH v5 11/20] i386: Support modules_per_die in X86CPUTopoInfo Date: Tue, 24 Oct 2023 17:03:14 +0800 Message-Id: <20231024090323.1859210-12-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231024090323.1859210-1-zhao1.liu@linux.intel.com> References: <20231024090323.1859210-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=198.175.65.9; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1698137767811100007 Content-Type: text/plain; charset="utf-8" From: Zhuocheng Ding Support module level in i386 cpu topology structure "X86CPUTopoInfo". Since x86 does not yet support the "clusters" parameter in "-smp", X86CPUTopoInfo.modules_per_die is currently always 1. Therefore, the module level width in APIC ID, which can be calculated by "apicid_bitwidth_for_count(topo_info->modules_per_die)", is always 0 for now, so we can directly add APIC ID related helpers to support module level parsing. In addition, update topology structure in test-x86-topo.c. Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin --- Changes since v3: * Drop the description about not exposing module level in commit message. * Update topology related calculation in newly added helpers: num_cpus_by_topo_level() and apicid_offset_by_topo_level(). * Since the code change, drop the "Acked-by" tag. Changes since v1: * Include module level related helpers (apicid_module_width() and apicid_module_offset()) in this patch. (Yanan) --- hw/i386/x86.c | 3 ++- include/hw/i386/topology.h | 22 +++++++++++++++---- target/i386/cpu.c | 17 +++++++++----- tests/unit/test-x86-topo.c | 45 ++++++++++++++++++++------------------ 4 files changed, 55 insertions(+), 32 deletions(-) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 24628c1d2f73..8503d30a133a 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -72,7 +72,8 @@ static void init_topo_info(X86CPUTopoInfo *topo_info, MachineState *ms =3D MACHINE(x86ms); =20 topo_info->dies_per_pkg =3D ms->smp.dies; - topo_info->cores_per_die =3D ms->smp.cores; + topo_info->modules_per_die =3D ms->smp.clusters; + topo_info->cores_per_module =3D ms->smp.cores; topo_info->threads_per_core =3D ms->smp.threads; } =20 diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index d4eeb7ab8290..517e51768c13 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -56,7 +56,8 @@ typedef struct X86CPUTopoIDs { =20 typedef struct X86CPUTopoInfo { unsigned dies_per_pkg; - unsigned cores_per_die; + unsigned modules_per_die; + unsigned cores_per_module; unsigned threads_per_core; } X86CPUTopoInfo; =20 @@ -77,7 +78,13 @@ static inline unsigned apicid_smt_width(X86CPUTopoInfo *= topo_info) /* Bit width of the Core_ID field */ static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info) { - return apicid_bitwidth_for_count(topo_info->cores_per_die); + return apicid_bitwidth_for_count(topo_info->cores_per_module); +} + +/* Bit width of the Module_ID (cluster ID) field */ +static inline unsigned apicid_module_width(X86CPUTopoInfo *topo_info) +{ + return apicid_bitwidth_for_count(topo_info->modules_per_die); } =20 /* Bit width of the Die_ID field */ @@ -92,10 +99,16 @@ static inline unsigned apicid_core_offset(X86CPUTopoInf= o *topo_info) return apicid_smt_width(topo_info); } =20 +/* Bit offset of the Module_ID (cluster ID) field */ +static inline unsigned apicid_module_offset(X86CPUTopoInfo *topo_info) +{ + return apicid_core_offset(topo_info) + apicid_core_width(topo_info); +} + /* Bit offset of the Die_ID field */ static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info) { - return apicid_core_offset(topo_info) + apicid_core_width(topo_info); + return apicid_module_offset(topo_info) + apicid_module_width(topo_info= ); } =20 /* Bit offset of the Pkg_ID (socket ID) field */ @@ -127,7 +140,8 @@ static inline void x86_topo_ids_from_idx(X86CPUTopoInfo= *topo_info, X86CPUTopoIDs *topo_ids) { unsigned nr_dies =3D topo_info->dies_per_pkg; - unsigned nr_cores =3D topo_info->cores_per_die; + unsigned nr_cores =3D topo_info->cores_per_module * + topo_info->modules_per_die; unsigned nr_threads =3D topo_info->threads_per_core; =20 topo_ids->pkg_id =3D cpu_index / (nr_dies * nr_cores * nr_threads); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a33d2f83a6a8..63c33b77ba74 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -278,10 +278,11 @@ static uint32_t num_cpus_by_topo_level(X86CPUTopoInfo= *topo_info, case CPU_TOPO_LEVEL_CORE: return topo_info->threads_per_core; case CPU_TOPO_LEVEL_DIE: - return topo_info->threads_per_core * topo_info->cores_per_die; + return topo_info->threads_per_core * topo_info->cores_per_module * + topo_info->modules_per_die; case CPU_TOPO_LEVEL_PACKAGE: - return topo_info->threads_per_core * topo_info->cores_per_die * - topo_info->dies_per_pkg; + return topo_info->threads_per_core * topo_info->cores_per_module * + topo_info->modules_per_die * topo_info->dies_per_pkg; default: g_assert_not_reached(); } @@ -450,7 +451,9 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *ca= che, =20 /* L3 is shared among multiple cores */ if (cache->level =3D=3D 3) { - l3_threads =3D topo_info->cores_per_die * topo_info->threads_per_c= ore; + l3_threads =3D topo_info->modules_per_die * + topo_info->cores_per_module * + topo_info->threads_per_core; *eax |=3D (l3_threads - 1) << 14; } else { *eax |=3D ((topo_info->threads_per_core - 1) << 14); @@ -6130,10 +6133,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, uint32_t cpus_per_pkg; =20 topo_info.dies_per_pkg =3D env->nr_dies; - topo_info.cores_per_die =3D cs->nr_cores / env->nr_dies; + topo_info.modules_per_die =3D env->nr_modules; + topo_info.cores_per_module =3D cs->nr_cores / env->nr_dies / env->nr_m= odules; topo_info.threads_per_core =3D cs->nr_threads; =20 - cores_per_pkg =3D topo_info.cores_per_die * topo_info.dies_per_pkg; + cores_per_pkg =3D topo_info.cores_per_module * topo_info.modules_per_d= ie * + topo_info.dies_per_pkg; cpus_per_pkg =3D cores_per_pkg * topo_info.threads_per_core; =20 /* Calculate & apply limits for different index ranges */ diff --git a/tests/unit/test-x86-topo.c b/tests/unit/test-x86-topo.c index 2b104f86d7c2..f21b8a5d95c2 100644 --- a/tests/unit/test-x86-topo.c +++ b/tests/unit/test-x86-topo.c @@ -30,13 +30,16 @@ static void test_topo_bits(void) { X86CPUTopoInfo topo_info =3D {0}; =20 - /* simple tests for 1 thread per core, 1 core per die, 1 die per packa= ge */ - topo_info =3D (X86CPUTopoInfo) {1, 1, 1}; + /* + * simple tests for 1 thread per core, 1 core per module, + * 1 module per die, 1 die per package + */ + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 1}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 0); g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 0); g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 0); =20 - topo_info =3D (X86CPUTopoInfo) {1, 1, 1}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 1}; g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 0), =3D=3D, 0); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1), =3D=3D, 1); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2), =3D=3D, 2); @@ -45,39 +48,39 @@ static void test_topo_bits(void) =20 /* Test field width calculation for multiple values */ - topo_info =3D (X86CPUTopoInfo) {1, 1, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 2}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 1); - topo_info =3D (X86CPUTopoInfo) {1, 1, 3}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 3}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 2); - topo_info =3D (X86CPUTopoInfo) {1, 1, 4}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 4}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 2); =20 - topo_info =3D (X86CPUTopoInfo) {1, 1, 14}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 14}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 4); - topo_info =3D (X86CPUTopoInfo) {1, 1, 15}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 15}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 4); - topo_info =3D (X86CPUTopoInfo) {1, 1, 16}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 16}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 4); - topo_info =3D (X86CPUTopoInfo) {1, 1, 17}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 17}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 5); =20 =20 - topo_info =3D (X86CPUTopoInfo) {1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 30, 2}; g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 5); - topo_info =3D (X86CPUTopoInfo) {1, 31, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 31, 2}; g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 5); - topo_info =3D (X86CPUTopoInfo) {1, 32, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 32, 2}; g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 5); - topo_info =3D (X86CPUTopoInfo) {1, 33, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 33, 2}; g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 6); =20 - topo_info =3D (X86CPUTopoInfo) {1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 0); - topo_info =3D (X86CPUTopoInfo) {2, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {2, 1, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 1); - topo_info =3D (X86CPUTopoInfo) {3, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {3, 1, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 2); - topo_info =3D (X86CPUTopoInfo) {4, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {4, 1, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 2); =20 /* build a weird topology and see if IDs are calculated correctly @@ -85,18 +88,18 @@ static void test_topo_bits(void) =20 /* This will use 2 bits for thread ID and 3 bits for core ID */ - topo_info =3D (X86CPUTopoInfo) {1, 6, 3}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 6, 3}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 2); g_assert_cmpuint(apicid_core_offset(&topo_info), =3D=3D, 2); g_assert_cmpuint(apicid_die_offset(&topo_info), =3D=3D, 5); g_assert_cmpuint(apicid_pkg_offset(&topo_info), =3D=3D, 5); =20 - topo_info =3D (X86CPUTopoInfo) {1, 6, 3}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 6, 3}; g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 0), =3D=3D, 0); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1), =3D=3D, 1); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2), =3D=3D, 2); =20 - topo_info =3D (X86CPUTopoInfo) {1, 6, 3}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 6, 3}; g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 3 + 0), =3D= =3D, (1 << 2) | 0); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 3 + 1), =3D= =3D, --=20 2.34.1