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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834621; x=1698439421; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HcidF9Jk1N+Ej8dbQUUvFmfE2V7LiGtPgLbzAI4Qab4=; b=KmYY5kSuhKvWvreARar5znrPZwqqrCquIekLLmI9/Lr/ARU9EPyZZuUTlfnUBXh2gm YJ9SP/gQiaG4EHIEDoPO/n1kGn726U6CKF3RNuVHlLapOUHAfTBux1hl1r2m3gjwGcMp +bFuCVkvywD1lot+ohOrexCG8svDxt69Wcz75SO84g8Kj/Ds1Ek0GdTMW3JY8RvuFSIr EDXRtWVixTCGAnIgL4DW6vylvRPSFyedk0lRGQ4tbjCVkFU2Qli9+HhvmEt4gxuSkNxW Rcm1ODiHQXNV+uMURY2phNRfLKgW8bTaHfqyEaI6z9Qyr/D7IKWIdNAQXU/I9tdYuTA0 D1xQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834621; x=1698439421; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HcidF9Jk1N+Ej8dbQUUvFmfE2V7LiGtPgLbzAI4Qab4=; b=r6BsAe4z5OyxBrgxMyhIwKXQsp//Ig7I0DuUSdSBaHvmNTBY2mTBxekoEQTuXDFjur MJtfE8KwPkXIMiLFNn4/wKdbHUMzqOUhIvOXpbev2DEktS3aoaEzLz1i90+GCfIRGoZZ aCHXond4IqYwM1ddU2/0AaYHIHU2lTYG7D0PdK43XlI0j/8LYMzlZXWLu+AB63dnWdEw 2wG3EyUPF2pMI/deuCzG/pa4LmcKqAxuTZpV9Y7Tsu0ctL7BAtOgBxsT979X+uI3yzuy 9i/kji9PO4XR8W/TsIn6ZgFd8KFTb1C90z2ueymGtKm/z70NFzodWbl5L5tx/iRYIgYi xvfA== X-Gm-Message-State: AOJu0YzUBgMYqS0bdu1+2+h7y6CRu5sQYIANAIWJXwpM5HXHaNbSokY0 Q5/+AYRhCVJ5bIV7Vdj42yz9K6Pd0Ye2OA/1XnI= X-Google-Smtp-Source: AGHT+IG2VzdtieHwUPaLTUo80MnvMR35uXisXNK0sntO+EJ50z1PhX17kCIjz4B6zyGqlGQFlE3qUw== X-Received: by 2002:a05:6a00:10c4:b0:6b5:608d:64f6 with SMTP id d4-20020a056a0010c400b006b5608d64f6mr3132210pfu.20.1697834620857; Fri, 20 Oct 2023 13:43:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 08/65] target/hppa: Truncate rotate count in trans_shrpw_sar Date: Fri, 20 Oct 2023 13:42:34 -0700 Message-Id: <20231020204331.139847-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834683861100003 Content-Type: text/plain; charset="utf-8" When forcing rotate by i32, the shift count must be as well. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ff559ed21d..e6ab113a1c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3105,8 +3105,11 @@ static bool trans_shrpw_sar(DisasContext *ctx, arg_s= hrpw_sar *a) tcg_gen_shr_reg(dest, dest, cpu_sar); } else if (a->r1 =3D=3D a->r2) { TCGv_i32 t32 =3D tcg_temp_new_i32(); + TCGv_i32 s32 =3D tcg_temp_new_i32(); + tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); - tcg_gen_rotr_i32(t32, t32, cpu_sar); + tcg_gen_trunc_reg_i32(s32, cpu_sar); + tcg_gen_rotr_i32(t32, t32, s32); tcg_gen_extu_i32_reg(dest, t32); } else { TCGv_i64 t =3D tcg_temp_new_i64(); --=20 2.34.1