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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u7-20020aa78487000000b00694fee1011asm1946775pfn.208.2023.10.20.13.47.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:47:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834845; x=1698439645; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F7SjukT8MkZFkJ3ExB67ZCgDVB5vB1uA1Vxc0UPcY5M=; b=Wd6zEQjK9XYvKTmVQHYP47ko5V4Q9dwE1ExYNtRAkjhw2pihaFgqllh8WzVfFjtTxO A3P3y9vAcPfVF4qZX+DyT20Kfgsyczcjvzl1h+W6DJ0WoSctsvhhgbLo4FPEm4XBW3TA EapbZfNoJZivVy3lV1LByH1byScJH65Q7GLZOYGO8vE1W1bqYAMwiBmbKedtW7TI2hiR 23RLKvLSmuGqldf36TgjllJxpi8rGzw095S4pJKy0b4LhqrhBpZvwgATE9RG6n1sKZmV 63J2Sl2IDJEsCl8xNO0ivLSTv0vmn1+Or8PS17RgFpf3YAsiWRe5WLTNt0DYyibS7S23 bxmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834845; x=1698439645; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F7SjukT8MkZFkJ3ExB67ZCgDVB5vB1uA1Vxc0UPcY5M=; b=u/TyQ443f6xTMaImtLBu+Ye2a2nBZSGKHvLdBvK4SgwQXkTYm9q1QR5PQlc6ApcrIu NV1/mnJlJsFkqiU7tN9ccIY6nWyqkSO6rbHBXtriQgYD4jmipiM4mhwOgSSQHslxzA1w +c/nT4n5ltJM+6JgTq5nsT/OVBzwTKKKvEs+idohvD7jNMkwTaruFv5x9n+ds6fnPFl4 sbe7N3tbgVsjHt9Cew0/QDrTGOqhae3zQiu84QFNhzKeLEu5rA/R7lmkUDQoBkYMChvx wKW0JBGpXzeCmf5HCjV3IZGWtGrr7IsW1x6wA0L6o0VP3jKQGsj1MUdCHDHA2PRzeyf1 HS+g== X-Gm-Message-State: AOJu0YwhosRnT4QzIf0z/eDeMi8YW4eOFz88fuI1iTRg4DI6Gg07b5mq EtOutKNzAA4JwK6ADjrBMwuqUGI85P5kuOj1ywg= X-Google-Smtp-Source: AGHT+IFwtF5UxrHInrf5vQ59AXDFyDdf4tB55t/WQlUQj+N5s3TKmVa4M30sJvYW1VNcojuZMtOMFg== X-Received: by 2002:a05:6a21:66c7:b0:16b:9285:69f5 with SMTP id ze7-20020a056a2166c700b0016b928569f5mr2544162pzb.35.1697834845498; Fri, 20 Oct 2023 13:47:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 60/65] target/hppa: Precompute zero into DisasContext Date: Fri, 20 Oct 2023 13:43:26 -0700 Message-Id: <20231020204331.139847-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835289965100008 Content-Type: text/plain; charset="utf-8" Reduce the number of times we look for the constant 0. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/hppa/translate.c | 34 ++++++++++++++++++---------------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index a79cf52fcc..9b60924057 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -53,6 +53,8 @@ typedef struct DisasContext { DisasCond null_cond; TCGLabel *null_lab; =20 + TCGv_i64 zero; + uint32_t insn; uint32_t tb_flags; int mmu_idx; @@ -1004,14 +1006,13 @@ static void do_add(DisasContext *ctx, unsigned rt, = TCGv_i64 in1, } =20 if (!is_l || cond_need_cb(c)) { - TCGv_i64 zero =3D tcg_constant_i64(0); cb_msb =3D tcg_temp_new_i64(); cb =3D tcg_temp_new_i64(); =20 - tcg_gen_add2_i64(dest, cb_msb, in1, zero, in2, zero); + tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero, in2, ctx->zero); if (is_c) { tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb, - get_psw_carry(ctx, d), zero); + get_psw_carry(ctx, d), ctx->zero); } tcg_gen_xor_i64(cb, in1, in2); tcg_gen_xor_i64(cb, cb, dest); @@ -1089,7 +1090,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_i64 in1, TCGv_i64 in2, bool is_tsv, bool is_b, bool is_tc, unsigned cf, bool d) { - TCGv_i64 dest, sv, cb, cb_msb, zero, tmp; + TCGv_i64 dest, sv, cb, cb_msb, tmp; unsigned c =3D cf >> 1; DisasCond cond; =20 @@ -1097,12 +1098,12 @@ static void do_sub(DisasContext *ctx, unsigned rt, = TCGv_i64 in1, cb =3D tcg_temp_new_i64(); cb_msb =3D tcg_temp_new_i64(); =20 - zero =3D tcg_constant_i64(0); if (is_b) { /* DEST,C =3D IN1 + ~IN2 + C. */ tcg_gen_not_i64(cb, in2); - tcg_gen_add2_i64(dest, cb_msb, in1, zero, get_psw_carry(ctx, d), z= ero); - tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb, cb, zero); + tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero, + get_psw_carry(ctx, d), ctx->zero); + tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb, cb, ctx->zero); tcg_gen_xor_i64(cb, cb, in1); tcg_gen_xor_i64(cb, cb, dest); } else { @@ -1111,7 +1112,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_i64 in1, * operations by seeding the high word with 1 and subtracting. */ TCGv_i64 one =3D tcg_constant_i64(1); - tcg_gen_sub2_i64(dest, cb_msb, in1, one, in2, zero); + tcg_gen_sub2_i64(dest, cb_msb, in1, one, in2, ctx->zero); tcg_gen_eqv_i64(cb, in1, in2); tcg_gen_xor_i64(cb, cb, dest); } @@ -2430,7 +2431,7 @@ static bool trans_lci(DisasContext *ctx, arg_lci *a) physical address. Two addresses with the same CI have a coherent view of the cache. Our implementation is to return 0 for all, since the entire address space is coherent. */ - save_gpr(ctx, a->t, tcg_constant_i64(0)); + save_gpr(ctx, a->t, ctx->zero); =20 cond_free(&ctx->null_cond); return true; @@ -2639,7 +2640,7 @@ static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf= _d *a) =20 static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) { - TCGv_i64 dest, add1, add2, addc, zero, in1, in2; + TCGv_i64 dest, add1, add2, addc, in1, in2; TCGv_i64 cout; =20 nullify_over(ctx); @@ -2651,7 +2652,6 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) add2 =3D tcg_temp_new_i64(); addc =3D tcg_temp_new_i64(); dest =3D tcg_temp_new_i64(); - zero =3D tcg_constant_i64(0); =20 /* Form R1 << 1 | PSW[CB]{8}. */ tcg_gen_add_i64(add1, in1, in1); @@ -2667,8 +2667,9 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) tcg_gen_xor_i64(add2, in2, addc); tcg_gen_andi_i64(addc, addc, 1); =20 - tcg_gen_add2_i64(dest, cpu_psw_cb_msb, add1, zero, add2, zero); - tcg_gen_add2_i64(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zer= o); + tcg_gen_add2_i64(dest, cpu_psw_cb_msb, add1, ctx->zero, add2, ctx->zer= o); + tcg_gen_add2_i64(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, + addc, ctx->zero); =20 /* Write back the result register. */ save_gpr(ctx, a->t, dest); @@ -2968,7 +2969,7 @@ static bool trans_st(DisasContext *ctx, arg_ldst *a) static bool trans_ldc(DisasContext *ctx, arg_ldst *a) { MemOp mop =3D MO_TE | MO_ALIGN | a->size; - TCGv_i64 zero, dest, ofs; + TCGv_i64 dest, ofs; TCGv_i64 addr; =20 if (!ctx->is_pa20 && a->size > MO_32) { @@ -2998,8 +2999,7 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) */ gen_helper_ldc_check(addr); =20 - zero =3D tcg_constant_i64(0); - tcg_gen_atomic_xchg_i64(dest, addr, zero, ctx->mmu_idx, mop); + tcg_gen_atomic_xchg_i64(dest, addr, ctx->zero, ctx->mmu_idx, mop); =20 if (a->m) { save_gpr(ctx, a->b, ofs); @@ -4336,6 +4336,8 @@ static void hppa_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) ctx->iaoq_n =3D -1; ctx->iaoq_n_var =3D NULL; =20 + ctx->zero =3D tcg_constant_i64(0); + /* Bound the number of instructions by those left on the page. */ bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; ctx->base.max_insns =3D MIN(ctx->base.max_insns, bound); --=20 2.34.1