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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u7-20020aa78487000000b00694fee1011asm1946775pfn.208.2023.10.20.13.47.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:47:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834844; x=1698439644; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wM6oyD2tzl0dJH7FSQ0obv2SUstAr+kC/PKso0mR/f4=; b=q9J1mEZKolsO6/7XmrUFsT34HsbqbORm7fg+kk24XJCVTOAf7XW84i8Uzx9dqJ04Rv /nLdNIDjvp8lm+d6zP7NDCc+J/gyBgIHxe6tQvq/+YAcLj2XryXh7ZL0AelPzcaP7VJR cDcnX/OVqJFnuI/HlONwa8l0giHiFdGczv1zt2KkyK2z5VK2HLAP1bIpm4s6Wyt7yNbc br6r1x18MRCheTAYUTB1evqi6Hbn9MBGUV6X5fyY5sBHH0vs4gXzw6KS6JTLTmmOPImh SE/qzuU5ZmvU4pyQ02+K5jwUL69cBiEVqTvwhfYx2b2QPLLY1VdkB33kpjqnHsRK8sWc MH7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834844; x=1698439644; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wM6oyD2tzl0dJH7FSQ0obv2SUstAr+kC/PKso0mR/f4=; b=OqFAPBYvI9Giw/FS+YOlJQewZ1C+59Wnr6MQsa27o3p0brUQst3vqSxssxbJVbygy0 8pL5sfpgZhRlFtoJprUQsIQ9f5vGzF1uy0URm9UveyWa8JClyA79R1dBZml67xoR3Jzk Z47uGBaoLosXcqwzKcBynhFHiB2kGQlTy2tSSgdIdT2q/OdfM1vE6vrvEmTqeHTnbqV8 CSGgzlL9mYQT3OE3jFAdW+HMYu9gTDO20BL0sW0hv62tgINkceDnNA/t8IoMJoHXl0cQ 3RUwg+nW4RFXRW1YA/Eamkuoi054HrHlsaOKQ82lbh8WXF7wi5eCara41lURtH9r7y9M uMJw== X-Gm-Message-State: AOJu0YwldJMGonYqR3w9skaNVjCOCKlWs9SfxQvuYaOAiK9yHUt3kWr/ USngwE/T6nqsulJGqKZbwJvggLg6UqpvfdM9+sk= X-Google-Smtp-Source: AGHT+IGgedYkJ4+aYJ0ItGSgAnG8FqxW+rR5zzjI95FeHd3wpNqTvo0SsIvh+QoM5LijD5kKqK8FZg== X-Received: by 2002:a05:6a00:1389:b0:68f:d35d:217e with SMTP id t9-20020a056a00138900b0068fd35d217emr3115072pfg.2.1697834844678; Fri, 20 Oct 2023 13:47:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 59/65] target/hppa: Fix interruption based on default PSW Date: Fri, 20 Oct 2023 13:43:25 -0700 Message-Id: <20231020204331.139847-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835075111100007 Content-Type: text/plain; charset="utf-8" From: Helge Deller The default PSW is set by the operating system with the PDC_PSW firmware call. Use that setting to decide if wide mode is to be enabled for interruptions and EIRR usage. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 ++ target/hppa/int_helper.c | 18 ++++++++++++++---- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c9a9b9d3be..4aea46442a 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -124,6 +124,8 @@ #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ =20 #define CR_RC 0 +#define CR_PSW_DEFAULT 6 /* see SeaBIOS PDC_PSW firmware call */ +#define PDC_PSW_WIDE_BIT 2 #define CR_PID1 8 #define CR_PID2 9 #define CR_PID3 12 diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index f355c4c76b..a11d607b31 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -52,9 +52,17 @@ static void io_eir_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { HPPACPU *cpu =3D opaque; - int le_bit =3D ~data & 31; + CPUHPPAState *env =3D &cpu->env; + int widthm1 =3D 31; + int le_bit; =20 - cpu->env.cr[CR_EIRR] |=3D (target_ulong)1 << le_bit; + /* The default PSW.W controls the width of EIRR. */ + if (hppa_is_pa20(env) && env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT) { + widthm1 =3D 63; + } + le_bit =3D ~data & widthm1; + + env->cr[CR_EIRR] |=3D 1ull << le_bit; eval_interrupt(cpu); } =20 @@ -104,8 +112,10 @@ void hppa_cpu_do_interrupt(CPUState *cs) /* step 1 */ env->cr[CR_IPSW] =3D old_psw =3D cpu_hppa_get_psw(env); =20 - /* step 2 -- note PSW_W =3D=3D 0 for !HPPA64. */ - cpu_hppa_put_psw(env, PSW_W | (i =3D=3D EXCP_HPMC ? PSW_M : 0)); + /* step 2 -- Note PSW_W is masked out again for pa1.x */ + cpu_hppa_put_psw(env, + (env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT ? PSW_W := 0) | + (i =3D=3D EXCP_HPMC ? PSW_M : 0)); =20 /* step 3 */ env->cr[CR_IIASQ] =3D iasq_f >> 32; --=20 2.34.1