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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834631; x=1698439431; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kr+C20DtXtMGy3xs/PIBOfM94TBLe/tVvjYddrVGe/s=; b=VYK1KCH8P88I1lQcPtliJgur28/Cvh5PwVaYNli3FUZvqQ4CMC//Q3VaFA9ulhfUrJ m69nR+qBddUE4XGtj3uJs1cHY3vni4MulZXd7fpoUlPQtGBBYNmKti6mfABV8hl87nMi 5UO2d4zKb133HyO2SyIJrGGh0NmfC8uvWTz1rKMgDMyVHXXnOREzpejiCqNyL1hQq6tb HwcFjsou36fGqEsSXLJ8qblBfBbfEXoEKHkS2Rc/LNZiZUZyq0efmKNzxcQl4zsnn1AI IDULg2s/WnckL5BQDMFvv5N7SdOSrljNQCdYRL3OTk4xz9Dd282xk8XOV8RIiieaIMPx 7CVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834631; x=1698439431; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kr+C20DtXtMGy3xs/PIBOfM94TBLe/tVvjYddrVGe/s=; b=K713+T4Cf1LIQkrXuAqH737pHUU7z2ZBSerIQ/6CqpzlOPMUO/mxJD/cnGETAhnQJo Dmhlaq1zlS+B41+pWo98oEkZcimxAIXqvmllEkseMjq6Fkbgk7ml0pHURGKCAjYp20lX YWgJfHPZ31UEKa5MqqSdl0/R2n8NtKvkZ9zQ7aKpHKBEmxxpkjZXZ5pOFxXbiaODtAdh QWTUMiWoyUYOXgNqM3Z9XE7exaHw9CASwerIzxSX0pcp5i2PThnP5yMTCOG8I6N1DdAG W+2NK+bUxhTgHZ/91QG7c5eTHP/jtFFIAVrqfOoGvefpxXL6wcFi2PHAay1kIOMkQMuO cKIA== X-Gm-Message-State: AOJu0Yy8OcTd9PVeS5xanpdrNj3NJqKOzWwQLUIKKXle+F5t6nB0uCh1 zrvZFB9F/j1VzUIIzsjJel7JFNZIsbrr+aIrkBw= X-Google-Smtp-Source: AGHT+IGNkexM96nN65R+76815n4z/UR/WGXkS1IA/C5hBtFQGMs40ARITpXnx81Q4qMMQYyWMoe6Ug== X-Received: by 2002:a05:6a00:1747:b0:6b1:c1c4:ae98 with SMTP id j7-20020a056a00174700b006b1c1c4ae98mr3458507pfc.18.1697834630740; Fri, 20 Oct 2023 13:43:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 20/65] target/hppa: Fix hppa64 addressing Date: Fri, 20 Oct 2023 13:42:46 -0700 Message-Id: <20231020204331.139847-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835270047100003 Content-Type: text/plain; charset="utf-8" In form_gva and cpu_get_tb_cpu_state, we must truncate when PSW_W =3D=3D 0. In space_select, the bits that choose the space depend on PSW_W. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 7 +++---- target/hppa/translate.c | 22 +++++++++++++--------- 2 files changed, 16 insertions(+), 13 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 622b4af890..2182437882 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -273,7 +273,7 @@ static inline target_ulong hppa_form_gva_psw(target_ure= g psw, uint64_t spc, #ifdef CONFIG_USER_ONLY return off; #else - off &=3D (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull); + off &=3D psw & PSW_W ? MAKE_64BIT_MASK(0, 62) : MAKE_64BIT_MASK(0, 32); return spc | off; #endif } @@ -314,9 +314,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *e= nv, vaddr *pc, flags |=3D env->psw & (PSW_W | PSW_C | PSW_D); flags |=3D (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; =20 - *pc =3D (env->psw & PSW_C - ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4) - : env->iaoq_f & -4); + *pc =3D hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : = 0), + env->iaoq_f & -4); *cs_base =3D env->iasq_f; =20 /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise = zero diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 83115c944b..c7d17900f1 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -764,6 +764,13 @@ static bool gen_illegal(DisasContext *ctx) } while (0) #endif =20 +static target_ureg gva_offset_mask(DisasContext *ctx) +{ + return (ctx->tb_flags & PSW_W + ? MAKE_64BIT_MASK(0, 62) + : MAKE_64BIT_MASK(0, 32)); +} + static bool use_goto_tb(DisasContext *ctx, target_ureg dest) { return translator_use_goto_tb(&ctx->base, dest); @@ -1398,7 +1405,8 @@ static TCGv_i64 space_select(DisasContext *ctx, int s= p, TCGv_reg base) tmp =3D tcg_temp_new(); spc =3D tcg_temp_new_tl(); =20 - tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5); + /* Extract top 2 bits of the address, shift left 3 for uint64_t index.= */ + tcg_gen_shri_reg(tmp, base, (ctx->tb_flags & PSW_W ? 64 : 32) - 5); tcg_gen_andi_reg(tmp, tmp, 030); tcg_gen_trunc_reg_ptr(ptr, tmp); =20 @@ -1415,6 +1423,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva= , TCGv_reg *pofs, { TCGv_reg base =3D load_gpr(ctx, rb); TCGv_reg ofs; + TCGv_tl addr; =20 /* Note that RX is mutually exclusive with DISP. */ if (rx) { @@ -1429,18 +1438,13 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pg= va, TCGv_reg *pofs, } =20 *pofs =3D ofs; -#ifdef CONFIG_USER_ONLY - *pgva =3D (modify <=3D 0 ? ofs : base); -#else - TCGv_tl addr =3D tcg_temp_new_tl(); + *pgva =3D addr =3D tcg_temp_new_tl(); tcg_gen_extu_reg_tl(addr, modify <=3D 0 ? ofs : base); - if (ctx->tb_flags & PSW_W) { - tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); - } + tcg_gen_andi_tl(addr, addr, gva_offset_mask(ctx)); +#ifndef CONFIG_USER_ONLY if (!is_phys) { tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base)); } - *pgva =3D addr; #endif } =20 --=20 2.34.1