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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834628; x=1698439428; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/Td/Ysv7eoH4uj7r0UKubRW7kAk7MGHOo1UhYXHuswg=; b=jW/ul2Slp828MP+g9H2aGmAcE6rfJS84M1qrSQhvBpG9uDxMxzfg43tzMCzGnWyFUh RHKB1r52nWEtu7EHS7aFf+lyuoB7vXUdf9YZu0+OqGzDLC0/16rIgpmOxxywcpp/tq6z dn7C1LJEn9tJg7zRmyl/VA/32Pd9BV/tts21SyCy5ssoYTqHWCCUr7RSfodtv7Yn2Orv xnCEJ/+hve8m8miHpCIjTjo2IWfTMgm6jnMDQR5fZZlyy4tdC6QY4aIB8qdO2tgxr4eW mJyv1Ms2+ZeaCWQGBhe7CJ+/o1JvB7KwExvNrKx/djw7qJb7A2m+vYKCbQuvC60Df0/M mR4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834628; x=1698439428; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/Td/Ysv7eoH4uj7r0UKubRW7kAk7MGHOo1UhYXHuswg=; b=acuBzn0V4onwTRhABNmHkC7npzKjJA7Y5tcmUmBU1PjN5LzM4OdzDybLyHryUDFMGR /WU+Kt+QTgTUFxgFjasTMRWLSIhCc/ZOiaUKHPQZoa65IXehHJ1uz10nm3Dzasq9w1CC LFxeUeq7Yg0czLsZ4Oj7YvUFYTpBnX5xaoflDUR4PEYoUXESDtUN+jXi6AXVKNgxwbzo J1wuvFSKjznQ8Y7CcPPZrIEmUV4pPHPGXvkQ3qBIbqBK/XbUHTXVaEyuRd3jP3pBaXq+ vfbwOI/M1Uzc5xznVJQbZBM7k5b2vnpk77qt3yDdF6QyDZZXOdgfMtGDm/vsgY+7lYjP YB3A== X-Gm-Message-State: AOJu0YyNKxF84YboBHUv1peRFlDnuvatNCsDil2UPvVdTXaUHwOO59DQ Zbmml2aW+5Tba5cgUR7qbcHS5eYpk/B6JSKLIH8= X-Google-Smtp-Source: AGHT+IEzM4bAcBvwJOt0gYevFx0yP49REFNMh2Bqnh409jBtYHB7nDYtH4N1EmfXAU3BnAR+/5UU/A== X-Received: by 2002:a05:6a20:7fa6:b0:17a:eddb:ac6a with SMTP id d38-20020a056a207fa600b0017aeddbac6amr4113829pzj.6.1697834628432; Fri, 20 Oct 2023 13:43:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 17/65] target/hppa: Update cpu_hppa_get/put_psw for hppa64 Date: Fri, 20 Oct 2023 13:42:43 -0700 Message-Id: <20231020204331.139847-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834705893100001 Content-Type: text/plain; charset="utf-8" With 64-bit registers, there are 16 carry bits in the PSW. Clear reserved bits based on cpu revision. Signed-off-by: Richard Henderson --- target/hppa/helper.c | 63 ++++++++++++++++++++++++++++++++++++-------- 1 file changed, 52 insertions(+), 11 deletions(-) diff --git a/target/hppa/helper.c b/target/hppa/helper.c index a8d3f456ee..534a9e374c 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -28,19 +28,35 @@ target_ureg cpu_hppa_get_psw(CPUHPPAState *env) { target_ureg psw; + target_ureg mask1 =3D (target_ureg)-1 / 0xf; + target_ureg maskf =3D (target_ureg)-1 / 0xffff * 0xf; =20 /* Fold carry bits down to 8 consecutive bits. */ - /* ??? Needs tweaking for hppa64. */ - /* .......b...c...d...e...f...g...h */ - psw =3D (env->psw_cb >> 4) & 0x01111111; - /* .......b..bc..cd..de..ef..fg..gh */ + /* ^^^b^^^c^^^d^^^e^^^f^^^g^^^h^^^i^^^j^^^k^^^l^^^m^^^n^^^o^^^p^^^^ */ + /* ^^^b^^^c^^^d^^^e^^^f^^^g^^^h^^^^ */ + psw =3D (env->psw_cb >> 4) & mask1; + /* .......b...c...d...e...f...g...h...i...j...k...l...m...n...o...p */ + /* .......b...c...d...e...f...g...h */ psw |=3D psw >> 3; - /* .............bcd............efgh */ - psw |=3D (psw >> 6) & 0x000f000f; - /* .........................bcdefgh */ - psw |=3D (psw >> 12) & 0xf; - psw |=3D env->psw_cb_msb << 7; - psw =3D (psw & 0xff) << 8; + /* .......b..bc..cd..de..ef..fg..gh..hi..ij..jk..kl..lm..mn..no..op */ + /* .......b..bc..cd..de..ef..fg..gh */ + psw |=3D psw >> 6; + psw &=3D maskf; + /* .............bcd............efgh............ijkl............mnop */ + /* .............bcd............efgh */ + psw |=3D psw >> 12; + /* .............bcd.........bcdefgh........efghijkl........ijklmnop */ + /* .............bcd.........bcdefgh */ + psw |=3D env->psw_cb_msb << (TARGET_REGISTER_BITS =3D=3D 64 ? 39 : 7); + /* .............bcd........abcdefgh........efghijkl........ijklmnop */ + /* .............bcd........abcdefgh */ + + /* For hppa64, the two 8-bit fields are discontiguous. */ + if (hppa_is_pa20(env)) { + psw =3D (psw & 0xff00000000ull) | ((psw & 0xff) << 8); + } else { + psw =3D (psw & 0xff) << 8; + } =20 psw |=3D env->psw_n * PSW_N; psw |=3D (env->psw_v < 0) * PSW_V; @@ -51,14 +67,39 @@ target_ureg cpu_hppa_get_psw(CPUHPPAState *env) =20 void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) { + uint64_t reserved; target_ureg old_psw =3D env->psw; target_ureg cb =3D 0; =20 + /* Do not allow reserved bits to be set. */ + if (hppa_is_pa20(env)) { + reserved =3D MAKE_64BIT_MASK(40, 24) | MAKE_64BIT_MASK(28, 4); + reserved |=3D PSW_G; /* PA1.x only */ + reserved |=3D PSW_E; /* not implemented */ + } else { + reserved =3D MAKE_64BIT_MASK(32, 32) | MAKE_64BIT_MASK(28, 2); + reserved |=3D PSW_O | PSW_W; /* PA2.0 only */ + reserved |=3D PSW_E | PSW_Y | PSW_Z; /* not implemented */ + } + psw &=3D ~reserved; + env->psw =3D psw & ~(PSW_N | PSW_V | PSW_CB); env->psw_n =3D (psw / PSW_N) & 1; env->psw_v =3D -((psw / PSW_V) & 1); - env->psw_cb_msb =3D (psw >> 15) & 1; =20 +#if TARGET_REGISTER_BITS =3D=3D 32 + env->psw_cb_msb =3D (psw >> 15) & 1; +#else + env->psw_cb_msb =3D (psw >> 39) & 1; + cb |=3D ((psw >> 38) & 1) << 60; + cb |=3D ((psw >> 37) & 1) << 56; + cb |=3D ((psw >> 36) & 1) << 52; + cb |=3D ((psw >> 35) & 1) << 48; + cb |=3D ((psw >> 34) & 1) << 44; + cb |=3D ((psw >> 33) & 1) << 40; + cb |=3D ((psw >> 32) & 1) << 36; + cb |=3D ((psw >> 15) & 1) << 32; +#endif cb |=3D ((psw >> 14) & 1) << 28; cb |=3D ((psw >> 13) & 1) << 24; cb |=3D ((psw >> 12) & 1) << 20; --=20 2.34.1