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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834621; x=1698439421; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jy+spAs5u7WgOQZspkjRSxDs5g0jtQCLczTslsy9ExE=; b=hC8IZ3VinQnesMt+Lo0qkAAfWtu1W1+oc1WqznhSBsVZSP8JvQH84i7abk+qC1XArd 68ubvz804AEdxvOjO4B/7cjZYS5mpIthz+CI2d7LlzqSwfKbU41UPsUbL2vBiz7tGc7k 6uySOVzg1rgNh2jnfhJoI2MyFrSJBQcFKdO/jx8d3yLR33eEICZsoGC4pNFbBgAwKRLH do1Tt2+zvMt+tQSD7ue/641FoaDKsIVVpSuZ+U5cv6VxW1tbePDQTaU6CrVUYgFghHfn OTFBlJK7W9tgfA8dJOMqlbNr/+yTQVAewm57ebeBrK8TeDz92JoqVhsY1yCamNzeMGjt v3Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834621; x=1698439421; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jy+spAs5u7WgOQZspkjRSxDs5g0jtQCLczTslsy9ExE=; b=c2jFXilOmQ+y9g8hgiobAXczsMinA61rPfSaphDFYuE8bfGcFpCA5m4KwxywZLVK8d vK6g8F6IMcFT66ZbbRargW0Fipj2nHYwlgENHNDaaq+sdCEb1JY+v90frpqMK3XeyKRr Z7q8suJzotIf6GcpdGNntJKoCeokL5YmdadsZGfx4RsYO6eNDH6WgEQ5L+WHOmZRN2Qj t0q6qmG2LUzD8AyU3EnVHI2kKAYoZiC6mox/yu/2HliV/xBxq8bHkURNYKqOlekWNtHt t8NHaSrL2jEjavatyp/RWkmOm70ucrau1B9MoWN7UX6FS3hXEIpt7LE25JbCUeuz8dBO OrQA== X-Gm-Message-State: AOJu0Yza2pEjZJPdP0Roel7JZmpRxELUVTRdDW9ZqSPcj+dwq4EeIte1 RZRydY3GlBtl4v0W50uRLMqmNXxXoRHCUX37XJY= X-Google-Smtp-Source: AGHT+IHwfLE/aeY5SMA6wSXKTfQ4aQ0hqo/e1Hst9rbmUD6yqyrf0kMVrliJnmQVzRtRq6oRb0Q4PQ== X-Received: by 2002:a05:6a00:22c5:b0:6b4:c21c:8b56 with SMTP id f5-20020a056a0022c500b006b4c21c8b56mr3193565pfj.23.1697834621559; Fri, 20 Oct 2023 13:43:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 09/65] target/hppa: Fix trans_ds for hppa64 Date: Fri, 20 Oct 2023 13:42:35 -0700 Message-Id: <20231020204331.139847-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834928877100006 Content-Type: text/plain; charset="utf-8" This instruction always uses the input carry from bit 32, but produces all 16 output carry bits. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 48 +++++++++++++++++++++++++++++++---------- 1 file changed, 37 insertions(+), 11 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e6ab113a1c..fb7a295367 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -803,6 +803,12 @@ static bool cond_need_cb(int c) return c =3D=3D 4 || c =3D=3D 5; } =20 +/* Need extensions from TCGv_i32 to TCGv_reg. */ +static bool cond_need_ext(DisasContext *ctx, bool d) +{ + return TARGET_REGISTER_BITS =3D=3D 64 && !d; +} + /* * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of * the Parisc 1.1 Architecture Reference Manual for details. @@ -1040,6 +1046,22 @@ static DisasCond do_unit_cond(unsigned cf, TCGv_reg = res, return cond; } =20 +static TCGv_reg get_carry(DisasContext *ctx, bool d, + TCGv_reg cb, TCGv_reg cb_msb) +{ + if (cond_need_ext(ctx, d)) { + TCGv_reg t =3D tcg_temp_new(); + tcg_gen_extract_reg(t, cb, 32, 1); + return t; + } + return cb_msb; +} + +static TCGv_reg get_psw_carry(DisasContext *ctx, bool d) +{ + return get_carry(ctx, d, cpu_psw_cb, cpu_psw_cb_msb); +} + /* Compute signed overflow for addition. */ static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res, TCGv_reg in1, TCGv_reg in2) @@ -2712,6 +2734,7 @@ static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf= *a) static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) { TCGv_reg dest, add1, add2, addc, zero, in1, in2; + TCGv_reg cout; =20 nullify_over(ctx); =20 @@ -2726,18 +2749,20 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf = *a) =20 /* Form R1 << 1 | PSW[CB]{8}. */ tcg_gen_add_reg(add1, in1, in1); - tcg_gen_add_reg(add1, add1, cpu_psw_cb_msb); + tcg_gen_add_reg(add1, add1, get_psw_carry(ctx, false)); =20 - /* Add or subtract R2, depending on PSW[V]. Proper computation of - carry{8} requires that we subtract via + ~R2 + 1, as described in - the manual. By extracting and masking V, we can produce the - proper inputs to the addition without movcond. */ - tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1); + /* + * Add or subtract R2, depending on PSW[V]. Proper computation of + * carry requires that we subtract via + ~R2 + 1, as described in + * the manual. By extracting and masking V, we can produce the + * proper inputs to the addition without movcond. + */ + tcg_gen_sextract_reg(addc, cpu_psw_v, 31, 1); tcg_gen_xor_reg(add2, in2, addc); tcg_gen_andi_reg(addc, addc, 1); - /* ??? This is only correct for 32-bit. */ - tcg_gen_add2_i32(dest, cpu_psw_cb_msb, add1, zero, add2, zero); - tcg_gen_add2_i32(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zer= o); + + tcg_gen_add2_reg(dest, cpu_psw_cb_msb, add1, zero, add2, zero); + tcg_gen_add2_reg(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zer= o); =20 /* Write back the result register. */ save_gpr(ctx, a->t, dest); @@ -2747,7 +2772,8 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) tcg_gen_xor_reg(cpu_psw_cb, cpu_psw_cb, dest); =20 /* Write back PSW[V] for the division step. */ - tcg_gen_neg_reg(cpu_psw_v, cpu_psw_cb_msb); + cout =3D get_psw_carry(ctx, false); + tcg_gen_neg_reg(cpu_psw_v, cout); tcg_gen_xor_reg(cpu_psw_v, cpu_psw_v, in2); =20 /* Install the new nullification. */ @@ -2757,7 +2783,7 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) /* ??? The lshift is supposed to contribute to overflow. */ sv =3D do_add_sv(ctx, dest, add1, add2); } - ctx->null_cond =3D do_cond(a->cf, dest, cpu_psw_cb_msb, sv); + ctx->null_cond =3D do_cond(a->cf, dest, cout, sv); } =20 return nullify_end(ctx); --=20 2.34.1