From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697834667; cv=none; d=zohomail.com; s=zohoarc; b=VPRK9TG96jWm8U7TDHKcwWmISEZjcu3spIK8mwCggV4frcF2JWxoTIx48o+LWdMNl3+rLeQoWcuJ6/r5hE6SxIo2BqzY1im0B2zmB8o/uXZwO0pqdsXsMvRW2iKyoyKIRZczF+N3DC+/uwafsnYxhuNraNQjZSGzWcxJo3V6Xxo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697834667; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=J3OQEiXHHMGRWFPueeKCKBwMI85PiFBLtHqDQ0TceE8=; b=akn0oJJqLgMle4YK8V2hgiYNY5zC0edIfy/2Ri7g3qppfD2dl9NZf/fFJVFv2a15N+E5vYWQMt9fRR7uWS6dJfXHtfex4XDp0+Ul7xBFrvXke2WNybD1wtaBPbEGlcItVAHh9WQagrTIyw90EorBtg0htTx7e0Q1K7u2EJlyNp4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697834667147257.8871932810215; Fri, 20 Oct 2023 13:44:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwLL-0007fT-NV; Fri, 20 Oct 2023 16:43:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwLJ-0007ef-Jq for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:37 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwLH-000884-QV for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:37 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-6b77ab73c6fso996491b3a.1 for ; Fri, 20 Oct 2023 13:43:35 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834614; x=1698439414; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J3OQEiXHHMGRWFPueeKCKBwMI85PiFBLtHqDQ0TceE8=; b=j/h+rT+K17RJJ0J0tLcUmY3pXxuv+YNNE3tT8J7p2pes6ltTCKR5gDq7lEjTZ71XEG 1s3vr3w/KsPYPe71YwocADV0P1SmfqG2YebS+zoTg7I9mOxaFXP8PNmoY5Ul+mIhdb0T SaeiN/nz+Gseb8nk0/7qcKFixwX25zN0oPKbdnz90bRkvwkYkP+gmUhx4tmOcsXmqBxa ugQsxgtU1AUgvXGdFY5sSKMaog20eTGTP4AEm4vb82RbjVUiUecJ/ulBCC4qt8kfKhLF p5/AEOSXHL8efxodvy4qgnKSeeAVEk3zF6Gsm+YzlfSV4I+CG8Cg8P3KaNGtRXmu9n7J Sf+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834614; x=1698439414; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J3OQEiXHHMGRWFPueeKCKBwMI85PiFBLtHqDQ0TceE8=; b=HdJLOqvwAzs/VDm0rLUfURDGXrIDRStHTA9pKoM7D/z/anGYiWZV7s3pUHCU8/O61p MvTEjeR93ptZ6FQhz8pYNA2zjo+0gNGOcQ2NzPWuBRuIgsrGG19Rlqbcko/5QbwSmQF0 /o5Cx+wdG8fPta+6SXMx4DtmPCQIGroMXpjY4XIvS/Xa+o6a5g/sKEjObN0QHZCBODV1 NiCYimPIznSt9mUEBaZzbUDl0JqGr0ZkEJYHL6S1sskkvCIdQKixwPbKQ2wBqX7TecAE MVDkzxtpUa+r43Xj8uh/n3pRuDgEd6+K5BVR5WXQu++Z7nkbr00xx8NKD3P7AFzFjABt sfTw== X-Gm-Message-State: AOJu0YyxlpV+sjGLdu4KNW2q54to1Q2+U1S+SW8UXt8HtC5agbI4Jw+/ RQKlZG7u8R38kaYG7GliYfUjuKsDFpjSJ0AhJMY= X-Google-Smtp-Source: AGHT+IHY5gQsHQSYD+RUopRh4y+KWBG/a5CPdnmXVVnH12SqTy+Kn5dx0nWJfXBp7QIesIKrV8RMCQ== X-Received: by 2002:a05:6a00:1c8c:b0:68f:cdb8:ae33 with SMTP id y12-20020a056a001c8c00b0068fcdb8ae33mr8909450pfw.10.1697834614185; Fri, 20 Oct 2023 13:43:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 01/65] tcg: Improve expansion of deposit of constant Date: Fri, 20 Oct 2023 13:42:27 -0700 Message-Id: <20231020204331.139847-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834667989100001 Content-Type: text/plain; charset="utf-8" The extract2 expansion is too difficult for the optimizer to simplify. If we have an immediate input, use and+or instead, skipping the and if the field becomes all 1's. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 393dbcd01c..2ef4b866e2 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -602,6 +602,7 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, T= CGv_i32 arg2, { uint32_t mask; TCGv_i32 t1; + TCGTemp *ts; =20 tcg_debug_assert(ofs < 32); tcg_debug_assert(len > 0); @@ -617,6 +618,19 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, = TCGv_i32 arg2, return; } =20 + /* Deposit of a constant into a value. */ + ts =3D tcgv_i32_temp(arg2); + if (ts->kind =3D=3D TEMP_CONST) { + uint32_t mask0 =3D deposit32(-1, ofs, len, 0); + uint32_t maski =3D deposit32(0, ofs, len, ts->val); + + if (mask0 !=3D ~maski) { + tcg_gen_andi_i32(ret, arg1, mask0); + } + tcg_gen_ori_i32(ret, ret, maski); + return; + } + t1 =3D tcg_temp_ebb_new_i32(); =20 if (TCG_TARGET_HAS_extract2_i32) { @@ -2217,6 +2231,7 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,= TCGv_i64 arg2, { uint64_t mask; TCGv_i64 t1; + TCGTemp *ts; =20 tcg_debug_assert(ofs < 64); tcg_debug_assert(len > 0); @@ -2232,6 +2247,19 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1= , TCGv_i64 arg2, return; } =20 + /* Deposit of a constant into a value. */ + ts =3D tcgv_i64_temp(arg2); + if (ts->kind =3D=3D TEMP_CONST) { + uint64_t mask0 =3D deposit64(-1, ofs, len, 0); + uint64_t maski =3D deposit64(0, ofs, len, ts->val); + + if (mask0 !=3D ~maski) { + tcg_gen_andi_i64(ret, arg1, mask0); + } + tcg_gen_ori_i64(ret, ret, maski); + return; + } + if (TCG_TARGET_REG_BITS =3D=3D 32) { if (ofs >=3D 32) { tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697834667; cv=none; d=zohomail.com; s=zohoarc; b=Y4HGvmp6eJZZQ9nrhpoaYRow9oAd7fYxHJXwnf34JMhIofmCKViuBDDrQvzYWKA89I1+ieR2FYbDDEuWLN9nfFogMgUONfeGnn8IyjrCJVxUVrQR1ugUTAc6JR/RVILNAl1uRUkNspIFu0VZbd6HBXR6iHzHmopFQN/Xfu0/Yxk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697834667; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2zsMSRhlbZwVzQVen6DKnQDDskBCrZAwA6YeAeDVn/c=; b=O5pIzPUQe5tMx2++zEQWuhxhyMWff+EuReTUN+e0vMpUk3cbnB3UugG3DFREodDkZuZeQLSKwUQ3AkJ77Cs8TUP9Z+6lDWCdsQX8tOaaVz6euItTPi2KeiSMsJxrI15GIXcamNr10P7WVm4K+G3ylpfGD1mkX8nu2zLKAU3K+XI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697834666997324.005085764624; Fri, 20 Oct 2023 13:44:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwLQ-0007hH-EF; Fri, 20 Oct 2023 16:43:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwLL-0007fP-Fb for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:39 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwLJ-00088B-DD for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:39 -0400 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-6b9af7d41d2so1253114b3a.0 for ; Fri, 20 Oct 2023 13:43:37 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834615; x=1698439415; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2zsMSRhlbZwVzQVen6DKnQDDskBCrZAwA6YeAeDVn/c=; b=xYdEHX353qnw1YqndbLVA53rMSjfEm0aJfZHoW/8+UZvismFWM9wgN0GQPw/g2q/ci hJVwC6+GqhZUlMw3fckshKHDxBYEM94RLba2SmfFm34fzLm3cHYfUwWb5X64dC1QisnD GEUoPMpPrXJifYrgf3vJFWLCWPZHMXiwQgSPvY8hga2jddyFnRXP/leqRj8Zy/al4wO1 mV+rmYrBxBAmw3PRiIsUL14Q2nSUkCYYbi7gDxIQjLHxw5e89fMDXyPSHMR7TPkQqw6E HeFhddoz6DkGeP3s32n7P6nCaqcEq1hXyqsL0dSdLqzDIFK4tCbKvmwaLwIScsv4jgBB NBvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834615; x=1698439415; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2zsMSRhlbZwVzQVen6DKnQDDskBCrZAwA6YeAeDVn/c=; b=wvlpSAVG/HU4LAHbDZMZQ2maHqlP8l/UVL8tvVb8BhVDehIH486L0Bgw3c4DCNGpbd +evkqGLsKyjL9iDFP7TrFJSqZTC0opXB6nVWb5rb2gVRi+n9ZjvoBHwex6RpZwyoG/2I moEf0wy37ICgLIQ02Zr6ZLsE8a15qTS2VXSVAzkblm2LB5eIXMi+VpWv4qexK8/vk7/R iBSnWX/2S9kB8MI3xiDMkerKObM8D1pz4XRAXHEXho/wdF7FCqpFclCT+v/ygETfdotp cGqgPwddTQrSqgvQcRp2Puywjdpk0YIWcrWqL7qLtzEOmdl3TsKau1PbAaKly0pyyAYl rkPQ== X-Gm-Message-State: AOJu0YxBAv8GHpwEpFBDs52/iWk7W/p/61xGea7GyMuC7r37b0vgov3i nJQTr2+QFwBCnLYLnnxLYGysjrSiQ3Ym0sR+PW8= X-Google-Smtp-Source: AGHT+IEjYQOMPArhPrF0UiRjWZYzveHBmKchjORI0BYG/7QnMb3N6Pedu7ntykgjquRMYWAQ9zwcSg== X-Received: by 2002:a05:6a20:1604:b0:14e:43b0:5f99 with SMTP id l4-20020a056a20160400b0014e43b05f99mr2903499pzj.52.1697834615290; Fri, 20 Oct 2023 13:43:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 02/65] tcg: Improve expansion of deposit into a constant Date: Fri, 20 Oct 2023 13:42:28 -0700 Message-Id: <20231020204331.139847-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834668075100005 Content-Type: text/plain; charset="utf-8" Generalize tcg_gen_deposit_z_* from 0 to any constant. Use this to automatically simplify tcg_gen_deposit_*. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 295 ++++++++++++++++++++++++++++++--------------------- 1 file changed, 174 insertions(+), 121 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 2ef4b866e2..049b684ccc 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -597,6 +597,70 @@ void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, in= t32_t arg2) } } =20 +static void tcg_gen_deposit_i_i32(TCGv_i32 ret, uint32_t i, TCGv_i32 arg, + unsigned int ofs, unsigned int len) +{ + i =3D deposit32(i, ofs, len, 0); + + if (ofs + len =3D=3D 32) { + tcg_gen_shli_i32(ret, arg, ofs); + goto finish; + } + if (ofs =3D=3D 0) { + tcg_gen_andi_i32(ret, arg, (1u << len) - 1); + goto finish; + } + if (TCG_TARGET_HAS_deposit_i32 + && TCG_TARGET_deposit_i32_valid(ofs, len)) { + tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, + tcg_constant_i32(i), arg, ofs, len); + return; + } + + /* + * To help two-operand hosts we prefer to zero-extend first, + * which allows ARG to stay live. + */ + switch (len) { + case 16: + if (TCG_TARGET_HAS_ext16u_i32) { + tcg_gen_ext16u_i32(ret, arg); + tcg_gen_shli_i32(ret, ret, ofs); + goto finish; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8u_i32) { + tcg_gen_ext8u_i32(ret, arg); + tcg_gen_shli_i32(ret, ret, ofs); + goto finish; + } + break; + } + /* Otherwise prefer zero-extension over AND for code size. */ + switch (ofs + len) { + case 16: + if (TCG_TARGET_HAS_ext16u_i32) { + tcg_gen_shli_i32(ret, arg, ofs); + tcg_gen_ext16u_i32(ret, ret); + goto finish; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8u_i32) { + tcg_gen_shli_i32(ret, arg, ofs); + tcg_gen_ext8u_i32(ret, ret); + goto finish; + } + break; + } + tcg_gen_andi_i32(ret, arg, (1u << len) - 1); + tcg_gen_shli_i32(ret, ret, ofs); + + finish: + tcg_gen_ori_i32(ret, ret, i); +} + void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, unsigned int ofs, unsigned int len) { @@ -613,6 +677,14 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, = TCGv_i32 arg2, tcg_gen_mov_i32(ret, arg2); return; } + + /* Deposit of a value into a constant. */ + ts =3D tcgv_i32_temp(arg1); + if (ts->kind =3D=3D TEMP_CONST) { + tcg_gen_deposit_i_i32(ret, ts->val, arg2, ofs, len); + return; + } + if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, le= n)) { tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len); return; @@ -667,53 +739,7 @@ void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, tcg_debug_assert(len <=3D 32); tcg_debug_assert(ofs + len <=3D 32); =20 - if (ofs + len =3D=3D 32) { - tcg_gen_shli_i32(ret, arg, ofs); - } else if (ofs =3D=3D 0) { - tcg_gen_andi_i32(ret, arg, (1u << len) - 1); - } else if (TCG_TARGET_HAS_deposit_i32 - && TCG_TARGET_deposit_i32_valid(ofs, len)) { - TCGv_i32 zero =3D tcg_constant_i32(0); - tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, zero, arg, ofs, len); - } else { - /* To help two-operand hosts we prefer to zero-extend first, - which allows ARG to stay live. */ - switch (len) { - case 16: - if (TCG_TARGET_HAS_ext16u_i32) { - tcg_gen_ext16u_i32(ret, arg); - tcg_gen_shli_i32(ret, ret, ofs); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i32) { - tcg_gen_ext8u_i32(ret, arg); - tcg_gen_shli_i32(ret, ret, ofs); - return; - } - break; - } - /* Otherwise prefer zero-extension over AND for code size. */ - switch (ofs + len) { - case 16: - if (TCG_TARGET_HAS_ext16u_i32) { - tcg_gen_shli_i32(ret, arg, ofs); - tcg_gen_ext16u_i32(ret, ret); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i32) { - tcg_gen_shli_i32(ret, arg, ofs); - tcg_gen_ext8u_i32(ret, ret); - return; - } - break; - } - tcg_gen_andi_i32(ret, arg, (1u << len) - 1); - tcg_gen_shli_i32(ret, ret, ofs); - } + tcg_gen_deposit_i_i32(ret, 0, arg, ofs, len); } =20 void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, @@ -2226,6 +2252,98 @@ void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, = int64_t arg2) } } =20 +static void tcg_gen_deposit_i_i64(TCGv_i64 ret, uint64_t i, TCGv_i64 arg, + unsigned int ofs, unsigned int len) +{ + i =3D deposit64(i, ofs, len, 0); + + if (ofs + len =3D=3D 64) { + tcg_gen_shli_i64(ret, arg, ofs); + goto finish; + } + if (ofs =3D=3D 0) { + tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); + goto finish; + } + if (TCG_TARGET_HAS_deposit_i64 + && TCG_TARGET_deposit_i64_valid(ofs, len)) { + tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, + tcg_constant_i64(i), arg, ofs, len); + return; + } + + if (TCG_TARGET_REG_BITS =3D=3D 32) { + if (ofs >=3D 32) { + tcg_gen_deposit_i_i32(TCGV_HIGH(ret), i >> 32, + TCGV_LOW(arg), ofs - 32, len); + tcg_gen_movi_i32(TCGV_LOW(ret), i); + return; + } + if (ofs + len <=3D 32) { + tcg_gen_deposit_i_i32(TCGV_LOW(ret), i, TCGV_LOW(arg), ofs, le= n); + tcg_gen_movi_i32(TCGV_HIGH(ret), i >> 32); + return; + } + } + + /* + * To help two-operand hosts we prefer to zero-extend first, + * which allows ARG to stay live. + */ + switch (len) { + case 32: + if (TCG_TARGET_HAS_ext32u_i64) { + tcg_gen_ext32u_i64(ret, arg); + tcg_gen_shli_i64(ret, ret, ofs); + goto finish; + } + break; + case 16: + if (TCG_TARGET_HAS_ext16u_i64) { + tcg_gen_ext16u_i64(ret, arg); + tcg_gen_shli_i64(ret, ret, ofs); + goto finish; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8u_i64) { + tcg_gen_ext8u_i64(ret, arg); + tcg_gen_shli_i64(ret, ret, ofs); + goto finish; + } + break; + } + /* Otherwise prefer zero-extension over AND for code size. */ + switch (ofs + len) { + case 32: + if (TCG_TARGET_HAS_ext32u_i64) { + tcg_gen_shli_i64(ret, arg, ofs); + tcg_gen_ext32u_i64(ret, ret); + goto finish; + } + break; + case 16: + if (TCG_TARGET_HAS_ext16u_i64) { + tcg_gen_shli_i64(ret, arg, ofs); + tcg_gen_ext16u_i64(ret, ret); + goto finish; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8u_i64) { + tcg_gen_shli_i64(ret, arg, ofs); + tcg_gen_ext8u_i64(ret, ret); + goto finish; + } + break; + } + tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); + tcg_gen_shli_i64(ret, ret, ofs); + + finish: + tcg_gen_ori_i64(ret, ret, i); +} + void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, unsigned int ofs, unsigned int len) { @@ -2242,6 +2360,14 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1= , TCGv_i64 arg2, tcg_gen_mov_i64(ret, arg2); return; } + + /* Deposit of a value into a constant. */ + ts =3D tcgv_i64_temp(arg1); + if (ts->kind =3D=3D TEMP_CONST) { + tcg_gen_deposit_i_i64(ret, ts->val, arg2, ofs, len); + return; + } + if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, le= n)) { tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len); return; @@ -2311,80 +2437,7 @@ void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 ar= g, tcg_debug_assert(len <=3D 64); tcg_debug_assert(ofs + len <=3D 64); =20 - if (ofs + len =3D=3D 64) { - tcg_gen_shli_i64(ret, arg, ofs); - } else if (ofs =3D=3D 0) { - tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); - } else if (TCG_TARGET_HAS_deposit_i64 - && TCG_TARGET_deposit_i64_valid(ofs, len)) { - TCGv_i64 zero =3D tcg_constant_i64(0); - tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, zero, arg, ofs, len); - } else { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - if (ofs >=3D 32) { - tcg_gen_deposit_z_i32(TCGV_HIGH(ret), TCGV_LOW(arg), - ofs - 32, len); - tcg_gen_movi_i32(TCGV_LOW(ret), 0); - return; - } - if (ofs + len <=3D 32) { - tcg_gen_deposit_z_i32(TCGV_LOW(ret), TCGV_LOW(arg), ofs, l= en); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - return; - } - } - /* To help two-operand hosts we prefer to zero-extend first, - which allows ARG to stay live. */ - switch (len) { - case 32: - if (TCG_TARGET_HAS_ext32u_i64) { - tcg_gen_ext32u_i64(ret, arg); - tcg_gen_shli_i64(ret, ret, ofs); - return; - } - break; - case 16: - if (TCG_TARGET_HAS_ext16u_i64) { - tcg_gen_ext16u_i64(ret, arg); - tcg_gen_shli_i64(ret, ret, ofs); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i64) { - tcg_gen_ext8u_i64(ret, arg); - tcg_gen_shli_i64(ret, ret, ofs); - return; - } - break; - } - /* Otherwise prefer zero-extension over AND for code size. */ - switch (ofs + len) { - case 32: - if (TCG_TARGET_HAS_ext32u_i64) { - tcg_gen_shli_i64(ret, arg, ofs); - tcg_gen_ext32u_i64(ret, ret); - return; - } - break; - case 16: - if (TCG_TARGET_HAS_ext16u_i64) { - tcg_gen_shli_i64(ret, arg, ofs); - tcg_gen_ext16u_i64(ret, ret); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i64) { - tcg_gen_shli_i64(ret, arg, ofs); - tcg_gen_ext8u_i64(ret, ret); - return; - } - break; - } - tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); - tcg_gen_shli_i64(ret, ret, ofs); - } + tcg_gen_deposit_i_i64(ret, 0, arg, ofs, len); } =20 void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835039; cv=none; d=zohomail.com; s=zohoarc; b=QHQuoH2Pl0cUKA7W1w4oi368mfbUibvjWmMn+hhW6V8G546YvkiPYNR5NHkO7pPTn6sqFDW8PQMzsJ1vGit+qByDvvfVy9wrlwICtCliSARVjukOI1r/BLybw6HlJYKJTlYtyleszDrqQDKvAS19EJ7j9sP3wwA8QXjnoL3jaig= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834616; x=1698439416; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EEVa0UToFhXataikrG28OSq2vCy6h8vLUqtzrSHrlk8=; b=FiHA/uDIV9XFAaj/zdJdSGoX9N3o6t0QR/JKVxJ7t5lYAvXGCpHAlAi7keRiYBCuS3 P0baMmmC3SBR1lSn3MSrDCDQrqizc8GOt1ftrQAb0vcWtVEpeJ+nTSVHylyVvXtJgnP2 FtUbPMGgoQTFd5r6c4HsJaRuuCD9kyYZkKay8kdPej5hbd5XfNxIg7CeD8wlanNVvaQZ 7xQYK2rUEv3tgA219/BRt1yuT80ryOLcSq+7vTyR5wxEwy1psDv1ZofZtGt/Z4UiODPE FD5zF+QhxxEOSWaArdwg9MEZE0hvwZUSQUSzjtp9nT+fPrciM6alcZCwmjs3Mio+a5nw Er1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834616; x=1698439416; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EEVa0UToFhXataikrG28OSq2vCy6h8vLUqtzrSHrlk8=; b=gNaRuw+SUG8oYRmzip9UQh4InYorUHVdW51ALXFyEC6NW59O+ZE7pmMCeMCr4B7vJh ABeg6QaSky0rXp0zz7MQt+oqO48/+HNzcwUdPIFyaMhIZ9U1pQnlkOc6MvwumeiYV3nm BrK3UQ1nFWgR9j3NX1t/0jIyCdhCr5IWvgyb9aTu5TtOjFCJZ26nrZt6PQlTa49mzae2 9dupmWU1oWrU3SAwGka6mu6gEg6zsMTeewLReLX6BgjNFx0rY+9GtsoRwwTQeId0Inax RQ/LPi3sNR1bU9Ja+d/VDjGVR5AWJh3u8gwQlCuu5XqemFN8k4TJT7zPAeCwyMy4IXWy BjVA== X-Gm-Message-State: AOJu0YwBOunYQ5ZRnbTB7/egF1s8SZiK5bd2D10NhZoOjprEo9uKCt94 w9M38NQgnY6DUSeZ/km6SyqUzejXQ5yizFVver4= X-Google-Smtp-Source: AGHT+IHBySjp39F5QRjMzZcRNV5AnkAKKw5Fjd+Cf5YPZ9KqiQ11w6o2tT+71q7/IPvcbvM1u1t97w== X-Received: by 2002:a05:6a00:194c:b0:6b7:18c1:c09a with SMTP id s12-20020a056a00194c00b006b718c1c09amr2737723pfk.5.1697834616278; Fri, 20 Oct 2023 13:43:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 03/65] target/hppa: Remove get_temp Date: Fri, 20 Oct 2023 13:42:29 -0700 Message-Id: <20231020204331.139847-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835041056100003 Replace with tcg_temp_new without recording into ctx. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/hppa/translate.c | 76 +++++++++++++++++------------------------ 1 file changed, 31 insertions(+), 45 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 9f3ba9f42f..3065fbf625 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -254,8 +254,7 @@ typedef struct DisasContext { target_ureg iaoq_n; TCGv_reg iaoq_n_var; =20 - int ntempr, ntempl; - TCGv_reg tempr[8]; + int ntempl; TCGv_tl templ[4]; =20 DisasCond null_cond; @@ -492,13 +491,6 @@ static void cond_free(DisasCond *cond) } } =20 -static TCGv_reg get_temp(DisasContext *ctx) -{ - unsigned i =3D ctx->ntempr++; - g_assert(i < ARRAY_SIZE(ctx->tempr)); - return ctx->tempr[i] =3D tcg_temp_new(); -} - #ifndef CONFIG_USER_ONLY static TCGv_tl get_temp_tl(DisasContext *ctx) { @@ -510,7 +502,7 @@ static TCGv_tl get_temp_tl(DisasContext *ctx) =20 static TCGv_reg load_const(DisasContext *ctx, target_sreg v) { - TCGv_reg t =3D get_temp(ctx); + TCGv_reg t =3D tcg_temp_new(); tcg_gen_movi_reg(t, v); return t; } @@ -518,7 +510,7 @@ static TCGv_reg load_const(DisasContext *ctx, target_sr= eg v) static TCGv_reg load_gpr(DisasContext *ctx, unsigned reg) { if (reg =3D=3D 0) { - TCGv_reg t =3D get_temp(ctx); + TCGv_reg t =3D tcg_temp_new(); tcg_gen_movi_reg(t, 0); return t; } else { @@ -529,7 +521,7 @@ static TCGv_reg load_gpr(DisasContext *ctx, unsigned re= g) static TCGv_reg dest_gpr(DisasContext *ctx, unsigned reg) { if (reg =3D=3D 0 || ctx->null_cond.c !=3D TCG_COND_NEVER) { - return get_temp(ctx); + return tcg_temp_new(); } else { return cpu_gr[reg]; } @@ -1071,7 +1063,7 @@ static DisasCond do_unit_cond(unsigned cf, TCGv_reg r= es, static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res, TCGv_reg in1, TCGv_reg in2) { - TCGv_reg sv =3D get_temp(ctx); + TCGv_reg sv =3D tcg_temp_new(); TCGv_reg tmp =3D tcg_temp_new(); =20 tcg_gen_xor_reg(sv, res, in1); @@ -1085,7 +1077,7 @@ static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg= res, static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_reg res, TCGv_reg in1, TCGv_reg in2) { - TCGv_reg sv =3D get_temp(ctx); + TCGv_reg sv =3D tcg_temp_new(); TCGv_reg tmp =3D tcg_temp_new(); =20 tcg_gen_xor_reg(sv, res, in1); @@ -1108,20 +1100,20 @@ static void do_add(DisasContext *ctx, unsigned rt, = TCGv_reg in1, cb_msb =3D NULL; =20 if (shift) { - tmp =3D get_temp(ctx); + tmp =3D tcg_temp_new(); tcg_gen_shli_reg(tmp, in1, shift); in1 =3D tmp; } =20 if (!is_l || cond_need_cb(c)) { TCGv_reg zero =3D tcg_constant_reg(0); - cb_msb =3D get_temp(ctx); + cb_msb =3D tcg_temp_new(); tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero); if (is_c) { tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, z= ero); } if (!is_l) { - cb =3D get_temp(ctx); + cb =3D tcg_temp_new(); tcg_gen_xor_reg(cb, in1, in2); tcg_gen_xor_reg(cb, cb, dest); } @@ -1414,11 +1406,11 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pg= va, TCGv_reg *pofs, =20 /* Note that RX is mutually exclusive with DISP. */ if (rx) { - ofs =3D get_temp(ctx); + ofs =3D tcg_temp_new(); tcg_gen_shli_reg(ofs, cpu_gr[rx], scale); tcg_gen_add_reg(ofs, ofs, base); } else if (disp || modify) { - ofs =3D get_temp(ctx); + ofs =3D tcg_temp_new(); tcg_gen_addi_reg(ofs, base, disp); } else { ofs =3D base; @@ -1538,7 +1530,7 @@ static bool do_load(DisasContext *ctx, unsigned rt, u= nsigned rb, dest =3D dest_gpr(ctx, rt); } else { /* Make sure if RT =3D=3D RB, we see the result of the load. */ - dest =3D get_temp(ctx); + dest =3D tcg_temp_new(); } do_load_reg(ctx, dest, rb, rx, scale, disp, sp, modify, mop); save_gpr(ctx, rt, dest); @@ -1854,7 +1846,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg de= st, if (link !=3D 0) { copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); } - next =3D get_temp(ctx); + next =3D tcg_temp_new(); tcg_gen_mov_reg(next, dest); if (is_n) { if (use_nullify_skip(ctx)) { @@ -1896,7 +1888,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg de= st, a1 =3D ctx->null_cond.a1; =20 tmp =3D tcg_temp_new(); - next =3D get_temp(ctx); + next =3D tcg_temp_new(); =20 copy_iaoq_entry(tmp, ctx->iaoq_n, ctx->iaoq_n_var); tcg_gen_movcond_reg(c, next, a0, a1, tmp, dest); @@ -1938,11 +1930,11 @@ static TCGv_reg do_ibranch_priv(DisasContext *ctx, = TCGv_reg offset) return offset; case 3: /* Privilege 3 is minimum and is never allowed to increase. */ - dest =3D get_temp(ctx); + dest =3D tcg_temp_new(); tcg_gen_ori_reg(dest, offset, 3); break; default: - dest =3D get_temp(ctx); + dest =3D tcg_temp_new(); tcg_gen_andi_reg(dest, offset, -4); tcg_gen_ori_reg(dest, dest, ctx->privilege); tcg_gen_movcond_reg(TCG_COND_GTU, dest, dest, offset, dest, offset= ); @@ -2104,7 +2096,7 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl = *a) break; } =20 - tmp =3D get_temp(ctx); + tmp =3D tcg_temp_new(); tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); save_gpr(ctx, rt, tmp); =20 @@ -2177,7 +2169,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl = *a) case CR_IIAOQ: /* FIXME: Respect PSW_Q bit */ /* The write advances the queue and stores to the back element. */ - tmp =3D get_temp(ctx); + tmp =3D tcg_temp_new(); tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); tcg_gen_st_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); @@ -2243,7 +2235,7 @@ static bool trans_rsm(DisasContext *ctx, arg_rsm *a) =20 nullify_over(ctx); =20 - tmp =3D get_temp(ctx); + tmp =3D tcg_temp_new(); tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw)); tcg_gen_andi_reg(tmp, tmp, ~a->i); gen_helper_swap_system_mask(tmp, tcg_env, tmp); @@ -2263,7 +2255,7 @@ static bool trans_ssm(DisasContext *ctx, arg_ssm *a) =20 nullify_over(ctx); =20 - tmp =3D get_temp(ctx); + tmp =3D tcg_temp_new(); tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw)); tcg_gen_ori_reg(tmp, tmp, a->i); gen_helper_swap_system_mask(tmp, tcg_env, tmp); @@ -2283,7 +2275,7 @@ static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a) nullify_over(ctx); =20 reg =3D load_gpr(ctx, a->r); - tmp =3D get_temp(ctx); + tmp =3D tcg_temp_new(); gen_helper_swap_system_mask(tmp, tcg_env, reg); =20 /* Exit the TB to recognize new interrupts. */ @@ -2692,7 +2684,7 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf *= a, bool is_tc) } tcg_r1 =3D load_gpr(ctx, a->r1); tcg_r2 =3D load_gpr(ctx, a->r2); - tmp =3D get_temp(ctx); + tmp =3D tcg_temp_new(); tcg_gen_not_reg(tmp, tcg_r2); do_unit(ctx, a->t, tcg_r1, tmp, a->cf, is_tc, tcg_gen_add_reg); return nullify_end(ctx); @@ -2714,7 +2706,7 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf *a, = bool is_i) =20 nullify_over(ctx); =20 - tmp =3D get_temp(ctx); + tmp =3D tcg_temp_new(); tcg_gen_shri_reg(tmp, cpu_psw_cb, 3); if (!is_i) { tcg_gen_not_reg(tmp, tmp); @@ -2866,7 +2858,7 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) if (a->m) { /* Base register modification. Make sure if RT =3D=3D RB, we see the result of the load. */ - dest =3D get_temp(ctx); + dest =3D tcg_temp_new(); } else { dest =3D dest_gpr(ctx, a->t); } @@ -2992,7 +2984,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TC= Gv_reg in1, DisasCond cond; =20 in2 =3D load_gpr(ctx, r); - dest =3D get_temp(ctx); + dest =3D tcg_temp_new(); =20 tcg_gen_sub_reg(dest, in1, in2); =20 @@ -3029,7 +3021,7 @@ static bool do_addb(DisasContext *ctx, unsigned r, TC= Gv_reg in1, cb_msb =3D NULL; =20 if (cond_need_cb(c)) { - cb_msb =3D get_temp(ctx); + cb_msb =3D tcg_temp_new(); tcg_gen_movi_reg(cb_msb, 0); tcg_gen_add2_reg(dest, cb_msb, in1, cb_msb, in2, cb_msb); } else { @@ -3388,7 +3380,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a) nullify_over(ctx); #endif =20 - tmp =3D get_temp(ctx); + tmp =3D tcg_temp_new(); tcg_gen_addi_reg(tmp, load_gpr(ctx, a->b), a->disp); tmp =3D do_ibranch_priv(ctx, tmp); =20 @@ -3485,7 +3477,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gat= e *a) static bool trans_blr(DisasContext *ctx, arg_blr *a) { if (a->x) { - TCGv_reg tmp =3D get_temp(ctx); + TCGv_reg tmp =3D tcg_temp_new(); tcg_gen_shli_reg(tmp, load_gpr(ctx, a->x), 3); tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8); /* The computation here never changes privilege level. */ @@ -3503,7 +3495,7 @@ static bool trans_bv(DisasContext *ctx, arg_bv *a) if (a->x =3D=3D 0) { dest =3D load_gpr(ctx, a->b); } else { - dest =3D get_temp(ctx); + dest =3D tcg_temp_new(); tcg_gen_shli_reg(dest, load_gpr(ctx, a->x), 3); tcg_gen_add_reg(dest, dest, load_gpr(ctx, a->b)); } @@ -3834,7 +3826,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest = *a) =20 nullify_over(ctx); =20 - t =3D get_temp(ctx); + t =3D tcg_temp_new(); tcg_gen_ld32u_reg(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow)); =20 if (a->y =3D=3D 1) { @@ -4089,9 +4081,7 @@ static void hppa_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; ctx->base.max_insns =3D MIN(ctx->base.max_insns, bound); =20 - ctx->ntempr =3D 0; ctx->ntempl =3D 0; - memset(ctx->tempr, 0, sizeof(ctx->tempr)); memset(ctx->templ, 0, sizeof(ctx->templ)); } =20 @@ -4140,7 +4130,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) This will be overwritten by a branch. */ if (ctx->iaoq_b =3D=3D -1) { ctx->iaoq_n =3D -1; - ctx->iaoq_n_var =3D get_temp(ctx); + ctx->iaoq_n_var =3D tcg_temp_new(); tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); } else { ctx->iaoq_n =3D ctx->iaoq_b + 4; @@ -4161,13 +4151,9 @@ static void hppa_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cs) } =20 /* Forget any temporaries allocated. */ - for (i =3D 0, n =3D ctx->ntempr; i < n; ++i) { - ctx->tempr[i] =3D NULL; - } for (i =3D 0, n =3D ctx->ntempl; i < n; ++i) { ctx->templ[i] =3D NULL; } - ctx->ntempr =3D 0; ctx->ntempl =3D 0; =20 /* Advance the insn queue. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834617; x=1698439417; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cad+KwQheUGAcPjvv3O2I1LwfS0pIqR17J6IWZnIATQ=; b=yrLd8elnFUXOPkMWbt7snigo7S8/mpPGXZad+c4iuMVkhqRUTENPF2vKEvl4tjGCry 2n7SRxex6CoPTmXwo5WMnyhhcmmUpR5OMOaxD0wxwQOuMPPiWtI3DhYos9d9tV/jardS 0tI3eRNSNyD2MTN3AFwBceYkk1FdpPvFlZiF6AxmMbu9MuJyGMea1+ScVB1rN9y5MwuH vafhPBL7/fEt+QJq62M2iOxvhH3qouARVbcVfDOT/ywvAFYV3m9jH59Ajk7D79encrv2 ZDb+C+unTvHHVfQvFiOXhwyQ+W1/e+zcD0ABkO9ToNfCKiHSrWGjMuJwn1CqwTpQpse0 6W8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834617; x=1698439417; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cad+KwQheUGAcPjvv3O2I1LwfS0pIqR17J6IWZnIATQ=; b=TRy2IkE9v3W+Kgr8SZgqm3zgpxrAaoBx+a0fgdXYuoe/YaQIe9yomuKfuLQHmU36bn /7aRsxmQ6wMCzrr04/nl1W++2SWW72rxr3zkIj6Few5yNKHlAipgCUEGOiEkKfQLzKEz vFYo/6gE3h1xwyp8/JTrspgjbgeYLlsFTqDSJ/M+Ay31NkTweVQ+1UN4wz7wOLmN4MaD uS2fZZxBVN/oaEy0o8WH2Yx+Q0YKR+EX3l2P4gbUFlP30lhBfIQiur3v8afbRyx20/wR AjBl66P2/3TItTgR/8UKr7CF/1dbqbRCngJIj/yzOZ7Gz8FUvoWX/EqMIVSs6CyetArw W/Yg== X-Gm-Message-State: AOJu0YzKCkwy4BF6efVy0WhVqpmBL4J4JXPWvfikuwT0XkqTXpNhKSLi 2XopIZ46E1onWTUqXiQ/j21b0MPFg1sGDwgKAMI= X-Google-Smtp-Source: AGHT+IEpELimzyakNmbobOsPfsNo4t6ny6h8iQF5fJ6ErPUND8CVBNMIlycwWvxhNf9peNjxV/nJ2Q== X-Received: by 2002:a05:6a20:e125:b0:f0:50c4:4c43 with SMTP id kr37-20020a056a20e12500b000f050c44c43mr4314914pzb.5.1697834617169; Fri, 20 Oct 2023 13:43:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 04/65] target/hppa: Remove get_temp_tl Date: Fri, 20 Oct 2023 13:42:30 -0700 Message-Id: <20231020204331.139847-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834900645100007 Replace with tcg_temp_new_tl without recording into ctx. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/hppa/translate.c | 28 +++------------------------- 1 file changed, 3 insertions(+), 25 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3065fbf625..5302381a56 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -254,9 +254,6 @@ typedef struct DisasContext { target_ureg iaoq_n; TCGv_reg iaoq_n_var; =20 - int ntempl; - TCGv_tl templ[4]; - DisasCond null_cond; TCGLabel *null_lab; =20 @@ -491,15 +488,6 @@ static void cond_free(DisasCond *cond) } } =20 -#ifndef CONFIG_USER_ONLY -static TCGv_tl get_temp_tl(DisasContext *ctx) -{ - unsigned i =3D ctx->ntempl++; - g_assert(i < ARRAY_SIZE(ctx->templ)); - return ctx->templ[i] =3D tcg_temp_new_tl(); -} -#endif - static TCGv_reg load_const(DisasContext *ctx, target_sreg v) { TCGv_reg t =3D tcg_temp_new(); @@ -1374,7 +1362,7 @@ static TCGv_i64 space_select(DisasContext *ctx, int s= p, TCGv_reg base) if (sp < 0) { sp =3D ~sp; } - spc =3D get_temp_tl(ctx); + spc =3D tcg_temp_new_tl(); load_spr(ctx, spc, sp); return spc; } @@ -1384,7 +1372,7 @@ static TCGv_i64 space_select(DisasContext *ctx, int s= p, TCGv_reg base) =20 ptr =3D tcg_temp_new_ptr(); tmp =3D tcg_temp_new(); - spc =3D get_temp_tl(ctx); + spc =3D tcg_temp_new_tl(); =20 tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5); tcg_gen_andi_reg(tmp, tmp, 030); @@ -1420,7 +1408,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva= , TCGv_reg *pofs, #ifdef CONFIG_USER_ONLY *pgva =3D (modify <=3D 0 ? ofs : base); #else - TCGv_tl addr =3D get_temp_tl(ctx); + TCGv_tl addr =3D tcg_temp_new_tl(); tcg_gen_extu_reg_tl(addr, modify <=3D 0 ? ofs : base); if (ctx->tb_flags & PSW_W) { tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); @@ -4080,9 +4068,6 @@ static void hppa_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) /* Bound the number of instructions by those left on the page. */ bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; ctx->base.max_insns =3D MIN(ctx->base.max_insns, bound); - - ctx->ntempl =3D 0; - memset(ctx->templ, 0, sizeof(ctx->templ)); } =20 static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) @@ -4111,7 +4096,6 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUHPPAState *env =3D cpu_env(cs); DisasJumpType ret; - int i, n; =20 /* Execute one insn. */ #ifdef CONFIG_USER_ONLY @@ -4150,12 +4134,6 @@ static void hppa_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cs) } } =20 - /* Forget any temporaries allocated. */ - for (i =3D 0, n =3D ctx->ntempl; i < n; ++i) { - ctx->templ[i] =3D NULL; - } - ctx->ntempl =3D 0; - /* Advance the insn queue. Note that this check also detects a priority change within the instruction queue. */ if (ret =3D=3D DISAS_NEXT && ctx->iaoq_b !=3D ctx->iaoq_f + 4) { --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835052; cv=none; d=zohomail.com; s=zohoarc; b=NEbYQlmdvkYqV1CyX99CY8ECdvJ5mjqXvhbepqe17vOnih3dlYf+3yuDe9rC8umi9hwJ0v+AiPSCR+dWIH5e+b0M6cODjR75UYS6zILp6rTvkoIxQtji3Jav13rLqBS1YxqXgZSUMNXCKcB8nxwPYEW9pyFnL3u9iQ+Biwj4fqM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697835052; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mNZMizemvrujc4XnqyNiXy5WpOSPf3XvMMBFfWR0das=; b=RAPpfMUDNuQLGgCP2TgTXk0NiXCXyZ+bQJbMThYMs8pLpufvx/StPEbR5Vi3v8ll4sI/XhLmBzq3vwOzPpjJR+luAvTRbIG+zHZhAiKy9DqA4Z9YcENE3PD7Z6DDHKZsIX3hgUed5YW+BNzYcF9luusWOp3QyIxGIBdcDxbbKRg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697835052274173.9573417516068; Fri, 20 Oct 2023 13:50:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwLq-0007oi-Ex; Fri, 20 Oct 2023 16:44:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwLN-0007hh-Pp for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:42 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwLM-00088k-53 for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:41 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-6be0277c05bso1102452b3a.0 for ; Fri, 20 Oct 2023 13:43:39 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834618; x=1698439418; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mNZMizemvrujc4XnqyNiXy5WpOSPf3XvMMBFfWR0das=; b=RnmRBdrI+h5w9HRYz5jsc0pzZA+pd/07bKZNk8Au1qN48sQiBy5lFCgv9e/RtuLL1q GiEs+2tuuz1a8ncXaT2Cq23IvAFsJlYVKN/g0vQiPh6YDH9HsHucPG8y8Ar5D9NAJjbF MoIVwKnFUx5adszealubgwGKkZ6+U9ZEVqqRv98m776tw60lSouaS52qEMg8II1i1Hrj FhHDoKS356gCCWuigb3/G7XeHUa44lhWBJ7cfoUvt5m2Ddatygycs4EePh4iGrV6qRHP NrGPtQ8L0E13C1V+tO5PgLaa0372IWgR0JkylgTmYtRi6eXWVatAkknXLewv0fND5moa c1/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834618; x=1698439418; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mNZMizemvrujc4XnqyNiXy5WpOSPf3XvMMBFfWR0das=; b=qyTcaXOfhuDSQQXn0C3g4v1x/7jngbDGdcNQ2kz3tCK9ZX0aCCZn/ENeq2cs4V6BOD TOl4ltFaN5Xkx/hk22oWWD3MJXYqWSmfyG40pZXZaTpFL05J8RHYMfQJY9oAZSAOuaj7 V5THhE6i5LtwZBQgiZC16qeGXt+ZkYGsOgJeBGBgUgjdi41qnkK+yA3GGzkezbXbB68M lrW1FZT2JEmcDwASPpZ52EfrS9hJfEQJHm9hL1hMqAzXttaFE999cBvUYenGhVsu9Q1A Fjfo/Q1PLpGfKviXO1x+eO8w4+3dq5INb6+hN9YSY8yDMMFOUlj587SwxDP+k+723ocs encQ== X-Gm-Message-State: AOJu0YyHbqR59Y7f+Ot2NLhZ0q6yHGNJsHhDv96/FdXuBeZl7RRyuDyS PgP/R5SrFydDoe+Rc7UaHOBuWI0oY+azrmcSRsc= X-Google-Smtp-Source: AGHT+IE6Vhd2w20Jgcz08xYJXysD2LbJdnbS3UYmvCXAC4bSjDKOBqG6maCGRz6NWoASekZRP/3T9w== X-Received: by 2002:a05:6a20:728c:b0:15a:836:7239 with SMTP id o12-20020a056a20728c00b0015a08367239mr3260263pzk.11.1697834618352; Fri, 20 Oct 2023 13:43:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 05/65] target/hppa: Remove load_const Date: Fri, 20 Oct 2023 13:42:31 -0700 Message-Id: <20231020204331.139847-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835053074100001 Content-Type: text/plain; charset="utf-8" Replace with tcg_constant_reg. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/hppa/translate.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 5302381a56..21f97f63a9 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -488,13 +488,6 @@ static void cond_free(DisasCond *cond) } } =20 -static TCGv_reg load_const(DisasContext *ctx, target_sreg v) -{ - TCGv_reg t =3D tcg_temp_new(); - tcg_gen_movi_reg(t, v); - return t; -} - static TCGv_reg load_gpr(DisasContext *ctx, unsigned reg) { if (reg =3D=3D 0) { @@ -1164,7 +1157,7 @@ static bool do_add_imm(DisasContext *ctx, arg_rri_cf = *a, if (a->cf) { nullify_over(ctx); } - tcg_im =3D load_const(ctx, a->i); + tcg_im =3D tcg_constant_reg(a->i); tcg_r2 =3D load_gpr(ctx, a->r); do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf); return nullify_end(ctx); @@ -1253,7 +1246,7 @@ static bool do_sub_imm(DisasContext *ctx, arg_rri_cf = *a, bool is_tsv) if (a->cf) { nullify_over(ctx); } - tcg_im =3D load_const(ctx, a->i); + tcg_im =3D tcg_constant_reg(a->i); tcg_r2 =3D load_gpr(ctx, a->r); do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf); return nullify_end(ctx); @@ -2808,7 +2801,7 @@ static bool trans_cmpiclr(DisasContext *ctx, arg_rri_= cf *a) nullify_over(ctx); } =20 - tcg_im =3D load_const(ctx, a->i); + tcg_im =3D tcg_constant_reg(a->i); tcg_r2 =3D load_gpr(ctx, a->r); do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf); =20 @@ -2994,7 +2987,7 @@ static bool trans_cmpb(DisasContext *ctx, arg_cmpb *a) static bool trans_cmpbi(DisasContext *ctx, arg_cmpbi *a) { nullify_over(ctx); - return do_cmpb(ctx, a->r, load_const(ctx, a->i), a->c, a->f, a->n, a->= disp); + return do_cmpb(ctx, a->r, tcg_constant_reg(a->i), a->c, a->f, a->n, a-= >disp); } =20 static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1, @@ -3033,7 +3026,7 @@ static bool trans_addb(DisasContext *ctx, arg_addb *a) static bool trans_addbi(DisasContext *ctx, arg_addbi *a) { nullify_over(ctx); - return do_addb(ctx, a->r, load_const(ctx, a->i), a->c, a->f, a->n, a->= disp); + return do_addb(ctx, a->r, tcg_constant_reg(a->i), a->c, a->f, a->n, a-= >disp); } =20 static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) @@ -3345,7 +3338,7 @@ static bool trans_depwi_sar(DisasContext *ctx, arg_de= pwi_sar *a) if (a->c) { nullify_over(ctx); } - return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_const(ctx, a-= >i)); + return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, tcg_constant_reg(a= ->i)); } =20 static bool trans_be(DisasContext *ctx, arg_be *a) @@ -3852,7 +3845,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest = *a) return true; } if (inv) { - TCGv_reg c =3D load_const(ctx, mask); + TCGv_reg c =3D tcg_constant_reg(mask); tcg_gen_or_reg(t, t, c); ctx->null_cond =3D cond_make(TCG_COND_EQ, t, c); } else { --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Signed-off-by: Richard Henderson --- target/hppa/machine.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/hppa/machine.c b/target/hppa/machine.c index 905991d7f9..0c0bba68c0 100644 --- a/target/hppa/machine.c +++ b/target/hppa/machine.c @@ -24,9 +24,9 @@ #if TARGET_REGISTER_BITS =3D=3D 64 #define qemu_put_betr qemu_put_be64 #define qemu_get_betr qemu_get_be64 -#define VMSTATE_UINTTL_V(_f, _s, _v) \ +#define VMSTATE_UINTTR_V(_f, _s, _v) \ VMSTATE_UINT64_V(_f, _s, _v) -#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \ +#define VMSTATE_UINTTR_ARRAY_V(_f, _s, _n, _v) \ VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v) #else #define qemu_put_betr qemu_put_be32 --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835108; cv=none; d=zohomail.com; s=zohoarc; b=If0bCjykEzTZiTbnIiHYeFfJeYD8C6E/ovQ7v4DD6bfmwfv0Kzh0SGro3Qb8RHxY/GC0HptiBky7Zf0c3CnSvsWLhMd/ZgF0eDcKJiKrc4JeKSHVIIWgqFA+lO56nB1Uz2hZEsR+FGBEaDVA6ADaOWX2OzUiWJ67qlYGsV9pxdQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697835108; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gizyszKoYOssiFVO/W3NqegBEKVfjjL7AQSlumE/K80=; b=Te08vGPycgXubyVIUsDwceKwR/2Fz2vs4AqoSZ7mkNfb5Mb6fjWjKRslMVLrAZcZlPQVeaeiNT6mXMc+rdVEfLAL1LKzff7to2XU5cBsekqXE2aUMSQBdmvmATmkbzR412Fm0z5F8Q/yyTBgVDCCOkfiW31yVu8Y1JddRVdc0MA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169783510831822.95580126272671; Fri, 20 Oct 2023 13:51:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwLu-0007t8-VJ; Fri, 20 Oct 2023 16:44:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwLP-0007iH-SX for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:44 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwLN-00089G-9Y for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:42 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-6b3c2607d9bso1163944b3a.1 for ; Fri, 20 Oct 2023 13:43:40 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834620; x=1698439420; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gizyszKoYOssiFVO/W3NqegBEKVfjjL7AQSlumE/K80=; b=t6u4/ecE9d+4l1w1L/AD+gd9pFhZAsHDD3w66yDJOIIJw5lVU9ue2SeZG3obp/U6GF fLGrNwLYue3AmYzSNudq3NASvxGJJOfVIsNOPbNTCUVv79Am8hxLt/VCzUcYmo6aJLO8 xdSipfKU6VT82J0sgeqXDKzet0Sq/BY0NxTmGazZFcW8Ufzoo7TeuHTQMVp3JcyGNecm pmRfBLoPThHFowT15sCJKDyGf0srQmUwFXDDaoCEjeczhwKeuYe5IYuYBNc4cDp5SwLS nBB1K5YXhxUML0/JG0UFgLhFCSZAQoCAfc1BD0QwAqbOCZ7sBARIPoJ5ibh4AALdSICW /+iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834620; x=1698439420; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gizyszKoYOssiFVO/W3NqegBEKVfjjL7AQSlumE/K80=; b=aDDkgHfX+4ZwA3QesXN+FEo7LgqIPdffO8uBH5iPts/zHgF4dQDvdSFkQs5nCyujEk yc36IvbxN7tPGfAdFSPu3oBbbPAnal9rEh+BTQCjkCvG8ZetT/YEbcWGYhdks5HyqqHF j4p4ALmfMxlv8PO4F3GE4qK1TTYoHr6dkDpfrIU+Az4+yrf7/b9LwyMF6ugcPZ2+ax7s ngeNNt+lZpc7ZHzWeq3blcLRdTrF1JmEBVHf6S4ksn2xRs6u9YFYif+kIMVAWIn1/FK+ QXWJvWI1XW9K2s7LkI5GJFMnps6UlaDnaxdw5wPUsewuxFHLcMeTOyvS7Z5lz5/2oqwH N7ag== X-Gm-Message-State: AOJu0YwIShPI6Nt3W8QujaGJ2YC5GfVw2g+nuQh10kMd8X9+JS31U3hY kGZVJ20YpD/PVp3lKcQQy7UaFEtDREw5WBgHjag= X-Google-Smtp-Source: AGHT+IHl3jppGiyWvMDbCxMIbQzJfGTR3CHWSOobPHvxxmO/4c3WyLCaKZyhK08uHrV0TVTPRIVbfg== X-Received: by 2002:a05:6a00:2d10:b0:6b2:2a2d:7a26 with SMTP id fa16-20020a056a002d1000b006b22a2d7a26mr3084508pfb.28.1697834620086; Fri, 20 Oct 2023 13:43:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 07/65] target/hppa: Fix load in do_load_32 Date: Fri, 20 Oct 2023 13:42:33 -0700 Message-Id: <20231020204331.139847-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835109283100001 The destination is TCGv_i32, so use tcg_gen_qemu_ld_i32 not tcg_gen_qemu_ld_reg. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 21f97f63a9..ff559ed21d 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1430,7 +1430,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 de= st, unsigned rb, =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); - tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); + tcg_gen_qemu_ld_i32(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697834681; cv=none; d=zohomail.com; s=zohoarc; b=TyeaY4Dnzdsx18SDg9OpdBmLy+K+9LxMOmnI9Faseq59b6XvZZGdVuRn4cQu/59BUafV2igMBsUoyVnPtEVa6ZnAXRqQKjzODX8iI/WDeMTCoKEPr+Jx1zhawftJ2UxzSsV/5dDlfqopdGbW4qqO1++ji9w74k4ht90fv1xO0nU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697834681; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HcidF9Jk1N+Ej8dbQUUvFmfE2V7LiGtPgLbzAI4Qab4=; b=Ib1Z0M7/orv1jXp8RJ8tvorOFIMthIJZjzMwDvDZfIRukHlwcQiBv4iJiqTO33sXuMmQyEEbysLmFDVVk0DpxaI0g36oQY77bHN6IwzyrANpQtqlt6OAI4MddlIPbmoYuHAivS9OUYTapUF4Q4HEbttDsxOv3gXwTsruQrCztTI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697834681944137.91604548455632; Fri, 20 Oct 2023 13:44:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwLs-0007pM-TI; Fri, 20 Oct 2023 16:44:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwLQ-0007iX-K5 for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:45 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwLO-00089d-CS for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:43 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-6b1e46ca282so1210179b3a.2 for ; Fri, 20 Oct 2023 13:43:42 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834621; x=1698439421; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HcidF9Jk1N+Ej8dbQUUvFmfE2V7LiGtPgLbzAI4Qab4=; b=KmYY5kSuhKvWvreARar5znrPZwqqrCquIekLLmI9/Lr/ARU9EPyZZuUTlfnUBXh2gm YJ9SP/gQiaG4EHIEDoPO/n1kGn726U6CKF3RNuVHlLapOUHAfTBux1hl1r2m3gjwGcMp +bFuCVkvywD1lot+ohOrexCG8svDxt69Wcz75SO84g8Kj/Ds1Ek0GdTMW3JY8RvuFSIr EDXRtWVixTCGAnIgL4DW6vylvRPSFyedk0lRGQ4tbjCVkFU2Qli9+HhvmEt4gxuSkNxW Rcm1ODiHQXNV+uMURY2phNRfLKgW8bTaHfqyEaI6z9Qyr/D7IKWIdNAQXU/I9tdYuTA0 D1xQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834621; x=1698439421; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HcidF9Jk1N+Ej8dbQUUvFmfE2V7LiGtPgLbzAI4Qab4=; b=r6BsAe4z5OyxBrgxMyhIwKXQsp//Ig7I0DuUSdSBaHvmNTBY2mTBxekoEQTuXDFjur MJtfE8KwPkXIMiLFNn4/wKdbHUMzqOUhIvOXpbev2DEktS3aoaEzLz1i90+GCfIRGoZZ aCHXond4IqYwM1ddU2/0AaYHIHU2lTYG7D0PdK43XlI0j/8LYMzlZXWLu+AB63dnWdEw 2wG3EyUPF2pMI/deuCzG/pa4LmcKqAxuTZpV9Y7Tsu0ctL7BAtOgBxsT979X+uI3yzuy 9i/kji9PO4XR8W/TsIn6ZgFd8KFTb1C90z2ueymGtKm/z70NFzodWbl5L5tx/iRYIgYi xvfA== X-Gm-Message-State: AOJu0YzUBgMYqS0bdu1+2+h7y6CRu5sQYIANAIWJXwpM5HXHaNbSokY0 Q5/+AYRhCVJ5bIV7Vdj42yz9K6Pd0Ye2OA/1XnI= X-Google-Smtp-Source: AGHT+IG2VzdtieHwUPaLTUo80MnvMR35uXisXNK0sntO+EJ50z1PhX17kCIjz4B6zyGqlGQFlE3qUw== X-Received: by 2002:a05:6a00:10c4:b0:6b5:608d:64f6 with SMTP id d4-20020a056a0010c400b006b5608d64f6mr3132210pfu.20.1697834620857; Fri, 20 Oct 2023 13:43:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 08/65] target/hppa: Truncate rotate count in trans_shrpw_sar Date: Fri, 20 Oct 2023 13:42:34 -0700 Message-Id: <20231020204331.139847-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834683861100003 Content-Type: text/plain; charset="utf-8" When forcing rotate by i32, the shift count must be as well. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ff559ed21d..e6ab113a1c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3105,8 +3105,11 @@ static bool trans_shrpw_sar(DisasContext *ctx, arg_s= hrpw_sar *a) tcg_gen_shr_reg(dest, dest, cpu_sar); } else if (a->r1 =3D=3D a->r2) { TCGv_i32 t32 =3D tcg_temp_new_i32(); + TCGv_i32 s32 =3D tcg_temp_new_i32(); + tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); - tcg_gen_rotr_i32(t32, t32, cpu_sar); + tcg_gen_trunc_reg_i32(s32, cpu_sar); + tcg_gen_rotr_i32(t32, t32, s32); tcg_gen_extu_i32_reg(dest, t32); } else { TCGv_i64 t =3D tcg_temp_new_i64(); --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697834928; cv=none; d=zohomail.com; s=zohoarc; b=RVn37Tth3b5p8urvVIxRfmYq2BaaUT/RzNwq4LTrbVUZT0/ZNJl/8h964js3L/NtBV3g+3tL5S8WQHKv7XsPF5rLgG77FmuktisVuB7J31Xzkff3URkyunTc8NL7xOvx31owRAF43ZJ/dFAJwm3mXfQQFOL7P476QZdjTVkJ4YA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697834928; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=jy+spAs5u7WgOQZspkjRSxDs5g0jtQCLczTslsy9ExE=; b=T4P85JEBkEXXEsSVxpvAD4h3FOGbYWXgpcF+KbHYAqt4fdtT/VWowGQ85ZEDnsXsjzs9ySPxYJUw8cot6VBlL4KNwEb8u0Z10eD1XVDIhf5l9UZQQVFkNHzMhgWzl/RuZZ3htPZqD+uVjGXj4ZTvWaC0moEm8oPo1noiLr4+CSE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697834928403271.296736578954; Fri, 20 Oct 2023 13:48:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwLs-0007pK-Eu; Fri, 20 Oct 2023 16:44:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwLT-0007iv-6T for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:47 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwLP-00089q-P7 for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:45 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-6b87c1edfd5so1107289b3a.1 for ; Fri, 20 Oct 2023 13:43:42 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834621; x=1698439421; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jy+spAs5u7WgOQZspkjRSxDs5g0jtQCLczTslsy9ExE=; b=hC8IZ3VinQnesMt+Lo0qkAAfWtu1W1+oc1WqznhSBsVZSP8JvQH84i7abk+qC1XArd 68ubvz804AEdxvOjO4B/7cjZYS5mpIthz+CI2d7LlzqSwfKbU41UPsUbL2vBiz7tGc7k 6uySOVzg1rgNh2jnfhJoI2MyFrSJBQcFKdO/jx8d3yLR33eEICZsoGC4pNFbBgAwKRLH do1Tt2+zvMt+tQSD7ue/641FoaDKsIVVpSuZ+U5cv6VxW1tbePDQTaU6CrVUYgFghHfn OTFBlJK7W9tgfA8dJOMqlbNr/+yTQVAewm57ebeBrK8TeDz92JoqVhsY1yCamNzeMGjt v3Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834621; x=1698439421; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jy+spAs5u7WgOQZspkjRSxDs5g0jtQCLczTslsy9ExE=; b=c2jFXilOmQ+y9g8hgiobAXczsMinA61rPfSaphDFYuE8bfGcFpCA5m4KwxywZLVK8d vK6g8F6IMcFT66ZbbRargW0Fipj2nHYwlgENHNDaaq+sdCEb1JY+v90frpqMK3XeyKRr Z7q8suJzotIf6GcpdGNntJKoCeokL5YmdadsZGfx4RsYO6eNDH6WgEQ5L+WHOmZRN2Qj t0q6qmG2LUzD8AyU3EnVHI2kKAYoZiC6mox/yu/2HliV/xBxq8bHkURNYKqOlekWNtHt t8NHaSrL2jEjavatyp/RWkmOm70ucrau1B9MoWN7UX6FS3hXEIpt7LE25JbCUeuz8dBO OrQA== X-Gm-Message-State: AOJu0Yza2pEjZJPdP0Roel7JZmpRxELUVTRdDW9ZqSPcj+dwq4EeIte1 RZRydY3GlBtl4v0W50uRLMqmNXxXoRHCUX37XJY= X-Google-Smtp-Source: AGHT+IHwfLE/aeY5SMA6wSXKTfQ4aQ0hqo/e1Hst9rbmUD6yqyrf0kMVrliJnmQVzRtRq6oRb0Q4PQ== X-Received: by 2002:a05:6a00:22c5:b0:6b4:c21c:8b56 with SMTP id f5-20020a056a0022c500b006b4c21c8b56mr3193565pfj.23.1697834621559; Fri, 20 Oct 2023 13:43:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 09/65] target/hppa: Fix trans_ds for hppa64 Date: Fri, 20 Oct 2023 13:42:35 -0700 Message-Id: <20231020204331.139847-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834928877100006 Content-Type: text/plain; charset="utf-8" This instruction always uses the input carry from bit 32, but produces all 16 output carry bits. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 48 +++++++++++++++++++++++++++++++---------- 1 file changed, 37 insertions(+), 11 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e6ab113a1c..fb7a295367 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -803,6 +803,12 @@ static bool cond_need_cb(int c) return c =3D=3D 4 || c =3D=3D 5; } =20 +/* Need extensions from TCGv_i32 to TCGv_reg. */ +static bool cond_need_ext(DisasContext *ctx, bool d) +{ + return TARGET_REGISTER_BITS =3D=3D 64 && !d; +} + /* * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of * the Parisc 1.1 Architecture Reference Manual for details. @@ -1040,6 +1046,22 @@ static DisasCond do_unit_cond(unsigned cf, TCGv_reg = res, return cond; } =20 +static TCGv_reg get_carry(DisasContext *ctx, bool d, + TCGv_reg cb, TCGv_reg cb_msb) +{ + if (cond_need_ext(ctx, d)) { + TCGv_reg t =3D tcg_temp_new(); + tcg_gen_extract_reg(t, cb, 32, 1); + return t; + } + return cb_msb; +} + +static TCGv_reg get_psw_carry(DisasContext *ctx, bool d) +{ + return get_carry(ctx, d, cpu_psw_cb, cpu_psw_cb_msb); +} + /* Compute signed overflow for addition. */ static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res, TCGv_reg in1, TCGv_reg in2) @@ -2712,6 +2734,7 @@ static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf= *a) static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) { TCGv_reg dest, add1, add2, addc, zero, in1, in2; + TCGv_reg cout; =20 nullify_over(ctx); =20 @@ -2726,18 +2749,20 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf = *a) =20 /* Form R1 << 1 | PSW[CB]{8}. */ tcg_gen_add_reg(add1, in1, in1); - tcg_gen_add_reg(add1, add1, cpu_psw_cb_msb); + tcg_gen_add_reg(add1, add1, get_psw_carry(ctx, false)); =20 - /* Add or subtract R2, depending on PSW[V]. Proper computation of - carry{8} requires that we subtract via + ~R2 + 1, as described in - the manual. By extracting and masking V, we can produce the - proper inputs to the addition without movcond. */ - tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1); + /* + * Add or subtract R2, depending on PSW[V]. Proper computation of + * carry requires that we subtract via + ~R2 + 1, as described in + * the manual. By extracting and masking V, we can produce the + * proper inputs to the addition without movcond. + */ + tcg_gen_sextract_reg(addc, cpu_psw_v, 31, 1); tcg_gen_xor_reg(add2, in2, addc); tcg_gen_andi_reg(addc, addc, 1); - /* ??? This is only correct for 32-bit. */ - tcg_gen_add2_i32(dest, cpu_psw_cb_msb, add1, zero, add2, zero); - tcg_gen_add2_i32(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zer= o); + + tcg_gen_add2_reg(dest, cpu_psw_cb_msb, add1, zero, add2, zero); + tcg_gen_add2_reg(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zer= o); =20 /* Write back the result register. */ save_gpr(ctx, a->t, dest); @@ -2747,7 +2772,8 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) tcg_gen_xor_reg(cpu_psw_cb, cpu_psw_cb, dest); =20 /* Write back PSW[V] for the division step. */ - tcg_gen_neg_reg(cpu_psw_v, cpu_psw_cb_msb); + cout =3D get_psw_carry(ctx, false); + tcg_gen_neg_reg(cpu_psw_v, cout); tcg_gen_xor_reg(cpu_psw_v, cpu_psw_v, in2); =20 /* Install the new nullification. */ @@ -2757,7 +2783,7 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) /* ??? The lshift is supposed to contribute to overflow. */ sv =3D do_add_sv(ctx, dest, add1, add2); } - ctx->null_cond =3D do_cond(a->cf, dest, cpu_psw_cb_msb, sv); + ctx->null_cond =3D do_cond(a->cf, dest, cout, sv); } =20 return nullify_end(ctx); --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697834783; cv=none; d=zohomail.com; s=zohoarc; b=MqbC9StZs/9RZAsNybwRKemkbziAfyJWM2s6b+N90b0RoIOdaT78VZ59g52w51s3oEsWEJuYlPY20bJ5ON2b6iX4WRv+qTJRi5Xr6UCP/8IATCGB5dfgiKGh/DakkYmXz8myp1VGSqKbDmLdCny8izApsYpj1Me+nVynC97aOt0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697834783; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=vj5Zj+Bw57JH4E175sUuTw9SkCPkXc9sWUiIDH26gck=; b=NAm/ob6nuhkeXyz5gCZYcVsQ0yKu7cks93pJvxys9P1K03Aa0KcnSXuOaTzu20pWnXmGdJi2uCCMDJyAB3OtUkMgLG5sdtGkwG4PSR3XCBnOvmgzjscdT4i/+beqPY16mMD3CeBdYnPyzUp5OD1In4DwwNcl1LbgAnjZOwHu3v0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697834783926320.1013606859725; Fri, 20 Oct 2023 13:46:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwLs-0007pG-5L; Fri, 20 Oct 2023 16:44:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwLU-0007jO-Dj for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:51 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwLQ-0008A0-DB for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:48 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6b709048d8eso1082101b3a.2 for ; Fri, 20 Oct 2023 13:43:43 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834622; x=1698439422; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vj5Zj+Bw57JH4E175sUuTw9SkCPkXc9sWUiIDH26gck=; b=enH7rGJb+3DB9sJMVEgD+exnNafObOJfJKbLWTeia8Ssb5b3w6rToSXFOq/Dh8umAx tae8x8ddcnEBiLLpXdXQKupb8i5YFRhd01eqjgTR8CeYCPMhPvCHOFFQSPJhQRjFvu2e ZU7DCHb65I2sbZ97V1vbp6YgsLes4Zp8B6kdmwOG9s08Ull1yiPr11hhdaamK4k6r3aW 0m1nS4Zrb5NXLqasSu043ZwShouPHK/Ntsxibhr5UBa0rY7mROFgmyz2Voip0LYHVetF OUtnuPe8/Q3+J29BdLPtGwPhmka6rI6fQLzmWXHnU7gnaRyKA6vvA8rc0gbVFXxyCYRy yzvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834622; x=1698439422; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vj5Zj+Bw57JH4E175sUuTw9SkCPkXc9sWUiIDH26gck=; b=oL7Pl2l4Aj/1fMdPq4ZfDmxtF7lvQAf8bchkKD2VrOkdWmXVgOONr9GD4kfA49E0IE x8wgPPNIzde2+VcqPF1cjjGSJfsRVqvPz1tuIwOpzEIOwPOCgCdrzdGxSH6Ky7vMmmXV XXJJYFI9mmYgSkpMsm37iL4dB1q1DigOEVZ27CtzY/1QfgjcLs8PQFW419zwQf+JJrEz CDQOQOcqZr7wO3sHXo0CAGsDqK9vIj9ivSK/EhkSWlfZzKs+ksE5P/OC0aGF+xJHTtvF jdDtbmutyZ2GR/75qmH+DC11EgVdajlHT5PM4W8c2R+ct+WXu5GsPGL1uIPQPortpL9J DFDQ== X-Gm-Message-State: AOJu0Yw1y6YpTDyoMi9guTdSJvLaXBNjHDZEsQ/X7EdbXBg/YV69k7vW ZFKngXpnZAbpbMYvYbUbREbRgZSMiusXwWubqYQ= X-Google-Smtp-Source: AGHT+IH/mrDpKNwmCG2mQMKMC6ffKpRFf7JQe6WGYDPrM5+djX73VlIdwTtQdb66sUM1WrqnLAOIrQ== X-Received: by 2002:a05:6a00:99e:b0:6be:265:1bf5 with SMTP id u30-20020a056a00099e00b006be02651bf5mr3314607pfg.24.1697834622534; Fri, 20 Oct 2023 13:43:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 10/65] target/hppa: Fix do_add, do_sub for hppa64 Date: Fri, 20 Oct 2023 13:42:36 -0700 Message-Id: <20231020204331.139847-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834784270100005 Content-Type: text/plain; charset="utf-8" Select the proper carry bit for input to the arithmetic and for output for the condition. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 50 ++++++++++++++++++++++++++--------------- 1 file changed, 32 insertions(+), 18 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index fb7a295367..8ebe7523a7 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1094,13 +1094,15 @@ static void do_add(DisasContext *ctx, unsigned rt, = TCGv_reg in1, TCGv_reg in2, unsigned shift, bool is_l, bool is_tsv, bool is_tc, bool is_c, unsigned cf) { - TCGv_reg dest, cb, cb_msb, sv, tmp; + TCGv_reg dest, cb, cb_msb, cb_cond, sv, tmp; unsigned c =3D cf >> 1; DisasCond cond; + bool d =3D false; =20 dest =3D tcg_temp_new(); cb =3D NULL; cb_msb =3D NULL; + cb_cond =3D NULL; =20 if (shift) { tmp =3D tcg_temp_new(); @@ -1111,19 +1113,22 @@ static void do_add(DisasContext *ctx, unsigned rt, = TCGv_reg in1, if (!is_l || cond_need_cb(c)) { TCGv_reg zero =3D tcg_constant_reg(0); cb_msb =3D tcg_temp_new(); + cb =3D tcg_temp_new(); + tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero); if (is_c) { - tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, z= ero); + tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, + get_psw_carry(ctx, d), zero); } - if (!is_l) { - cb =3D tcg_temp_new(); - tcg_gen_xor_reg(cb, in1, in2); - tcg_gen_xor_reg(cb, cb, dest); + tcg_gen_xor_reg(cb, in1, in2); + tcg_gen_xor_reg(cb, cb, dest); + if (cond_need_cb(c)) { + cb_cond =3D get_carry(ctx, d, cb, cb_msb); } } else { tcg_gen_add_reg(dest, in1, in2); if (is_c) { - tcg_gen_add_reg(dest, dest, cpu_psw_cb_msb); + tcg_gen_add_reg(dest, dest, get_psw_carry(ctx, d)); } } =20 @@ -1138,7 +1143,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, } =20 /* Emit any conditional trap before any writeback. */ - cond =3D do_cond(cf, dest, cb_msb, sv); + cond =3D do_cond(cf, dest, cb_cond, sv); if (is_tc) { tmp =3D tcg_temp_new(); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); @@ -1192,6 +1197,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, TCGv_reg dest, sv, cb, cb_msb, zero, tmp; unsigned c =3D cf >> 1; DisasCond cond; + bool d =3D false; =20 dest =3D tcg_temp_new(); cb =3D tcg_temp_new(); @@ -1201,15 +1207,17 @@ static void do_sub(DisasContext *ctx, unsigned rt, = TCGv_reg in1, if (is_b) { /* DEST,C =3D IN1 + ~IN2 + C. */ tcg_gen_not_reg(cb, in2); - tcg_gen_add2_reg(dest, cb_msb, in1, zero, cpu_psw_cb_msb, zero); + tcg_gen_add2_reg(dest, cb_msb, in1, zero, get_psw_carry(ctx, d), z= ero); tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cb, zero); tcg_gen_xor_reg(cb, cb, in1); tcg_gen_xor_reg(cb, cb, dest); } else { - /* DEST,C =3D IN1 + ~IN2 + 1. We can produce the same result in f= ewer - operations by seeding the high word with 1 and subtracting. */ - tcg_gen_movi_reg(cb_msb, 1); - tcg_gen_sub2_reg(dest, cb_msb, in1, cb_msb, in2, zero); + /* + * DEST,C =3D IN1 + ~IN2 + 1. We can produce the same result in f= ewer + * operations by seeding the high word with 1 and subtracting. + */ + TCGv_reg one =3D tcg_constant_reg(1); + tcg_gen_sub2_reg(dest, cb_msb, in1, one, in2, zero); tcg_gen_eqv_reg(cb, in1, in2); tcg_gen_xor_reg(cb, cb, dest); } @@ -1227,7 +1235,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, if (!is_b) { cond =3D do_sub_cond(cf, dest, in1, in2, sv); } else { - cond =3D do_cond(cf, dest, cb_msb, sv); + cond =3D do_cond(cf, dest, get_carry(ctx, d, cb, cb_msb), sv); } =20 /* Emit any conditional trap before any writeback. */ @@ -3019,18 +3027,24 @@ static bool trans_cmpbi(DisasContext *ctx, arg_cmpb= i *a) static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1, unsigned c, unsigned f, unsigned n, int disp) { - TCGv_reg dest, in2, sv, cb_msb; + TCGv_reg dest, in2, sv, cb_cond; DisasCond cond; + bool d =3D false; =20 in2 =3D load_gpr(ctx, r); dest =3D tcg_temp_new(); sv =3D NULL; - cb_msb =3D NULL; + cb_cond =3D NULL; =20 if (cond_need_cb(c)) { - cb_msb =3D tcg_temp_new(); + TCGv_reg cb =3D tcg_temp_new(); + TCGv_reg cb_msb =3D tcg_temp_new(); + tcg_gen_movi_reg(cb_msb, 0); tcg_gen_add2_reg(dest, cb_msb, in1, cb_msb, in2, cb_msb); + tcg_gen_xor_reg(cb, in1, in2); + tcg_gen_xor_reg(cb, cb, dest); + cb_cond =3D get_carry(ctx, d, cb, cb_msb); } else { tcg_gen_add_reg(dest, in1, in2); } @@ -3038,7 +3052,7 @@ static bool do_addb(DisasContext *ctx, unsigned r, TC= Gv_reg in1, sv =3D do_add_sv(ctx, dest, in1, in2); } =20 - cond =3D do_cond(c * 2 + f, dest, cb_msb, sv); + cond =3D do_cond(c * 2 + f, dest, cb_cond, sv); save_gpr(ctx, r, dest); return do_cbranch(ctx, disp, n, &cond); } --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835095; cv=none; d=zohomail.com; s=zohoarc; b=K2SLN8150vyRwlRSUxmiDaboIoIuYvksQGwj2cOgmb4jr8mycVANkXBx8MgmYwFTPscqTcnl3QvOb8mSAXyBY1mO9nY10fwiRXqieDSYEVvvULovoSGf6gfY3mSUFTiF24K9QiqK2W/NwSXwkGD3QVrTxDIDtl0T52sgpQzomak= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697835095; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+3Cca9a0dUfxOMmsrbDZSCnt4BuRnsfCclCPiSMy9B8=; b=DV46TxHxpTrr+A1pGouMcbcCgCdM9bQa0yFgwftXj0bQTipafbYWmgrZ5eSp6K2j3ELtbDetpJqImHidLbkeY1CSYKCrm4YOAWjxLUvqPSHrsMDktNnyWw4bBnzI/TNTP4XjEcGzPc6eWOBp85Ki3bPHkww9tzlH6sO1RlYvhmE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697835095482462.7198778443336; Fri, 20 Oct 2023 13:51:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwLt-0007pO-6D; Fri, 20 Oct 2023 16:44:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwLU-0007jP-Du for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:51 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwLS-0008AD-Lt for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:48 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-6b709048f32so1136118b3a.0 for ; Fri, 20 Oct 2023 13:43:44 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834623; x=1698439423; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+3Cca9a0dUfxOMmsrbDZSCnt4BuRnsfCclCPiSMy9B8=; b=ikUtBKj+/5QIBQ8z8gMQcGNZow41MD5jPJqIkK00UwMACNaeEoPlkWGsbP1qvW0R1+ eKDze6xwHSKC0cnUq+OA1KWzV9VdcKBgdzolDMYyBUDFnz/kGbIU1FP1pIyEJQ4BUH31 qiFT079IDJQAYAQEVdgpIvxPxB4Yl9SUnwP/W0+zZQki+wBS8p/xI6netdKDC3Z95USg zfnepvNpI++tdsVja3MpY8o1HFOc/Zt2uKw0OABYLRiszFpJVwFKCDu0SKNupnnj9kCD CCRRjrugcl7qsQXDUK+Q8XIu05Hf7Ya5yykQaLCprwPoLhqnc8URvWIPDT8mHYGI8ulj 8YFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834623; x=1698439423; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+3Cca9a0dUfxOMmsrbDZSCnt4BuRnsfCclCPiSMy9B8=; b=OSQrE1FEt3RLkI0KpiahwcDy1hxv3ULcI2ObInVug3gkFmIk2zGD1hkg5em3IwXpuW juKGF+HQrnVZXb1IeUk7rmusca5z3Y0Kqhc7XbJJ1GC8pzEXFb1IOWyvdVta9HO3xMHm b9vqoZqSBj/U+ldoQf7Qs2kc+8Fo0yjpx2lz1k/1qcN87Lw/j0QT9JEj6dvWIZWcz8VW MmdoHR7u0m+76F/cWry1xKYHuFCjaZZ0meM4DD15suKxcqRfKg/9Za5QgyIXyVhdmtE3 SAevbDZNkiw2GHLmFI3iO5v7+eMO7FGKqpeMO8Lgk+UY092OhNupQ7+0UjRts8rOL6Qt iooQ== X-Gm-Message-State: AOJu0YwAEzEqeOlKLec8fuV35z7yIPbU8iqXN2ov1F3sCUJ/f9EtDGCc NRFJS6DGVE1IQyBFMDkmtIJl9P7vwsx6Cv4IRBE= X-Google-Smtp-Source: AGHT+IEgHVms0FprHai/z+q6cUO5mRdGHx2R5gxSBQlvfFv2K9sKW8seRJhEmG+9aqNPyUQKAn8tpw== X-Received: by 2002:a05:6a20:4924:b0:14c:5dc3:f1c9 with SMTP id ft36-20020a056a20492400b0014c5dc3f1c9mr2380653pzb.49.1697834623353; Fri, 20 Oct 2023 13:43:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 11/65] target/hppa: Fix bb_sar for hppa64 Date: Fri, 20 Oct 2023 13:42:37 -0700 Message-Id: <20231020204331.139847-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835097170100011 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8ebe7523a7..119422870c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3073,14 +3073,21 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_= sar *a) { TCGv_reg tmp, tcg_r; DisasCond cond; + bool d =3D false; =20 nullify_over(ctx); =20 tmp =3D tcg_temp_new(); tcg_r =3D load_gpr(ctx, a->r); - tcg_gen_shl_reg(tmp, tcg_r, cpu_sar); + if (cond_need_ext(ctx, d)) { + /* Force shift into [32,63] */ + tcg_gen_ori_reg(tmp, cpu_sar, 32); + tcg_gen_shl_reg(tmp, tcg_r, tmp); + } else { + tcg_gen_shl_reg(tmp, tcg_r, cpu_sar); + } =20 - cond =3D cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); + cond =3D cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); return do_cbranch(ctx, a->disp, a->n, &cond); } =20 @@ -3088,12 +3095,15 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_= imm *a) { TCGv_reg tmp, tcg_r; DisasCond cond; + bool d =3D false; + int p; =20 nullify_over(ctx); =20 tmp =3D tcg_temp_new(); tcg_r =3D load_gpr(ctx, a->r); - tcg_gen_shli_reg(tmp, tcg_r, a->p); + p =3D a->p | (cond_need_ext(ctx, d) ? 32 : 0); + tcg_gen_shli_reg(tmp, tcg_r, p); =20 cond =3D cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); return do_cbranch(ctx, a->disp, a->n, &cond); --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835048; cv=none; d=zohomail.com; s=zohoarc; b=Dd9MBn/iUZ279Aaloax2WaWlIQ5MdWdUUIDk/PAGxAsSxGANhf1aZfefrObGXGZM4x5G9Duzfy5yBZYGdZWYEZ49n1hTvNw1q38Xbs2F1Yjix/mdopOBN/xlPdLsQC/ftqVZuGmteMIBKMudaexVprZI//QKCaZSkoOgiprXchI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697835048; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=T6DEfOhGSAuzHVOiFy6ZRmh1nqeZSzZi7HDKv5g8+j0=; b=NqvBHQSTf17os+8O1/VzBCxkNNRn48zM4ZJzsbLozeXxWhxH2gHeompu75SPAGIXDvD8HonroCC1nWw3TqtkZJcsQIlAWoSRByyFwsa0ZhfNwcdrNPrKGEyLPUX02GF77jq8KXhrVvfr7UfDfb8tP+zmPtYGR2myH5+/oMDAzMA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697835048724674.6466119951767; Fri, 20 Oct 2023 13:50:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwLv-0007tw-LL; Fri, 20 Oct 2023 16:44:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwLV-0007jQ-TZ for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:52 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwLS-0008AL-U4 for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:49 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6bd32d1a040so1213420b3a.3 for ; Fri, 20 Oct 2023 13:43:45 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834624; x=1698439424; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T6DEfOhGSAuzHVOiFy6ZRmh1nqeZSzZi7HDKv5g8+j0=; b=BsNZ67kc7dWCgOMVsBf0JFCqD79DLaZDrGCUzvsdUCPWwm6gQhnrpuq8SzI/7/7bkf VIuV7gu8G1cQPiPUIz4TksdANcT0tQlqRY7GGJ5/dcnaU66DNvtoCNo3JeMT/hku9FCV zs+66E+kR1tr6XrTyFqoMw1D7qdPvmOTyYhRdkplyoG0ZAZC4aqrWCyI+sVC0u1bBSy9 KadQDApw5c//NAl8We7C4yeZpSou3eQ/HUgxYabVe4nFI3dUmoZAB6q7SDR2KOH1CQCJ 6EuWM/rCDXnpWyhSmZvlVCy3y+Q6SeVofK7PGU1bw8NThnPAbZ0JTbBgOE7DXyrovCGH KRAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834624; x=1698439424; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T6DEfOhGSAuzHVOiFy6ZRmh1nqeZSzZi7HDKv5g8+j0=; b=o0OisxBZBumrWwkq5h3KMX6IGsIU+cA0VyW4ayT59jFWQmPU71q1kqiMZuALR3lPsj HjeJ6+l8Sp8aMDu1Ma2LkdFs+JyWhyHJKcWG5oUxQAA88B0EWZnFvxrN8moIx+IrwLPg uRfdbYq/57UU8CfoaiH6j/AnFANltZoiu5EXAn5qII29ZdLA4XCvahwraIZvHdh8iCkE /P/R7tesV31ZNnDxM4lNpIYF9tuKPkIg+nTIrYrbxhumdFgxTUIspPVpBYaDZzsbvXlo b1eawsemXRLq1NtvBBJr7vywp77cT8g5JevEwWWRKifnMQb5zLUoTadcBRnHgKtsnfGC 0YuA== X-Gm-Message-State: AOJu0YxPkejekG7aynsEghq4L5qz+ffWYTaUWzilguJGxHtGPhMqm+Q9 /Z+6K9jHMAADpS6ndLHDUnoJT4Gjz0bIohWidow= X-Google-Smtp-Source: AGHT+IHqB3WJ/vu9PLoRlGuVe5QnRyuvoHJi1cgadBn0jjy5vDe6Xk1F9HxDKAEpBzk+MmWbSvfyNA== X-Received: by 2002:a05:6a00:84f:b0:6bd:b3b9:649f with SMTP id q15-20020a056a00084f00b006bdb3b9649fmr3273030pfk.7.1697834624318; Fri, 20 Oct 2023 13:43:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 12/65] target/hppa: Fix extrw and depw with sar for hppa64 Date: Fri, 20 Oct 2023 13:42:38 -0700 Message-Id: <20231020204331.139847-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835049114100001 Content-Type: text/plain; charset="utf-8" These are 32-bit operations regardless of processor. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 119422870c..f86ea9b9ca 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3230,7 +3230,9 @@ static bool trans_extrw_sar(DisasContext *ctx, arg_ex= trw_sar *a) tmp =3D tcg_temp_new(); =20 /* Recall that SAR is using big-endian bit numbering. */ - tcg_gen_xori_reg(tmp, cpu_sar, TARGET_REGISTER_BITS - 1); + tcg_gen_andi_reg(tmp, cpu_sar, 31); + tcg_gen_xori_reg(tmp, tmp, 31); + if (a->se) { tcg_gen_sar_reg(dest, src, tmp); tcg_gen_sextract_reg(dest, dest, 0, len); @@ -3355,7 +3357,8 @@ static bool do_depw_sar(DisasContext *ctx, unsigned r= t, unsigned c, tmp =3D tcg_temp_new(); =20 /* Convert big-endian bit numbering in SAR to left-shift. */ - tcg_gen_xori_reg(shift, cpu_sar, TARGET_REGISTER_BITS - 1); + tcg_gen_andi_reg(shift, cpu_sar, 31); + tcg_gen_xori_reg(shift, shift, 31); =20 mask =3D tcg_temp_new(); tcg_gen_movi_reg(mask, msb + (msb - 1)); --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835112; cv=none; d=zohomail.com; s=zohoarc; b=PIGnw/EZDHEd63LYVjV2av4PWQm9FEF8VtafgPzEi4egcF1DqqCRsr2ektdDDy1elfCM7p8qo4P3sjuinxw7xxtSGn0eSY8SMrN5J/o1asJpvdHa2dZ7Dggy189gJ0AwQDKVDmBmQigDnoDItk3Gj+T4hQf36ke1Ur1ncBmGFJc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697835112; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3+gAls5QIov6whAU2ymHpvhxd4z68DFwK7+v+pcFR8U=; b=PhGEJPtGumtFqTxJqTZV3CczOH6B7tGZI8MVNIfCVrRtQDlzsOFGGztgS8Fhil85eHx5NbrxFUOmoWajfGgtB8ZapyufaPIgHvR3+Z5P3ilpu9svqIO9m6htcRH+VdGogU2cBlWj+U1WpdEoENaqwDOEQRQIIiCVkfOXVWzNyaU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697835112689892.1471173737956; Fri, 20 Oct 2023 13:51:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwLt-0007pd-IC; Fri, 20 Oct 2023 16:44:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwLW-0007jR-GE for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:54 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwLS-0008AP-Mz for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:49 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-6b497c8575aso1217919b3a.1 for ; Fri, 20 Oct 2023 13:43:45 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834625; x=1698439425; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3+gAls5QIov6whAU2ymHpvhxd4z68DFwK7+v+pcFR8U=; b=UC1E1T0QoBTZaYUaS/aVXB1qWv4b6R559A+euFUfEW1Ukygv+BpAxtlgjfc0QmV7oS 4ZenXhxFLs2bw/7NhNcMFQJboU+xirzc943ZkJJOhuLYK9UwPhefWMkfxxHsmvPIzWpg H95HCBYx9Pouh5K9QDFere82+g2tvXUyhPvovPzFDS034JnPEzjlDN/WUwfuezuyrqNg 4ttYpZEPAuhCKH9aIMj6IuYAss3Q6GSrnBsymOC1P6v7VH/NWZtLk29d+99wcRagwn/T HlP3cEC/BBE8MM0M3Qa4piFWK55IeLlY/WGItkWRpWjJr8xucjnZHb/UKb32mMezjU6V OpmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834625; x=1698439425; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3+gAls5QIov6whAU2ymHpvhxd4z68DFwK7+v+pcFR8U=; b=JbTJtJyLhcO9zxfl43jNxuyk6b2N39NRAd5KE92wTDG3Hs/9g/X3HWaJtpHV5mMnP+ 61g6m69ySQf2dpeRKd4lMJ/UosLDQt4nRHrm89ppaHDaGI8sNKZRv5K5LsCER8P/u1AL KHjFxAGYOSvztogSbBkeLSqbZhZA8Dc15u7RCjv5X/3iy3dUqbQPm4iFS7X9YwQiXV5b skEOPJ8V1efppo0FSsTuMYwXwdOuIoM4784F1y1TDzHfMs5VnqOVUfTWZsSbp83PInjr zCD+DEMsCxVViad6jde3aO4I0ILa5MImRd6bC/CjdKIRSH/7PgQ8Lq8BKvy16Det2+z6 /AUg== X-Gm-Message-State: AOJu0YxI24rOnuA8Pw+dtRVKmuXIwzapTGqKl2kUL8FSOpX07Y5uqV4b MnAGvhuQhcR9ntQth9cML96tKj9KA3M88nd0vbE= X-Google-Smtp-Source: AGHT+IE01Q9dMV3mRB2iqWgjHRyHUerWOS5i7FmtpEE73CEgg/wnWe3rZEozr/q7gAeGVi7C6dHk7A== X-Received: by 2002:a05:6a20:3950:b0:17c:d4f0:87e0 with SMTP id r16-20020a056a20395000b0017cd4f087e0mr733413pzg.53.1697834625141; Fri, 20 Oct 2023 13:43:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 13/65] target/hppa: Introduce TYPE_HPPA64_CPU Date: Fri, 20 Oct 2023 13:42:39 -0700 Message-Id: <20231020204331.139847-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835113280100011 Content-Type: text/plain; charset="utf-8" Prepare for the qemu binary supporting both pa10 and pa20 at the same time. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/hppa/cpu-qom.h | 1 + target/hppa/cpu.h | 5 +++++ target/hppa/cpu.c | 34 +++++++++++++++++++--------------- target/hppa/translate.c | 2 ++ 4 files changed, 27 insertions(+), 15 deletions(-) diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h index b96e0318c7..4a85ebf5e0 100644 --- a/target/hppa/cpu-qom.h +++ b/target/hppa/cpu-qom.h @@ -24,6 +24,7 @@ #include "qom/object.h" =20 #define TYPE_HPPA_CPU "hppa-cpu" +#define TYPE_HPPA64_CPU "hppa64-cpu" =20 OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU) =20 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 798d0c26d7..6995eb69ef 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -243,6 +243,11 @@ struct ArchCPU { =20 #include "exec/cpu-all.h" =20 +static inline bool hppa_is_pa20(CPUHPPAState *env) +{ + return object_dynamic_cast(OBJECT(env_cpu(env)), TYPE_HPPA64_CPU) !=3D= NULL; +} + static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 1644297bf8..192aae268d 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -207,20 +207,24 @@ static void hppa_cpu_class_init(ObjectClass *oc, void= *data) cc->tcg_ops =3D &hppa_tcg_ops; } =20 -static const TypeInfo hppa_cpu_type_info =3D { - .name =3D TYPE_HPPA_CPU, - .parent =3D TYPE_CPU, - .instance_size =3D sizeof(HPPACPU), - .instance_align =3D __alignof(HPPACPU), - .instance_init =3D hppa_cpu_initfn, - .abstract =3D false, - .class_size =3D sizeof(HPPACPUClass), - .class_init =3D hppa_cpu_class_init, +static const TypeInfo hppa_cpu_type_infos[] =3D { + { + .name =3D TYPE_HPPA_CPU, + .parent =3D TYPE_CPU, + .instance_size =3D sizeof(HPPACPU), + .instance_align =3D __alignof(HPPACPU), + .instance_init =3D hppa_cpu_initfn, + .abstract =3D false, + .class_size =3D sizeof(HPPACPUClass), + .class_init =3D hppa_cpu_class_init, + }, +#ifdef TARGET_HPPA64 + { + .name =3D TYPE_HPPA64_CPU, + .parent =3D TYPE_HPPA_CPU, + .instance_init =3D hppa64_cpu_initfn, + }, +#endif }; =20 -static void hppa_cpu_register_types(void) -{ - type_register_static(&hppa_cpu_type_info); -} - -type_init(hppa_cpu_register_types) +DEFINE_TYPES(hppa_cpu_type_infos) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index f86ea9b9ca..83115c944b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -262,6 +262,7 @@ typedef struct DisasContext { int mmu_idx; int privilege; bool psw_n_nonzero; + bool is_pa20; =20 #ifdef CONFIG_USER_ONLY MemOp unalign; @@ -4091,6 +4092,7 @@ static void hppa_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) =20 ctx->cs =3D cs; ctx->tb_flags =3D ctx->base.tb->flags; + ctx->is_pa20 =3D hppa_is_pa20(cpu_env(cs)); =20 #ifdef CONFIG_USER_ONLY ctx->privilege =3D MMU_IDX_TO_PRIV(MMU_USER_IDX); --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835405; cv=none; d=zohomail.com; s=zohoarc; b=Jfdgkftt5aLpGeFuCHzTjnxjgIZunAJDPLUSHeSCxDMk1ln1gc2H4d2B8P9nf12ocIlv4/6rwtSS+qrbxIv6RgB26kBSpvnQbWXngl9Hbu8EUbtBUxLKcpqI8fCoIcZHMe4agz+ySCRpTw8zKxoIXhMWOc6G85r4URaaqeQo9/U= ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834626; x=1698439426; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UGijUKxOjssioK5c9G9sCxgwEWxi/0wrwl9TMa9PkY0=; b=i2DlNLCQ5pbZ4c3vp3z81bYED6D+1uMs5Sfa0XqFMUfKPv0M0mdar+4/VQUCZESS8c rgJGIae5p6zvfsc/bNr2nqgTVk9TBy5BUNbJWJ/5Qn2NKrV5rK2Qz2sJv7YGE8sGKJDt IjFWhuCkmkJp4gvEHFPxeGXxMLJvhZfd8tRrOo8kZeAKcXe6GplRABkCi8vqJdrH/i+1 BVl537irErTfSuKnNwTUPANgCmaEDPl1R76nqe6afp9ky4jlLTcSdrjmAGzoUgHvcpgg i+bAYo7QvR6W1VNLHHImk5S4QB7D+rhhQLXjWW3fsHMdyjagblIBoLJzGZyVnOa3vesJ 3gOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834626; x=1698439426; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UGijUKxOjssioK5c9G9sCxgwEWxi/0wrwl9TMa9PkY0=; b=mEAlchh29DDhVOZMCq7VEzBqK807NgS+aPq0SyB1+xcGqjfcsyKhQFcDm4d2oqOfLj kDP04cqKFyj3AWBCpRrE+zf61fEFoSu1i3dq/Pxd9EwECx3afjV+hs723zs9tbyAtFke UMUUBk/heWg92CueknePF4demjG5ZJyym9lhRedlyt1j9fF8iGgPvwP0JLkDWVMpxPsv eM72c7hkG2W8GMSZOSUDxg53Eu7KjhgyxMFCqJAvNT3okkanT1lvAov+a2syPkm+mw6U B6uwCy8L7d+Rry0G8OEHdQQpfSQlV7PNk4L2dpQO9c/FtEiDeYanHS7iypVZzt+TMgSq VhFg== X-Gm-Message-State: AOJu0YzJ5HQxzdItWTEqZll2Txh/t7zRRd3TI+l2hw5zVrDngdijEOGh YstsiFpSD2H4cmZtVYna9rZSCVhxiIQVj31diuo= X-Google-Smtp-Source: AGHT+IGCkGCjsnpc91uQqcneYTjwC/wonMzBp04nYbQyMsTNgwiNRGFUlqvO74jrd9WcEpMCdvnH/w== X-Received: by 2002:a05:6a21:4983:b0:172:83b8:67f7 with SMTP id ax3-20020a056a21498300b0017283b867f7mr2752274pzc.44.1697834626130; Fri, 20 Oct 2023 13:43:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 14/65] target/hppa: Make HPPA_BTLB_ENTRIES variable Date: Fri, 20 Oct 2023 13:42:40 -0700 Message-Id: <20231020204331.139847-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835406380100001 Content-Type: text/plain; charset="utf-8" Depend on hppa_is_pa20. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 19 +++++++++++-------- hw/hppa/machine.c | 9 +++------ target/hppa/cpu.c | 3 +++ target/hppa/mem_helper.c | 40 ++++++++++++++++++++++------------------ 4 files changed, 39 insertions(+), 32 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 6995eb69ef..60fdd9e295 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -210,15 +210,13 @@ typedef struct CPUArchState { target_ureg cr_back[2]; /* back of cr17/cr18 */ target_ureg shadow[7]; /* shadow registers */ =20 - /* ??? The number of entries isn't specified by the architecture. */ -#ifdef TARGET_HPPA64 -#define HPPA_BTLB_FIXED 0 /* BTLBs are not supported in 64-b= it machines */ -#else -#define HPPA_BTLB_FIXED 16 -#endif -#define HPPA_BTLB_VARIABLE 0 + /* + * ??? The number of entries isn't specified by the architecture. + * BTLBs are not supported in 64-bit machines. + */ +#define PA10_BTLB_FIXED 16 +#define PA10_BTLB_VARIABLE 0 #define HPPA_TLB_ENTRIES 256 -#define HPPA_BTLB_ENTRIES (HPPA_BTLB_FIXED + HPPA_BTLB_VARIABLE) =20 /* ??? Implement a unified itlb/dtlb for the moment. */ /* ??? We should use a more intelligent data structure. */ @@ -248,6 +246,11 @@ static inline bool hppa_is_pa20(CPUHPPAState *env) return object_dynamic_cast(OBJECT(env_cpu(env)), TYPE_HPPA64_CPU) !=3D= NULL; } =20 +static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) +{ + return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE; +} + static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 67d4d1b5e0..85682e6bab 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -185,6 +185,7 @@ static FWCfgState *create_fw_cfg(MachineState *ms, PCIB= us *pci_bus) uint64_t val; const char qemu_version[] =3D QEMU_VERSION; MachineClass *mc =3D MACHINE_GET_CLASS(ms); + int btlb_entries =3D HPPA_BTLB_ENTRIES(&cpu[0]->env); int len; =20 fw_cfg =3D fw_cfg_init_mem(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4); @@ -196,11 +197,11 @@ static FWCfgState *create_fw_cfg(MachineState *ms, PC= IBus *pci_bus) fw_cfg_add_file(fw_cfg, "/etc/firmware-min-version", g_memdup(&val, sizeof(val)), sizeof(val)); =20 - val =3D cpu_to_le64(HPPA_TLB_ENTRIES - HPPA_BTLB_ENTRIES); + val =3D cpu_to_le64(HPPA_TLB_ENTRIES - btlb_entries); fw_cfg_add_file(fw_cfg, "/etc/cpu/tlb_entries", g_memdup(&val, sizeof(val)), sizeof(val)); =20 - val =3D cpu_to_le64(HPPA_BTLB_ENTRIES); + val =3D cpu_to_le64(btlb_entries); fw_cfg_add_file(fw_cfg, "/etc/cpu/btlb_entries", g_memdup(&val, sizeof(val)), sizeof(val)); =20 @@ -608,10 +609,6 @@ static void hppa_machine_reset(MachineState *ms, Shutd= ownCause reason) =20 cs->exception_index =3D -1; cs->halted =3D 0; - - /* clear any existing TLB and BTLB entries */ - memset(cpu[i]->env.tlb, 0, sizeof(cpu[i]->env.tlb)); - cpu[i]->env.tlb_last =3D HPPA_BTLB_ENTRIES; } =20 /* already initialized by machine_hppa_init()? */ diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 192aae268d..e1293857f5 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -139,6 +139,9 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error = **errp) HPPACPU *cpu =3D HPPA_CPU(cs); cpu->alarm_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, hppa_cpu_alarm_timer, cpu); + + memset(cpu->env.tlb, 0, sizeof(cpu->env.tlb)); + cpu->env.tlb_last =3D HPPA_BTLB_ENTRIES(&cpu->env); } #endif } diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 350485f619..48cb5b0d76 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -57,7 +57,7 @@ static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tl= b_entry *ent, HPPA_MMU_FLUSH_MASK, TARGET_LONG_BITS); =20 /* never clear BTLBs, unless forced to do so. */ - if (ent < &env->tlb[HPPA_BTLB_ENTRIES] && !force_flush_btlb) { + if (ent < &env->tlb[HPPA_BTLB_ENTRIES(env)] && !force_flush_btlb) { return; } =20 @@ -68,11 +68,11 @@ static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_= tlb_entry *ent, static hppa_tlb_entry *hppa_alloc_tlb_ent(CPUHPPAState *env) { hppa_tlb_entry *ent; - uint32_t i; + uint32_t i, btlb_entries =3D HPPA_BTLB_ENTRIES(env); =20 - if (env->tlb_last < HPPA_BTLB_ENTRIES || env->tlb_last >=3D ARRAY_SIZE= (env->tlb)) { - i =3D HPPA_BTLB_ENTRIES; - env->tlb_last =3D HPPA_BTLB_ENTRIES + 1; + if (env->tlb_last < btlb_entries || env->tlb_last >=3D ARRAY_SIZE(env-= >tlb)) { + i =3D btlb_entries; + env->tlb_last =3D btlb_entries + 1; } else { i =3D env->tlb_last; env->tlb_last++; @@ -279,7 +279,7 @@ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr= , target_ureg reg) int i; =20 /* Zap any old entries covering ADDR; notice empty entries on the way.= */ - for (i =3D HPPA_BTLB_ENTRIES; i < ARRAY_SIZE(env->tlb); ++i) { + for (i =3D HPPA_BTLB_ENTRIES(env); i < ARRAY_SIZE(env->tlb); ++i) { hppa_tlb_entry *ent =3D &env->tlb[i]; if (ent->va_b <=3D addr && addr <=3D ent->va_e) { if (ent->entry_valid) { @@ -363,11 +363,13 @@ void HELPER(ptlb)(CPUHPPAState *env, target_ulong add= r) number of pages/entries (we choose all), and is local to the cpu. */ void HELPER(ptlbe)(CPUHPPAState *env) { + uint32_t btlb_entries =3D HPPA_BTLB_ENTRIES(env); + trace_hppa_tlb_ptlbe(env); qemu_log_mask(CPU_LOG_MMU, "FLUSH ALL TLB ENTRIES\n"); - memset(&env->tlb[HPPA_BTLB_ENTRIES], 0, - sizeof(env->tlb) - HPPA_BTLB_ENTRIES * sizeof(env->tlb[0])); - env->tlb_last =3D HPPA_BTLB_ENTRIES; + memset(&env->tlb[btlb_entries], 0, + sizeof(env->tlb) - btlb_entries * sizeof(env->tlb[0])); + env->tlb_last =3D btlb_entries; tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK); } =20 @@ -427,12 +429,14 @@ void HELPER(diag_btlb)(CPUHPPAState *env) hppa_tlb_entry *btlb; uint64_t virt_page; uint32_t *vaddr; + uint32_t btlb_entries =3D HPPA_BTLB_ENTRIES(env); =20 -#ifdef TARGET_HPPA64 /* BTLBs are not supported on 64-bit CPUs */ - env->gr[28] =3D -1; /* nonexistent procedure */ - return; -#endif + if (btlb_entries =3D=3D 0) { + env->gr[28] =3D -1; /* nonexistent procedure */ + return; + } + env->gr[28] =3D 0; /* PDC_OK */ =20 switch (env->gr[25]) { @@ -446,8 +450,8 @@ void HELPER(diag_btlb)(CPUHPPAState *env) } else { vaddr[0] =3D cpu_to_be32(1); vaddr[1] =3D cpu_to_be32(16 * 1024); - vaddr[2] =3D cpu_to_be32(HPPA_BTLB_FIXED); - vaddr[3] =3D cpu_to_be32(HPPA_BTLB_VARIABLE); + vaddr[2] =3D cpu_to_be32(PA10_BTLB_FIXED); + vaddr[3] =3D cpu_to_be32(PA10_BTLB_VARIABLE); } break; case 1: @@ -464,7 +468,7 @@ void HELPER(diag_btlb)(CPUHPPAState *env) (long long) virt_page << TARGET_PAGE_BITS, (long long) (virt_page + len) << TARGET_PAGE_BITS, (long long) virt_page, phys_page, len, slot); - if (slot < HPPA_BTLB_ENTRIES) { + if (slot < btlb_entries) { btlb =3D &env->tlb[slot]; /* force flush of possibly existing BTLB entry */ hppa_flush_tlb_ent(env, btlb, true); @@ -484,7 +488,7 @@ void HELPER(diag_btlb)(CPUHPPAState *env) slot =3D env->gr[22]; qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_PURGE slot %d\= n", slot); - if (slot < HPPA_BTLB_ENTRIES) { + if (slot < btlb_entries) { btlb =3D &env->tlb[slot]; hppa_flush_tlb_ent(env, btlb, true); } else { @@ -494,7 +498,7 @@ void HELPER(diag_btlb)(CPUHPPAState *env) case 3: /* Purge all BTLB entries */ qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_PURGE_ALL\n"); - for (slot =3D 0; slot < HPPA_BTLB_ENTRIES; slot++) { + for (slot =3D 0; slot < btlb_entries; slot++) { btlb =3D &env->tlb[slot]; hppa_flush_tlb_ent(env, btlb, true); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835073137100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 5 +++++ target/hppa/cpu.c | 24 ++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 60fdd9e295..e087879399 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -366,4 +366,9 @@ int hppa_artype_for_page(CPUHPPAState *env, target_ulon= g vaddr); #endif G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t r= a); =20 +#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU + +#define cpu_list hppa_cpu_list +void hppa_cpu_list(void); + #endif /* HPPA_CPU_H */ diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index e1293857f5..b063255b30 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -162,6 +162,30 @@ static ObjectClass *hppa_cpu_class_by_name(const char = *cpu_model) return object_class_by_name(TYPE_HPPA_CPU); } =20 +static void hppa_cpu_list_entry(gpointer data, gpointer user_data) +{ + ObjectClass *oc =3D data; + CPUClass *cc =3D CPU_CLASS(oc); + const char *tname =3D object_class_get_name(oc); + g_autofree char *name =3D g_strndup(tname, strchr(tname, '-') - tname); + + if (cc->deprecation_note) { + qemu_printf(" %s (deprecated)\n", name); + } else { + qemu_printf(" %s\n", name); + } +} + +void hppa_cpu_list(void) +{ + GSList *list; + + list =3D object_class_get_list_sorted(TYPE_HPPA_CPU, false); + qemu_printf("Available CPUs:\n"); + g_slist_foreach(list, hppa_cpu_list_entry, NULL); + g_slist_free(list); +} + #ifndef CONFIG_USER_ONLY #include "hw/core/sysemu-cpu-ops.h" =20 --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697834768; cv=none; d=zohomail.com; s=zohoarc; b=I7iOs7OD7NzPUbFYIp94lRcq14676YZKwJ7nFKLZ/vV0WFiWyA6VO/RqeNd9fOyXTLZTna+IuPanCLw+mdq+DvdL1BpLOxt2z605CSfvLRAaBZo1CDlIvTUCbvIq5/x6VzWMlouqAy1XjyxPFSX3dys7bUomkjbVWAmtjnqf4eY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697834768; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834627; x=1698439427; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9ctFFMD0i4UBxb8cY/h6EWp2LE3DVdzDCEH3soxezJg=; b=A0sRakxqQFl7yfixQ3EG/Fvq2FLgA+y/9L/W5+WgGO2kuoDq+wFeASq0ZitjQbU5Qc C9SBJhlL2WHZWidS252JcdmJI91EKbT3f5cVkOJFpKS+2fal02nKjKo51/+xd2CkT4hA /s/lCiuM2qRGHEhusLCWvbtNLJPVsDGSPZ5QMuqDki4zO95IEwd5wssUlh0vdtG8H3+v kF01kYabU7kRY3NSd98o2H4e+GumQwSMdizEhlZMhFO9dM9brK9FgzBZrGAvW7ApzRIt sslVqLF96sZjSA1PqMTvpQVXXgDFutCkESHMoxmVD2XiN3tT9wC7OnnW4XaWXvDGQQox 8Suw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834627; x=1698439427; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834770219100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- linux-user/hppa/target_elf.h | 2 +- target/hppa/cpu.c | 10 +++++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/linux-user/hppa/target_elf.h b/linux-user/hppa/target_elf.h index 82b4e9535e..19cae8bd65 100644 --- a/linux-user/hppa/target_elf.h +++ b/linux-user/hppa/target_elf.h @@ -9,6 +9,6 @@ #define HPPA_TARGET_ELF_H static inline const char *cpu_get_model(uint32_t eflags) { - return "any"; + return "hppa"; } #endif diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index b063255b30..81d51e98b6 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -159,7 +159,15 @@ static void hppa_cpu_initfn(Object *obj) =20 static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) { - return object_class_by_name(TYPE_HPPA_CPU); + g_autofree char *typename =3D g_strconcat(cpu_model, "-cpu", NULL); + ObjectClass *oc =3D object_class_by_name(typename); + + if (oc && + !object_class_is_abstract(oc) && + object_class_dynamic_cast(oc, TYPE_HPPA_CPU)) { + return oc; + } + return NULL; } =20 static void hppa_cpu_list_entry(gpointer data, gpointer user_data) --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834628; x=1698439428; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/Td/Ysv7eoH4uj7r0UKubRW7kAk7MGHOo1UhYXHuswg=; b=jW/ul2Slp828MP+g9H2aGmAcE6rfJS84M1qrSQhvBpG9uDxMxzfg43tzMCzGnWyFUh RHKB1r52nWEtu7EHS7aFf+lyuoB7vXUdf9YZu0+OqGzDLC0/16rIgpmOxxywcpp/tq6z dn7C1LJEn9tJg7zRmyl/VA/32Pd9BV/tts21SyCy5ssoYTqHWCCUr7RSfodtv7Yn2Orv xnCEJ/+hve8m8miHpCIjTjo2IWfTMgm6jnMDQR5fZZlyy4tdC6QY4aIB8qdO2tgxr4eW mJyv1Ms2+ZeaCWQGBhe7CJ+/o1JvB7KwExvNrKx/djw7qJb7A2m+vYKCbQuvC60Df0/M mR4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834628; x=1698439428; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/Td/Ysv7eoH4uj7r0UKubRW7kAk7MGHOo1UhYXHuswg=; b=acuBzn0V4onwTRhABNmHkC7npzKjJA7Y5tcmUmBU1PjN5LzM4OdzDybLyHryUDFMGR /WU+Kt+QTgTUFxgFjasTMRWLSIhCc/ZOiaUKHPQZoa65IXehHJ1uz10nm3Dzasq9w1CC LFxeUeq7Yg0czLsZ4Oj7YvUFYTpBnX5xaoflDUR4PEYoUXESDtUN+jXi6AXVKNgxwbzo J1wuvFSKjznQ8Y7CcPPZrIEmUV4pPHPGXvkQ3qBIbqBK/XbUHTXVaEyuRd3jP3pBaXq+ vfbwOI/M1Uzc5xznVJQbZBM7k5b2vnpk77qt3yDdF6QyDZZXOdgfMtGDm/vsgY+7lYjP YB3A== X-Gm-Message-State: AOJu0YyNKxF84YboBHUv1peRFlDnuvatNCsDil2UPvVdTXaUHwOO59DQ Zbmml2aW+5Tba5cgUR7qbcHS5eYpk/B6JSKLIH8= X-Google-Smtp-Source: AGHT+IEzM4bAcBvwJOt0gYevFx0yP49REFNMh2Bqnh409jBtYHB7nDYtH4N1EmfXAU3BnAR+/5UU/A== X-Received: by 2002:a05:6a20:7fa6:b0:17a:eddb:ac6a with SMTP id d38-20020a056a207fa600b0017aeddbac6amr4113829pzj.6.1697834628432; Fri, 20 Oct 2023 13:43:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 17/65] target/hppa: Update cpu_hppa_get/put_psw for hppa64 Date: Fri, 20 Oct 2023 13:42:43 -0700 Message-Id: <20231020204331.139847-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834705893100001 Content-Type: text/plain; charset="utf-8" With 64-bit registers, there are 16 carry bits in the PSW. Clear reserved bits based on cpu revision. Signed-off-by: Richard Henderson --- target/hppa/helper.c | 63 ++++++++++++++++++++++++++++++++++++-------- 1 file changed, 52 insertions(+), 11 deletions(-) diff --git a/target/hppa/helper.c b/target/hppa/helper.c index a8d3f456ee..534a9e374c 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -28,19 +28,35 @@ target_ureg cpu_hppa_get_psw(CPUHPPAState *env) { target_ureg psw; + target_ureg mask1 =3D (target_ureg)-1 / 0xf; + target_ureg maskf =3D (target_ureg)-1 / 0xffff * 0xf; =20 /* Fold carry bits down to 8 consecutive bits. */ - /* ??? Needs tweaking for hppa64. */ - /* .......b...c...d...e...f...g...h */ - psw =3D (env->psw_cb >> 4) & 0x01111111; - /* .......b..bc..cd..de..ef..fg..gh */ + /* ^^^b^^^c^^^d^^^e^^^f^^^g^^^h^^^i^^^j^^^k^^^l^^^m^^^n^^^o^^^p^^^^ */ + /* ^^^b^^^c^^^d^^^e^^^f^^^g^^^h^^^^ */ + psw =3D (env->psw_cb >> 4) & mask1; + /* .......b...c...d...e...f...g...h...i...j...k...l...m...n...o...p */ + /* .......b...c...d...e...f...g...h */ psw |=3D psw >> 3; - /* .............bcd............efgh */ - psw |=3D (psw >> 6) & 0x000f000f; - /* .........................bcdefgh */ - psw |=3D (psw >> 12) & 0xf; - psw |=3D env->psw_cb_msb << 7; - psw =3D (psw & 0xff) << 8; + /* .......b..bc..cd..de..ef..fg..gh..hi..ij..jk..kl..lm..mn..no..op */ + /* .......b..bc..cd..de..ef..fg..gh */ + psw |=3D psw >> 6; + psw &=3D maskf; + /* .............bcd............efgh............ijkl............mnop */ + /* .............bcd............efgh */ + psw |=3D psw >> 12; + /* .............bcd.........bcdefgh........efghijkl........ijklmnop */ + /* .............bcd.........bcdefgh */ + psw |=3D env->psw_cb_msb << (TARGET_REGISTER_BITS =3D=3D 64 ? 39 : 7); + /* .............bcd........abcdefgh........efghijkl........ijklmnop */ + /* .............bcd........abcdefgh */ + + /* For hppa64, the two 8-bit fields are discontiguous. */ + if (hppa_is_pa20(env)) { + psw =3D (psw & 0xff00000000ull) | ((psw & 0xff) << 8); + } else { + psw =3D (psw & 0xff) << 8; + } =20 psw |=3D env->psw_n * PSW_N; psw |=3D (env->psw_v < 0) * PSW_V; @@ -51,14 +67,39 @@ target_ureg cpu_hppa_get_psw(CPUHPPAState *env) =20 void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) { + uint64_t reserved; target_ureg old_psw =3D env->psw; target_ureg cb =3D 0; =20 + /* Do not allow reserved bits to be set. */ + if (hppa_is_pa20(env)) { + reserved =3D MAKE_64BIT_MASK(40, 24) | MAKE_64BIT_MASK(28, 4); + reserved |=3D PSW_G; /* PA1.x only */ + reserved |=3D PSW_E; /* not implemented */ + } else { + reserved =3D MAKE_64BIT_MASK(32, 32) | MAKE_64BIT_MASK(28, 2); + reserved |=3D PSW_O | PSW_W; /* PA2.0 only */ + reserved |=3D PSW_E | PSW_Y | PSW_Z; /* not implemented */ + } + psw &=3D ~reserved; + env->psw =3D psw & ~(PSW_N | PSW_V | PSW_CB); env->psw_n =3D (psw / PSW_N) & 1; env->psw_v =3D -((psw / PSW_V) & 1); - env->psw_cb_msb =3D (psw >> 15) & 1; =20 +#if TARGET_REGISTER_BITS =3D=3D 32 + env->psw_cb_msb =3D (psw >> 15) & 1; +#else + env->psw_cb_msb =3D (psw >> 39) & 1; + cb |=3D ((psw >> 38) & 1) << 60; + cb |=3D ((psw >> 37) & 1) << 56; + cb |=3D ((psw >> 36) & 1) << 52; + cb |=3D ((psw >> 35) & 1) << 48; + cb |=3D ((psw >> 34) & 1) << 44; + cb |=3D ((psw >> 33) & 1) << 40; + cb |=3D ((psw >> 32) & 1) << 36; + cb |=3D ((psw >> 15) & 1) << 32; +#endif cb |=3D ((psw >> 14) & 1) << 28; cb |=3D ((psw >> 13) & 1) << 24; cb |=3D ((psw >> 12) & 1) << 20; --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697834958; cv=none; d=zohomail.com; s=zohoarc; b=FYYqDsRKX+f90kZ90pe53/U2pxkZPLbvKhR9rOVhJupA+8lncfVy+jeO4mGyJ9BhWjsZqfx+xlaXWN5Vl1JxxLZCvGo9kCVJyikO3f6dsv2ng7h42lJVfWK+tGCWIQ/rbATCkWEqo00vfcDlSE1EYPbMP8rR2mhr9t5lIWAyd4w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697834958; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Bc0q97Cx2QaZpbCyXU6bCv+F4YXYfta8rMxuf/N3B78=; b=D4AXuw9i3dJy5ToyRxLAE5osgj9H4oOq0Pnz+2ZmctSDAD9WlTy9bmrxgpHFZz/0jJGbiXcEDmk2mgS/nh3m0VhHyqdJU/KlfgPAY9nzsrIpil59kOhPB99Udqqic2FSGCbMxYh8DfRGwPLgVpthdZgIvpbGF8gPZnJJ+fgS//k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697834958196779.9093839061053; Fri, 20 Oct 2023 13:49:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwLs-0007pI-6D; Fri, 20 Oct 2023 16:44:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwLd-0007kQ-M3 for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:44:01 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwLW-0008BJ-M2 for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:53 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-6b6f4c118b7so1179584b3a.0 for ; Fri, 20 Oct 2023 13:43:50 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834629; x=1698439429; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Bc0q97Cx2QaZpbCyXU6bCv+F4YXYfta8rMxuf/N3B78=; b=rW/kjKelHxED4dVZpxbclHoxpPgzeOVW9Bx3NWCM7cHYvBKjrHTn2+K4Lp73se4As/ HcWVShCzKZDjSlrGpyrhKrjW6kgsomJwSClOM8cpFZgIIulhBu/vXXNYvw1C8lzWjgaq DF23daqYyVf7xwMBZSaANpjZ6Y7lLV8X1lar6xwn2Fy14I1tvN4Q6HeFtnlRrnZbujQM q+c5RUsX5GtvF/qLV1L7zh2aJL3Oh5pEXPPYaPCDr23GJAxBLQ/bWMU8+tHhk2QgkSOZ dWW97c+5ZvWvICQJ47Y+GS1gHVwG8Zx0ox02VqONvS/EvvwDJRieNTFWQzgqWUEm3c2M dU/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834629; x=1698439429; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Bc0q97Cx2QaZpbCyXU6bCv+F4YXYfta8rMxuf/N3B78=; b=lZ68XeQRv39RPora6Ka4SSaONAZkOw5ji98iyF8gkwjMoSsTO96HEg3JvTYtZ0fWFK 1dX95lPdZJN2yVIE/N+JwBGMSlJ2VF9NRZ32TnYIOnUj+qtfSWzsBPYl780WyxEOvWq2 Kfp3XNqeo6XsCRcX+xMrQZ7zaWNEO0BYwc0z6ar0Uh1aLK+SpGtXl+H/qx+nsCN9WAgy 2a+6WWpLQW18kOX3eVjMBap2Uk67UYFLBXAKCuKyWnrShqjB0Qu+Cmzxhz2agKmiGh9+ RdhGumuOQ00PZR0khgQniIXvbBRUR+uM8Bssc/olBVRxx/xg3pgSFmoDmyY7zA4wBiwY iQnw== X-Gm-Message-State: AOJu0YxPRP1U0SqUMaNFnuTdgsbgAlbGR4YwQz8CSjrBafh+aDmTX7SM BM3I2G68rZrdYK5x0yVKNgVBxdBg3Wdc1oAESXw= X-Google-Smtp-Source: AGHT+IFRrUqCi4F4ezaQ5obwJH+7vkAaJBNwK2avlftUHjM+h601fXnyGJAU6V9UNZwqhhAf6x9dFw== X-Received: by 2002:a05:6a20:918e:b0:179:f81b:12d9 with SMTP id v14-20020a056a20918e00b00179f81b12d9mr3080473pzd.11.1697834629239; Fri, 20 Oct 2023 13:43:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 18/65] target/hppa: Handle absolute addresses for pa2.0 Date: Fri, 20 Oct 2023 13:42:44 -0700 Message-Id: <20231020204331.139847-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834958779100001 Content-Type: text/plain; charset="utf-8" With pa2.0, absolute addresses are not the same as physical addresses, and undergo a transformation based on PSW_W. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 3 +++ target/hppa/helper.c | 4 ++-- target/hppa/mem_helper.c | 49 +++++++++++++++++++++++++++++++++++++--- target/hppa/sys_helper.c | 9 ++++++++ 4 files changed, 60 insertions(+), 5 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index e087879399..622b4af890 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -284,6 +284,9 @@ static inline target_ulong hppa_form_gva(CPUHPPAState *= env, uint64_t spc, return hppa_form_gva_psw(env->psw, spc, off); } =20 +hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr); +hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); + /* * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 534a9e374c..6a00085dae 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -109,8 +109,8 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg ps= w) cb |=3D ((psw >> 8) & 1) << 4; env->psw_cb =3D cb; =20 - /* If PSW_P changes, it affects how we translate addresses. */ - if ((psw ^ old_psw) & PSW_P) { + /* If P or W changes, it affects how we translate addresses. */ + if ((psw ^ old_psw) & (PSW_P | PSW_W)) { #ifndef CONFIG_USER_ONLY tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK); #endif diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 48cb5b0d76..1a63717571 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -25,6 +25,45 @@ #include "hw/core/cpu.h" #include "trace.h" =20 +hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr) +{ + if (likely(extract64(addr, 58, 4) !=3D 0xf)) { + /* Memory address space */ + return addr & MAKE_64BIT_MASK(0, 62); + } + if (extract64(addr, 54, 4) !=3D 0) { + /* I/O address space */ + return addr | MAKE_64BIT_MASK(62, 2); + } + /* PDC address space */ + return (addr & MAKE_64BIT_MASK(0, 54)) | MAKE_64BIT_MASK(60, 4); +} + +hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr) +{ + if (likely(extract32(addr, 28, 4) !=3D 0xf)) { + /* Memory address space */ + return addr & MAKE_64BIT_MASK(0, 32); + } + if (extract32(addr, 24, 4) !=3D 0) { + /* I/O address space */ + return addr | MAKE_64BIT_MASK(32, 32); + } + /* PDC address space */ + return (addr & MAKE_64BIT_MASK(0, 24)) | MAKE_64BIT_MASK(60, 4); +} + +static hwaddr hppa_abs_to_phys(CPUHPPAState *env, vaddr addr) +{ + if (!hppa_is_pa20(env)) { + return addr; + } else if (env->psw & PSW_W) { + return hppa_abs_to_phys_pa2_w1(addr); + } else { + return hppa_abs_to_phys_pa2_w0(addr); + } +} + static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) { int i; @@ -99,7 +138,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr a= ddr, int mmu_idx, =20 /* Virtual translation disabled. Direct map virtual to physical. */ if (mmu_idx =3D=3D MMU_PHYS_IDX) { - phys =3D addr; + phys =3D hppa_abs_to_phys(env, addr); prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; goto egress; } @@ -213,7 +252,7 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr= addr) /* ??? We really ought to know if the code mmu is disabled too, in order to get the correct debugging dumps. */ if (!(cpu->env.psw & PSW_D)) { - return addr; + return hppa_abs_to_phys(&cpu->env, addr); } =20 excp =3D hppa_get_physical_address(&cpu->env, addr, MMU_KERNEL_IDX, 0, @@ -299,7 +338,11 @@ void HELPER(itlba)(CPUHPPAState *env, target_ulong add= r, target_ureg reg) /* Note that empty->entry_valid =3D=3D 0 already. */ empty->va_b =3D addr & TARGET_PAGE_MASK; empty->va_e =3D empty->va_b + TARGET_PAGE_SIZE - 1; - empty->pa =3D extract32(reg, 5, 20) << TARGET_PAGE_BITS; + /* + * FIXME: This is wrong, as this is a pa1.1 function. + * But for the moment translate abs address for pa2.0. + */ + empty->pa =3D hppa_abs_to_phys(env, extract32(reg, 5, 20) << TARGET_PA= GE_BITS); trace_hppa_tlb_itlba(env, empty, empty->va_b, empty->va_e, empty->pa); } =20 diff --git a/target/hppa/sys_helper.c b/target/hppa/sys_helper.c index 4bb4cf611c..f0dd5a08e7 100644 --- a/target/hppa/sys_helper.c +++ b/target/hppa/sys_helper.c @@ -71,6 +71,15 @@ target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, = target_ureg nsm) * so let this go without comment. */ env->psw =3D (psw & ~PSW_SM) | (nsm & PSW_SM); + + /* + * Changes to PSW_W change the translation of absolute to physical. + * This currently (incorrectly) affects all translations. + */ + if ((psw ^ env->psw) & (PSW_P | PSW_W)) { + tlb_flush(env_cpu(env)); + } + return psw & PSW_SM; } =20 --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697834854; cv=none; d=zohomail.com; s=zohoarc; b=n1XGg2yOsnnVyVWlmu0jzam+84fjGZ0LWAnUgeEMId5GBZ0BLOQAsfc2y6ll3yBCl/M57815DCEg8g3D5hVPO72eBku4cA+5F8LkA7gCIIEwblgiAmREDzcjEtuKIBZTKsjRwk+Im5mGlaJ2UsY7XB15v9n9T6RKHMkfcIGd7Jw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697834854; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ka76jULHKdXJXE2rW24+yLIEC0vFTRHnoerX56yKdQY=; b=fnw6U0/3g+FunjvV3pE+zSIwc4aQ5q47xKbb1OHX1O6JB3uOAct8XTjG+v1CoItl6zxS0Raik5Z0WdSpQ3EYUhrUjnocZXioG2Od7pjgzDJbjCbYs+UIY1uP0b4Xz2SGyb6vjtn/6cm3g3XOx89z1LGLAZw2y/dn4yhf85GHzJ8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697834854064566.884624228787; Fri, 20 Oct 2023 13:47:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwLx-0007v6-IE; Fri, 20 Oct 2023 16:44:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwLd-0007kR-Ox for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:44:01 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwLX-0008BU-Qg for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:43:53 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-6b44befac59so1870647b3a.0 for ; Fri, 20 Oct 2023 13:43:50 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834630; x=1698439430; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ka76jULHKdXJXE2rW24+yLIEC0vFTRHnoerX56yKdQY=; b=Qk9+nZ6oQUhUh9SXpMX4MSu6yV0rykmmZVlWtU5JL6qDcKcq2lGWUxbra8bN/CNIco peQ2i6QNEa0WI+OyvRK+XIyHS0HrUCqoKd6ARbG+ln+eQhxYNWwy3eAtDaIAdrfeD1qI uJxtYUgbGbj/wt4G+rYfa7fjTuydqgd+heIUOE/M/eFGjK1oSh1A28bAfsJJGxWWyVuE wkMAAYoPZY4KZBss/RYMnCZ4z7CaJVbUM1g7I6dG0Yd+kqSxPxMMKVXWEq+XpVKwLNa5 2k15bFevOU9GVy9BOST5B3AYdfn3ftEB+SVqCDPwJ+tJLxtpmG1uNTmqnK1x68J7bV57 yYtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834630; x=1698439430; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ka76jULHKdXJXE2rW24+yLIEC0vFTRHnoerX56yKdQY=; b=Ta2f7c9sLKg8+rIOd/QIg6CxaYpYB9KCP9N/xvqFMTgafITaNnqUKW1yiTzi+5oRPO nKkVcVI/6Ip+Gi/bBpaOtvsKOnqka4htiRF+52JWNDyH4DlTJWd8OQc/FRVEzJdw8Yaw Q8lXoIrMhdod9Q4XvSJO5LlssJLSJq1fEv7i+OoDVP3tEe/U6hmWkErBYy4lnlLjHL8H EDPHZWYwC9osr7u/Y3H1xNT5WfHAp+7qW3WAFOCT1pWQUlSeCDnxo5O/pdS2kW4TR6dL F+scVwxzl39sLWNSOE/bFw+gNlINcDwVzQtab0N+MEy/+ENS0EQLx9Z5MECM3uuob5Z5 No/g== X-Gm-Message-State: AOJu0Yw8e1O9INfCPkA0fjcgkdp+xTZKy3SABQQbRSnN0TqSm3bmooPd 0HVVWndRcP3AkyMOftrCPeoE+MDjeAIZITDiCbw= X-Google-Smtp-Source: AGHT+IHs449f6mvQ13E4i6iz+RUOERkmN3ovxLCa64A5qnUQ766ELwz0VtGwlDjOsbbe+J6RGOI6rA== X-Received: by 2002:a05:6a20:a110:b0:17b:40:ccc6 with SMTP id q16-20020a056a20a11000b0017b0040ccc6mr3754626pzk.4.1697834630033; Fri, 20 Oct 2023 13:43:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 19/65] target/hppa: Adjust hppa_cpu_dump_state for hppa64 Date: Fri, 20 Oct 2023 13:42:45 -0700 Message-Id: <20231020204331.139847-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834854435100001 Content-Type: text/plain; charset="utf-8" Dump all 64 bits for pa2.0 and low 32 bits for pa1.x. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/hppa/helper.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 6a00085dae..a2ae7aca30 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -119,18 +119,26 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg = psw) =20 void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - HPPACPU *cpu =3D HPPA_CPU(cs); - CPUHPPAState *env =3D &cpu->env; + CPUHPPAState *env =3D cpu_env(cs); target_ureg psw =3D cpu_hppa_get_psw(env); target_ureg psw_cb; char psw_c[20]; - int i; + int i, w; + uint64_t m; + + if (hppa_is_pa20(env)) { + w =3D 16; + m =3D UINT64_MAX; + } else { + w =3D 8; + m =3D UINT32_MAX; + } =20 qemu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx - " IIR " TREG_FMT_lx "\n", + " IIR %0*" PRIx64 "\n", hppa_form_gva_psw(psw, env->iasq_f, env->iaoq_f), hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b), - env->cr[CR_IIR]); + w, m & env->cr[CR_IIR]); =20 psw_c[0] =3D (psw & PSW_W ? 'W' : '-'); psw_c[1] =3D (psw & PSW_E ? 'E' : '-'); @@ -151,13 +159,15 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int f= lags) psw_c[16] =3D (psw & PSW_D ? 'D' : '-'); psw_c[17] =3D (psw & PSW_I ? 'I' : '-'); psw_c[18] =3D '\0'; - psw_cb =3D ((env->psw_cb >> 4) & 0x01111111) | (env->psw_cb_msb << 28); + psw_cb =3D ((env->psw_cb >> 4) & ((target_ureg)-1 / 0xf)) + | (env->psw_cb_msb << (TARGET_REGISTER_BITS - 4)); =20 - qemu_fprintf(f, "PSW " TREG_FMT_lx " CB " TREG_FMT_lx " %s\n", - psw, psw_cb, psw_c); + qemu_fprintf(f, "PSW %0*" PRIx64 " CB %0*" PRIx64 " %s\n", + w, m & psw, w, m & psw_cb, psw_c); =20 for (i =3D 0; i < 32; i++) { - qemu_fprintf(f, "GR%02d " TREG_FMT_lx "%c", i, env->gr[i], + qemu_fprintf(f, "GR%02d %0*" PRIx64 "%c", + i, w, m & env->gr[i], (i & 3) =3D=3D 3 ? '\n' : ' '); } #ifndef CONFIG_USER_ONLY --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835268; cv=none; d=zohomail.com; s=zohoarc; b=gU5J8/wMikQPuF4LQM5arA7teZtTI96SgGiO8j+VViYcOTW6QOCrxTu4TWwvF+S+vspCKOsQisg50RWIutPySXL1lZae+xC1LcGoraR4StlWjeBj4QTgsEieXkQD8DPgXWxhHmgH12z+XShs56b3QjMqjawgaLobNPSuIUxO+Ws= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697835268; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=kr+C20DtXtMGy3xs/PIBOfM94TBLe/tVvjYddrVGe/s=; b=OpHk9DLRVP2hoPsRle/LZPeijVL6u8DWKwjjqgPmK4LyBQHZ27Klp0ORIMUNQsOdqVnd86HL1WW5RJpezTjMpoXH7Z5SHnJHHKbzGkc4dYl7pwa/Mvd8rexfiU07z34D6AnfD9croABuciqhUGI3Ikau8NwtE0vyE5F4Mc54clQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697835268931803.5449261776308; Fri, 20 Oct 2023 13:54:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwM2-0007yI-LU; Fri, 20 Oct 2023 16:44:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwLh-0007ka-GF for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:44:03 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwLZ-0008Bh-IM for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:44:00 -0400 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-6934202b8bdso1184928b3a.1 for ; Fri, 20 Oct 2023 13:43:51 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834631; x=1698439431; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kr+C20DtXtMGy3xs/PIBOfM94TBLe/tVvjYddrVGe/s=; b=VYK1KCH8P88I1lQcPtliJgur28/Cvh5PwVaYNli3FUZvqQ4CMC//Q3VaFA9ulhfUrJ m69nR+qBddUE4XGtj3uJs1cHY3vni4MulZXd7fpoUlPQtGBBYNmKti6mfABV8hl87nMi 5UO2d4zKb133HyO2SyIJrGGh0NmfC8uvWTz1rKMgDMyVHXXnOREzpejiCqNyL1hQq6tb HwcFjsou36fGqEsSXLJ8qblBfBbfEXoEKHkS2Rc/LNZiZUZyq0efmKNzxcQl4zsnn1AI IDULg2s/WnckL5BQDMFvv5N7SdOSrljNQCdYRL3OTk4xz9Dd282xk8XOV8RIiieaIMPx 7CVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834631; x=1698439431; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kr+C20DtXtMGy3xs/PIBOfM94TBLe/tVvjYddrVGe/s=; b=K713+T4Cf1LIQkrXuAqH737pHUU7z2ZBSerIQ/6CqpzlOPMUO/mxJD/cnGETAhnQJo Dmhlaq1zlS+B41+pWo98oEkZcimxAIXqvmllEkseMjq6Fkbgk7ml0pHURGKCAjYp20lX YWgJfHPZ31UEKa5MqqSdl0/R2n8NtKvkZ9zQ7aKpHKBEmxxpkjZXZ5pOFxXbiaODtAdh QWTUMiWoyUYOXgNqM3Z9XE7exaHw9CASwerIzxSX0pcp5i2PThnP5yMTCOG8I6N1DdAG W+2NK+bUxhTgHZ/91QG7c5eTHP/jtFFIAVrqfOoGvefpxXL6wcFi2PHAay1kIOMkQMuO cKIA== X-Gm-Message-State: AOJu0Yy8OcTd9PVeS5xanpdrNj3NJqKOzWwQLUIKKXle+F5t6nB0uCh1 zrvZFB9F/j1VzUIIzsjJel7JFNZIsbrr+aIrkBw= X-Google-Smtp-Source: AGHT+IGNkexM96nN65R+76815n4z/UR/WGXkS1IA/C5hBtFQGMs40ARITpXnx81Q4qMMQYyWMoe6Ug== X-Received: by 2002:a05:6a00:1747:b0:6b1:c1c4:ae98 with SMTP id j7-20020a056a00174700b006b1c1c4ae98mr3458507pfc.18.1697834630740; Fri, 20 Oct 2023 13:43:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 20/65] target/hppa: Fix hppa64 addressing Date: Fri, 20 Oct 2023 13:42:46 -0700 Message-Id: <20231020204331.139847-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835270047100003 Content-Type: text/plain; charset="utf-8" In form_gva and cpu_get_tb_cpu_state, we must truncate when PSW_W =3D=3D 0. In space_select, the bits that choose the space depend on PSW_W. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 7 +++---- target/hppa/translate.c | 22 +++++++++++++--------- 2 files changed, 16 insertions(+), 13 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 622b4af890..2182437882 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -273,7 +273,7 @@ static inline target_ulong hppa_form_gva_psw(target_ure= g psw, uint64_t spc, #ifdef CONFIG_USER_ONLY return off; #else - off &=3D (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull); + off &=3D psw & PSW_W ? MAKE_64BIT_MASK(0, 62) : MAKE_64BIT_MASK(0, 32); return spc | off; #endif } @@ -314,9 +314,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *e= nv, vaddr *pc, flags |=3D env->psw & (PSW_W | PSW_C | PSW_D); flags |=3D (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; =20 - *pc =3D (env->psw & PSW_C - ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4) - : env->iaoq_f & -4); + *pc =3D hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : = 0), + env->iaoq_f & -4); *cs_base =3D env->iasq_f; =20 /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise = zero diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 83115c944b..c7d17900f1 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -764,6 +764,13 @@ static bool gen_illegal(DisasContext *ctx) } while (0) #endif =20 +static target_ureg gva_offset_mask(DisasContext *ctx) +{ + return (ctx->tb_flags & PSW_W + ? MAKE_64BIT_MASK(0, 62) + : MAKE_64BIT_MASK(0, 32)); +} + static bool use_goto_tb(DisasContext *ctx, target_ureg dest) { return translator_use_goto_tb(&ctx->base, dest); @@ -1398,7 +1405,8 @@ static TCGv_i64 space_select(DisasContext *ctx, int s= p, TCGv_reg base) tmp =3D tcg_temp_new(); spc =3D tcg_temp_new_tl(); =20 - tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5); + /* Extract top 2 bits of the address, shift left 3 for uint64_t index.= */ + tcg_gen_shri_reg(tmp, base, (ctx->tb_flags & PSW_W ? 64 : 32) - 5); tcg_gen_andi_reg(tmp, tmp, 030); tcg_gen_trunc_reg_ptr(ptr, tmp); =20 @@ -1415,6 +1423,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva= , TCGv_reg *pofs, { TCGv_reg base =3D load_gpr(ctx, rb); TCGv_reg ofs; + TCGv_tl addr; =20 /* Note that RX is mutually exclusive with DISP. */ if (rx) { @@ -1429,18 +1438,13 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pg= va, TCGv_reg *pofs, } =20 *pofs =3D ofs; -#ifdef CONFIG_USER_ONLY - *pgva =3D (modify <=3D 0 ? ofs : base); -#else - TCGv_tl addr =3D tcg_temp_new_tl(); + *pgva =3D addr =3D tcg_temp_new_tl(); tcg_gen_extu_reg_tl(addr, modify <=3D 0 ? ofs : base); - if (ctx->tb_flags & PSW_W) { - tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); - } + tcg_gen_andi_tl(addr, addr, gva_offset_mask(ctx)); +#ifndef CONFIG_USER_ONLY if (!is_phys) { tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base)); } - *pgva =3D addr; #endif } =20 --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835152; cv=none; d=zohomail.com; s=zohoarc; b=fFlgyJMrwuQHn+A9pHQrbWDyKegxUzlRkwL47BlFA8QIVAK7FXMVU71Ku9PJbNYeNPEw5OTOs05IoAEfAlXox9Rwdy4SM8oSylqm3YTWWFmnB11cynOH/MonASAeIllkhsCY0r7QuMiNfsFqz1V2zivC9M9t9TkV8HAA+6nDflA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697835152; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DKFMtzklc2r0hLRnVa0CHOkIqsensBgIOA/UoJLswZ8=; b=S9VX83rv5geQnEOl5Jhm0tvflhzTi3lbryoFl8Tb+VAHTtd5L3XfaL38wOg0uDAxs7cP94pYPh6+Rl9/rUo+IEl47yNlWuE00HxLXoax3RmfCxxau+xi+GnIvzpzmmr/LD88Qa4XOtRVAWfYTdgCnCXL4EDhlSPtn3qzr5UIGZI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697835152003111.00805441873013; Fri, 20 Oct 2023 13:52:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwM2-0007yH-HA; Fri, 20 Oct 2023 16:44:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwLh-0007kb-H9 for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:44:03 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwLc-0008Bt-Qa for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:44:00 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6be0277c05bso1102640b3a.0 for ; Fri, 20 Oct 2023 13:43:52 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834631; x=1698439431; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DKFMtzklc2r0hLRnVa0CHOkIqsensBgIOA/UoJLswZ8=; b=n+vv0XYaVqyTsUQorrO2xte/AXynlK78uJjPYUpgjDxEPO89urosIvSTgz1f4112vD z5Fp61HzLGZ3p0QdtiffK8EUo5yqzCoOUFZW8qxDZ298JKb1mmhheEioGdWiypadY0mj Ma2eptDMgYc+ohB7TlYp6a0eaqmAHjCCfMkuFjl4I+AGog9A3erHh1qszZdHhzXvWm87 BBBE+KGL7YJ4prU8496zDifMJhXCF77wttrGJadV54zf0/KBnGXwedeDRZWzuMJACiJN pSku9bvyI4/6MUMIhoB9qaU94NOYbXHoPJldWI8lCgvpAWhARbrMsNyhPuz8pDouEMPF qLig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834631; x=1698439431; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DKFMtzklc2r0hLRnVa0CHOkIqsensBgIOA/UoJLswZ8=; b=MZE+Z/lxQ1gMMFH97VkJ1NnyAKZGr0I/+0f73vBru1ldx6ZqUfzzJ47cDngMkmnAXR 3x+W2m+Z+3LvIGBslHfzO8vgMlExCCDmmP8WHHzTEDJrhjoVO/ZY07FkQrTB5cvb1ZCC RhzFcgomynAZ33FpVh1SLY2KZPNusV2Dv+yO8ErZKx72I1/NgUPKq7IypXrSJNfCaE1N I2AMnnR/aoZZRXLA2Rm/tWyOEzNr0GqhnAHhqOy7FuphKqMMNKBmPbeCI3mOnrG6qWZD Bx1xN1U+hI/3Q0wMyag9dDxMxVGHSNnuO2540DOXhmBoct+ep6AJqDn3cUg4v3ZeelOx Gazw== X-Gm-Message-State: AOJu0YzU/wrJrgJluJBEyjd9pfLph5Ix9+Lhizv8kld0JZP9vdhPxg5o 2yaFEh9hfK47FlSG8bQtjzDm0xKxnwU6v7vUklI= X-Google-Smtp-Source: AGHT+IHsArr4eNcWg5ZDi9MKJsqplA/+pJkOd4kenAcVTUBX+3f1XOMOKQVad0FtSDFV7hRYW9GHyA== X-Received: by 2002:a05:6a20:cea3:b0:174:af85:954b with SMTP id if35-20020a056a20cea300b00174af85954bmr3091205pzb.22.1697834631577; Fri, 20 Oct 2023 13:43:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 21/65] target/hppa: sar register allows only 5 bits on 32-bit CPU Date: Fri, 20 Oct 2023 13:42:47 -0700 Message-Id: <20231020204331.139847-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835153410100003 Content-Type: text/plain; charset="utf-8" From: Helge Deller The sar shift amount register is limited to 5 bits when running a 32-bit CPU. Strip off the remaining bits. The interesting part is, that this register allows to detect at runtime if a physical CPU is capable to execute PA2.0 (64-bit) instructions. Signed-off-by: Helge Deller --- target/hppa/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c7d17900f1..cb60485cbb 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2155,7 +2155,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl = *a) if (ctl =3D=3D CR_SAR) { reg =3D load_gpr(ctx, a->r); tmp =3D tcg_temp_new(); - tcg_gen_andi_reg(tmp, reg, TARGET_REGISTER_BITS - 1); + tcg_gen_andi_reg(tmp, reg, ctx->is_pa20 ? 63 : 31); save_or_nullify(ctx, cpu_sar, tmp); =20 cond_free(&ctx->null_cond); @@ -2216,7 +2216,7 @@ static bool trans_mtsarcm(DisasContext *ctx, arg_mtsa= rcm *a) TCGv_reg tmp =3D tcg_temp_new(); =20 tcg_gen_not_reg(tmp, load_gpr(ctx, a->r)); - tcg_gen_andi_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); + tcg_gen_andi_reg(tmp, tmp, ctx->is_pa20 ? 63 : 31); save_or_nullify(ctx, cpu_sar, tmp); =20 cond_free(&ctx->null_cond); --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697834903; cv=none; d=zohomail.com; s=zohoarc; b=jYa6zgRoRVSGJt1jbNew84n+uPH5hne/wxxPbKdg9rB87Jqfo5GczQEQZ7CauWV381lRTmV/KEeXYOqBbiFLYFvN0OZlY9j2WfzrDiaHizgzwOcDK3s79iE/ZDLdty0hEaR02E26L49N753mJTlalYARHvn6DNrQPQQt/G+oJ60= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697834903; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Zge3ex/yn6oStv5+4EsP6t9DbvB5wzQOrcigC9xjD9g=; b=mqY43eEOHaCm9+JtyR5j4X678ELfSozeiySu9d9Id6OOlXkdqL2jMF7nTqGtTuLYnkkeKn8SFtAzPfAmNcwYEb29hmmtqLnrskpLm5nMQAgWnOwttuovn9KY3M4aH/uvihR7VIn0Ta84aixUbNmDc1VGqT8/Q2s9KTjUJItA9Fo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697834903755431.78369725833545; Fri, 20 Oct 2023 13:48:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwM5-0007yz-DH; Fri, 20 Oct 2023 16:44:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwLk-0007lp-Vi for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:44:08 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwLd-0008C0-IH for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:44:03 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-6bd73395bceso1020900b3a.0 for ; Fri, 20 Oct 2023 13:43:53 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834632; x=1698439432; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zge3ex/yn6oStv5+4EsP6t9DbvB5wzQOrcigC9xjD9g=; b=bFe1R92j1iz1zLM9bnysicrjk0VttdwlJrKhDBGb8eAUaqbYw3T8YWYBQvMkYZ2xjU fDmNPxTQ7h3wYItN3H5oMiwZhM82uo7SiszoQWotWF0fHX21EO4PwagLasyy/hZu+sI9 6dnOxdEm2GFlnTt1iK8vI4y9oLH0GwmnfkDla7pbNzWvy3wepJHvY0cFtlVF5jSgqghL 6DeEPJM0Ue46F4BECGpK4xeOKCqx75m2o/SV1J0hLJpCYee0z0zluoghdT8m7kbTu63B z8w8/HWs3tmsksKd7KZi0En5hgGmpbbPrtLwaNgKGZp58b3cNLqL3Zz9J0EtKVoNc9B/ Ki2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834632; x=1698439432; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zge3ex/yn6oStv5+4EsP6t9DbvB5wzQOrcigC9xjD9g=; b=wVd+eK92N6YkvZL5Ul/EzxKtCdIZ1Q+YFSiOPZJba/VcRvaJGVMlMyi6dKkM/6hpQ5 xlGeewXPcLD9z6sg6aFurRWVTAq+sIts0VwGlr8I3tThidzeceyzTKbPMHq3HndsuTPO 2kT70O1fAcxFl8hADBhlezlJc9fF+F/Xcs4VtVaYa5sojqJB8i2zQZaSFWPQrBkrwgES KQgmaAxAsgSTaEXEvJ75D5n9hjE9qJedTJ8fgYPPWi1fLvcsxGseovAMhqsJ37Lg9Pnj CIQtVaYfi+j4R2zqMeavvUGf7MR2jkJnO8NsrcUTkkFQfjiqGTmhJsXw/002onxeia8k E2wA== X-Gm-Message-State: AOJu0YyTyBXHy3pZ4m3AQGU8jlKKxq27GxxwKoIjkhADjdsPIG0PU7LU oKSRKHI3zDNMq4CWxFeayg/e/YJWpw1T9VmMHzE= X-Google-Smtp-Source: AGHT+IH2D211wsmqXhSSrl8qs171g37dZk6xITI3smIGKU5Dsnc9jgOvIVBvYbWMzdVkF9QNBcuE/Q== X-Received: by 2002:a05:6a20:2593:b0:15d:8366:65be with SMTP id k19-20020a056a20259300b0015d836665bemr3794091pzd.9.1697834632468; Fri, 20 Oct 2023 13:43:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 22/65] target/hppa: Pass d to do_cond Date: Fri, 20 Oct 2023 13:42:48 -0700 Message-Id: <20231020204331.139847-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834904642100003 Content-Type: text/plain; charset="utf-8" Hoist the resolution of d up one level above do_cond. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 82 +++++++++++++++++++++++++++-------------- 1 file changed, 54 insertions(+), 28 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index cb60485cbb..e84311d886 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -814,7 +814,7 @@ static bool cond_need_cb(int c) /* Need extensions from TCGv_i32 to TCGv_reg. */ static bool cond_need_ext(DisasContext *ctx, bool d) { - return TARGET_REGISTER_BITS =3D=3D 64 && !d; + return TARGET_REGISTER_BITS =3D=3D 64 && !(ctx->is_pa20 && d); } =20 /* @@ -822,8 +822,8 @@ static bool cond_need_ext(DisasContext *ctx, bool d) * the Parisc 1.1 Architecture Reference Manual for details. */ =20 -static DisasCond do_cond(unsigned cf, TCGv_reg res, - TCGv_reg cb_msb, TCGv_reg sv) +static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, + TCGv_reg res, TCGv_reg cb_msb, TCGv_reg sv) { DisasCond cond; TCGv_reg tmp; @@ -833,11 +833,19 @@ static DisasCond do_cond(unsigned cf, TCGv_reg res, cond =3D cond_make_f(); break; case 1: /* =3D / <> (Z / !Z) */ + if (cond_need_ext(ctx, d)) { + tmp =3D tcg_temp_new(); + tcg_gen_ext32u_reg(tmp, res); + res =3D tmp; + } cond =3D cond_make_0(TCG_COND_EQ, res); break; case 2: /* < / >=3D (N ^ V / !(N ^ V) */ tmp =3D tcg_temp_new(); tcg_gen_xor_reg(tmp, res, sv); + if (cond_need_ext(ctx, d)) { + tcg_gen_ext32s_reg(tmp, tmp); + } cond =3D cond_make_0_tmp(TCG_COND_LT, tmp); break; case 3: /* <=3D / > (N ^ V) | Z / !((N ^ V) | Z) */ @@ -852,20 +860,35 @@ static DisasCond do_cond(unsigned cf, TCGv_reg res, */ tmp =3D tcg_temp_new(); tcg_gen_eqv_reg(tmp, res, sv); - tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); - tcg_gen_and_reg(tmp, tmp, res); + if (cond_need_ext(ctx, d)) { + tcg_gen_sextract_reg(tmp, tmp, 31, 1); + tcg_gen_and_reg(tmp, tmp, res); + tcg_gen_ext32u_reg(tmp, tmp); + } else { + tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); + tcg_gen_and_reg(tmp, tmp, res); + } cond =3D cond_make_0_tmp(TCG_COND_EQ, tmp); break; case 4: /* NUV / UV (!C / C) */ + /* Only bit 0 of cb_msb is ever set. */ cond =3D cond_make_0(TCG_COND_EQ, cb_msb); break; case 5: /* ZNV / VNZ (!C | Z / C & !Z) */ tmp =3D tcg_temp_new(); tcg_gen_neg_reg(tmp, cb_msb); tcg_gen_and_reg(tmp, tmp, res); + if (cond_need_ext(ctx, d)) { + tcg_gen_ext32u_reg(tmp, tmp); + } cond =3D cond_make_0_tmp(TCG_COND_EQ, tmp); break; case 6: /* SV / NSV (V / !V) */ + if (cond_need_ext(ctx, d)) { + tmp =3D tcg_temp_new(); + tcg_gen_ext32s_reg(tmp, sv); + sv =3D tmp; + } cond =3D cond_make_0(TCG_COND_LT, sv); break; case 7: /* OD / EV */ @@ -887,10 +910,11 @@ static DisasCond do_cond(unsigned cf, TCGv_reg res, can use the inputs directly. This can allow other computation to be deleted as unused. */ =20 -static DisasCond do_sub_cond(unsigned cf, TCGv_reg res, +static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, TCGv_reg res, TCGv_reg in1, TCGv_reg in2, TCGv_reg sv) { DisasCond cond; + bool d =3D false; =20 switch (cf >> 1) { case 1: /* =3D / <> */ @@ -909,7 +933,7 @@ static DisasCond do_sub_cond(unsigned cf, TCGv_reg res, cond =3D cond_make(TCG_COND_LEU, in1, in2); break; default: - return do_cond(cf, res, NULL, sv); + return do_cond(ctx, cf, d, res, NULL, sv); } if (cf & 1) { cond.c =3D tcg_invert_cond(cond.c); @@ -927,8 +951,10 @@ static DisasCond do_sub_cond(unsigned cf, TCGv_reg res, * how cases c=3D{2,3} are treated. */ =20 -static DisasCond do_log_cond(unsigned cf, TCGv_reg res) +static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, TCGv_reg res) { + bool d =3D false; + switch (cf) { case 0: /* never */ case 9: /* undef, C */ @@ -957,7 +983,7 @@ static DisasCond do_log_cond(unsigned cf, TCGv_reg res) =20 case 14: /* OD */ case 15: /* EV */ - return do_cond(cf, res, NULL, NULL); + return do_cond(ctx, cf, d, res, NULL, NULL); =20 default: g_assert_not_reached(); @@ -966,7 +992,7 @@ static DisasCond do_log_cond(unsigned cf, TCGv_reg res) =20 /* Similar, but for shift/extract/deposit conditions. */ =20 -static DisasCond do_sed_cond(unsigned orig, TCGv_reg res) +static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, TCGv_reg re= s) { unsigned c, f; =20 @@ -979,7 +1005,7 @@ static DisasCond do_sed_cond(unsigned orig, TCGv_reg r= es) } f =3D (orig & 4) / 4; =20 - return do_log_cond(c * 2 + f, res); + return do_log_cond(ctx, c * 2 + f, res); } =20 /* Similar, but for unit conditions. */ @@ -1151,7 +1177,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, } =20 /* Emit any conditional trap before any writeback. */ - cond =3D do_cond(cf, dest, cb_cond, sv); + cond =3D do_cond(ctx, cf, d, dest, cb_cond, sv); if (is_tc) { tmp =3D tcg_temp_new(); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); @@ -1241,9 +1267,9 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, =20 /* Compute the condition. We cannot use the special case for borrow. = */ if (!is_b) { - cond =3D do_sub_cond(cf, dest, in1, in2, sv); + cond =3D do_sub_cond(ctx, cf, dest, in1, in2, sv); } else { - cond =3D do_cond(cf, dest, get_carry(ctx, d, cb, cb_msb), sv); + cond =3D do_cond(ctx, cf, d, dest, get_carry(ctx, d, cb, cb_msb), = sv); } =20 /* Emit any conditional trap before any writeback. */ @@ -1306,7 +1332,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt,= TCGv_reg in1, } =20 /* Form the condition for the compare. */ - cond =3D do_sub_cond(cf, dest, in1, in2, sv); + cond =3D do_sub_cond(ctx, cf, dest, in1, in2, sv); =20 /* Clear. */ tcg_gen_movi_reg(dest, 0); @@ -1330,7 +1356,7 @@ static void do_log(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, /* Install the new nullification. */ cond_free(&ctx->null_cond); if (cf) { - ctx->null_cond =3D do_log_cond(cf, dest); + ctx->null_cond =3D do_log_cond(ctx, cf, dest); } } =20 @@ -2796,7 +2822,7 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) /* ??? The lshift is supposed to contribute to overflow. */ sv =3D do_add_sv(ctx, dest, add1, add2); } - ctx->null_cond =3D do_cond(a->cf, dest, cout, sv); + ctx->null_cond =3D do_cond(ctx, a->cf, false, dest, cout, sv); } =20 return nullify_end(ctx); @@ -3013,7 +3039,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TC= Gv_reg in1, sv =3D do_sub_sv(ctx, dest, in1, in2); } =20 - cond =3D do_sub_cond(c * 2 + f, dest, in1, in2, sv); + cond =3D do_sub_cond(ctx, c * 2 + f, dest, in1, in2, sv); return do_cbranch(ctx, disp, n, &cond); } =20 @@ -3057,7 +3083,7 @@ static bool do_addb(DisasContext *ctx, unsigned r, TC= Gv_reg in1, sv =3D do_add_sv(ctx, dest, in1, in2); } =20 - cond =3D do_cond(c * 2 + f, dest, cb_cond, sv); + cond =3D do_cond(ctx, c * 2 + f, d, dest, cb_cond, sv); save_gpr(ctx, r, dest); return do_cbranch(ctx, disp, n, &cond); } @@ -3128,7 +3154,7 @@ static bool trans_movb(DisasContext *ctx, arg_movb *a) tcg_gen_mov_reg(dest, cpu_gr[a->r1]); } =20 - cond =3D do_sed_cond(a->c, dest); + cond =3D do_sed_cond(ctx, a->c, dest); return do_cbranch(ctx, a->disp, a->n, &cond); } =20 @@ -3142,7 +3168,7 @@ static bool trans_movbi(DisasContext *ctx, arg_movbi = *a) dest =3D dest_gpr(ctx, a->r); tcg_gen_movi_reg(dest, a->i); =20 - cond =3D do_sed_cond(a->c, dest); + cond =3D do_sed_cond(ctx, a->c, dest); return do_cbranch(ctx, a->disp, a->n, &cond); } =20 @@ -3180,7 +3206,7 @@ static bool trans_shrpw_sar(DisasContext *ctx, arg_sh= rpw_sar *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); } return nullify_end(ctx); } @@ -3216,7 +3242,7 @@ static bool trans_shrpw_imm(DisasContext *ctx, arg_sh= rpw_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); } return nullify_end(ctx); } @@ -3250,7 +3276,7 @@ static bool trans_extrw_sar(DisasContext *ctx, arg_ex= trw_sar *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); } return nullify_end(ctx); } @@ -3277,7 +3303,7 @@ static bool trans_extrw_imm(DisasContext *ctx, arg_ex= trw_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); } return nullify_end(ctx); } @@ -3314,7 +3340,7 @@ static bool trans_depwi_imm(DisasContext *ctx, arg_de= pwi_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); } return nullify_end(ctx); } @@ -3344,7 +3370,7 @@ static bool trans_depw_imm(DisasContext *ctx, arg_dep= w_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); } return nullify_end(ctx); } @@ -3381,7 +3407,7 @@ static bool do_depw_sar(DisasContext *ctx, unsigned r= t, unsigned c, /* Install the new nullification. */ cond_free(&ctx->null_cond); if (c) { - ctx->null_cond =3D do_sed_cond(c, dest); + ctx->null_cond =3D do_sed_cond(ctx, c, dest); } return nullify_end(ctx); } --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697834739; cv=none; d=zohomail.com; s=zohoarc; b=Lgx6PIa3qqGWpjvUrY9rUu6yIgL86bY0UNzWTN9lO4wUMZz+IGgZo1avvTWR2p4hahuhVN08KOhpGJjNRYDmGA3GopHZVGEq58AvzGiTzsSj6fDSZYWToUlfyR810b3v2IaYGOVRaxOo3fGwEvbhqmo1bJcs79pM6AQR69bnazA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697834739; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834633; x=1698439433; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=61l8ExG3pdb1L+cR7hfS5b3i51MeOrIbY/vnXSWadm4=; b=dCiXlaK2kHSljTK/igJI3QQU27804QsS/5MbTT86LN5C7FvSVIJYoHeS4RkX4i3Irm 6rEgfgFKtTrgcLNULyI97/GK5TuBXtgV9wgNW7acObHqJcSs2SkJFRD7X98Pal/3ISkI Ckkiac44HnIjOlGCNMU7td/asBS7zicdwy8DMt5ptu/5y9ykaFaF7EZrtkOZV8Kgq62q 5pPOzc0QVZ8E9wHabjRJ72F6DHd27JHSNUWrPhE1uSivEDeFuKu/urfupTKFxg+H8IAQ 5lHh3hGn0fBAqZVCnUoyRx2khhiAi+70t9qCH+xuMMlPNYB+kEeD6pvrppL+Z6K85laS PsBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834633; x=1698439433; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=61l8ExG3pdb1L+cR7hfS5b3i51MeOrIbY/vnXSWadm4=; b=THgxj04q5Pmt6OrZpaSeeGXYffnUmf5opypimKVc52MNfTIVemxwD3wtVyhrM+zpYb Qyzxb5Va91FdzeocBJrBXRYiFe4aG9SVrkGFgW9dUTGUdOjlivxPJa6EzQhQnEBnuDwP 3IkbVAPUYCke5lrE3ymriayd/L3fUv+GPKDAkn+1gIMLlGtIhCAxjVsqyptfWgn+LI8W Vnct6zGDq5EYb7nYJc18+pyukVdykVZRwNT6nOBE/WkeUJjA3Ekr9H+gKmGdv6mngiIH 6dlXoolHfVb0hPwxAdzXpsDQVFCTy36zsG8wkBV4RvHSNdFX8ixn6t3bngT4BmBveqIF Zs7w== X-Gm-Message-State: AOJu0Yw1UYkW7zz0OsxKX8NdRAsM1w9W4v/cPPMX+HNzvyx9ir8CL7Lh CXK5tu2GxGT9HhbzSfAyrA4uiEi0TEeL3F69O7k= X-Google-Smtp-Source: AGHT+IF3jRXXKUZw52u4NGvgTX5AK2C0vSZFmtW2TDzykD2d1Pnm9DdeB0LmCeMR6bjDBztfeyF5Uw== X-Received: by 2002:a05:6a00:138f:b0:68f:dd50:aef8 with SMTP id t15-20020a056a00138f00b0068fdd50aef8mr3484027pfg.4.1697834633290; Fri, 20 Oct 2023 13:43:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 23/65] target/hppa: Pass d to do_sub_cond Date: Fri, 20 Oct 2023 13:42:49 -0700 Message-Id: <20231020204331.139847-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834740141100001 Content-Type: text/plain; charset="utf-8" Hoist the resolution of d up one level above do_sub_cond. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 77 ++++++++++++++++++++++++++--------------- 1 file changed, 49 insertions(+), 28 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e84311d886..d480bac03d 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -446,12 +446,15 @@ static DisasCond cond_make_n(void) }; } =20 -static DisasCond cond_make_0_tmp(TCGCond c, TCGv_reg a0) +static DisasCond cond_make_tmp(TCGCond c, TCGv_reg a0, TCGv_reg a1) { assert (c !=3D TCG_COND_NEVER && c !=3D TCG_COND_ALWAYS); - return (DisasCond){ - .c =3D c, .a0 =3D a0, .a1 =3D tcg_constant_reg(0) - }; + return (DisasCond){ .c =3D c, .a0 =3D a0, .a1 =3D a1 }; +} + +static DisasCond cond_make_0_tmp(TCGCond c, TCGv_reg a0) +{ + return cond_make_tmp(c, a0, tcg_constant_reg(0)); } =20 static DisasCond cond_make_0(TCGCond c, TCGv_reg a0) @@ -463,15 +466,12 @@ static DisasCond cond_make_0(TCGCond c, TCGv_reg a0) =20 static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1) { - DisasCond r =3D { .c =3D c }; + TCGv_reg t0 =3D tcg_temp_new(); + TCGv_reg t1 =3D tcg_temp_new(); =20 - assert (c !=3D TCG_COND_NEVER && c !=3D TCG_COND_ALWAYS); - r.a0 =3D tcg_temp_new(); - tcg_gen_mov_reg(r.a0, a0); - r.a1 =3D tcg_temp_new(); - tcg_gen_mov_reg(r.a1, a1); - - return r; + tcg_gen_mov_reg(t0, a0); + tcg_gen_mov_reg(t1, a1); + return cond_make_tmp(c, t0, t1); } =20 static void cond_free(DisasCond *cond) @@ -910,36 +910,55 @@ static DisasCond do_cond(DisasContext *ctx, unsigned = cf, bool d, can use the inputs directly. This can allow other computation to be deleted as unused. */ =20 -static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, TCGv_reg res, - TCGv_reg in1, TCGv_reg in2, TCGv_reg sv) +static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d, + TCGv_reg res, TCGv_reg in1, + TCGv_reg in2, TCGv_reg sv) { - DisasCond cond; - bool d =3D false; + TCGCond tc; + bool ext_uns; =20 switch (cf >> 1) { case 1: /* =3D / <> */ - cond =3D cond_make(TCG_COND_EQ, in1, in2); + tc =3D TCG_COND_EQ; + ext_uns =3D true; break; case 2: /* < / >=3D */ - cond =3D cond_make(TCG_COND_LT, in1, in2); + tc =3D TCG_COND_LT; + ext_uns =3D false; break; case 3: /* <=3D / > */ - cond =3D cond_make(TCG_COND_LE, in1, in2); + tc =3D TCG_COND_LE; + ext_uns =3D false; break; case 4: /* << / >>=3D */ - cond =3D cond_make(TCG_COND_LTU, in1, in2); + tc =3D TCG_COND_LTU; + ext_uns =3D true; break; case 5: /* <<=3D / >> */ - cond =3D cond_make(TCG_COND_LEU, in1, in2); + tc =3D TCG_COND_LEU; + ext_uns =3D true; break; default: return do_cond(ctx, cf, d, res, NULL, sv); } - if (cf & 1) { - cond.c =3D tcg_invert_cond(cond.c); - } =20 - return cond; + if (cf & 1) { + tc =3D tcg_invert_cond(tc); + } + if (cond_need_ext(ctx, d)) { + TCGv_reg t1 =3D tcg_temp_new(); + TCGv_reg t2 =3D tcg_temp_new(); + + if (ext_uns) { + tcg_gen_ext32u_reg(t1, in1); + tcg_gen_ext32u_reg(t2, in2); + } else { + tcg_gen_ext32s_reg(t1, in1); + tcg_gen_ext32s_reg(t2, in2); + } + return cond_make_tmp(tc, t1, t2); + } + return cond_make(tc, in1, in2); } =20 /* @@ -1267,7 +1286,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, =20 /* Compute the condition. We cannot use the special case for borrow. = */ if (!is_b) { - cond =3D do_sub_cond(ctx, cf, dest, in1, in2, sv); + cond =3D do_sub_cond(ctx, cf, d, dest, in1, in2, sv); } else { cond =3D do_cond(ctx, cf, d, dest, get_carry(ctx, d, cb, cb_msb), = sv); } @@ -1321,6 +1340,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt,= TCGv_reg in1, { TCGv_reg dest, sv; DisasCond cond; + bool d =3D false; =20 dest =3D tcg_temp_new(); tcg_gen_sub_reg(dest, in1, in2); @@ -1332,7 +1352,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt,= TCGv_reg in1, } =20 /* Form the condition for the compare. */ - cond =3D do_sub_cond(ctx, cf, dest, in1, in2, sv); + cond =3D do_sub_cond(ctx, cf, d, dest, in1, in2, sv); =20 /* Clear. */ tcg_gen_movi_reg(dest, 0); @@ -3028,6 +3048,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TC= Gv_reg in1, { TCGv_reg dest, in2, sv; DisasCond cond; + bool d =3D false; =20 in2 =3D load_gpr(ctx, r); dest =3D tcg_temp_new(); @@ -3039,7 +3060,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TC= Gv_reg in1, sv =3D do_sub_sv(ctx, dest, in1, in2); } =20 - cond =3D do_sub_cond(ctx, c * 2 + f, dest, in1, in2, sv); + cond =3D do_sub_cond(ctx, c * 2 + f, d, dest, in1, in2, sv); return do_cbranch(ctx, disp, n, &cond); } =20 --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697834954; cv=none; d=zohomail.com; s=zohoarc; b=M82m1x0XtAjkKT6pqqTNDxODvzA8zV+Comf8DhB/0rrsj1jsZea+TPO6ORX28te5q1ERK3rL/nlDJ6W+/NYqNpXVcjefvjDo5hRQJftnpmXSJQ4NJEI5XDAldf9vp56XIJAQPQcfaueW5wQyfAeFy8NwZsHjdeHtkUsRdRCWBac= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697834954; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Bjm4am++QtRrdDOjyV6ZJHM+umovDVM2bFLkEqCxtAk=; b=DwWnEeZ7UTOmyu/9AKmVvE15OBikKnFny+/yLuQpsZIDAoJjUfq+czOS11/KHlhE09TMxToTNzDkwmiLwpc/EuoDrX92ndrOC9xbszSmbfKTQxnDNjToYO5xBQxH/52+vpK24GaSP2GGDhD9Nir+qrSKiDBRyGP5j52+SehYvLI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697834954307685.864565471679; Fri, 20 Oct 2023 13:49:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwM5-0007zb-Sc; Fri, 20 Oct 2023 16:44:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwLj-0007l6-5n for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:44:08 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwLd-0008CM-7V for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:44:01 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-6b26a3163acso1100580b3a.2 for ; Fri, 20 Oct 2023 13:43:54 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834634; x=1698439434; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Bjm4am++QtRrdDOjyV6ZJHM+umovDVM2bFLkEqCxtAk=; b=pzji8I/dj8/xU9X3fl+0d+zcblcAexYgpsEEEtnrUzLBLR/wQGgJqUQ70gxDhjP9Nu cQLujwi6o8MFyOZ4Mk9nUPGZ8mWOHCpcVRyUyhYCJMzww6LsE3wi458Ya7Tpu0Di4XOQ MG7EZtGDQxD3A5ptqOmTmXB5UdmeP1xwAx5QC2nvvGTRX0DqD3SA1uehRtG1tYFKvndJ 5/xwd2Dy6bb2Fw2ZbX1lAyqHkSiv/RDGC8xEmMUmRaIzZFeO1PVq86wfbd1vtQLsUwh3 8+a5gf+3Y1quAYQi+t19H8ifd0c3aFD+2PYx0voBdHVIwo6rKuzRI8M6p6qOhcVd2w8n urGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834634; x=1698439434; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Bjm4am++QtRrdDOjyV6ZJHM+umovDVM2bFLkEqCxtAk=; b=Rccx6pqw6l9KiglkRKbHu1JsxkPICuB9QZhN8ex7h8zBOwv/nsD4DTICu54DHS0bFH NK8ltAWT48zlLuHTjEtaz6jubpYp+A/pg2lXkr3dECw/2vZKDvxdhxXkCqrnpTFu/ANp iBPOhMOJnq/k6KtzC0et/PGQ0n1rmeVTlz2E8wio4iJQIy+NvT1SQJiiBRymtYlPulOx OVyqjs6j44bZo5szbrZEqs7aUYfRX1nevO2BjECZ0rfGfLUma60vXa52eXDup8VQiC5l 3SUIaQAPKowlXPA9wDWht0oHZGXUaoCfrCAn9TZMH6YfSzqhoyckgB3co++wAoEXlw9C m4nw== X-Gm-Message-State: AOJu0Yzfr3Q1XRG04tZf4N1OmWZdF/SeOSxOjcHLVNPEaNs/0vV+MGY6 sQyn4ldS0kdplEYmiwtgfzeb0xm/H3/x+swVFVY= X-Google-Smtp-Source: AGHT+IEMNARZVyv/tJlZTmt0KAFfIkY1al8oV+YgvBUyp06NqT2DQfZm3voslnWtCksiQPr7SUQf6A== X-Received: by 2002:a05:6a00:15c2:b0:693:3be8:feba with SMTP id o2-20020a056a0015c200b006933be8febamr2895362pfu.19.1697834634035; Fri, 20 Oct 2023 13:43:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 24/65] target/hppa: Pass d to do_log_cond Date: Fri, 20 Oct 2023 13:42:50 -0700 Message-Id: <20231020204331.139847-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834954766100001 Content-Type: text/plain; charset="utf-8" Hoist the resolution of d up one level above do_log_cond. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 48 ++++++++++++++++++++++++++++++++--------- 1 file changed, 38 insertions(+), 10 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d480bac03d..d629f5f7f8 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -970,9 +970,11 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsign= ed cf, bool d, * how cases c=3D{2,3} are treated. */ =20 -static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, TCGv_reg res) +static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d, + TCGv_reg res) { - bool d =3D false; + TCGCond tc; + bool ext_uns; =20 switch (cf) { case 0: /* never */ @@ -988,17 +990,29 @@ static DisasCond do_log_cond(DisasContext *ctx, unsig= ned cf, TCGv_reg res) return cond_make_t(); =20 case 2: /* =3D=3D */ - return cond_make_0(TCG_COND_EQ, res); + tc =3D TCG_COND_EQ; + ext_uns =3D true; + break; case 3: /* <> */ - return cond_make_0(TCG_COND_NE, res); + tc =3D TCG_COND_NE; + ext_uns =3D true; + break; case 4: /* < */ - return cond_make_0(TCG_COND_LT, res); + tc =3D TCG_COND_LT; + ext_uns =3D false; + break; case 5: /* >=3D */ - return cond_make_0(TCG_COND_GE, res); + tc =3D TCG_COND_GE; + ext_uns =3D false; + break; case 6: /* <=3D */ - return cond_make_0(TCG_COND_LE, res); + tc =3D TCG_COND_LE; + ext_uns =3D false; + break; case 7: /* > */ - return cond_make_0(TCG_COND_GT, res); + tc =3D TCG_COND_GT; + ext_uns =3D false; + break; =20 case 14: /* OD */ case 15: /* EV */ @@ -1007,6 +1021,18 @@ static DisasCond do_log_cond(DisasContext *ctx, unsi= gned cf, TCGv_reg res) default: g_assert_not_reached(); } + + if (cond_need_ext(ctx, d)) { + TCGv_reg tmp =3D tcg_temp_new(); + + if (ext_uns) { + tcg_gen_ext32u_reg(tmp, res); + } else { + tcg_gen_ext32s_reg(tmp, res); + } + return cond_make_0_tmp(tc, tmp); + } + return cond_make_0(tc, res); } =20 /* Similar, but for shift/extract/deposit conditions. */ @@ -1014,6 +1040,7 @@ static DisasCond do_log_cond(DisasContext *ctx, unsig= ned cf, TCGv_reg res) static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, TCGv_reg re= s) { unsigned c, f; + bool d =3D false; =20 /* Convert the compressed condition codes to standard. 0-2 are the same as logicals (nv,<,<=3D), while 3 is OD. @@ -1024,7 +1051,7 @@ static DisasCond do_sed_cond(DisasContext *ctx, unsig= ned orig, TCGv_reg res) } f =3D (orig & 4) / 4; =20 - return do_log_cond(ctx, c * 2 + f, res); + return do_log_cond(ctx, c * 2 + f, d, res); } =20 /* Similar, but for unit conditions. */ @@ -1368,6 +1395,7 @@ static void do_log(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) { TCGv_reg dest =3D dest_gpr(ctx, rt); + bool d =3D false; =20 /* Perform the operation, and writeback. */ fn(dest, in1, in2); @@ -1376,7 +1404,7 @@ static void do_log(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, /* Install the new nullification. */ cond_free(&ctx->null_cond); if (cf) { - ctx->null_cond =3D do_log_cond(ctx, cf, dest); + ctx->null_cond =3D do_log_cond(ctx, cf, d, dest); } } =20 --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834635; x=1698439435; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BBKuip3A0RhkTWc5ebdaF2DgmzVxIGNwRkilYwMnVKc=; b=SkjZHAepIfLdW5H34mCJtRoeu6DC08sS+XTsnGgD0laB6J4BhwQEOTGux1b+qrK+Od 4+5JZFiTl/3clzl731s+5tdoBB+G2EfVy15KTsDUbaG6cu5/iqEB1LWr1i4FhPht34bm +8kIqxAPAxnCxJE9BbWiI+oznXYv0BGtlWKX5bwUTr5d95yhQqyOm3UXETl6E8O4gdiY nNqR1qIOiwNfpPQ+JkzIHFGBm5oF9HGpiwK5SlXzxCz3ZVi74n+8Pi33NKB1o6MgCvt7 oZhzgp+UwLJskfas8TpU8KvuuufzqSSS6hWH4aG7pGNvxIVmk6c6DVOQgvlBGrd5xZ+E yQkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834635; x=1698439435; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BBKuip3A0RhkTWc5ebdaF2DgmzVxIGNwRkilYwMnVKc=; b=PfdPDpaNzbzZAtqX7JKgN55sfmuruVA/jGVTqy/X5scLjkzjNjxaishi7bDeFv8RLw BcpEGbvMrkj0YULN+t966LMHw8fwF3SkvT1cKg/FQkZDpxmkyOO19HEaQPiymn62vCLc /yUyyaNSyY1JVFfZrA+MD8pzfDd+xOUuCaKK08WyZGD9GbIfec5hzdfIhkrptCoIMX/x fxcNseVZbPM7lGO8G/l02whSBzX8ixjQ//PncQumt/Hknh+irYAp7I5TaJQwqA+wh0/I w45kyTEKpKyZpn9jp1eK3QYbRSJz78lSjCP5DNKpaLz0gaD1Qm+O0BwCYYA3D5XQFybG crAA== X-Gm-Message-State: AOJu0YyYmnKys8FAXgcjt7mj8XGloV1v1MLUzXUM7ib1CMulYcvTZ8o4 mDLqsr4+YN5jaH8brrnnbkHAIJgYZuBI+w87+8w= X-Google-Smtp-Source: AGHT+IECPfGRqnaJ8m1ooi4yCKD6HxdZXYTgDHPkARICpKLFcwCCMaURoYHAUno0sR3Zi2nGvdIUug== X-Received: by 2002:a05:6a20:bb1b:b0:17b:7dda:c0fc with SMTP id fc27-20020a056a20bb1b00b0017b7ddac0fcmr2655742pzb.8.1697834634889; Fri, 20 Oct 2023 13:43:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 25/65] target/hppa: Pass d to do_sed_cond Date: Fri, 20 Oct 2023 13:42:51 -0700 Message-Id: <20231020204331.139847-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835077124100011 Content-Type: text/plain; charset="utf-8" Hoist the resolution of d up one level above do_sed_cond. The MOVB comparison and the existing shift/extract/deposit are all 32-bit. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d629f5f7f8..9995749237 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1037,10 +1037,10 @@ static DisasCond do_log_cond(DisasContext *ctx, uns= igned cf, bool d, =20 /* Similar, but for shift/extract/deposit conditions. */ =20 -static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, TCGv_reg re= s) +static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, bool d, + TCGv_reg res) { unsigned c, f; - bool d =3D false; =20 /* Convert the compressed condition codes to standard. 0-2 are the same as logicals (nv,<,<=3D), while 3 is OD. @@ -3203,7 +3203,8 @@ static bool trans_movb(DisasContext *ctx, arg_movb *a) tcg_gen_mov_reg(dest, cpu_gr[a->r1]); } =20 - cond =3D do_sed_cond(ctx, a->c, dest); + /* All MOVB conditions are 32-bit. */ + cond =3D do_sed_cond(ctx, a->c, false, dest); return do_cbranch(ctx, a->disp, a->n, &cond); } =20 @@ -3217,7 +3218,8 @@ static bool trans_movbi(DisasContext *ctx, arg_movbi = *a) dest =3D dest_gpr(ctx, a->r); tcg_gen_movi_reg(dest, a->i); =20 - cond =3D do_sed_cond(ctx, a->c, dest); + /* All MOVBI conditions are 32-bit. */ + cond =3D do_sed_cond(ctx, a->c, false, dest); return do_cbranch(ctx, a->disp, a->n, &cond); } =20 @@ -3255,7 +3257,7 @@ static bool trans_shrpw_sar(DisasContext *ctx, arg_sh= rpw_sar *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); } return nullify_end(ctx); } @@ -3291,7 +3293,7 @@ static bool trans_shrpw_imm(DisasContext *ctx, arg_sh= rpw_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); } return nullify_end(ctx); } @@ -3325,7 +3327,7 @@ static bool trans_extrw_sar(DisasContext *ctx, arg_ex= trw_sar *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); } return nullify_end(ctx); } @@ -3352,7 +3354,7 @@ static bool trans_extrw_imm(DisasContext *ctx, arg_ex= trw_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); } return nullify_end(ctx); } @@ -3389,7 +3391,7 @@ static bool trans_depwi_imm(DisasContext *ctx, arg_de= pwi_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); } return nullify_end(ctx); } @@ -3419,7 +3421,7 @@ static bool trans_depw_imm(DisasContext *ctx, arg_dep= w_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834636; x=1698439436; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=z2Fl5YhgRkzSF9REjLtMOkcrzmKFDkU8I1AFTwJdP2A=; b=vcvQZwCJ2UXqZUx/rEdiLvl5rQtfm+5CEraMApVzNpOE3Y4ZGaxu2ucRPjlA3BaZT6 V3VJphOYcNisLP39aeFW/XPDuDSFOmkdNOMdo/lKODdRnnmckX4dTttKXA2C/7cBYood 7gX6Do23JLw5ctE8XExQDIk38MGuU5WaQpiuM1hYVXoU4iErtArEGs0KXZmKq9CyvYJM +VoEg4skgOcxTZyCxAhUGDY/pRFisqGVzbeKFtwKU00vRxQZ4EgxyeXv1zbpdo2nH7EE zARWqw2LeeKMl1IipgpEJyhUvFaG7FT/kQicVELEHtDmWfNOUkE5viPVzb83AgAScsUO +2vQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834636; x=1698439436; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z2Fl5YhgRkzSF9REjLtMOkcrzmKFDkU8I1AFTwJdP2A=; b=nkzLefBNn8jzaAqwMXfRluMHPTSxB3I/Z/trRvALiH0jYQuJDXYrwswQJFLBmK7t91 QdfVd2H4IkU38VGN/E32vYPMQo8ajduyTFuTsuMwCBRPc/NeBBpeHHVfSPsB+W6/5dfC S+g9JEQvppJ8zDvhubz42PdfkUM+QXZ/pjHFFljQ9jjIMfSYZdjWTtc7hPzYRktaYZJt /fqUmWUjMCn+PFefWi+HJqOFT83Sn9CwBWf62olrJIR6PcfOY0xF/4Cpu/ruxflWLWoe GfSCatWMvQMILwYGisXS7eAiomwHEC4MTh3VYu98chV40W+Kf/GDn+LmWo2YMHl8gxYs uecA== X-Gm-Message-State: AOJu0Yzamdm0JV4d/TS8FeXrfjrgPWhlrIo1Ny19UOnVp0Jw5CsA6yHa 869J4KD/KBqQtxqhaQYA+Diy/n6T97n0HE4/ooE= X-Google-Smtp-Source: AGHT+IEC5+ZzB0uxsX6Kxlyl107/8O0nB+GJqaSJlzXO5LbLM+79l7jG4tOgh2Ro6MUDcDKDYnSy+Q== X-Received: by 2002:a05:6a00:10c4:b0:6b5:608d:64f6 with SMTP id d4-20020a056a0010c400b006b5608d64f6mr3132724pfu.20.1697834636206; Fri, 20 Oct 2023 13:43:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 26/65] target/hppa: Pass d to do_unit_cond Date: Fri, 20 Oct 2023 13:42:52 -0700 Message-Id: <20231020204331.139847-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834928863100005 Content-Type: text/plain; charset="utf-8" Hoist the resolution of d up one level above do_unit_cond. All computations are logical, and are simplified by using a mask of the correct width, after which the result may be compared with zero. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 9995749237..be1763cb45 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1056,11 +1056,12 @@ static DisasCond do_sed_cond(DisasContext *ctx, uns= igned orig, bool d, =20 /* Similar, but for unit conditions. */ =20 -static DisasCond do_unit_cond(unsigned cf, TCGv_reg res, +static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_reg res, TCGv_reg in1, TCGv_reg in2) { DisasCond cond; TCGv_reg tmp, cb =3D NULL; + target_ureg d_repl =3D d ? 0x0000000100000001ull : 1; =20 if (cf & 8) { /* Since we want to test lots of carry-out bits all at once, do not @@ -1087,32 +1088,32 @@ static DisasCond do_unit_cond(unsigned cf, TCGv_reg= res, * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord */ tmp =3D tcg_temp_new(); - tcg_gen_subi_reg(tmp, res, 0x01010101u); + tcg_gen_subi_reg(tmp, res, d_repl * 0x01010101u); tcg_gen_andc_reg(tmp, tmp, res); - tcg_gen_andi_reg(tmp, tmp, 0x80808080u); + tcg_gen_andi_reg(tmp, tmp, d_repl * 0x80808080u); cond =3D cond_make_0(TCG_COND_NE, tmp); break; =20 case 3: /* SHZ / NHZ */ tmp =3D tcg_temp_new(); - tcg_gen_subi_reg(tmp, res, 0x00010001u); + tcg_gen_subi_reg(tmp, res, d_repl * 0x00010001u); tcg_gen_andc_reg(tmp, tmp, res); - tcg_gen_andi_reg(tmp, tmp, 0x80008000u); + tcg_gen_andi_reg(tmp, tmp, d_repl * 0x80008000u); cond =3D cond_make_0(TCG_COND_NE, tmp); break; =20 case 4: /* SDC / NDC */ - tcg_gen_andi_reg(cb, cb, 0x88888888u); + tcg_gen_andi_reg(cb, cb, d_repl * 0x88888888u); cond =3D cond_make_0(TCG_COND_NE, cb); break; =20 case 6: /* SBC / NBC */ - tcg_gen_andi_reg(cb, cb, 0x80808080u); + tcg_gen_andi_reg(cb, cb, d_repl * 0x80808080u); cond =3D cond_make_0(TCG_COND_NE, cb); break; =20 case 7: /* SHC / NHC */ - tcg_gen_andi_reg(cb, cb, 0x80008000u); + tcg_gen_andi_reg(cb, cb, d_repl * 0x80008000u); cond =3D cond_make_0(TCG_COND_NE, cb); break; =20 @@ -1428,6 +1429,7 @@ static void do_unit(DisasContext *ctx, unsigned rt, T= CGv_reg in1, { TCGv_reg dest; DisasCond cond; + bool d =3D false; =20 if (cf =3D=3D 0) { dest =3D dest_gpr(ctx, rt); @@ -1438,7 +1440,7 @@ static void do_unit(DisasContext *ctx, unsigned rt, T= CGv_reg in1, dest =3D tcg_temp_new(); fn(dest, in1, in2); =20 - cond =3D do_unit_cond(cf, dest, in1, in2); + cond =3D do_unit_cond(cf, d, dest, in1, in2); =20 if (is_tc) { TCGv_reg tmp =3D tcg_temp_new(); --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697834724; cv=none; d=zohomail.com; s=zohoarc; b=TSvlgV3HPDBA5kIQrKBUDm9wC+7HGfhm2Qg1qw/PRBxb0cD/LdYRxzAhKk24ZfuwXllzweCXsr12Ts6JPEz8nWhKAw+TYWHdL1/UEby/z54OMeLSXRIf10gC8A8YE/e1BXVmFtrGnh0wG5gMnjNb5joy92PulGPtxPrkifxWxAg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697834724; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xtkaJF9+gMYoqpzUR8ATyW8aKIy9V4St1iGFcMEqLNY=; b=UkrJUiem0++9bSu+mb2CIUIv4y4+759Cs4hioNAbZ+igLT2jiJhGp162+nD5L9j1L/pfqr0OLYQZ1N29XOEEOCydq1jHLY+bOz0uDZsHDgV4K5UnogPTI8smHpt6zKI408ZB0jasDUi3vxRLHADLRO2+2KxRz1A5pTI7OP7u7bk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697834724481607.8567413226071; Fri, 20 Oct 2023 13:45:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwLt-0007pW-C2; Fri, 20 Oct 2023 16:44:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwLl-0007lt-8N for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:44:09 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwLg-0008EJ-3G for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:44:04 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-6ba172c5f3dso1169952b3a.0 for ; Fri, 20 Oct 2023 13:43:58 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834637; x=1698439437; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xtkaJF9+gMYoqpzUR8ATyW8aKIy9V4St1iGFcMEqLNY=; b=Q1kQJfKi0tLI6b2j2sfX3Ct8L/VNVY4Leijjc9HzBwts34D7JovNpFb/F9PNb9Imxd sbYN1kUL81zZRKscpn3mmWHdSoAACULSeZzwsqedrKLeizHhnbBXit5u1VxwFB4yaVSO nqOwbnqxZfpsmSW6UnZ1ydxt/kC0yFPpEQXTp78+ZgyVpNb5WsBj+d1zZF3oa3NiaL7U FcxhrBadfuGHAsLCsokyQFjgAt3zxD2X5gzNH82U10ZEH0LMoNGD59EVN/JhujWL5igX SdNjQpMzIQYF2Zfy4wi2fRFkyhJfZsxBAYWn2/CxHtrNRkVMGwG/UPoCx40hhfQ8RjOH MS8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834637; x=1698439437; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xtkaJF9+gMYoqpzUR8ATyW8aKIy9V4St1iGFcMEqLNY=; b=ad9zRFLH+8L5YdEBz9lkt2mrg7zOT3vFlpCbnggG0Ev+9JgY5Uy//egrJURsGenMcO cTuoYTcX37IHbq+bBjf+huveKfFNgQySGxeXyEqH0P+p3vN0+PeKrQJIV8JAWuwaNsiR zmW0CkdyNO4AYyRczrdcHiSY5GvVJgI5AY7sJCPyJw0ebsv72gt2wT0DUIkCOjXAsY88 +IFI8vyKZkNyoHKp4bEtkY8tUZeLm7X16PDiijr5WyeMIGaU5lEeX4HGXTLVzXGhVdTU ExlHI4p5AlDJaqSbTXs+ONZSnxUEr/DVbzDTWaQGg8uyik/lSN/4w9/10DFht8kBASfj GCuA== X-Gm-Message-State: AOJu0YwjVUcl5DeUAi5MnktahASDo/lb4EyD7C0kxm5Ijs5hRQ7+TJP7 Vrelwwl+prhB5a7Q/ftC0FajEVyY3i/M70gI1WA= X-Google-Smtp-Source: AGHT+IGM//x5ApiXin/v3nGC26YxLavWQe1ptKNFzJjWZ1x/zIB48HDQf5DRgDfmhQmpXDq3+vPXeA== X-Received: by 2002:a05:6a21:47c6:b0:174:f06:34dc with SMTP id as6-20020a056a2147c600b001740f0634dcmr2418905pzc.28.1697834637418; Fri, 20 Oct 2023 13:43:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 27/65] linux-user/hppa: Fixes for TARGET_ABI32 Date: Fri, 20 Oct 2023 13:42:53 -0700 Message-Id: <20231020204331.139847-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834725982100003 Avoid target_ulong and use abi_* types. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- linux-user/hppa/signal.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/linux-user/hppa/signal.c b/linux-user/hppa/signal.c index ec5f5412d1..4400ce4df4 100644 --- a/linux-user/hppa/signal.c +++ b/linux-user/hppa/signal.c @@ -72,7 +72,7 @@ static void setup_sigcontext(struct target_sigcontext *sc= , CPUArchState *env) =20 static void restore_sigcontext(CPUArchState *env, struct target_sigcontext= *sc) { - target_ulong psw; + abi_ulong psw; int i; =20 __get_user(psw, &sc->sc_gr[0]); @@ -146,10 +146,10 @@ void setup_rt_frame(int sig, struct target_sigaction = *ka, haddr =3D ka->_sa_handler; if (haddr & 2) { /* Function descriptor. */ - target_ulong *fdesc, dest; + abi_ptr *fdesc, dest; =20 haddr &=3D -4; - fdesc =3D lock_user(VERIFY_READ, haddr, 2 * sizeof(target_ulong), = 1); + fdesc =3D lock_user(VERIFY_READ, haddr, 2 * sizeof(abi_ptr), 1); if (!fdesc) { goto give_sigsegv; } --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697834745; cv=none; d=zohomail.com; s=zohoarc; b=LcHAMdyffBxYNfgR6z4okqPxI9zDWXEJ0JB4Pvo01Dtp/UifBLuZpdnNEW/LXEHR8DMd6FUaoj7DQIDvZ49L58PiyWXE7aFVoqtfmyNH5P3PCxGvaetgjehJsup8zk2KnL4lflDaZPLQLWh8TYrsXy7QGfz30fEtEw4wBJ8Reb8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697834745; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fDB1iCB7dFrTdi+sskzC1+DL914HNFrtvGBOgbigGUk=; b=gP7/67RfJlqY81aqHPIwFwsbBFesism08liDTbK+m7nvEWIwniv9qLUbMDIvBykvQuN/xWEjKXAyNLyrLUlOmOvMqoEJZUE5AHAEVyX3mepyhSZg/2C6LW7surPfUxTuAtp9ngjjOJAeMMEwVoO8fwglXruOj3sHLfu65yf4cmE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697834745302846.4877128867383; Fri, 20 Oct 2023 13:45:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwLz-0007wL-TU; Fri, 20 Oct 2023 16:44:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwLl-0007lu-8a for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:44:09 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwLh-0008EV-8j for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:44:04 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-6b497c8575aso1218027b3a.1 for ; Fri, 20 Oct 2023 13:43:59 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834638; x=1698439438; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fDB1iCB7dFrTdi+sskzC1+DL914HNFrtvGBOgbigGUk=; b=TpMVXKfGaKEaDH6VFA+Vv4ks6+LaEGg3C2JeHcCwJPsbo/0JP0/YvZOg3zXvf0MVG4 DPyH6tssDXF5B9BOBNL8MmQnoemL9ilgZLN2tMookuisAxrc6qay7/+gZWcRZZEpJo1p 9VKfwXScwTjUxsmRreu16jC4Ki+EH+HHGdyqEyBk9B6thWPGUITclaXXPhV6ZdYkAM2y zKr03RAT7UK7TiP1VLywFohThBgGnn7SLGyQD+I0ctqwDYXZosDVp9wgxWN8ypwp0dtr fQL5/k2XJxCHAaYBs9Sto1iGyaE+m4MGFKG1F4m9eaUXnPUL3JJGnvpQ3tNhnPXPMR9o XbVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834638; x=1698439438; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fDB1iCB7dFrTdi+sskzC1+DL914HNFrtvGBOgbigGUk=; b=D0oXCps+ml1rMhlsPvAl7M2z1U1jGOjNyUcI3rqHbX6Sqj25EsCNfrEPQjGeMkl3VO it9x7Xp985iSdDl2YsPN6XtJE6yooroJgoy6zqqTxyt3Bf3e9CbTXu1OS2/WT12yQNnb d9IJMGiJgAegHFK+6NLr9uV7kFFjJaUazHKJipsQAc8AaH/DbdfCug4trXD+RSFAs+G1 uPknCZ0b0UW4mz8iH6zUYGK00UENnOjIlTGo3+tP5MGsJF+wOw14Vk2hB9yE8v4hnNEA peAivPw1rvDye/yF96LR1NWTaMaVFuj8h/K1cXPES1BkWG6USbZAveXgUt7hAb9WNao3 E82Q== X-Gm-Message-State: AOJu0YwXvLu5eAtmynHtTQ6CkvrUKaf2VSnDxAZ1MKVPIzp7WMEAP5MU QfCkb6w8eWFW1KZCJrLkKASbSW5S+aasdGzHb5Q= X-Google-Smtp-Source: AGHT+IFkCHfsiIGJL1VO1KrPzgOMlehNMxV2i6uFxPVpEKbcrLZTg12WSlHq1IjSmGdqr2CNtaAkFQ== X-Received: by 2002:a05:6a00:24c6:b0:690:1c1b:aefd with SMTP id d6-20020a056a0024c600b006901c1baefdmr3062144pfv.5.1697834638209; Fri, 20 Oct 2023 13:43:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 28/65] target/hppa: Drop attempted gdbstub support for hppa64 Date: Fri, 20 Oct 2023 13:42:54 -0700 Message-Id: <20231020204331.139847-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834746041100001 Content-Type: text/plain; charset="utf-8" There is no support for hppa64 in gdb. Any attempt to provide the data for the larger hppa64 registers results in an error from gdb. Mask CR_SAR writes to the width of the register: 5 or 6 bits. Signed-off-by: Richard Henderson --- target/hppa/gdbstub.c | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index 48a514384f..4a965b38d7 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -21,11 +21,16 @@ #include "cpu.h" #include "gdbstub/helpers.h" =20 +/* + * GDB 15 only supports PA1.0 via the remote protocol, and ignores + * any provided xml. Which means that any attempt to provide more + * data results in "Remote 'g' packet reply is too long". + */ + int hppa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - HPPACPU *cpu =3D HPPA_CPU(cs); - CPUHPPAState *env =3D &cpu->env; - target_ureg val; + CPUHPPAState *env =3D cpu_env(cs); + uint32_t val; =20 switch (n) { case 0: @@ -139,24 +144,13 @@ int hppa_cpu_gdb_read_register(CPUState *cs, GByteArr= ay *mem_buf, int n) break; } =20 - if (TARGET_REGISTER_BITS =3D=3D 64) { - return gdb_get_reg64(mem_buf, val); - } else { - return gdb_get_reg32(mem_buf, val); - } + return gdb_get_reg32(mem_buf, val); } =20 int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - HPPACPU *cpu =3D HPPA_CPU(cs); - CPUHPPAState *env =3D &cpu->env; - target_ureg val; - - if (TARGET_REGISTER_BITS =3D=3D 64) { - val =3D ldq_p(mem_buf); - } else { - val =3D ldl_p(mem_buf); - } + CPUHPPAState *env =3D cpu_env(cs); + uint32_t val =3D ldl_p(mem_buf); =20 switch (n) { case 0: @@ -166,7 +160,7 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *= mem_buf, int n) env->gr[n] =3D val; break; case 32: - env->cr[CR_SAR] =3D val; + env->cr[CR_SAR] =3D val & (hppa_is_pa20(env) ? 63 : 31); break; case 33: env->iaoq_f =3D val; @@ -278,5 +272,5 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *= mem_buf, int n) } break; } - return sizeof(target_ureg); + return 4; } --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835110; cv=none; d=zohomail.com; s=zohoarc; b=KzYu5QLJtau5qEZxrqHlI/S0+XGC/XuKGQvQbZGewYnpU9NW+hWR7omZC9J+7iY1Vj5v7GSWFerQvaKYphoXhT6w/SaX3Nh/pd/7lWiIyV2dB3EVAjLSnMEx/5reLYEX8d9HpJAsInGJUSoeT63h22i0K33rXeX9jp+Yk9n+0Io= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697835110; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mLJZOZT+lQfb7f2jxY8G9POC0Jl6++4YjRa95Z5whBs=; b=C6Yo4se9jucE1uj5VNqSwlAPr3YXh8dwN8WzYDfOWxXxhqy+CjFp6c6zcN0iGH7urHq6w3eq0Q8tzekXQhW9JxKyNbcfh5zX9x0Eos1xS1ezQHaY/kjKi2gK+hpGcLes9NknPWCwTM58I2J56XiUjTJXlL92iGRlFMZbPyxVmD0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697835110547293.5480608196141; Fri, 20 Oct 2023 13:51:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwLt-0007rE-T8; Fri, 20 Oct 2023 16:44:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwLl-0007lv-9M for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:44:09 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwLh-0008Ea-92 for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:44:04 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-6b5cac99cfdso1154679b3a.2 for ; Fri, 20 Oct 2023 13:44:00 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.43.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:43:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834639; x=1698439439; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mLJZOZT+lQfb7f2jxY8G9POC0Jl6++4YjRa95Z5whBs=; b=KEmwcthD0ITAkDvHlOVkgAITZWT2k6uUCKsn5oIA5QBzGR4Z8oKycd+y3lo3ge9ptF HYXOuAW0IuwhEhkRCstIxOjsI92vz83Zf5lQQoKLzfBm2QmbnO4dfRma/iTYmo8Hw5jm AzaXWhkx6sPsaGM/AuokX3NIhS5Fo3BEo/I7vbParkzH/+HDJk0pbD77PydiRKmDGoQD GVthDp/ITnhzptsKybxFsOVtyi6Gj+7MavTlNy+k2sCisZr7Ka03HlFaN1xq7vnO/SHU iY6w0irGT8Wm8kcQfFpD+9XzlCP3BcyzZrejmwQQc6vmJScI/FgSkGzw9xhlFoJjduy2 exPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834639; x=1698439439; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mLJZOZT+lQfb7f2jxY8G9POC0Jl6++4YjRa95Z5whBs=; b=MR6TUUDcLHSJpymoBJtcvW4CJm87Qd6ZHLHHi6nOJXNP55nw01tgNEsDdiz/b6Tjbo OERlhFBmNQxbVv0UYI83Z/WQDS8SvpTggFTWyXM4TKeZi1WKdt4zFkrlr3yTboKbJEIf IwObaBIcLxWuXX/d9PoNKzT2ZGOjLEcaA/trjoKx7KBgSh14DFde2z296ZEDF2nGLouR KeLz2CvKhBz90SfLMDe3YCVxGF5Lebgvbw+jRLgAiC1xhwDp7bKs9lvF9XlJ1rWzRY8R rtQw1Z5VM6CF2tO+7GuWk/XLVue/SmvclXVATMfFItmZw4r3jV7W7DF8J99KsgSbjwSu v5GA== X-Gm-Message-State: AOJu0Yxml19zMRjcoWsWBi2SREvJ3sSiuV70BSEDMZZK+ye0JH6vg2hI 3NIkvxOV/QQHGHCLryhrAXd1v67gpC+VC1+X/jA= X-Google-Smtp-Source: AGHT+IGfwqAUNIaFqmf7/BNw4Jab48mDUqppZWmGj3apEd+xxoRYtt1/uEx9Op5WItnVXOQ5oso5sQ== X-Received: by 2002:a05:6a20:258b:b0:15e:bb88:b771 with SMTP id k11-20020a056a20258b00b0015ebb88b771mr2486228pzd.37.1697834639434; Fri, 20 Oct 2023 13:43:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 29/65] target/hppa: Remove TARGET_HPPA64 Date: Fri, 20 Oct 2023 13:42:55 -0700 Message-Id: <20231020204331.139847-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835111231100005 Content-Type: text/plain; charset="utf-8" Allow both user-only and system mode to run pa2.0 cpus. Avoid creating a separate qemu-system-hppa64 binary; force the qemu-hppa binary to use TARGET_ABI32. Signed-off-by: Richard Henderson --- configs/targets/hppa-linux-user.mak | 1 + target/hppa/cpu-param.h | 23 +++++++---------------- target/hppa/cpu.h | 9 --------- target/hppa/cpu.c | 3 --- target/hppa/translate.c | 2 -- 5 files changed, 8 insertions(+), 30 deletions(-) diff --git a/configs/targets/hppa-linux-user.mak b/configs/targets/hppa-lin= ux-user.mak index 361ea39d71..8e0a80492f 100644 --- a/configs/targets/hppa-linux-user.mak +++ b/configs/targets/hppa-linux-user.mak @@ -1,4 +1,5 @@ TARGET_ARCH=3Dhppa +TARGET_ABI32=3Dy TARGET_SYSTBL_ABI=3Dcommon,32 TARGET_SYSTBL=3Dsyscall.tbl TARGET_BIG_ENDIAN=3Dy diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index c2791ae5f2..2fb8e7924b 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -8,26 +8,17 @@ #ifndef HPPA_CPU_PARAM_H #define HPPA_CPU_PARAM_H =20 -#ifdef TARGET_HPPA64 -# define TARGET_LONG_BITS 64 -# define TARGET_REGISTER_BITS 64 -# define TARGET_VIRT_ADDR_SPACE_BITS 64 -# define TARGET_PHYS_ADDR_SPACE_BITS 64 -#elif defined(CONFIG_USER_ONLY) -# define TARGET_LONG_BITS 32 -# define TARGET_REGISTER_BITS 32 +#define TARGET_LONG_BITS 64 +#define TARGET_REGISTER_BITS 64 + +#if defined(CONFIG_USER_ONLY) && defined(TARGET_ABI32) +# define TARGET_PHYS_ADDR_SPACE_BITS 32 # define TARGET_VIRT_ADDR_SPACE_BITS 32 -# define TARGET_PHYS_ADDR_SPACE_BITS 32 #else -/* - * In order to form the GVA from space:offset, - * we need a 64-bit virtual address space. - */ -# define TARGET_LONG_BITS 64 -# define TARGET_REGISTER_BITS 32 +# define TARGET_PHYS_ADDR_SPACE_BITS 64 # define TARGET_VIRT_ADDR_SPACE_BITS 64 -# define TARGET_PHYS_ADDR_SPACE_BITS 32 #endif + #define TARGET_PAGE_BITS 12 =20 #endif diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 2182437882..8320f82464 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -107,11 +107,7 @@ #define PSW_T 0x01000000 #define PSW_S 0x02000000 #define PSW_E 0x04000000 -#ifdef TARGET_HPPA64 #define PSW_W 0x08000000 /* PA2.0 only */ -#else -#define PSW_W 0 -#endif #define PSW_Z 0x40000000 /* PA1.x only */ #define PSW_Y 0x80000000 /* PA1.x only */ =20 @@ -124,13 +120,8 @@ #define PSW_SM_P PSW_P #define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */ #define PSW_SM_R PSW_R /* Enable Recover Counter Trap */ -#ifdef TARGET_HPPA64 #define PSW_SM_E 0x100 #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ -#else -#define PSW_SM_E 0 -#define PSW_SM_W 0 -#endif =20 #define CR_RC 0 #define CR_PID1 8 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 81d51e98b6..36875a6a1a 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -253,13 +253,10 @@ static const TypeInfo hppa_cpu_type_infos[] =3D { .class_size =3D sizeof(HPPACPUClass), .class_init =3D hppa_cpu_class_init, }, -#ifdef TARGET_HPPA64 { .name =3D TYPE_HPPA64_CPU, .parent =3D TYPE_HPPA_CPU, - .instance_init =3D hppa64_cpu_initfn, }, -#endif }; =20 DEFINE_TYPES(hppa_cpu_type_infos) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index be1763cb45..450f64bac3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2156,7 +2156,6 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl = *a) =20 switch (ctl) { case CR_SAR: -#ifdef TARGET_HPPA64 if (a->e =3D=3D 0) { /* MFSAR without ,W masks low 5 bits. */ tmp =3D dest_gpr(ctx, rt); @@ -2164,7 +2163,6 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl = *a) save_gpr(ctx, rt, tmp); goto done; } -#endif save_gpr(ctx, rt, cpu_sar); goto done; case CR_IT: /* Interval Timer */ --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835063; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835065098100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 10 ++++++---- target/hppa/translate.c | 15 +++++++-------- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index aebe03ccfd..26ca9f1063 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -61,6 +61,7 @@ =20 &rr_cf t r cf &rrr_cf t r1 r2 cf +&rrr_cf_d t r1 r2 cf d &rrr_cf_sh t r1 r2 cf sh &rri_cf t r i cf =20 @@ -73,6 +74,7 @@ =20 @rr_cf ...... r:5 ..... cf:4 ....... t:5 &rr_cf @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf +@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d @rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh @rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=3D0 @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=3D%lowsi= gn_11 @@ -150,10 +152,10 @@ lci 000001 ----- ----- -- 01001100 0 t:5 # Arith/Log #### =20 -andcm 000010 ..... ..... .... 000000 - ..... @rrr_cf -and 000010 ..... ..... .... 001000 - ..... @rrr_cf -or 000010 ..... ..... .... 001001 - ..... @rrr_cf -xor 000010 ..... ..... .... 001010 0 ..... @rrr_cf +andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d +and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d +or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d +xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 450f64bac3..733d5fe067 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1392,11 +1392,10 @@ static void do_cmpclr(DisasContext *ctx, unsigned r= t, TCGv_reg in1, } =20 static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, unsigned cf, + TCGv_reg in2, unsigned cf, bool d, void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) { TCGv_reg dest =3D dest_gpr(ctx, rt); - bool d =3D false; =20 /* Perform the operation, and writeback. */ fn(dest, in1, in2); @@ -1409,7 +1408,7 @@ static void do_log(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, } } =20 -static bool do_log_reg(DisasContext *ctx, arg_rrr_cf *a, +static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a, void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) { TCGv_reg tcg_r1, tcg_r2; @@ -1419,7 +1418,7 @@ static bool do_log_reg(DisasContext *ctx, arg_rrr_cf = *a, } tcg_r1 =3D load_gpr(ctx, a->r1); tcg_r2 =3D load_gpr(ctx, a->r2); - do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, fn); + do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, fn); return nullify_end(ctx); } =20 @@ -2672,17 +2671,17 @@ static bool trans_sub_b_tsv(DisasContext *ctx, arg_= rrr_cf *a) return do_sub_reg(ctx, a, true, true, false); } =20 -static bool trans_andcm(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_andcm(DisasContext *ctx, arg_rrr_cf_d *a) { return do_log_reg(ctx, a, tcg_gen_andc_reg); } =20 -static bool trans_and(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_and(DisasContext *ctx, arg_rrr_cf_d *a) { return do_log_reg(ctx, a, tcg_gen_and_reg); } =20 -static bool trans_or(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) { if (a->cf =3D=3D 0) { unsigned r2 =3D a->r2; @@ -2734,7 +2733,7 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf *a) return do_log_reg(ctx, a, tcg_gen_or_reg); } =20 -static bool trans_xor(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_xor(DisasContext *ctx, arg_rrr_cf_d *a) { return do_log_reg(ctx, a, tcg_gen_xor_reg); } --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697834941; cv=none; d=zohomail.com; s=zohoarc; b=Sj4jDJdNE30DNPWJYVjMrePvkbbEjIeBwY7EiZYIHywxqitrQFQFB/q6cEazp+IlV5Fgqijl74kUMmib/VpO50sLmTkBJqIpkaDg6boA06hB0LbFH4xavy8juD0tcgANEkdGwZAjvfSoGVf3pW18vbzx96zjUK9cQgIRohow/9o= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834942762100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 14 +++++++------- target/hppa/translate.c | 25 ++++++++++++------------- 2 files changed, 19 insertions(+), 20 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 26ca9f1063..03b1a11cac 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -59,7 +59,7 @@ # All insns that need to form a virtual address should use this set. &ldst t b x disp sp m scale size =20 -&rr_cf t r cf +&rr_cf_d t r cf d &rrr_cf t r1 r2 cf &rrr_cf_d t r1 r2 cf d &rrr_cf_sh t r1 r2 cf sh @@ -72,7 +72,7 @@ # Format definitions #### =20 -@rr_cf ...... r:5 ..... cf:4 ....... t:5 &rr_cf +@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf @rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d @rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh @@ -156,13 +156,13 @@ andcm 000010 ..... ..... .... 000000 . ....= . @rrr_cf_d and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d -uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf +uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf -uaddcm 000010 ..... ..... .... 100110 0 ..... @rrr_cf -uaddcm_tc 000010 ..... ..... .... 100111 0 ..... @rrr_cf -dcor 000010 ..... 00000 .... 101110 0 ..... @rr_cf -dcor_i 000010 ..... 00000 .... 101111 0 ..... @rr_cf +uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d +uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d +dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d +dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d =20 add 000010 ..... ..... .... 0110.. - ..... @rrr_cf_sh add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 733d5fe067..c08156772a 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1423,12 +1423,11 @@ static bool do_log_reg(DisasContext *ctx, arg_rrr_c= f_d *a, } =20 static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, unsigned cf, bool is_tc, + TCGv_reg in2, unsigned cf, bool d, bool is_tc, void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) { TCGv_reg dest; DisasCond cond; - bool d =3D false; =20 if (cf =3D=3D 0) { dest =3D dest_gpr(ctx, rt); @@ -2751,7 +2750,7 @@ static bool trans_cmpclr(DisasContext *ctx, arg_rrr_c= f *a) return nullify_end(ctx); } =20 -static bool trans_uxor(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_uxor(DisasContext *ctx, arg_rrr_cf_d *a) { TCGv_reg tcg_r1, tcg_r2; =20 @@ -2760,11 +2759,11 @@ static bool trans_uxor(DisasContext *ctx, arg_rrr_c= f *a) } tcg_r1 =3D load_gpr(ctx, a->r1); tcg_r2 =3D load_gpr(ctx, a->r2); - do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, false, tcg_gen_xor_reg); + do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, false, tcg_gen_xor_reg= ); return nullify_end(ctx); } =20 -static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf *a, bool is_tc) +static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc) { TCGv_reg tcg_r1, tcg_r2, tmp; =20 @@ -2775,21 +2774,21 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf= *a, bool is_tc) tcg_r2 =3D load_gpr(ctx, a->r2); tmp =3D tcg_temp_new(); tcg_gen_not_reg(tmp, tcg_r2); - do_unit(ctx, a->t, tcg_r1, tmp, a->cf, is_tc, tcg_gen_add_reg); + do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_reg); return nullify_end(ctx); } =20 -static bool trans_uaddcm(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a) { return do_uaddcm(ctx, a, false); } =20 -static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf_d *a) { return do_uaddcm(ctx, a, true); } =20 -static bool do_dcor(DisasContext *ctx, arg_rr_cf *a, bool is_i) +static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i) { TCGv_reg tmp; =20 @@ -2800,19 +2799,19 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf *a= , bool is_i) if (!is_i) { tcg_gen_not_reg(tmp, tmp); } - tcg_gen_andi_reg(tmp, tmp, 0x11111111); + tcg_gen_andi_reg(tmp, tmp, (target_ureg)0x1111111111111111ull); tcg_gen_muli_reg(tmp, tmp, 6); - do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, false, + do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, a->d, false, is_i ? tcg_gen_add_reg : tcg_gen_sub_reg); return nullify_end(ctx); } =20 -static bool trans_dcor(DisasContext *ctx, arg_rr_cf *a) +static bool trans_dcor(DisasContext *ctx, arg_rr_cf_d *a) { return do_dcor(ctx, a, false); } =20 -static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf *a) +static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf_d *a) { return do_dcor(ctx, a, true); } --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697834896; cv=none; d=zohomail.com; s=zohoarc; b=WtTDtAvz3wPvYknViTvwanz4yMo50nq9EHc1JDCukVwm7fnw31qo0Fm5JukzU8mGQ07w1f3U8z/DK09Mhsj3ogItSaO9u08BQgfs/2Un5N2Q27sT9Y2xGZN/cMD7837qn3x24mtHxFc4C8FJN/z79XRU2NseEwpHSNPlTRLCZOc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834896566100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 6 ++++-- target/hppa/translate.c | 11 +++++------ 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 03b1a11cac..d4a03b0299 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -64,6 +64,7 @@ &rrr_cf_d t r1 r2 cf d &rrr_cf_sh t r1 r2 cf sh &rri_cf t r i cf +&rri_cf_d t r i cf d =20 &rrb_c_f disp n c f r1 r2 &rib_c_f disp n c f r i @@ -78,6 +79,7 @@ @rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh @rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=3D0 @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=3D%lowsi= gn_11 +@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=3D%low= sign_11 =20 @rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ &rrb_c_f disp=3D%assemble_12 @@ -158,7 +160,7 @@ or 000010 ..... ..... .... 001001 . ..... = @rrr_cf_d xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf -cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf +cmpclr 000010 ..... ..... .... 100010 . ..... @rrr_cf_d uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d @@ -189,7 +191,7 @@ addi_tc_tsv 101100 ..... ..... .... 1 ........... = @rri_cf subi 100101 ..... ..... .... 0 ........... @rri_cf subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf =20 -cmpiclr 100100 ..... ..... .... 0 ........... @rri_cf +cmpiclr 100100 ..... ..... .... . ........... @rri_cf_d =20 #### # Index Mem diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c08156772a..4bc00d5bc6 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1364,11 +1364,10 @@ static bool do_sub_imm(DisasContext *ctx, arg_rri_c= f *a, bool is_tsv) } =20 static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, unsigned cf) + TCGv_reg in2, unsigned cf, bool d) { TCGv_reg dest, sv; DisasCond cond; - bool d =3D false; =20 dest =3D tcg_temp_new(); tcg_gen_sub_reg(dest, in1, in2); @@ -2737,7 +2736,7 @@ static bool trans_xor(DisasContext *ctx, arg_rrr_cf_d= *a) return do_log_reg(ctx, a, tcg_gen_xor_reg); } =20 -static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf_d *a) { TCGv_reg tcg_r1, tcg_r2; =20 @@ -2746,7 +2745,7 @@ static bool trans_cmpclr(DisasContext *ctx, arg_rrr_c= f *a) } tcg_r1 =3D load_gpr(ctx, a->r1); tcg_r2 =3D load_gpr(ctx, a->r2); - do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf); + do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d); return nullify_end(ctx); } =20 @@ -2904,7 +2903,7 @@ static bool trans_subi_tsv(DisasContext *ctx, arg_rri= _cf *a) return do_sub_imm(ctx, a, true); } =20 -static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf *a) +static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf_d *a) { TCGv_reg tcg_im, tcg_r2; =20 @@ -2914,7 +2913,7 @@ static bool trans_cmpiclr(DisasContext *ctx, arg_rri_= cf *a) =20 tcg_im =3D tcg_constant_reg(a->i); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834794251100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 16 ++++++++-------- target/hppa/translate.c | 21 +++++++++++---------- 2 files changed, 19 insertions(+), 18 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index d4a03b0299..0f29869949 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -62,7 +62,7 @@ &rr_cf_d t r cf d &rrr_cf t r1 r2 cf &rrr_cf_d t r1 r2 cf d -&rrr_cf_sh t r1 r2 cf sh +&rrr_cf_d_sh t r1 r2 cf d sh &rri_cf t r i cf &rri_cf_d t r i cf d =20 @@ -76,8 +76,8 @@ @rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf @rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d -@rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh -@rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=3D0 +@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh +@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=3D0 @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=3D%lowsi= gn_11 @rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=3D%low= sign_11 =20 @@ -166,11 +166,11 @@ uaddcm_tc 000010 ..... ..... .... 100111 . ....= . @rrr_cf_d dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d =20 -add 000010 ..... ..... .... 0110.. - ..... @rrr_cf_sh -add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh -add_tsv 000010 ..... ..... .... 1110.. 0 ..... @rrr_cf_sh -add_c 000010 ..... ..... .... 011100 0 ..... @rrr_cf_sh0 -add_c_tsv 000010 ..... ..... .... 111100 0 ..... @rrr_cf_sh0 +add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh +add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh +add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh +add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0 +add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0 =20 sub 000010 ..... ..... .... 010000 - ..... @rrr_cf sub_tsv 000010 ..... ..... .... 110000 0 ..... @rrr_cf diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 4bc00d5bc6..50be7df76c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1173,12 +1173,11 @@ static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_r= eg res, =20 static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1, TCGv_reg in2, unsigned shift, bool is_l, - bool is_tsv, bool is_tc, bool is_c, unsigned cf) + bool is_tsv, bool is_tc, bool is_c, unsigned cf, bool d) { TCGv_reg dest, cb, cb_msb, cb_cond, sv, tmp; unsigned c =3D cf >> 1; DisasCond cond; - bool d =3D false; =20 dest =3D tcg_temp_new(); cb =3D NULL; @@ -1243,7 +1242,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, ctx->null_cond =3D cond; } =20 -static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_sh *a, +static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_d_sh *a, bool is_l, bool is_tsv, bool is_tc, bool is_c) { TCGv_reg tcg_r1, tcg_r2; @@ -1253,7 +1252,8 @@ static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_= sh *a, } tcg_r1 =3D load_gpr(ctx, a->r1); tcg_r2 =3D load_gpr(ctx, a->r2); - do_add(ctx, a->t, tcg_r1, tcg_r2, a->sh, is_l, is_tsv, is_tc, is_c, a-= >cf); + do_add(ctx, a->t, tcg_r1, tcg_r2, a->sh, is_l, + is_tsv, is_tc, is_c, a->cf, a->d); return nullify_end(ctx); } =20 @@ -1267,7 +1267,8 @@ static bool do_add_imm(DisasContext *ctx, arg_rri_cf = *a, } tcg_im =3D tcg_constant_reg(a->i); tcg_r2 =3D load_gpr(ctx, a->r); - do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf); + /* All ADDI conditions are 32-bit. */ + do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf, false= ); return nullify_end(ctx); } =20 @@ -2614,27 +2615,27 @@ static bool trans_lci(DisasContext *ctx, arg_lci *a) return true; } =20 -static bool trans_add(DisasContext *ctx, arg_rrr_cf_sh *a) +static bool trans_add(DisasContext *ctx, arg_rrr_cf_d_sh *a) { return do_add_reg(ctx, a, false, false, false, false); } =20 -static bool trans_add_l(DisasContext *ctx, arg_rrr_cf_sh *a) +static bool trans_add_l(DisasContext *ctx, arg_rrr_cf_d_sh *a) { return do_add_reg(ctx, a, true, false, false, false); } =20 -static bool trans_add_tsv(DisasContext *ctx, arg_rrr_cf_sh *a) +static bool trans_add_tsv(DisasContext *ctx, arg_rrr_cf_d_sh *a) { return do_add_reg(ctx, a, false, true, false, false); } =20 -static bool trans_add_c(DisasContext *ctx, arg_rrr_cf_sh *a) +static bool trans_add_c(DisasContext *ctx, arg_rrr_cf_d_sh *a) { return do_add_reg(ctx, a, false, false, false, true); } =20 -static bool trans_add_c_tsv(DisasContext *ctx, arg_rrr_cf_sh *a) +static bool trans_add_c_tsv(DisasContext *ctx, arg_rrr_cf_d_sh *a) { return do_add_reg(ctx, a, false, true, false, true); } --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697834750; cv=none; d=zohomail.com; s=zohoarc; b=TAeZb3R2X6izDn1pfWT0a5Pa9mSMubBDdd1bMEWrOA0g+VO1c8zJyqt8LFppUuFlrhX0JT60WGD4t5sggBSbZJeRoOHBaH+kBsro0UGbsJMn7xfDb7FZRba9gNRW1DSRQZXYteA16C7nn+3FsTjQUg7geHGFKMG32UMML6C9tpQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697834750; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ObJx9R3yQ+h7Sn6gc+ZiKm70o/Xu9BpZYR8uMzdovJM=; b=Seq23uBFs70qRenYxbeacVFgKYIPj/dHNEtnVV4PRZTsr8UTALzPIKfFqpZnm/sqepp7WRVQgslgvz3lpEsxY6HnhH2TDBIWRrqpwhaGnHtK+RQ17Pdi2DQ16uhSVC6wtCqdykDS7Q7m3AKIXvj1hva0LffhBoiOlfML58X7aek= ARC-Authentication-Results: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834752132100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 12 ++++++------ target/hppa/translate.c | 22 +++++++++++----------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 0f29869949..ad454adcbb 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -172,12 +172,12 @@ add_tsv 000010 ..... ..... .... 1110.. . ....= . @rrr_cf_d_sh add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0 add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0 =20 -sub 000010 ..... ..... .... 010000 - ..... @rrr_cf -sub_tsv 000010 ..... ..... .... 110000 0 ..... @rrr_cf -sub_tc 000010 ..... ..... .... 010011 0 ..... @rrr_cf -sub_tsv_tc 000010 ..... ..... .... 110011 0 ..... @rrr_cf -sub_b 000010 ..... ..... .... 010100 0 ..... @rrr_cf -sub_b_tsv 000010 ..... ..... .... 110100 0 ..... @rrr_cf +sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d +sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d +sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d +sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d +sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d +sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d =20 ldil 001000 t:5 ..................... i=3D%assemble_21 addil 001010 r:5 ..................... i=3D%assemble_21 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 50be7df76c..df5a6dc896 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1274,12 +1274,11 @@ static bool do_add_imm(DisasContext *ctx, arg_rri_c= f *a, =20 static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1, TCGv_reg in2, bool is_tsv, bool is_b, - bool is_tc, unsigned cf) + bool is_tc, unsigned cf, bool d) { TCGv_reg dest, sv, cb, cb_msb, zero, tmp; unsigned c =3D cf >> 1; DisasCond cond; - bool d =3D false; =20 dest =3D tcg_temp_new(); cb =3D tcg_temp_new(); @@ -1337,7 +1336,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, ctx->null_cond =3D cond; } =20 -static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf *a, +static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tsv, bool is_b, bool is_tc) { TCGv_reg tcg_r1, tcg_r2; @@ -1347,7 +1346,7 @@ static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf = *a, } tcg_r1 =3D load_gpr(ctx, a->r1); tcg_r2 =3D load_gpr(ctx, a->r2); - do_sub(ctx, a->t, tcg_r1, tcg_r2, is_tsv, is_b, is_tc, a->cf); + do_sub(ctx, a->t, tcg_r1, tcg_r2, is_tsv, is_b, is_tc, a->cf, a->d); return nullify_end(ctx); } =20 @@ -1360,7 +1359,8 @@ static bool do_sub_imm(DisasContext *ctx, arg_rri_cf = *a, bool is_tsv) } tcg_im =3D tcg_constant_reg(a->i); tcg_r2 =3D load_gpr(ctx, a->r); - do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf); + /* All SUBI conditions are 32-bit. */ + do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf, false); return nullify_end(ctx); } =20 @@ -2640,32 +2640,32 @@ static bool trans_add_c_tsv(DisasContext *ctx, arg_= rrr_cf_d_sh *a) return do_add_reg(ctx, a, false, true, false, true); } =20 -static bool trans_sub(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_sub(DisasContext *ctx, arg_rrr_cf_d *a) { return do_sub_reg(ctx, a, false, false, false); } =20 -static bool trans_sub_tsv(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_sub_tsv(DisasContext *ctx, arg_rrr_cf_d *a) { return do_sub_reg(ctx, a, true, false, false); } =20 -static bool trans_sub_tc(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_sub_tc(DisasContext *ctx, arg_rrr_cf_d *a) { return do_sub_reg(ctx, a, false, false, true); } =20 -static bool trans_sub_tsv_tc(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_sub_tsv_tc(DisasContext *ctx, arg_rrr_cf_d *a) { return do_sub_reg(ctx, a, true, false, true); } =20 -static bool trans_sub_b(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_sub_b(DisasContext *ctx, arg_rrr_cf_d *a) { return do_sub_reg(ctx, a, false, true, false); } =20 -static bool trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf_d *a) { return do_sub_reg(ctx, a, true, true, false); } --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697834783; cv=none; d=zohomail.com; s=zohoarc; b=BXNkn4LQBGZqo6KDyBwNekwQ5vYdFwaUT4BpjbDwsHuOFQNCliOZDgenZPExgfxdSirOEP4fA94z8ZmdC32IiIoGTd13y4EIaUs1twAuXVeynUtpym0vRjItvfLGO3Snxer+Go/AsCB6EAxBZ00HBdvI+JTUYdGunzlipqiS/p0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697834783; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 4 ++-- target/hppa/translate.c | 6 ++---- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index ad454adcbb..b185523021 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -290,8 +290,8 @@ fmpysub_d 100110 ..... ..... ..... ..... 1 ..... = @mpyadd # Conditional Branches #### =20 -bb_sar 110000 00000 r:5 c:1 10 ........... n:1 . disp=3D%assembl= e_12 -bb_imm 110001 p:5 r:5 c:1 10 ........... n:1 . disp=3D%assembl= e_12 +bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=3D%assem= ble_12 +bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=3D%assem= ble_12 =20 movb 110010 ..... ..... ... ........... . . @rrb_cf f=3D0 movbi 110011 ..... ..... ... ........... . . @rib_cf f=3D0 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index df5a6dc896..543a694724 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3151,13 +3151,12 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_= sar *a) { TCGv_reg tmp, tcg_r; DisasCond cond; - bool d =3D false; =20 nullify_over(ctx); =20 tmp =3D tcg_temp_new(); tcg_r =3D load_gpr(ctx, a->r); - if (cond_need_ext(ctx, d)) { + if (cond_need_ext(ctx, a->d)) { /* Force shift into [32,63] */ tcg_gen_ori_reg(tmp, cpu_sar, 32); tcg_gen_shl_reg(tmp, tcg_r, tmp); @@ -3173,14 +3172,13 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_= imm *a) { TCGv_reg tmp, tcg_r; DisasCond cond; - bool d =3D false; int p; =20 nullify_over(ctx); =20 tmp =3D tcg_temp_new(); tcg_r =3D load_gpr(ctx, a->r); - p =3D a->p | (cond_need_ext(ctx, d) ? 32 : 0); + p =3D a->p | (cond_need_ext(ctx, a->d) ? 32 : 0); tcg_gen_shli_reg(tmp, tcg_r, p); =20 cond =3D cond_make_0(a->c ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834786168100011 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 9 +++++++-- target/hppa/translate.c | 12 ++++++++---- 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index b185523021..fc327e2bb3 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -67,6 +67,7 @@ &rri_cf_d t r i cf d =20 &rrb_c_f disp n c f r1 r2 +&rrb_c_d_f disp n c d f r1 r2 &rib_c_f disp n c f r i =20 #### @@ -83,6 +84,8 @@ =20 @rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ &rrb_c_f disp=3D%assemble_12 +@rrb_cdf ...... r2:5 r1:5 c:3 ........... n:1 . \ + &rrb_c_d_f disp=3D%assemble_12 @rib_cf ...... r:5 ..... c:3 ........... n:1 . \ &rib_c_f disp=3D%assemble_12 i=3D%im5_16 =20 @@ -296,8 +299,10 @@ bb_imm 110001 p:5 r:5 c:1 1 d:1 ...........= n:1 . disp=3D%assemble_12 movb 110010 ..... ..... ... ........... . . @rrb_cf f=3D0 movbi 110011 ..... ..... ... ........... . . @rib_cf f=3D0 =20 -cmpb 100000 ..... ..... ... ........... . . @rrb_cf f=3D0 -cmpb 100010 ..... ..... ... ........... . . @rrb_cf f=3D1 +cmpb 100000 ..... ..... ... ........... . . @rrb_cdf d=3D0 f= =3D0 +cmpb 100010 ..... ..... ... ........... . . @rrb_cdf d=3D0 f= =3D1 +cmpb 100111 ..... ..... ... ........... . . @rrb_cdf d=3D1 f= =3D0 +cmpb 101111 ..... ..... ... ........... . . @rrb_cdf d=3D1 f= =3D1 cmpbi 100001 ..... ..... ... ........... . . @rib_cf f=3D0 cmpbi 100011 ..... ..... ... ........... . . @rib_cf f=3D1 =20 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 543a694724..d1d9a4a137 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3070,11 +3070,10 @@ static bool trans_ldo(DisasContext *ctx, arg_ldo *a) } =20 static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1, - unsigned c, unsigned f, unsigned n, int disp) + unsigned c, unsigned f, bool d, unsigned n, int disp) { TCGv_reg dest, in2, sv; DisasCond cond; - bool d =3D false; =20 in2 =3D load_gpr(ctx, r); dest =3D tcg_temp_new(); @@ -3092,14 +3091,19 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, = TCGv_reg in1, =20 static bool trans_cmpb(DisasContext *ctx, arg_cmpb *a) { + if (!ctx->is_pa20 && a->d) { + return false; + } nullify_over(ctx); - return do_cmpb(ctx, a->r2, load_gpr(ctx, a->r1), a->c, a->f, a->n, a->= disp); + return do_cmpb(ctx, a->r2, load_gpr(ctx, a->r1), + a->c, a->f, a->d, a->n, a->disp); } =20 static bool trans_cmpbi(DisasContext *ctx, arg_cmpbi *a) { nullify_over(ctx); - return do_cmpb(ctx, a->r, tcg_constant_reg(a->i), a->c, a->f, a->n, a-= >disp); + return do_cmpb(ctx, a->r, tcg_constant_reg(a->i), + a->c, a->f, false, a->n, a->disp); } =20 static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1, --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k15-20020aa7998f000000b00688965c5227sm1944975pfh.120.2023.10.20.13.44.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:44:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834646; x=1698439446; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9Y0TWqbSJ7897PJsLkdK8seC1JV+I54PI/WHM1mCLlw=; b=I9rivRQQL2ByoK9jUSheD/9LkC29beFLKI9tAD3om2+tsEsGYeFVPl0biChVXo7Ov1 t7vmi/OjoZbbbPEuHcG1JJ4lO8EwAOj8BCofULZLYWUUJXVID1qeuXci1uor1fZPW3lp sFgw+wRzZ4FFWuXKpnhXEUyf3WUzGHaWEFuuXEajY5djdLDKsQCIhQ4Gb195CEdkfdSP C32X+Yvb+z3GLloge9xXrkFWXgEgiwDTcjSn0u1AgcMbd47fX7PKaE01EtM821LKBCm+ 0SAXBMOOFuoiXauKIUiEapgFoeYcDobP3kjLLPP3z2BgAGrwlzyWWsRw0aGLImm5xHfD NTfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834646; x=1698439446; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834802358100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 10 ++++++++-- target/hppa/translate.c | 11 ++++++++++- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index fc327e2bb3..48f09c9b06 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -51,6 +51,7 @@ %pos_to_m 0:1 !function=3Dpos_to_m %neg_to_m 0:1 !function=3Dneg_to_m %a_to_m 2:1 !function=3Dneg_to_m +%cmpbid_c 13:2 !function=3Dcmpbid_c =20 #### # Argument set definitions @@ -69,6 +70,7 @@ &rrb_c_f disp n c f r1 r2 &rrb_c_d_f disp n c d f r1 r2 &rib_c_f disp n c f r i +&rib_c_d_f disp n c d f r i =20 #### # Format definitions @@ -88,6 +90,8 @@ &rrb_c_d_f disp=3D%assemble_12 @rib_cf ...... r:5 ..... c:3 ........... n:1 . \ &rib_c_f disp=3D%assemble_12 i=3D%im5_16 +@rib_cdf ...... r:5 ..... c:3 ........... n:1 . \ + &rib_c_d_f disp=3D%assemble_12 i=3D%im5_16 =20 #### # System @@ -303,8 +307,10 @@ cmpb 100000 ..... ..... ... ........... . .= @rrb_cdf d=3D0 f=3D0 cmpb 100010 ..... ..... ... ........... . . @rrb_cdf d=3D0 f= =3D1 cmpb 100111 ..... ..... ... ........... . . @rrb_cdf d=3D1 f= =3D0 cmpb 101111 ..... ..... ... ........... . . @rrb_cdf d=3D1 f= =3D1 -cmpbi 100001 ..... ..... ... ........... . . @rib_cf f=3D0 -cmpbi 100011 ..... ..... ... ........... . . @rib_cf f=3D1 +cmpbi 100001 ..... ..... ... ........... . . @rib_cdf d=3D0 f= =3D0 +cmpbi 100011 ..... ..... ... ........... . . @rib_cdf d=3D0 f= =3D1 +cmpbi 111011 r:5 ..... f:1 .. ........... n:1 . \ + &rib_c_d_f d=3D1 disp=3D%assemble_12 c=3D%cmpbid_c i=3D%im= 5_16 =20 addb 101000 ..... ..... ... ........... . . @rrb_cf f=3D0 addb 101010 ..... ..... ... ........... . . @rrb_cf f=3D1 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d1d9a4a137..bb55718a4d 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -329,6 +329,12 @@ static int expand_shl11(DisasContext *ctx, int val) return val << 11; } =20 +/* Translate CMPI doubleword conditions to standard. */ +static int cmpbid_c(DisasContext *ctx, int val) +{ + return val ? val : 4; /* 0 =3D=3D "*<<" */ +} + =20 /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" @@ -3101,9 +3107,12 @@ static bool trans_cmpb(DisasContext *ctx, arg_cmpb *= a) =20 static bool trans_cmpbi(DisasContext *ctx, arg_cmpbi *a) { + if (!ctx->is_pa20 && a->d) { + return false; + } nullify_over(ctx); return do_cmpb(ctx, a->r, tcg_constant_reg(a->i), - a->c, a->f, false, a->n, a->disp); + a->c, a->f, a->d, a->n, a->disp); } =20 static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1, --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835384291100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index bb55718a4d..21f2819d12 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3122,6 +3122,17 @@ static bool do_addb(DisasContext *ctx, unsigned r, T= CGv_reg in1, DisasCond cond; bool d =3D false; =20 + /* + * For hppa64, the ADDB conditions change, dropping ZNV, SV, OD + * in favor of double-word EQ, LT, LE. + */ + if (ctx->is_pa20) { + d =3D c >=3D 5; + if (d) { + c &=3D 3; + } + } + in2 =3D load_gpr(ctx, r); dest =3D tcg_temp_new(); sv =3D NULL; --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835021; cv=none; d=zohomail.com; s=zohoarc; b=c5mEm2b+qYVsGdsiPVLoiTRur2DFbrGzFKkAmPHtukvKncEMzyxk2Xx+RTumajxW1vAtXZfH4oQWvb836qGWXL74r9ftd5EtWNQ8t/llLryR20OmUBv6x9IeMQk39XoZcmhkxt4YWCKR9vH8vSSWO5fKI3WuApZYgAFRfcJSK/Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697835021; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835022978100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 15 +++++++++++---- target/hppa/translate.c | 4 ++++ 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 48f09c9b06..33eec3f4c3 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -215,9 +215,14 @@ ld 000011 ..... ..... .. . 0 -- 00 size:2= ...... @ldstx st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5 ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 siz= e=3D2 ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx siz= e=3D2 +ldc 000011 ..... ..... .. . 1 -- 0101 ...... @ldim5 siz= e=3D3 +ldc 000011 ..... ..... .. . 0 -- 0101 ...... @ldstx siz= e=3D3 lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 siz= e=3D2 lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx siz= e=3D2 +lda 000011 ..... ..... .. . 1 -- 0100 ...... @ldim5 siz= e=3D3 +lda 000011 ..... ..... .. . 0 -- 0100 ...... @ldstx siz= e=3D3 sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 siz= e=3D2 +sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 siz= e=3D3 stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=3D%im= 5_0 =20 @fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \ @@ -244,6 +249,8 @@ fstd 001011 ..... ..... .. . 1 -- 100 0 . ..= ... @fldstdi # Offset Mem #### =20 +@ldstim11 ...... b:5 t:5 sp:2 .............. \ + &ldst disp=3D%assemble_11a m=3D%ma2_to_m x=3D0 scale=3D0 s= ize=3D3 @ldstim14 ...... b:5 t:5 sp:2 .............. \ &ldst disp=3D%lowsign_14 x=3D0 scale=3D0 m=3D0 @ldstim14m ...... b:5 t:5 sp:2 .............. \ @@ -275,11 +282,11 @@ fstw 011110 b:5 ..... sp:2 .............. = \ fstw 011111 b:5 ..... sp:2 ...........0.. \ &ldst disp=3D%assemble_12a t=3D%rm64 m=3D0 x=3D0 scale=3D0= size=3D2 =20 -fldd 010100 b:5 t:5 sp:2 .......... .. 1 . \ - &ldst disp=3D%assemble_11a m=3D%ma2_to_m x=3D0 scale=3D0 s= ize=3D3 +ld 010100 ..... ..... .. ............0. @ldstim11 +fldd 010100 ..... ..... .. ............1. @ldstim11 =20 -fstd 011100 b:5 t:5 sp:2 .......... .. 1 . \ - &ldst disp=3D%assemble_11a m=3D%ma2_to_m x=3D0 scale=3D0 s= ize=3D3 +st 011100 ..... ..... .. ............0. @ldstim11 +fstd 011100 ..... ..... .. ............1. @ldstim11 =20 #### # Floating-point Multiply Add diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 21f2819d12..da1dd7d74a 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2951,6 +2951,10 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) TCGv_reg zero, dest, ofs; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835018993100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 19 ++++++++-- target/hppa/translate.c | 80 +++++++++++++++++++++++++++------------- 2 files changed, 69 insertions(+), 30 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 33eec3f4c3..12684b590e 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -46,6 +46,10 @@ =20 %im5_0 0:s1 1:4 %im5_16 16:s1 17:4 +%len5 0:5 !function=3Dassemble_6 +%len6_8 8:1 0:5 !function=3Dassemble_6 +%len6_12 12:1 0:5 !function=3Dassemble_6 +%cpos6_11 11:1 5:5 %ma_to_m 5:1 13:1 !function=3Dma_to_m %ma2_to_m 2:2 !function=3Dma_to_m %pos_to_m 0:1 !function=3Dpos_to_m @@ -334,10 +338,17 @@ shrpw_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t= :5 extrw_sar 110100 r:5 t:5 c:3 10 se:1 00000 clen:5 extrw_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 clen:5 =20 -depw_sar 110101 t:5 r:5 c:3 00 nz:1 00000 clen:5 -depw_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 clen:5 -depwi_sar 110101 t:5 ..... c:3 10 nz:1 00000 clen:5 i=3D%im5_16 -depwi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 clen:5 i=3D%im5_16 +dep_sar 110101 t:5 r:5 c:3 00 nz:1 00 000 ..... d=3D0 len=3D= %len5 +dep_sar 110101 t:5 r:5 c:3 00 nz:1 1. 000 ..... d=3D1 len=3D= %len6_8 +dep_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 ..... d=3D0 len=3D= %len5 +dep_imm 111100 t:5 r:5 c:3 .. nz:1 ..... ..... \ + d=3D1 len=3D%len6_12 cpos=3D%cpos6_11 +depi_sar 110101 t:5 ..... c:3 10 nz:1 d:1 . 000 ..... \ + i=3D%im5_16 len=3D%len6_8 +depi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 ..... \ + d=3D0 i=3D%im5_16 len=3D%len5 +depi_imm 111101 t:5 ..... c:3 .. nz:1 ..... ..... \ + d=3D1 i=3D%im5_16 len=3D%len6_12 cpos=3D%cpos6_11 =20 #### # Branch External diff --git a/target/hppa/translate.c b/target/hppa/translate.c index da1dd7d74a..5d07d0d890 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -329,6 +329,17 @@ static int expand_shl11(DisasContext *ctx, int val) return val << 11; } =20 +static int assemble_6(DisasContext *ctx, int val) +{ + /* + * Officially, 32 * x + 32 - y. + * Here, x is already in bit 5, and y is [4:0]. + * Since -y =3D ~y + 1, in 5 bits 32 - y =3D> y ^ 31 + 1, + * with the overflow from bit 4 summing with x. + */ + return (val ^ 31) + 1; +} + /* Translate CMPI doubleword conditions to standard. */ static int cmpbid_c(DisasContext *ctx, int val) { @@ -3383,17 +3394,23 @@ static bool trans_extrw_imm(DisasContext *ctx, arg_= extrw_imm *a) return nullify_end(ctx); } =20 -static bool trans_depwi_imm(DisasContext *ctx, arg_depwi_imm *a) +static bool trans_depi_imm(DisasContext *ctx, arg_depi_imm *a) { - unsigned len =3D 32 - a->clen; + unsigned len, width; target_sreg mask0, mask1; TCGv_reg dest; =20 + if (!ctx->is_pa20 && a->d) { + return false; + } if (a->c) { nullify_over(ctx); } - if (a->cpos + len > 32) { - len =3D 32 - a->cpos; + + len =3D a->len; + width =3D a->d ? 64 : 32; + if (a->cpos + len > width) { + len =3D width - a->cpos; } =20 dest =3D dest_gpr(ctx, a->t); @@ -3402,11 +3419,8 @@ static bool trans_depwi_imm(DisasContext *ctx, arg_d= epwi_imm *a) =20 if (a->nz) { TCGv_reg src =3D load_gpr(ctx, a->t); - if (mask1 !=3D -1) { - tcg_gen_andi_reg(dest, src, mask1); - src =3D dest; - } - tcg_gen_ori_reg(dest, src, mask0); + tcg_gen_andi_reg(dest, src, mask1); + tcg_gen_ori_reg(dest, dest, mask0); } else { tcg_gen_movi_reg(dest, mask0); } @@ -3415,22 +3429,28 @@ static bool trans_depwi_imm(DisasContext *ctx, arg_= depwi_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, a->d, dest); } return nullify_end(ctx); } =20 -static bool trans_depw_imm(DisasContext *ctx, arg_depw_imm *a) +static bool trans_dep_imm(DisasContext *ctx, arg_dep_imm *a) { unsigned rs =3D a->nz ? a->t : 0; - unsigned len =3D 32 - a->clen; + unsigned len, width; TCGv_reg dest, val; =20 + if (!ctx->is_pa20 && a->d) { + return false; + } if (a->c) { nullify_over(ctx); } - if (a->cpos + len > 32) { - len =3D 32 - a->cpos; + + len =3D a->len; + width =3D a->d ? 64 : 32; + if (a->cpos + len > width) { + len =3D width - a->cpos; } =20 dest =3D dest_gpr(ctx, a->t); @@ -3445,26 +3465,26 @@ static bool trans_depw_imm(DisasContext *ctx, arg_d= epw_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, a->d, dest); } return nullify_end(ctx); } =20 -static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c, - unsigned nz, unsigned clen, TCGv_reg val) +static bool do_dep_sar(DisasContext *ctx, unsigned rt, unsigned c, + bool d, bool nz, unsigned len, TCGv_reg val) { unsigned rs =3D nz ? rt : 0; - unsigned len =3D 32 - clen; + unsigned widthm1 =3D d ? 63 : 31; TCGv_reg mask, tmp, shift, dest; - unsigned msb =3D 1U << (len - 1); + target_ureg msb =3D 1ULL << (len - 1); =20 dest =3D dest_gpr(ctx, rt); shift =3D tcg_temp_new(); tmp =3D tcg_temp_new(); =20 /* Convert big-endian bit numbering in SAR to left-shift. */ - tcg_gen_andi_reg(shift, cpu_sar, 31); - tcg_gen_xori_reg(shift, shift, 31); + tcg_gen_andi_reg(shift, cpu_sar, widthm1); + tcg_gen_xori_reg(shift, shift, widthm1); =20 mask =3D tcg_temp_new(); tcg_gen_movi_reg(mask, msb + (msb - 1)); @@ -3482,25 +3502,33 @@ static bool do_depw_sar(DisasContext *ctx, unsigned= rt, unsigned c, /* Install the new nullification. */ cond_free(&ctx->null_cond); if (c) { - ctx->null_cond =3D do_sed_cond(ctx, c, false, dest); + ctx->null_cond =3D do_sed_cond(ctx, c, d, dest); } return nullify_end(ctx); } =20 -static bool trans_depw_sar(DisasContext *ctx, arg_depw_sar *a) +static bool trans_dep_sar(DisasContext *ctx, arg_dep_sar *a) { + if (!ctx->is_pa20 && a->d) { + return false; + } if (a->c) { nullify_over(ctx); } - return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_gpr(ctx, a->r= )); + return do_dep_sar(ctx, a->t, a->c, a->d, a->nz, a->len, + load_gpr(ctx, a->r)); } =20 -static bool trans_depwi_sar(DisasContext *ctx, arg_depwi_sar *a) +static bool trans_depi_sar(DisasContext *ctx, arg_depi_sar *a) { + if (!ctx->is_pa20 && a->d) { + return false; + } if (a->c) { nullify_over(ctx); } - return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, tcg_constant_reg(a= ->i)); + return do_dep_sar(ctx, a->t, a->c, a->d, a->nz, a->len, + tcg_constant_reg(a->i)); } =20 static bool trans_be(DisasContext *ctx, arg_be *a) --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835094; cv=none; d=zohomail.com; s=zohoarc; b=dD2qFlA12O3xhTtx2bjhf+RDzQJvh8RKs8XZrECi5AAYcyp2pZ96mPL83oo88zye4AxQ/g97KHkllqPHLlSsbHm3bQvqP3wyYMleiO7pjFnawkOVNQ1mksWfEaOb832/m77N0MCfe+tGnrlz/9M04G0wzYwjkdu60FpvM0rbyZw= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835095197100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 7 +++++-- target/hppa/translate.c | 34 +++++++++++++++++++++++----------- 2 files changed, 28 insertions(+), 13 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 12684b590e..7b51f39b9e 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -335,8 +335,11 @@ addbi 101011 ..... ..... ... ........... . .= @rib_cf f=3D1 shrpw_sar 110100 r2:5 r1:5 c:3 00 0 00000 t:5 shrpw_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 =20 -extrw_sar 110100 r:5 t:5 c:3 10 se:1 00000 clen:5 -extrw_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 clen:5 +extr_sar 110100 r:5 t:5 c:3 10 se:1 00 000 ..... d=3D0 len=3D= %len5 +extr_sar 110100 r:5 t:5 c:3 10 se:1 1. 000 ..... d=3D1 len=3D= %len6_8 +extr_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 ..... d=3D0 len=3D= %len5 +extr_imm 110110 r:5 t:5 c:3 .. se:1 ..... ..... \ + d=3D1 len=3D%len6_12 pos=3D%cpos6_11 =20 dep_sar 110101 t:5 r:5 c:3 00 nz:1 00 000 ..... d=3D0 len=3D= %len5 dep_sar 110101 t:5 r:5 c:3 00 nz:1 1. 000 ..... d=3D1 len=3D= %len6_8 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 5d07d0d890..99b7622841 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3333,11 +3333,14 @@ static bool trans_shrpw_imm(DisasContext *ctx, arg_= shrpw_imm *a) return nullify_end(ctx); } =20 -static bool trans_extrw_sar(DisasContext *ctx, arg_extrw_sar *a) +static bool trans_extr_sar(DisasContext *ctx, arg_extr_sar *a) { - unsigned len =3D 32 - a->clen; + unsigned widthm1 =3D a->d ? 63 : 31; TCGv_reg dest, src, tmp; =20 + if (!ctx->is_pa20 && a->d) { + return false; + } if (a->c) { nullify_over(ctx); } @@ -3347,36 +3350,45 @@ static bool trans_extrw_sar(DisasContext *ctx, arg_= extrw_sar *a) tmp =3D tcg_temp_new(); =20 /* Recall that SAR is using big-endian bit numbering. */ - tcg_gen_andi_reg(tmp, cpu_sar, 31); - tcg_gen_xori_reg(tmp, tmp, 31); + tcg_gen_andi_reg(tmp, cpu_sar, widthm1); + tcg_gen_xori_reg(tmp, tmp, widthm1); =20 if (a->se) { tcg_gen_sar_reg(dest, src, tmp); - tcg_gen_sextract_reg(dest, dest, 0, len); + tcg_gen_sextract_reg(dest, dest, 0, a->len); } else { tcg_gen_shr_reg(dest, src, tmp); - tcg_gen_extract_reg(dest, dest, 0, len); + tcg_gen_extract_reg(dest, dest, 0, a->len); } save_gpr(ctx, a->t, dest); =20 /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, a->d, dest); } return nullify_end(ctx); } =20 -static bool trans_extrw_imm(DisasContext *ctx, arg_extrw_imm *a) +static bool trans_extr_imm(DisasContext *ctx, arg_extr_imm *a) { - unsigned len =3D 32 - a->clen; - unsigned cpos =3D 31 - a->pos; + unsigned len, cpos, width; TCGv_reg dest, src; =20 + if (!ctx->is_pa20 && a->d) { + return false; + } if (a->c) { nullify_over(ctx); } =20 + len =3D a->len; + width =3D a->d ? 64 : 32; + cpos =3D width - 1 - a->pos; + if (cpos + len > width) { + len =3D width - cpos; + } + dest =3D dest_gpr(ctx, a->t); src =3D load_gpr(ctx, a->r); if (a->se) { @@ -3389,7 +3401,7 @@ static bool trans_extrw_imm(DisasContext *ctx, arg_ex= trw_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, a->d, dest); } return nullify_end(ctx); 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u7-20020aa78487000000b00694fee1011asm1946775pfn.208.2023.10.20.13.47.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:47:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834831; x=1698439631; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BhzrhB16C9PweWmZVzgb1Vp7AhWyTVscP3gbZpvYFDM=; b=SUTxvSYoguvpHgN1y3GpbwOV0FWAE+rIC7ascr+kTs2HMknfDjKFTNpCXtCruZmRH1 /PcHsjjvS9BaCP32cULrZT7GugXHBwA6YATrgHTM+XENjXpktvw7cQA9aKx2ODkTX5Aq m2psBQyJCZyBjQaUp5801icEj/SOsrsqVA7i6jFVyDLGBA9gf45h+Zdcq1bRK3+xr5FP TnTndWyAmqL93ZQWR8fXOxLOHMm045Xc02hqr7hGXNgCaaEOgQgM2apBMmyMOoclkWZh TB9amJpdaDcDFZFIiNiX1fm0FHRt0Sknlol5p4czT8RmQjFfjmnfZrcVE8kDIMUwxI1t Vc8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834831; x=1698439631; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835113237100009 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 6 ++- target/hppa/translate.c | 79 ++++++++++++++++++++++++++++------------ 2 files changed, 60 insertions(+), 25 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 7b51f39b9e..6f0c3f6ea5 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -332,8 +332,10 @@ addbi 101011 ..... ..... ... ........... . .= @rib_cf f=3D1 # Shift, Extract, Deposit #### =20 -shrpw_sar 110100 r2:5 r1:5 c:3 00 0 00000 t:5 -shrpw_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 +shrp_sar 110100 r2:5 r1:5 c:3 00 0 d:1 0000 t:5 +shrp_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 d=3D0 +shrp_imm 110100 r2:5 r1:5 c:3 0. 1 ..... t:5 \ + d=3D1 cpos=3D%cpos6_11 =20 extr_sar 110100 r:5 t:5 c:3 10 se:1 00 000 ..... d=3D0 len=3D= %len5 extr_sar 110100 r:5 t:5 c:3 10 se:1 1. 000 ..... d=3D1 len=3D= %len6_8 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 99b7622841..05fe5bf7fe 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3258,32 +3258,56 @@ static bool trans_movbi(DisasContext *ctx, arg_movb= i *a) return do_cbranch(ctx, a->disp, a->n, &cond); } =20 -static bool trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a) +static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a) { - TCGv_reg dest; + TCGv_reg dest, tmp; =20 + if (!ctx->is_pa20 && a->d) { + return false; + } if (a->c) { nullify_over(ctx); } =20 dest =3D dest_gpr(ctx, a->t); if (a->r1 =3D=3D 0) { - tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2)); - tcg_gen_shr_reg(dest, dest, cpu_sar); + if (a->d) { + tcg_gen_shr_reg(dest, dest, cpu_sar); + } else { + tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2)); + tmp =3D tcg_temp_new(); + tcg_gen_andi_reg(tmp, cpu_sar, 31); + tcg_gen_shr_reg(dest, dest, tmp); + } } else if (a->r1 =3D=3D a->r2) { - TCGv_i32 t32 =3D tcg_temp_new_i32(); - TCGv_i32 s32 =3D tcg_temp_new_i32(); + if (a->d) { + tcg_gen_rotr_reg(dest, load_gpr(ctx, a->r2), cpu_sar); + } else { + TCGv_i32 t32 =3D tcg_temp_new_i32(); + TCGv_i32 s32 =3D tcg_temp_new_i32(); =20 - tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); - tcg_gen_trunc_reg_i32(s32, cpu_sar); - tcg_gen_rotr_i32(t32, t32, s32); - tcg_gen_extu_i32_reg(dest, t32); + tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); + tcg_gen_trunc_reg_i32(s32, cpu_sar); + tcg_gen_andi_i32(s32, s32, 31); + tcg_gen_rotr_i32(t32, t32, s32); + tcg_gen_extu_i32_reg(dest, t32); + } + } else if (a->d) { + TCGv_reg t =3D tcg_temp_new(); + TCGv_reg n =3D tcg_temp_new(); + + tcg_gen_xori_reg(n, cpu_sar, 63); + tcg_gen_shl_reg(t, load_gpr(ctx, a->r2), n); + tcg_gen_shli_reg(t, t, 1); + tcg_gen_shr_reg(dest, load_gpr(ctx, a->r1), cpu_sar); + tcg_gen_or_reg(dest, dest, t); } else { TCGv_i64 t =3D tcg_temp_new_i64(); TCGv_i64 s =3D tcg_temp_new_i64(); =20 tcg_gen_concat_reg_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r= 1)); tcg_gen_extu_reg_i64(s, cpu_sar); + tcg_gen_andi_i64(s, s, 31); tcg_gen_shr_i64(t, t, s); tcg_gen_trunc_i64_reg(dest, t); } @@ -3297,31 +3321,40 @@ static bool trans_shrpw_sar(DisasContext *ctx, arg_= shrpw_sar *a) return nullify_end(ctx); } =20 -static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a) +static bool trans_shrp_imm(DisasContext *ctx, arg_shrp_imm *a) { - unsigned sa =3D 31 - a->cpos; + unsigned width, sa; TCGv_reg dest, t2; =20 + if (!ctx->is_pa20 && a->d) { + return false; + } if (a->c) { nullify_over(ctx); } =20 + width =3D a->d ? 64 : 32; + sa =3D width - 1 - a->cpos; + dest =3D dest_gpr(ctx, a->t); t2 =3D load_gpr(ctx, a->r2); if (a->r1 =3D=3D 0) { - tcg_gen_extract_reg(dest, t2, sa, 32 - sa); - } else if (TARGET_REGISTER_BITS =3D=3D 32) { + tcg_gen_extract_reg(dest, t2, sa, width - sa); + } else if (width =3D=3D TARGET_REGISTER_BITS) { tcg_gen_extract2_reg(dest, t2, cpu_gr[a->r1], sa); - } else if (a->r1 =3D=3D a->r2) { - TCGv_i32 t32 =3D tcg_temp_new_i32(); - tcg_gen_trunc_reg_i32(t32, t2); - tcg_gen_rotri_i32(t32, t32, sa); - tcg_gen_extu_i32_reg(dest, t32); } else { - TCGv_i64 t64 =3D tcg_temp_new_i64(); - tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]); - tcg_gen_shri_i64(t64, t64, sa); - tcg_gen_trunc_i64_reg(dest, t64); + assert(!a->d); + if (a->r1 =3D=3D a->r2) { + TCGv_i32 t32 =3D tcg_temp_new_i32(); + tcg_gen_trunc_reg_i32(t32, t2); + tcg_gen_rotri_i32(t32, t32, sa); + tcg_gen_extu_i32_reg(dest, t32); + } else { + TCGv_i64 t64 =3D tcg_temp_new_i64(); + tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]); + tcg_gen_shri_i64(t64, t64, sa); + tcg_gen_trunc_i64_reg(dest, t64); + } } save_gpr(ctx, a->t, dest); =20 --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835245; cv=none; d=zohomail.com; s=zohoarc; b=ZGM6PvzIIKVhzjvEHTS9kX7r/klOhgwl2us6oDuLscQOPcnHQNJD2mooX1HfZ4FGCbnj9B/LgzLxSc2OOmMYcyClJpFn+uFy2TkMNiaMRpow44mN2FiAfsZe+lEQcoN+RBvVwennzt/HE7HJgq9tpG4glDJeo12XBLEWMsUdlFs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697835245; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835245689100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 2 ++ target/hppa/translate.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 6f0c3f6ea5..ba7731b517 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -381,6 +381,8 @@ bl 111010 ..... ..... 101 ........... n:1 = . &BL l=3D2 \ disp=3D%assemble_22 b_gate 111010 ..... ..... 001 ........... . . @bl blr 111010 l:5 x:5 010 00000000000 n:1 0 +nopbts 111010 00000 00000 010 0---------1 0 1 # clrbts/popbts +nopbts 111010 00000 ----- 010 00000000000 0 1 # pushbts/push= nom bv 111010 b:5 x:5 110 00000000000 n:1 0 bve 111010 b:5 00000 110 10000000000 n:1 - l=3D0 bve 111010 b:5 00000 111 10000000000 n:1 - l=3D2 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 05fe5bf7fe..4dccaff687 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3746,6 +3746,12 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a) #endif } =20 +static bool trans_nopbts(DisasContext *ctx, arg_nopbts *a) +{ + /* All branch target stack instructions implement as nop. */ + return ctx->is_pa20; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835263812100002 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/helper.h | 5 ++ target/hppa/insns.decode | 1 + target/hppa/op_helper.c | 178 +++++++++++++++++++++++++++++++++++++-- target/hppa/translate.c | 31 +++++++ 4 files changed, 210 insertions(+), 5 deletions(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 647f043c85..9920d38ded 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -16,6 +16,11 @@ DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void= , env, tl, tr) DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tr) DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr) =20 +DEF_HELPER_FLAGS_3(stdby_b, TCG_CALL_NO_WG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(stdby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(stdby_e, TCG_CALL_NO_WG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(stdby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr) + DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl) =20 DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tr, env, tl, i32, i32) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index ba7731b517..9d8c6a1a16 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -228,6 +228,7 @@ lda 000011 ..... ..... .. . 0 -- 0100 = ...... @ldstx size=3D3 sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 siz= e=3D2 sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 siz= e=3D3 stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=3D%im= 5_0 +stdby 000011 b:5 r:5 sp:2 a:1 1 -- 1101 m:1 ..... disp=3D%im= 5_0 =20 @fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \ &ldst t=3D%rt64 disp=3D0 size=3D2 diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 837e2b3117..94c9ca5858 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -56,11 +56,11 @@ void HELPER(tcond)(CPUHPPAState *env, target_ureg cond) } } =20 -static void atomic_store_3(CPUHPPAState *env, target_ulong addr, - uint32_t val, uintptr_t ra) +static void atomic_store_mask32(CPUHPPAState *env, target_ulong addr, + uint32_t val, uint32_t mask, uintptr_t ra) { int mmu_idx =3D cpu_mmu_index(env, 0); - uint32_t old, new, cmp, mask, *haddr; + uint32_t old, new, cmp, *haddr; void *vaddr; =20 vaddr =3D probe_access(env, addr, 3, MMU_DATA_STORE, mmu_idx, ra); @@ -81,6 +81,35 @@ static void atomic_store_3(CPUHPPAState *env, target_ulo= ng addr, } } =20 +static void atomic_store_mask64(CPUHPPAState *env, target_ulong addr, + uint64_t val, uint64_t mask, + int size, uintptr_t ra) +{ +#ifdef CONFIG_ATOMIC64 + int mmu_idx =3D cpu_mmu_index(env, 0); + uint64_t old, new, cmp, *haddr; + void *vaddr; + + vaddr =3D probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, ra); + if (vaddr =3D=3D NULL) { + cpu_loop_exit_atomic(env_cpu(env), ra); + } + haddr =3D (uint64_t *)((uintptr_t)vaddr & -8); + + old =3D *haddr; + while (1) { + new =3D be32_to_cpu((cpu_to_be32(old) & ~mask) | (val & mask)); + cmp =3D qatomic_cmpxchg__nocheck(haddr, old, new); + if (cmp =3D=3D old) { + return; + } + old =3D cmp; + } +#else + cpu_loop_exit_atomic(env_cpu(env), ra); +#endif +} + static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ureg va= l, bool parallel, uintptr_t ra) { @@ -94,7 +123,7 @@ static void do_stby_b(CPUHPPAState *env, target_ulong ad= dr, target_ureg val, case 1: /* The 3 byte store must appear atomic. */ if (parallel) { - atomic_store_3(env, addr, val, ra); + atomic_store_mask32(env, addr, val, 0x00ffffffu, ra); } else { cpu_stb_data_ra(env, addr, val >> 16, ra); cpu_stw_data_ra(env, addr + 1, val, ra); @@ -106,6 +135,62 @@ static void do_stby_b(CPUHPPAState *env, target_ulong = addr, target_ureg val, } } =20 +static void do_stdby_b(CPUHPPAState *env, target_ulong addr, uint64_t val, + bool parallel, uintptr_t ra) +{ + switch (addr & 7) { + case 7: + cpu_stb_data_ra(env, addr, val, ra); + break; + case 6: + cpu_stw_data_ra(env, addr, val, ra); + break; + case 5: + /* The 3 byte store must appear atomic. */ + if (parallel) { + atomic_store_mask32(env, addr, val, 0x00ffffffu, ra); + } else { + cpu_stb_data_ra(env, addr, val >> 16, ra); + cpu_stw_data_ra(env, addr + 1, val, ra); + } + break; + case 4: + cpu_stl_data_ra(env, addr, val, ra); + break; + case 3: + /* The 5 byte store must appear atomic. */ + if (parallel) { + atomic_store_mask64(env, addr, val, 0x000000ffffffffffull, 5, = ra); + } else { + cpu_stb_data_ra(env, addr, val >> 32, ra); + cpu_stl_data_ra(env, addr + 1, val, ra); + } + break; + case 2: + /* The 6 byte store must appear atomic. */ + if (parallel) { + atomic_store_mask64(env, addr, val, 0x0000ffffffffffffull, 6, = ra); + } else { + cpu_stw_data_ra(env, addr, val >> 32, ra); + cpu_stl_data_ra(env, addr + 2, val, ra); + } + break; + case 1: + /* The 7 byte store must appear atomic. */ + if (parallel) { + atomic_store_mask64(env, addr, val, 0x00ffffffffffffffull, 7, = ra); + } else { + cpu_stb_data_ra(env, addr, val >> 48, ra); + cpu_stw_data_ra(env, addr + 1, val >> 32, ra); + cpu_stl_data_ra(env, addr + 3, val, ra); + } + break; + default: + cpu_stl_data_ra(env, addr, val, ra); + break; + } +} + void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val) { do_stby_b(env, addr, val, false, GETPC()); @@ -117,6 +202,17 @@ void HELPER(stby_b_parallel)(CPUHPPAState *env, target= _ulong addr, do_stby_b(env, addr, val, true, GETPC()); } =20 +void HELPER(stdby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val) +{ + do_stdby_b(env, addr, val, false, GETPC()); +} + +void HELPER(stdby_b_parallel)(CPUHPPAState *env, target_ulong addr, + target_ureg val) +{ + do_stdby_b(env, addr, val, true, GETPC()); +} + static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ureg va= l, bool parallel, uintptr_t ra) { @@ -124,7 +220,68 @@ static void do_stby_e(CPUHPPAState *env, target_ulong = addr, target_ureg val, case 3: /* The 3 byte store must appear atomic. */ if (parallel) { - atomic_store_3(env, addr - 3, val, ra); + atomic_store_mask32(env, addr - 3, val, 0xffffff00u, ra); + } else { + cpu_stw_data_ra(env, addr - 3, val >> 16, ra); + cpu_stb_data_ra(env, addr - 1, val >> 8, ra); + } + break; + case 2: + cpu_stw_data_ra(env, addr - 2, val >> 16, ra); + break; + case 1: + cpu_stb_data_ra(env, addr - 1, val >> 24, ra); + break; + default: + /* Nothing is stored, but protection is checked and the + cacheline is marked dirty. */ + probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra); + break; + } +} + +static void do_stdby_e(CPUHPPAState *env, target_ulong addr, uint64_t val, + bool parallel, uintptr_t ra) +{ + switch (addr & 7) { + case 7: + /* The 7 byte store must appear atomic. */ + if (parallel) { + atomic_store_mask64(env, addr - 7, val, + 0xffffffffffffff00ull, 7, ra); + } else { + cpu_stl_data_ra(env, addr - 7, val >> 32, ra); + cpu_stw_data_ra(env, addr - 3, val >> 16, ra); + cpu_stb_data_ra(env, addr - 1, val >> 8, ra); + } + break; + case 6: + /* The 6 byte store must appear atomic. */ + if (parallel) { + atomic_store_mask64(env, addr - 6, val, + 0xffffffffffff0000ull, 6, ra); + } else { + cpu_stl_data_ra(env, addr - 6, val >> 32, ra); + cpu_stw_data_ra(env, addr - 2, val >> 16, ra); + } + break; + case 5: + /* The 5 byte store must appear atomic. */ + if (parallel) { + atomic_store_mask64(env, addr - 5, val, + 0xffffffffff000000ull, 5, ra); + } else { + cpu_stl_data_ra(env, addr - 5, val >> 32, ra); + cpu_stb_data_ra(env, addr - 1, val >> 24, ra); + } + break; + case 4: + cpu_stl_data_ra(env, addr - 4, val >> 32, ra); + break; + case 3: + /* The 3 byte store must appear atomic. */ + if (parallel) { + atomic_store_mask32(env, addr - 3, val, 0xffffff00u, ra); } else { cpu_stw_data_ra(env, addr - 3, val >> 16, ra); cpu_stb_data_ra(env, addr - 1, val >> 8, ra); @@ -155,6 +312,17 @@ void HELPER(stby_e_parallel)(CPUHPPAState *env, target= _ulong addr, do_stby_e(env, addr, val, true, GETPC()); } =20 +void HELPER(stdby_e)(CPUHPPAState *env, target_ulong addr, target_ureg val) +{ + do_stdby_e(env, addr, val, false, GETPC()); +} + +void HELPER(stdby_e_parallel)(CPUHPPAState *env, target_ulong addr, + target_ureg val) +{ + do_stdby_e(env, addr, val, true, GETPC()); +} + void HELPER(ldc_check)(target_ulong addr) { if (unlikely(addr & 0xf)) { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 4dccaff687..650f5812dd 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3031,6 +3031,37 @@ static bool trans_stby(DisasContext *ctx, arg_stby *= a) return nullify_end(ctx); } =20 +static bool trans_stdby(DisasContext *ctx, arg_stby *a) +{ + TCGv_reg ofs, val; + TCGv_tl addr; + + nullify_over(ctx); + + form_gva(ctx, &addr, &ofs, a->b, 0, 0, a->disp, a->sp, a->m, + ctx->mmu_idx =3D=3D MMU_PHYS_IDX); + val =3D load_gpr(ctx, a->r); + if (a->a) { + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + gen_helper_stdby_e_parallel(tcg_env, addr, val); + } else { + gen_helper_stdby_e(tcg_env, addr, val); + } + } else { + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + gen_helper_stdby_b_parallel(tcg_env, addr, val); + } else { + gen_helper_stdby_b(tcg_env, addr, val); + } + } + if (a->m) { + tcg_gen_andi_reg(ofs, ofs, ~7); + save_gpr(ctx, a->b, ofs); + } + + return nullify_end(ctx); +} + static bool trans_lda(DisasContext *ctx, arg_ldst *a) { int hold_mmu_idx =3D ctx->mmu_idx; --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835048; cv=none; d=zohomail.com; s=zohoarc; b=UAyi6QmvcBO33bSFny6wibJ3+MRodwFgmqxEVu+A45u1unLg+FVVm4AqGBv5QK7C0tQKBljxI0ptUbmlVuHH+0VIQeO7bxUIyr4gJaNeRzoNYMtukoI2WZF/iKNxYj6aJY2CBZuKDCp9Vh8vKsW6l+V+UnIc6dRk5WrUAp2552c= ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u7-20020aa78487000000b00694fee1011asm1946775pfn.208.2023.10.20.13.47.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:47:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834833; x=1698439633; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iceGonzdaVmnQSlk4xLAZNOj4sU0L4Dh8hQYUhsbnsk=; b=RUIZOgt8U72/28jbE5LeTnVldja5hDu+KRCmAazFLotW62Mg06DdUcPDJrPv2tZueO MYLdT61K+spYpaxr/yYyYU607dFkmLMjbDieMxrVxuNaAH2Qw0g1IZvYNmFal1ahQONr KlI8fZ5BBwD2VsR/jySAel5/MuGALJa+X/7n5es2zZ1HUineVuIK8NXyq46xGNRvsSr9 cf/Jgvo4Tz5yvB2xxRDn6jXkMHEhXmGDM4lHapL49ucJ0PSmwAXrci9OiEPckRZrWteg Mq6dqVq09h6EUw7gEjrc86725Tk57VuKZqGn9XO77By92cQFlXQU3yePYXKyPKZVhcn0 WT7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834833; x=1698439633; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iceGonzdaVmnQSlk4xLAZNOj4sU0L4Dh8hQYUhsbnsk=; b=NAyaXWPIK7yHSwAB+2f30yfjp9nV29FTGBwkZGN/Ill9ry6xg4LGcVoSkORGxIYjDc 4nAD1RPjZNQt9fbuijDbKI49UWAEx4R1e87Ihpdf6XKeAlWCDxrilg7dvg6KaAQApvyK 2pW/zAHnoODRxBMIsHlFZpwymyMYU3WcU1WOrc9g/Hr/KJ40JOLjFHsVfs3nEJTek69x /x/nlPZg97XwL76hK8tr5aBEWd0HBZGg6d/YGUiX3fSQNSyjvfExJ1GZO5hgtabJ9aV9 lgeDevDvplq90HFf01cAAif00K8tFLfkFUs+SsKohYG6F++SxuzBF+j7l+4oEWJWoiTo FpSA== X-Gm-Message-State: AOJu0Yy6g44+m/20metD0XJkH6eS6qIBSY3C6h1VWBfHakfI3iQkhbDa iycBqdygf66PSP2dKF5A4CRrxu6skbBnGjnWQaI= X-Google-Smtp-Source: AGHT+IGIw8dsdh9CoEJColH8n+ld3/QaZkus9Pm4STZ4qD/bvX93gG5GRd5Xp5KjiMDNrRy6C3DIVQ== X-Received: by 2002:a05:6a21:3889:b0:179:f761:4348 with SMTP id yj9-20020a056a21388900b00179f7614348mr2111249pzb.34.1697834833450; Fri, 20 Oct 2023 13:47:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 45/65] target/hppa: Implement IDTLBT, IITLBT Date: Fri, 20 Oct 2023 13:43:11 -0700 Message-Id: <20231020204331.139847-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835049134100002 Content-Type: text/plain; charset="utf-8" Rename the existing insert tlb helpers to emphasize that they are for pa1.1 cpus. Implement a combined i/d tlb for pa2.0. Still missing is the new 'P' tlb bit. Signed-off-by: Richard Henderson --- target/hppa/helper.h | 5 ++-- target/hppa/insns.decode | 4 +++ target/hppa/mem_helper.c | 63 +++++++++++++++++++++++++++++++++------- target/hppa/translate.c | 35 ++++++++++++++++++---- 4 files changed, 89 insertions(+), 18 deletions(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 9920d38ded..58b6754dbe 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -94,8 +94,9 @@ DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG,= void, env, tr) DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) -DEF_HELPER_FLAGS_3(itlba, TCG_CALL_NO_RWG, void, env, tl, tr) -DEF_HELPER_FLAGS_3(itlbp, TCG_CALL_NO_RWG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(itlba_pa11, TCG_CALL_NO_RWG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(itlbp_pa11, TCG_CALL_NO_RWG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(itlbt_pa20, TCG_CALL_NO_RWG, void, env, tr, tr) DEF_HELPER_FLAGS_2(ptlb, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_1(ptlbe, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(lpa, TCG_CALL_NO_WG, tr, env, tl) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 9d8c6a1a16..db1b9f750f 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -152,6 +152,10 @@ ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 000= 00 \ # pcxl and pcxl2 Fast TLB Insert instructions ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000 =20 +# pa2.0 tlb insert instructions +ixtlbt 000001 r2:5 r1:5 000 1100000 0 00000 # idtlbt +ixtlbt 000001 r2:5 r1:5 000 0100000 0 00000 # iitlbt + pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=3D1 pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \ sp=3D%assemble_sr3x data=3D0 diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 1a63717571..356746654c 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -312,7 +312,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int si= ze, } =20 /* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */ -void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg) +void HELPER(itlba_pa11)(CPUHPPAState *env, target_ulong addr, target_ureg = reg) { hppa_tlb_entry *empty =3D NULL; int i; @@ -338,15 +338,12 @@ void HELPER(itlba)(CPUHPPAState *env, target_ulong ad= dr, target_ureg reg) /* Note that empty->entry_valid =3D=3D 0 already. */ empty->va_b =3D addr & TARGET_PAGE_MASK; empty->va_e =3D empty->va_b + TARGET_PAGE_SIZE - 1; - /* - * FIXME: This is wrong, as this is a pa1.1 function. - * But for the moment translate abs address for pa2.0. - */ - empty->pa =3D hppa_abs_to_phys(env, extract32(reg, 5, 20) << TARGET_PA= GE_BITS); + empty->pa =3D extract32(reg, 5, 20) << TARGET_PAGE_BITS; trace_hppa_tlb_itlba(env, empty, empty->va_b, empty->va_e, empty->pa); } =20 -static void set_access_bits(CPUHPPAState *env, hppa_tlb_entry *ent, target= _ureg reg) +static void set_access_bits_pa11(CPUHPPAState *env, hppa_tlb_entry *ent, + target_ureg reg) { ent->access_id =3D extract32(reg, 1, 18); ent->u =3D extract32(reg, 19, 1); @@ -362,7 +359,7 @@ static void set_access_bits(CPUHPPAState *env, hppa_tlb= _entry *ent, target_ureg } =20 /* Insert (Insn/Data) TLB Protection. Note this is PA 1.1 only. */ -void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg) +void HELPER(itlbp_pa11)(CPUHPPAState *env, target_ulong addr, target_ureg = reg) { hppa_tlb_entry *ent =3D hppa_find_tlb(env, addr); =20 @@ -370,8 +367,54 @@ void HELPER(itlbp)(CPUHPPAState *env, target_ulong add= r, target_ureg reg) qemu_log_mask(LOG_GUEST_ERROR, "ITLBP not following ITLBA\n"); return; } + set_access_bits_pa11(env, ent, reg); +} =20 - set_access_bits(env, ent, reg); +void HELPER(itlbt_pa20)(CPUHPPAState *env, target_ureg r1, target_ureg r2) +{ + hppa_tlb_entry *ent, *empty =3D NULL; + vaddr va_b, va_e; + uint64_t page_size; + + va_b =3D deposit64(env->cr[CR_IIAOQ], 32, 32, env->cr[CR_IIASQ]); + va_b &=3D TARGET_PAGE_MASK; + page_size =3D TARGET_PAGE_SIZE << (2 * (r1 & 0xf)); + va_e =3D va_b + page_size - 1; + + for (int i =3D 0; i < ARRAY_SIZE(env->tlb); ++i) { + ent =3D &env->tlb[i]; + if (ent->entry_valid) { + if (ent->va_b <=3D va_e && va_b <=3D ent->va_e) { + hppa_flush_tlb_ent(env, ent, false); + empty =3D ent; + } + } else { + empty =3D ent; + } + } + + /* If we didn't see an empty entry, evict one. */ + ent =3D empty ? empty : hppa_alloc_tlb_ent(env); + + ent->va_b =3D va_b; + ent->va_e =3D va_e; + ent->pa =3D (r1 << 7) & TARGET_PAGE_MASK; + ent->t =3D extract64(r2, 61, 1); + ent->d =3D extract64(r2, 60, 1); + ent->b =3D extract64(r2, 59, 1); + ent->ar_type =3D extract64(r2, 56, 3); + ent->ar_pl1 =3D extract64(r2, 54, 2); + ent->ar_pl2 =3D extract64(r2, 52, 2); + ent->u =3D extract64(r2, 51, 1); + /* o =3D bit 50 */ + /* p =3D bit 49 */ + ent->access_id =3D extract64(r2, 1, 31); + ent->entry_valid =3D 1; + + trace_hppa_tlb_itlba(env, ent, ent->va_b, ent->va_e, ent->pa); + trace_hppa_tlb_itlbp(env, ent, ent->access_id, ent->u, + ent->ar_pl2, ent->ar_pl1, ent->ar_type, + ent->b, ent->d, ent->t); } =20 /* Purge (Insn/Data) TLB. This is explicitly page-based, and is @@ -519,7 +562,7 @@ void HELPER(diag_btlb)(CPUHPPAState *env) btlb->va_b =3D virt_page << TARGET_PAGE_BITS; btlb->va_e =3D btlb->va_b + len * TARGET_PAGE_SIZE - 1; btlb->pa =3D phys_page << TARGET_PAGE_BITS; - set_access_bits(env, btlb, env->gr[20]); + set_access_bits_pa11(env, btlb, env->gr[20]); btlb->t =3D 0; btlb->d =3D 1; } else { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 650f5812dd..2a09e1cdad 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2493,6 +2493,9 @@ static bool trans_probe(DisasContext *ctx, arg_probe = *a) =20 static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a) { + if (ctx->is_pa20) { + return false; + } CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY TCGv_tl addr; @@ -2503,9 +2506,9 @@ static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlb= x *a) form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); reg =3D load_gpr(ctx, a->r); if (a->addr) { - gen_helper_itlba(tcg_env, addr, reg); + gen_helper_itlba_pa11(tcg_env, addr, reg); } else { - gen_helper_itlbp(tcg_env, addr, reg); + gen_helper_itlbp_pa11(tcg_env, addr, reg); } =20 /* Exit TB for TLB change if mmu is enabled. */ @@ -2551,6 +2554,9 @@ static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlb= x *a) */ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a) { + if (ctx->is_pa20) { + return false; + } CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY TCGv_tl addr, atl, stl; @@ -2562,8 +2568,6 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtl= bxf *a) * FIXME: * if (not (pcxl or pcxl2)) * return gen_illegal(ctx); - * - * Note for future: these are 32-bit systems; no hppa64. */ =20 atl =3D tcg_temp_new_tl(); @@ -2581,9 +2585,9 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtl= bxf *a) =20 reg =3D load_gpr(ctx, a->r); if (a->addr) { - gen_helper_itlba(tcg_env, addr, reg); + gen_helper_itlba_pa11(tcg_env, addr, reg); } else { - gen_helper_itlbp(tcg_env, addr, reg); + gen_helper_itlbp_pa11(tcg_env, addr, reg); } =20 /* Exit TB for TLB change if mmu is enabled. */ @@ -2594,6 +2598,25 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixt= lbxf *a) #endif } =20 +static bool trans_ixtlbt(DisasContext *ctx, arg_ixtlbt *a) +{ + if (!ctx->is_pa20) { + return false; + } + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); +#ifndef CONFIG_USER_ONLY + nullify_over(ctx); + + gen_helper_itlbt_pa20(tcg_env, load_gpr(ctx, a->r1), load_gpr(ctx, a->= r2)); + + /* Exit TB for TLB change if mmu is enabled. */ + if (ctx->tb_flags & PSW_C) { + ctx->base.is_jmp =3D DISAS_IAQ_N_STALE; + } + return nullify_end(ctx); +#endif +} + static bool trans_lpa(DisasContext *ctx, arg_ldst *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u7-20020aa78487000000b00694fee1011asm1946775pfn.208.2023.10.20.13.47.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:47:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834834; x=1698439634; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZidGRalLwOY7DoY6Z59b3Uu+qUnyVDoR533dncqCuKQ=; b=TYyWj7ERVwiTehoWl00ATJF3C1+RyoSnGT/VNvkrM1PWbxtXNNGSoFwgVWZAEwLmUq JFtknzcOtU1deVFFbOUAil3zJzx8U3uyJstChaVfHXo/0HjWufzgIbRiYssx/egsqWWO NoteOkWjBTDXnEw3WwaRrJVcqpTN16Ig/amgtkbqCk7Hh/Z0onDZmxvEZE3RpbP3izPW G+yK5wAQcjZTOvI7IsVjK3AyjtRXZPaDf5jExeKRTQHx2RMRp7PDnRbAdt6tRndo+J69 MRtEHgplp4u7tAcL4eezjsJ6ZqtFw4ni25oQVNoDFBwZEHxTWSg0vk1zDu+YajpeT+4r skNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834834; x=1698439634; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZidGRalLwOY7DoY6Z59b3Uu+qUnyVDoR533dncqCuKQ=; b=G+ygttd6OIINY9a75TG2f+9chg1w5F+EOvKGMHoacjN+hNwcknYy+/LIAt12XtD1ZN fB0QHXf3/BFgp2WVQmZmVGXjFx5EkaGfzS4XZxvE1YOv5Vq3663VebuPd0h4o7hZzNJA ufxbCHxV7FZkPjq3pVAtiNZcrB56yDcJXXJB80zRT4j+IS4qicgmbKHr+HBSXevST8A3 Vqkzc9dnFu3udiSIDTo5pALIo23f9ba4Zr/A3/cDKzG0sVXWw94mA0n5TKOUL6mABEmB YwDuSZmQ9FjX4kEsUoLzq6qSoXDlyXS5mwfpWHgqNQ580epDzhC9Gj+VtW4g9344p3kB N2Tw== X-Gm-Message-State: AOJu0YwQiafCZIFciT9oIqqRayhMg6yIUOZTfz9W7k0KO5vPP8NMRpaU UnpPiB2b/K1uNZxZC9GQFnKPFeItQTxWfwDc/XA= X-Google-Smtp-Source: AGHT+IEFP55ATCFN+G94XJmCt3wRraixwdC1ujEb2lRTdf9+XW/SNut9Qout/F0DC8gEZcVE+HHv7Q== X-Received: by 2002:a05:6a20:da9f:b0:16b:c20d:fcd1 with SMTP id iy31-20020a056a20da9f00b0016bc20dfcd1mr3758942pzb.21.1697834834380; Fri, 20 Oct 2023 13:47:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 46/65] hw/hppa: Use uint32_t instead of target_ureg Date: Fri, 20 Oct 2023 13:43:12 -0700 Message-Id: <20231020204331.139847-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834938779100001 Content-Type: text/plain; charset="utf-8" The size of target_ureg is going to change. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/hppa/machine.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 85682e6bab..1f09b4b490 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -391,9 +391,9 @@ static void machine_HP_common_init_tail(MachineState *m= achine, PCIBus *pci_bus) true, EM_PARISC, 0, 0); =20 /* Unfortunately, load_elf sign-extends reading elf32. */ - firmware_entry =3D (target_ureg)firmware_entry; - firmware_low =3D (target_ureg)firmware_low; - firmware_high =3D (target_ureg)firmware_high; + firmware_entry =3D (uint32_t)firmware_entry; + firmware_low =3D (uint32_t)firmware_low; + firmware_high =3D (uint32_t)firmware_high; =20 if (size < 0) { error_report("could not load firmware '%s'", firmware_filename); @@ -420,9 +420,9 @@ static void machine_HP_common_init_tail(MachineState *m= achine, PCIBus *pci_bus) true, EM_PARISC, 0, 0); =20 /* Unfortunately, load_elf sign-extends reading elf32. */ - kernel_entry =3D (target_ureg) cpu_hppa_to_phys(NULL, kernel_entry= ); - kernel_low =3D (target_ureg)kernel_low; - kernel_high =3D (target_ureg)kernel_high; + kernel_entry =3D (uint32_t) cpu_hppa_to_phys(NULL, kernel_entry); + kernel_low =3D (uint32_t)kernel_low; + kernel_high =3D (uint32_t)kernel_high; =20 if (size < 0) { error_report("could not load kernel '%s'", kernel_filename); --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835041; cv=none; d=zohomail.com; s=zohoarc; b=kGxJj6geEECzBZ8OMXwrJ0l9xPgjytwVXJ0IeUxp6dE3Mmxz2lwGAggKu0eiANo+GCCnajpQfhpA6dw/RknQ3pUrHBiklxa8NP48qLdgp6JmH4+N+D2GQANoCuPFkYOadAgEReo77yQReCmI8/ASTFF0ptsqE5nPp4C5AjF74IU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697835041; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Kpdf7cOB1galYRUWIQJoZgm3BMmx0l8/le6WtehZMVk=; b=SrcVQ/QVfHZZXFFEcMvcpOoZUwskyYKgFw/wFotzm7TgGLuaJxajDBGQDOlKyLRuayrL85MIdpfzBHHWYuGv3xSWaukM+K/rBFA9IUZ0JG5uLLJ4RDej1iVb2iOA28UW21UFjT3v2iWe02Zk0H8/64jXtTWshh4nUktJUnZf03E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697835041461829.1731791376237; Fri, 20 Oct 2023 13:50:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwOw-0001pO-Da; Fri, 20 Oct 2023 16:47:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwOu-0001oe-SP for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:47:20 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwOq-0001B0-VP for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:47:20 -0400 Received: by mail-pg1-x530.google.com with SMTP id 41be03b00d2f7-5b5354da665so842065a12.2 for ; Fri, 20 Oct 2023 13:47:16 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u7-20020aa78487000000b00694fee1011asm1946775pfn.208.2023.10.20.13.47.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:47:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834835; x=1698439635; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Kpdf7cOB1galYRUWIQJoZgm3BMmx0l8/le6WtehZMVk=; b=y5D79em5XkqR6Pqq7M00OM3UtGT4sd/u3Lte0Ss4t67kQgzdKIhmDP5MO86kivV6zc kJtUKFcSed9NfvuG+1K9q/X9gmHLp9m48ohyOt0YTKuY//3MYLUH98CAHGX+WT5YWgKd O3mEpACUyWXawB9CYM3iICFHFoveUWGCYgNEC4IvDdqZu1pBVSnWlLXg/0gbW7aG04a0 RScrCWGx3v4sttdMTjpYQz5eqCrPjz6vN11gsu32kxoThxJ6osM8Hh27FX7QZmxVrRlF QrXOeuhr5wYrmUYKJKG8sNM+M5cljqspFAQhni0nQcrmVEz6Gy+HlPTYEgNH/eqNdCxI SPHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834835; x=1698439635; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Kpdf7cOB1galYRUWIQJoZgm3BMmx0l8/le6WtehZMVk=; b=J1iMCIwNeS6Nqzq/IDVHMdtgWnfGBgF4X8+SRbaQeDZzf4nli+E7Ju1oFEORiGh9q9 YahRWFIW2UbOPfBVnD4p9bDaX4tT5n126L21NiYyB9wsp+EZQXG9C0Ehdp5KRklUaTeR GuBkxmuIqRpQwpnQMqQwadRsjmd6EN+OYApMthmF8Xxda8rB3YXkCBly9tU+r7oVyPJO gTpJ9Cq1x1J1KuERDy4iueGKoQ//yvq0VctGYx2orxq1NWMgGH+NuNO5g+rKM/+lGEHr tQS1HBiJaIo1UcvCHUe2fa2mFQo5nCZpFvf9zLvIQCtfEMFfjaQyHp3f77+QtyQBzGGQ +9pg== X-Gm-Message-State: AOJu0YzwbajKHRwdReTtjDGfxWHOKlXTtjxhLKIo5dM1HFKGBtOfIKgu DgYbZsHeCg/C46YKx2h63wQRiY50d5zdoOaQeVM= X-Google-Smtp-Source: AGHT+IEsjPWP6gp2sXDfpigvu7xb01lmv0fHtIBUoXPjX0kare8Tg/rh0kihdckmNn+soTVQQbl1UA== X-Received: by 2002:a05:6a20:7489:b0:161:ffbf:d949 with SMTP id p9-20020a056a20748900b00161ffbfd949mr3132410pzd.3.1697834835271; Fri, 20 Oct 2023 13:47:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 47/65] target/hppa: Remove TARGET_REGISTER_BITS Date: Fri, 20 Oct 2023 13:43:13 -0700 Message-Id: <20231020204331.139847-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835043187100007 Content-Type: text/plain; charset="utf-8" Rely only on TARGET_LONG_BITS, fixed at 64, and hppa_is_pa20. Signed-off-by: Richard Henderson --- target/hppa/cpu-param.h | 1 - target/hppa/cpu.h | 50 ++++------- target/hppa/helper.h | 49 +++++------ target/hppa/cpu.c | 2 +- target/hppa/helper.c | 34 +++----- target/hppa/int_helper.c | 17 ++-- target/hppa/machine.c | 9 -- target/hppa/mem_helper.c | 10 +-- target/hppa/op_helper.c | 30 +++---- target/hppa/sys_helper.c | 4 +- target/hppa/translate.c | 184 ++++++++------------------------------- 11 files changed, 119 insertions(+), 271 deletions(-) diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index 2fb8e7924b..6746869a3b 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -9,7 +9,6 @@ #define HPPA_CPU_PARAM_H =20 #define TARGET_LONG_BITS 64 -#define TARGET_REGISTER_BITS 64 =20 #if defined(CONFIG_USER_ONLY) && defined(TARGET_ABI32) # define TARGET_PHYS_ADDR_SPACE_BITS 32 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 8320f82464..c9a9b9d3be 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -141,22 +141,10 @@ #define CR_IPSW 22 #define CR_EIRR 23 =20 -#if TARGET_REGISTER_BITS =3D=3D 32 -typedef uint32_t target_ureg; -typedef int32_t target_sreg; -#define TREG_FMT_lx "%08"PRIx32 -#define TREG_FMT_ld "%"PRId32 -#else -typedef uint64_t target_ureg; -typedef int64_t target_sreg; -#define TREG_FMT_lx "%016"PRIx64 -#define TREG_FMT_ld "%"PRId64 -#endif - typedef struct { uint64_t va_b; uint64_t va_e; - target_ureg pa; + target_ulong pa; unsigned u : 1; unsigned t : 1; unsigned d : 1; @@ -170,16 +158,16 @@ typedef struct { } hppa_tlb_entry; =20 typedef struct CPUArchState { - target_ureg iaoq_f; /* front */ - target_ureg iaoq_b; /* back, aka next instruction */ + target_ulong iaoq_f; /* front */ + target_ulong iaoq_b; /* back, aka next instruction */ =20 - target_ureg gr[32]; + target_ulong gr[32]; uint64_t fr[32]; uint64_t sr[8]; /* stored shifted into place for gva */ =20 - target_ureg psw; /* All psw bits except the following: */ - target_ureg psw_n; /* boolean */ - target_sreg psw_v; /* in most significant bit */ + target_ulong psw; /* All psw bits except the following: */ + target_ulong psw_n; /* boolean */ + target_long psw_v; /* in most significant bit */ =20 /* Splitting the carry-borrow field into the MSB and "the rest", allows * for "the rest" to be deleted when it is unused, but the MSB is in u= se. @@ -188,8 +176,8 @@ typedef struct CPUArchState { * host has the appropriate add-with-carry insn to compute the msb). * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110. */ - target_ureg psw_cb; /* in least significant bit of next nibble */ - target_ureg psw_cb_msb; /* boolean */ + target_ulong psw_cb; /* in least significant bit of next nibble */ + target_ulong psw_cb_msb; /* boolean */ =20 uint64_t iasq_f; uint64_t iasq_b; @@ -197,9 +185,9 @@ typedef struct CPUArchState { uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ float_status fp_status; =20 - target_ureg cr[32]; /* control registers */ - target_ureg cr_back[2]; /* back of cr17/cr18 */ - target_ureg shadow[7]; /* shadow registers */ + target_ulong cr[32]; /* control registers */ + target_ulong cr_back[2]; /* back of cr17/cr18 */ + target_ulong shadow[7]; /* shadow registers */ =20 /* * ??? The number of entries isn't specified by the architecture. @@ -258,8 +246,8 @@ void hppa_translate_init(void); =20 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU =20 -static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc, - target_ureg off) +static inline target_ulong hppa_form_gva_psw(target_ulong psw, uint64_t sp= c, + target_ulong off) { #ifdef CONFIG_USER_ONLY return off; @@ -270,7 +258,7 @@ static inline target_ulong hppa_form_gva_psw(target_ure= g psw, uint64_t spc, } =20 static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, - target_ureg off) + target_ulong off) { return hppa_form_gva_psw(env->psw, spc, off); } @@ -314,8 +302,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *e= nv, vaddr *pc, which is the primary case we care about -- using goto_tb within a p= age. Failure is indicated by a zero difference. */ if (env->iasq_f =3D=3D env->iasq_b) { - target_sreg diff =3D env->iaoq_b - env->iaoq_f; - if (TARGET_REGISTER_BITS =3D=3D 32 || diff =3D=3D (int32_t)diff) { + target_long diff =3D env->iaoq_b - env->iaoq_f; + if (diff =3D=3D (int32_t)diff) { *cs_base |=3D (uint32_t)diff; } } @@ -329,8 +317,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *e= nv, vaddr *pc, *pflags =3D flags; } =20 -target_ureg cpu_hppa_get_psw(CPUHPPAState *env); -void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg); +target_ulong cpu_hppa_get_psw(CPUHPPAState *env); +void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); void cpu_hppa_loaded_fr0(CPUHPPAState *env); =20 #ifdef CONFIG_USER_ONLY diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 58b6754dbe..4b2c66316f 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -1,29 +1,20 @@ -#if TARGET_REGISTER_BITS =3D=3D 64 -# define dh_alias_tr i64 -# define dh_typecode_tr dh_typecode_i64 -#else -# define dh_alias_tr i32 -# define dh_typecode_tr dh_typecode_i32 -#endif -#define dh_ctype_tr target_ureg - DEF_HELPER_2(excp, noreturn, env, int) -DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tr) -DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tr) +DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tl) +DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tl) =20 -DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tr) -DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tr) -DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tr) -DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tl) =20 -DEF_HELPER_FLAGS_3(stdby_b, TCG_CALL_NO_WG, void, env, tl, tr) -DEF_HELPER_FLAGS_3(stdby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tr) -DEF_HELPER_FLAGS_3(stdby_e, TCG_CALL_NO_WG, void, env, tl, tr) -DEF_HELPER_FLAGS_3(stdby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(stdby_b, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stdby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stdby_e, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stdby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tl) =20 DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl) =20 -DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tr, env, tl, i32, i32) +DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tl, env, tl, i32, i32) =20 DEF_HELPER_FLAGS_1(loaded_fr0, TCG_CALL_NO_RWG, void, env) =20 @@ -82,7 +73,7 @@ DEF_HELPER_FLAGS_4(fmpynfadd_s, TCG_CALL_NO_RWG, i32, env= , i32, i32, i32) DEF_HELPER_FLAGS_4(fmpyfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) =20 -DEF_HELPER_FLAGS_0(read_interval_timer, TCG_CALL_NO_RWG, tr) +DEF_HELPER_FLAGS_0(read_interval_timer, TCG_CALL_NO_RWG, tl) =20 #ifndef CONFIG_USER_ONLY DEF_HELPER_1(halt, noreturn, env) @@ -90,16 +81,16 @@ DEF_HELPER_1(reset, noreturn, env) DEF_HELPER_1(getshadowregs, void, env) DEF_HELPER_1(rfi, void, env) DEF_HELPER_1(rfi_r, void, env) -DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tr) -DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tr) -DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr) -DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) -DEF_HELPER_FLAGS_3(itlba_pa11, TCG_CALL_NO_RWG, void, env, tl, tr) -DEF_HELPER_FLAGS_3(itlbp_pa11, TCG_CALL_NO_RWG, void, env, tl, tr) -DEF_HELPER_FLAGS_3(itlbt_pa20, TCG_CALL_NO_RWG, void, env, tr, tr) +DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tl, env, tl) +DEF_HELPER_FLAGS_3(itlba_pa11, TCG_CALL_NO_RWG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(itlbp_pa11, TCG_CALL_NO_RWG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(itlbt_pa20, TCG_CALL_NO_RWG, void, env, tl, tl) DEF_HELPER_FLAGS_2(ptlb, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_1(ptlbe, TCG_CALL_NO_RWG, void, env) -DEF_HELPER_FLAGS_2(lpa, TCG_CALL_NO_WG, tr, env, tl) +DEF_HELPER_FLAGS_2(lpa, TCG_CALL_NO_WG, tl, env, tl) DEF_HELPER_FLAGS_1(change_prot_id, TCG_CALL_NO_RWG, void, env) DEF_HELPER_1(diag_btlb, void, env) #endif diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 36875a6a1a..95abe1ff17 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -77,7 +77,7 @@ static void hppa_restore_state_to_opc(CPUState *cs, HPPACPU *cpu =3D HPPA_CPU(cs); =20 cpu->env.iaoq_f =3D data[0]; - if (data[1] !=3D (target_ureg)-1) { + if (data[1] !=3D (target_ulong)-1) { cpu->env.iaoq_b =3D data[1]; } /* diff --git a/target/hppa/helper.c b/target/hppa/helper.c index a2ae7aca30..fe7d8c2664 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -25,31 +25,25 @@ #include "exec/helper-proto.h" #include "qemu/qemu-print.h" =20 -target_ureg cpu_hppa_get_psw(CPUHPPAState *env) +target_ulong cpu_hppa_get_psw(CPUHPPAState *env) { - target_ureg psw; - target_ureg mask1 =3D (target_ureg)-1 / 0xf; - target_ureg maskf =3D (target_ureg)-1 / 0xffff * 0xf; + target_ulong psw; + target_ulong mask1 =3D (target_ulong)-1 / 0xf; + target_ulong maskf =3D (target_ulong)-1 / 0xffff * 0xf; =20 /* Fold carry bits down to 8 consecutive bits. */ /* ^^^b^^^c^^^d^^^e^^^f^^^g^^^h^^^i^^^j^^^k^^^l^^^m^^^n^^^o^^^p^^^^ */ - /* ^^^b^^^c^^^d^^^e^^^f^^^g^^^h^^^^ */ psw =3D (env->psw_cb >> 4) & mask1; /* .......b...c...d...e...f...g...h...i...j...k...l...m...n...o...p */ - /* .......b...c...d...e...f...g...h */ psw |=3D psw >> 3; /* .......b..bc..cd..de..ef..fg..gh..hi..ij..jk..kl..lm..mn..no..op */ - /* .......b..bc..cd..de..ef..fg..gh */ psw |=3D psw >> 6; psw &=3D maskf; /* .............bcd............efgh............ijkl............mnop */ - /* .............bcd............efgh */ psw |=3D psw >> 12; /* .............bcd.........bcdefgh........efghijkl........ijklmnop */ - /* .............bcd.........bcdefgh */ - psw |=3D env->psw_cb_msb << (TARGET_REGISTER_BITS =3D=3D 64 ? 39 : 7); + psw |=3D env->psw_cb_msb << 39; /* .............bcd........abcdefgh........efghijkl........ijklmnop */ - /* .............bcd........abcdefgh */ =20 /* For hppa64, the two 8-bit fields are discontiguous. */ if (hppa_is_pa20(env)) { @@ -65,11 +59,11 @@ target_ureg cpu_hppa_get_psw(CPUHPPAState *env) return psw; } =20 -void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) +void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) { uint64_t reserved; - target_ureg old_psw =3D env->psw; - target_ureg cb =3D 0; + target_ulong old_psw =3D env->psw; + target_ulong cb =3D 0; =20 /* Do not allow reserved bits to be set. */ if (hppa_is_pa20(env)) { @@ -87,9 +81,6 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) env->psw_n =3D (psw / PSW_N) & 1; env->psw_v =3D -((psw / PSW_V) & 1); =20 -#if TARGET_REGISTER_BITS =3D=3D 32 - env->psw_cb_msb =3D (psw >> 15) & 1; -#else env->psw_cb_msb =3D (psw >> 39) & 1; cb |=3D ((psw >> 38) & 1) << 60; cb |=3D ((psw >> 37) & 1) << 56; @@ -99,7 +90,6 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) cb |=3D ((psw >> 33) & 1) << 40; cb |=3D ((psw >> 32) & 1) << 36; cb |=3D ((psw >> 15) & 1) << 32; -#endif cb |=3D ((psw >> 14) & 1) << 28; cb |=3D ((psw >> 13) & 1) << 24; cb |=3D ((psw >> 12) & 1) << 20; @@ -120,8 +110,8 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg ps= w) void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) { CPUHPPAState *env =3D cpu_env(cs); - target_ureg psw =3D cpu_hppa_get_psw(env); - target_ureg psw_cb; + target_ulong psw =3D cpu_hppa_get_psw(env); + target_ulong psw_cb; char psw_c[20]; int i, w; uint64_t m; @@ -159,8 +149,8 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) psw_c[16] =3D (psw & PSW_D ? 'D' : '-'); psw_c[17] =3D (psw & PSW_I ? 'I' : '-'); psw_c[18] =3D '\0'; - psw_cb =3D ((env->psw_cb >> 4) & ((target_ureg)-1 / 0xf)) - | (env->psw_cb_msb << (TARGET_REGISTER_BITS - 4)); + psw_cb =3D ((env->psw_cb >> 4) & 0x1111111111111111ull) + | (env->psw_cb_msb << 60); =20 qemu_fprintf(f, "PSW %0*" PRIx64 " CB %0*" PRIx64 " %s\n", w, m & psw, w, m & psw_cb, psw_c); diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 3ab9934a1d..f355c4c76b 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -52,9 +52,9 @@ static void io_eir_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { HPPACPU *cpu =3D opaque; - int le_bit =3D ~data & (TARGET_REGISTER_BITS - 1); + int le_bit =3D ~data & 31; =20 - cpu->env.cr[CR_EIRR] |=3D (target_ureg)1 << le_bit; + cpu->env.cr[CR_EIRR] |=3D (target_ulong)1 << le_bit; eval_interrupt(cpu); } =20 @@ -73,7 +73,7 @@ void hppa_cpu_alarm_timer(void *opaque) io_eir_write(opaque, 0, 0, 4); } =20 -void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val) +void HELPER(write_eirr)(CPUHPPAState *env, target_ulong val) { env->cr[CR_EIRR] &=3D ~val; qemu_mutex_lock_iothread(); @@ -81,7 +81,7 @@ void HELPER(write_eirr)(CPUHPPAState *env, target_ureg va= l) qemu_mutex_unlock_iothread(); } =20 -void HELPER(write_eiem)(CPUHPPAState *env, target_ureg val) +void HELPER(write_eiem)(CPUHPPAState *env, target_ulong val) { env->cr[CR_EIEM] =3D val; qemu_mutex_lock_iothread(); @@ -94,12 +94,11 @@ void hppa_cpu_do_interrupt(CPUState *cs) HPPACPU *cpu =3D HPPA_CPU(cs); CPUHPPAState *env =3D &cpu->env; int i =3D cs->exception_index; - target_ureg iaoq_f =3D env->iaoq_f; - target_ureg iaoq_b =3D env->iaoq_b; + target_ulong iaoq_f =3D env->iaoq_f; + target_ulong iaoq_b =3D env->iaoq_b; uint64_t iasq_f =3D env->iasq_f; uint64_t iasq_b =3D env->iasq_b; - - target_ureg old_psw; + target_ulong old_psw; =20 /* As documented in pa2.0 -- interruption handling. */ /* step 1 */ @@ -240,7 +239,7 @@ void hppa_cpu_do_interrupt(CPUState *cs) name =3D unknown; } qemu_log("INT %6d: %s @ " TARGET_FMT_lx "," TARGET_FMT_lx - " -> " TREG_FMT_lx " " TARGET_FMT_lx "\n", + " -> " TARGET_FMT_lx " " TARGET_FMT_lx "\n", ++count, name, hppa_form_gva(env, iasq_f, iaoq_f), hppa_form_gva(env, iasq_b, iaoq_b), diff --git a/target/hppa/machine.c b/target/hppa/machine.c index 0c0bba68c0..ab34b72910 100644 --- a/target/hppa/machine.c +++ b/target/hppa/machine.c @@ -21,21 +21,12 @@ #include "cpu.h" #include "migration/cpu.h" =20 -#if TARGET_REGISTER_BITS =3D=3D 64 #define qemu_put_betr qemu_put_be64 #define qemu_get_betr qemu_get_be64 #define VMSTATE_UINTTR_V(_f, _s, _v) \ VMSTATE_UINT64_V(_f, _s, _v) #define VMSTATE_UINTTR_ARRAY_V(_f, _s, _n, _v) \ VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v) -#else -#define qemu_put_betr qemu_put_be32 -#define qemu_get_betr qemu_get_be32 -#define VMSTATE_UINTTR_V(_f, _s, _v) \ - VMSTATE_UINT32_V(_f, _s, _v) -#define VMSTATE_UINTTR_ARRAY_V(_f, _s, _n, _v) \ - VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v) -#endif =20 #define VMSTATE_UINTTR(_f, _s) \ VMSTATE_UINTTR_V(_f, _s, 0) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 356746654c..8aa94bb266 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -312,7 +312,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int si= ze, } =20 /* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */ -void HELPER(itlba_pa11)(CPUHPPAState *env, target_ulong addr, target_ureg = reg) +void HELPER(itlba_pa11)(CPUHPPAState *env, target_ulong addr, target_ulong= reg) { hppa_tlb_entry *empty =3D NULL; int i; @@ -343,7 +343,7 @@ void HELPER(itlba_pa11)(CPUHPPAState *env, target_ulong= addr, target_ureg reg) } =20 static void set_access_bits_pa11(CPUHPPAState *env, hppa_tlb_entry *ent, - target_ureg reg) + target_ulong reg) { ent->access_id =3D extract32(reg, 1, 18); ent->u =3D extract32(reg, 19, 1); @@ -359,7 +359,7 @@ static void set_access_bits_pa11(CPUHPPAState *env, hpp= a_tlb_entry *ent, } =20 /* Insert (Insn/Data) TLB Protection. Note this is PA 1.1 only. */ -void HELPER(itlbp_pa11)(CPUHPPAState *env, target_ulong addr, target_ureg = reg) +void HELPER(itlbp_pa11)(CPUHPPAState *env, target_ulong addr, target_ulong= reg) { hppa_tlb_entry *ent =3D hppa_find_tlb(env, addr); =20 @@ -370,7 +370,7 @@ void HELPER(itlbp_pa11)(CPUHPPAState *env, target_ulong= addr, target_ureg reg) set_access_bits_pa11(env, ent, reg); } =20 -void HELPER(itlbt_pa20)(CPUHPPAState *env, target_ureg r1, target_ureg r2) +void HELPER(itlbt_pa20)(CPUHPPAState *env, target_ulong r1, target_ulong r= 2) { hppa_tlb_entry *ent, *empty =3D NULL; vaddr va_b, va_e; @@ -471,7 +471,7 @@ void HELPER(change_prot_id)(CPUHPPAState *env) cpu_hppa_change_prot_id(env); } =20 -target_ureg HELPER(lpa)(CPUHPPAState *env, target_ulong addr) +target_ulong HELPER(lpa)(CPUHPPAState *env, target_ulong addr) { hwaddr phys; int prot, excp; diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 94c9ca5858..0bccca1e11 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -42,14 +42,14 @@ G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, in= t excp, uintptr_t ra) cpu_loop_exit_restore(cs, ra); } =20 -void HELPER(tsv)(CPUHPPAState *env, target_ureg cond) +void HELPER(tsv)(CPUHPPAState *env, target_ulong cond) { - if (unlikely((target_sreg)cond < 0)) { + if (unlikely((target_long)cond < 0)) { hppa_dynamic_excp(env, EXCP_OVERFLOW, GETPC()); } } =20 -void HELPER(tcond)(CPUHPPAState *env, target_ureg cond) +void HELPER(tcond)(CPUHPPAState *env, target_ulong cond) { if (unlikely(cond)) { hppa_dynamic_excp(env, EXCP_COND, GETPC()); @@ -110,7 +110,7 @@ static void atomic_store_mask64(CPUHPPAState *env, targ= et_ulong addr, #endif } =20 -static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ureg va= l, +static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ulong v= al, bool parallel, uintptr_t ra) { switch (addr & 3) { @@ -191,29 +191,29 @@ static void do_stdby_b(CPUHPPAState *env, target_ulon= g addr, uint64_t val, } } =20 -void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val) +void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ulong val) { do_stby_b(env, addr, val, false, GETPC()); } =20 void HELPER(stby_b_parallel)(CPUHPPAState *env, target_ulong addr, - target_ureg val) + target_ulong val) { do_stby_b(env, addr, val, true, GETPC()); } =20 -void HELPER(stdby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val) +void HELPER(stdby_b)(CPUHPPAState *env, target_ulong addr, target_ulong va= l) { do_stdby_b(env, addr, val, false, GETPC()); } =20 void HELPER(stdby_b_parallel)(CPUHPPAState *env, target_ulong addr, - target_ureg val) + target_ulong val) { do_stdby_b(env, addr, val, true, GETPC()); } =20 -static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ureg va= l, +static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ulong v= al, bool parallel, uintptr_t ra) { switch (addr & 3) { @@ -301,24 +301,24 @@ static void do_stdby_e(CPUHPPAState *env, target_ulon= g addr, uint64_t val, } } =20 -void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ureg val) +void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ulong val) { do_stby_e(env, addr, val, false, GETPC()); } =20 void HELPER(stby_e_parallel)(CPUHPPAState *env, target_ulong addr, - target_ureg val) + target_ulong val) { do_stby_e(env, addr, val, true, GETPC()); } =20 -void HELPER(stdby_e)(CPUHPPAState *env, target_ulong addr, target_ureg val) +void HELPER(stdby_e)(CPUHPPAState *env, target_ulong addr, target_ulong va= l) { do_stdby_e(env, addr, val, false, GETPC()); } =20 void HELPER(stdby_e_parallel)(CPUHPPAState *env, target_ulong addr, - target_ureg val) + target_ulong val) { do_stdby_e(env, addr, val, true, GETPC()); } @@ -332,7 +332,7 @@ void HELPER(ldc_check)(target_ulong addr) } } =20 -target_ureg HELPER(probe)(CPUHPPAState *env, target_ulong addr, +target_ulong HELPER(probe)(CPUHPPAState *env, target_ulong addr, uint32_t level, uint32_t want) { #ifdef CONFIG_USER_ONLY @@ -364,7 +364,7 @@ target_ureg HELPER(probe)(CPUHPPAState *env, target_ulo= ng addr, #endif } =20 -target_ureg HELPER(read_interval_timer)(void) +target_ulong HELPER(read_interval_timer)(void) { #ifdef CONFIG_USER_ONLY /* In user-mode, QEMU_CLOCK_VIRTUAL doesn't exist. diff --git a/target/hppa/sys_helper.c b/target/hppa/sys_helper.c index f0dd5a08e7..bb57413199 100644 --- a/target/hppa/sys_helper.c +++ b/target/hppa/sys_helper.c @@ -24,7 +24,7 @@ #include "qemu/timer.h" #include "sysemu/runstate.h" =20 -void HELPER(write_interval_timer)(CPUHPPAState *env, target_ureg val) +void HELPER(write_interval_timer)(CPUHPPAState *env, target_ulong val) { HPPACPU *cpu =3D env_archcpu(env); uint64_t current =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); @@ -58,7 +58,7 @@ void HELPER(reset)(CPUHPPAState *env) helper_excp(env, EXCP_HLT); } =20 -target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) +target_ulong HELPER(swap_system_mask)(CPUHPPAState *env, target_ulong nsm) { target_ulong psw =3D env->psw; /* diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 2a09e1cdad..96082d1a9c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -40,21 +40,10 @@ #undef tcg_temp_new #undef tcg_global_mem_new =20 -#if TARGET_LONG_BITS =3D=3D 64 #define TCGv_tl TCGv_i64 #define tcg_temp_new_tl tcg_temp_new_i64 -#if TARGET_REGISTER_BITS =3D=3D 64 #define tcg_gen_extu_reg_tl tcg_gen_mov_i64 -#else -#define tcg_gen_extu_reg_tl tcg_gen_extu_i32_i64 -#endif -#else -#define TCGv_tl TCGv_i32 -#define tcg_temp_new_tl tcg_temp_new_i32 -#define tcg_gen_extu_reg_tl tcg_gen_mov_i32 -#endif =20 -#if TARGET_REGISTER_BITS =3D=3D 64 #define TCGv_reg TCGv_i64 =20 #define tcg_temp_new tcg_temp_new_i64 @@ -147,98 +136,6 @@ #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64 #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64 #define tcg_gen_trunc_reg_ptr tcg_gen_trunc_i64_ptr -#else -#define TCGv_reg TCGv_i32 -#define tcg_temp_new tcg_temp_new_i32 -#define tcg_global_mem_new tcg_global_mem_new_i32 - -#define tcg_gen_movi_reg tcg_gen_movi_i32 -#define tcg_gen_mov_reg tcg_gen_mov_i32 -#define tcg_gen_ld8u_reg tcg_gen_ld8u_i32 -#define tcg_gen_ld8s_reg tcg_gen_ld8s_i32 -#define tcg_gen_ld16u_reg tcg_gen_ld16u_i32 -#define tcg_gen_ld16s_reg tcg_gen_ld16s_i32 -#define tcg_gen_ld32u_reg tcg_gen_ld_i32 -#define tcg_gen_ld32s_reg tcg_gen_ld_i32 -#define tcg_gen_ld_reg tcg_gen_ld_i32 -#define tcg_gen_st8_reg tcg_gen_st8_i32 -#define tcg_gen_st16_reg tcg_gen_st16_i32 -#define tcg_gen_st32_reg tcg_gen_st32_i32 -#define tcg_gen_st_reg tcg_gen_st_i32 -#define tcg_gen_add_reg tcg_gen_add_i32 -#define tcg_gen_addi_reg tcg_gen_addi_i32 -#define tcg_gen_sub_reg tcg_gen_sub_i32 -#define tcg_gen_neg_reg tcg_gen_neg_i32 -#define tcg_gen_subfi_reg tcg_gen_subfi_i32 -#define tcg_gen_subi_reg tcg_gen_subi_i32 -#define tcg_gen_and_reg tcg_gen_and_i32 -#define tcg_gen_andi_reg tcg_gen_andi_i32 -#define tcg_gen_or_reg tcg_gen_or_i32 -#define tcg_gen_ori_reg tcg_gen_ori_i32 -#define tcg_gen_xor_reg tcg_gen_xor_i32 -#define tcg_gen_xori_reg tcg_gen_xori_i32 -#define tcg_gen_not_reg tcg_gen_not_i32 -#define tcg_gen_shl_reg tcg_gen_shl_i32 -#define tcg_gen_shli_reg tcg_gen_shli_i32 -#define tcg_gen_shr_reg tcg_gen_shr_i32 -#define tcg_gen_shri_reg tcg_gen_shri_i32 -#define tcg_gen_sar_reg tcg_gen_sar_i32 -#define tcg_gen_sari_reg tcg_gen_sari_i32 -#define tcg_gen_brcond_reg tcg_gen_brcond_i32 -#define tcg_gen_brcondi_reg tcg_gen_brcondi_i32 -#define tcg_gen_setcond_reg tcg_gen_setcond_i32 -#define tcg_gen_setcondi_reg tcg_gen_setcondi_i32 -#define tcg_gen_mul_reg tcg_gen_mul_i32 -#define tcg_gen_muli_reg tcg_gen_muli_i32 -#define tcg_gen_div_reg tcg_gen_div_i32 -#define tcg_gen_rem_reg tcg_gen_rem_i32 -#define tcg_gen_divu_reg tcg_gen_divu_i32 -#define tcg_gen_remu_reg tcg_gen_remu_i32 -#define tcg_gen_discard_reg tcg_gen_discard_i32 -#define tcg_gen_trunc_reg_i32 tcg_gen_mov_i32 -#define tcg_gen_trunc_i64_reg tcg_gen_extrl_i64_i32 -#define tcg_gen_extu_i32_reg tcg_gen_mov_i32 -#define tcg_gen_ext_i32_reg tcg_gen_mov_i32 -#define tcg_gen_extu_reg_i64 tcg_gen_extu_i32_i64 -#define tcg_gen_ext_reg_i64 tcg_gen_ext_i32_i64 -#define tcg_gen_ext8u_reg tcg_gen_ext8u_i32 -#define tcg_gen_ext8s_reg tcg_gen_ext8s_i32 -#define tcg_gen_ext16u_reg tcg_gen_ext16u_i32 -#define tcg_gen_ext16s_reg tcg_gen_ext16s_i32 -#define tcg_gen_ext32u_reg tcg_gen_mov_i32 -#define tcg_gen_ext32s_reg tcg_gen_mov_i32 -#define tcg_gen_bswap16_reg tcg_gen_bswap16_i32 -#define tcg_gen_bswap32_reg tcg_gen_bswap32_i32 -#define tcg_gen_concat_reg_i64 tcg_gen_concat_i32_i64 -#define tcg_gen_andc_reg tcg_gen_andc_i32 -#define tcg_gen_eqv_reg tcg_gen_eqv_i32 -#define tcg_gen_nand_reg tcg_gen_nand_i32 -#define tcg_gen_nor_reg tcg_gen_nor_i32 -#define tcg_gen_orc_reg tcg_gen_orc_i32 -#define tcg_gen_clz_reg tcg_gen_clz_i32 -#define tcg_gen_ctz_reg tcg_gen_ctz_i32 -#define tcg_gen_clzi_reg tcg_gen_clzi_i32 -#define tcg_gen_ctzi_reg tcg_gen_ctzi_i32 -#define tcg_gen_clrsb_reg tcg_gen_clrsb_i32 -#define tcg_gen_ctpop_reg tcg_gen_ctpop_i32 -#define tcg_gen_rotl_reg tcg_gen_rotl_i32 -#define tcg_gen_rotli_reg tcg_gen_rotli_i32 -#define tcg_gen_rotr_reg tcg_gen_rotr_i32 -#define tcg_gen_rotri_reg tcg_gen_rotri_i32 -#define tcg_gen_deposit_reg tcg_gen_deposit_i32 -#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32 -#define tcg_gen_extract_reg tcg_gen_extract_i32 -#define tcg_gen_sextract_reg tcg_gen_sextract_i32 -#define tcg_gen_extract2_reg tcg_gen_extract2_i32 -#define tcg_constant_reg tcg_constant_i32 -#define tcg_gen_movcond_reg tcg_gen_movcond_i32 -#define tcg_gen_add2_reg tcg_gen_add2_i32 -#define tcg_gen_sub2_reg tcg_gen_sub2_i32 -#define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i32 -#define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i32 -#define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32 -#define tcg_gen_trunc_reg_ptr tcg_gen_ext_i32_ptr -#endif /* TARGET_REGISTER_BITS */ =20 typedef struct DisasCond { TCGCond c; @@ -249,9 +146,9 @@ typedef struct DisasContext { DisasContextBase base; CPUState *cs; =20 - target_ureg iaoq_f; - target_ureg iaoq_b; - target_ureg iaoq_n; + uint64_t iaoq_f; + uint64_t iaoq_b; + uint64_t iaoq_n; TCGv_reg iaoq_n_var; =20 DisasCond null_cond; @@ -727,7 +624,7 @@ static bool nullify_end(DisasContext *ctx) return true; } =20 -static void copy_iaoq_entry(TCGv_reg dest, target_ureg ival, TCGv_reg vval) +static void copy_iaoq_entry(TCGv_reg dest, uint64_t ival, TCGv_reg vval) { if (unlikely(ival =3D=3D -1)) { tcg_gen_mov_reg(dest, vval); @@ -736,7 +633,7 @@ static void copy_iaoq_entry(TCGv_reg dest, target_ureg = ival, TCGv_reg vval) } } =20 -static inline target_ureg iaoq_dest(DisasContext *ctx, target_sreg disp) +static inline uint64_t iaoq_dest(DisasContext *ctx, int64_t disp) { return ctx->iaoq_f + disp + 8; } @@ -781,14 +678,14 @@ static bool gen_illegal(DisasContext *ctx) } while (0) #endif =20 -static target_ureg gva_offset_mask(DisasContext *ctx) +static uint64_t gva_offset_mask(DisasContext *ctx) { return (ctx->tb_flags & PSW_W ? MAKE_64BIT_MASK(0, 62) : MAKE_64BIT_MASK(0, 32)); } =20 -static bool use_goto_tb(DisasContext *ctx, target_ureg dest) +static bool use_goto_tb(DisasContext *ctx, uint64_t dest) { return translator_use_goto_tb(&ctx->base, dest); } @@ -804,7 +701,7 @@ static bool use_nullify_skip(DisasContext *ctx) } =20 static void gen_goto_tb(DisasContext *ctx, int which, - target_ureg f, target_ureg b) + uint64_t f, uint64_t b) { if (f !=3D -1 && b !=3D -1 && use_goto_tb(ctx, f)) { tcg_gen_goto_tb(which); @@ -831,7 +728,7 @@ static bool cond_need_cb(int c) /* Need extensions from TCGv_i32 to TCGv_reg. */ static bool cond_need_ext(DisasContext *ctx, bool d) { - return TARGET_REGISTER_BITS =3D=3D 64 && !(ctx->is_pa20 && d); + return !(ctx->is_pa20 && d); } =20 /* @@ -882,7 +779,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf= , bool d, tcg_gen_and_reg(tmp, tmp, res); tcg_gen_ext32u_reg(tmp, tmp); } else { - tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); + tcg_gen_sari_reg(tmp, tmp, 63); tcg_gen_and_reg(tmp, tmp, res); } cond =3D cond_make_0_tmp(TCG_COND_EQ, tmp); @@ -1078,7 +975,7 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCG= v_reg res, { DisasCond cond; TCGv_reg tmp, cb =3D NULL; - target_ureg d_repl =3D d ? 0x0000000100000001ull : 1; + uint64_t d_repl =3D d ? 0x0000000100000001ull : 1; =20 if (cf & 8) { /* Since we want to test lots of carry-out bits all at once, do not @@ -1509,7 +1406,7 @@ static TCGv_i64 space_select(DisasContext *ctx, int s= p, TCGv_reg base) #endif =20 static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, - unsigned rb, unsigned rx, int scale, target_sreg disp, + unsigned rb, unsigned rx, int scale, int64_t disp, unsigned sp, int modify, bool is_phys) { TCGv_reg base =3D load_gpr(ctx, rb); @@ -1545,7 +1442,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva= , TCGv_reg *pofs, * =3D 0 for no base register update. */ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, - unsigned rx, int scale, target_sreg disp, + unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { TCGv_reg ofs; @@ -1563,7 +1460,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 de= st, unsigned rb, } =20 static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, - unsigned rx, int scale, target_sreg disp, + unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { TCGv_reg ofs; @@ -1581,7 +1478,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 de= st, unsigned rb, } =20 static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, - unsigned rx, int scale, target_sreg disp, + unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { TCGv_reg ofs; @@ -1599,7 +1496,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 s= rc, unsigned rb, } =20 static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, - unsigned rx, int scale, target_sreg disp, + unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { TCGv_reg ofs; @@ -1616,16 +1513,11 @@ static void do_store_64(DisasContext *ctx, TCGv_i64= src, unsigned rb, } } =20 -#if TARGET_REGISTER_BITS =3D=3D 64 #define do_load_reg do_load_64 #define do_store_reg do_store_64 -#else -#define do_load_reg do_load_32 -#define do_store_reg do_store_32 -#endif =20 static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_sreg disp, + unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { TCGv_reg dest; @@ -1646,7 +1538,7 @@ static bool do_load(DisasContext *ctx, unsigned rt, u= nsigned rb, } =20 static bool do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_sreg disp, + unsigned rx, int scale, int64_t disp, unsigned sp, int modify) { TCGv_i32 tmp; @@ -1671,7 +1563,7 @@ static bool trans_fldw(DisasContext *ctx, arg_ldst *a) } =20 static bool do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_sreg disp, + unsigned rx, int scale, int64_t disp, unsigned sp, int modify) { TCGv_i64 tmp; @@ -1696,7 +1588,7 @@ static bool trans_fldd(DisasContext *ctx, arg_ldst *a) } =20 static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb, - target_sreg disp, unsigned sp, + int64_t disp, unsigned sp, int modify, MemOp mop) { nullify_over(ctx); @@ -1705,7 +1597,7 @@ static bool do_store(DisasContext *ctx, unsigned rt, = unsigned rb, } =20 static bool do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_sreg disp, + unsigned rx, int scale, int64_t disp, unsigned sp, int modify) { TCGv_i32 tmp; @@ -1725,7 +1617,7 @@ static bool trans_fstw(DisasContext *ctx, arg_ldst *a) } =20 static bool do_fstored(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_sreg disp, + unsigned rx, int scale, int64_t disp, unsigned sp, int modify) { TCGv_i64 tmp; @@ -1838,7 +1730,7 @@ static bool do_fop_dedd(DisasContext *ctx, unsigned r= t, =20 /* Emit an unconditional branch to a direct target, which may or may not have already had nullification handled. */ -static bool do_dbranch(DisasContext *ctx, target_ureg dest, +static bool do_dbranch(DisasContext *ctx, uint64_t dest, unsigned link, bool is_n) { if (ctx->null_cond.c =3D=3D TCG_COND_NEVER && ctx->null_lab =3D=3D NUL= L) { @@ -1875,10 +1767,10 @@ static bool do_dbranch(DisasContext *ctx, target_ur= eg dest, =20 /* Emit a conditional branch to a direct target. If the branch itself is nullified, we should have already used nullify_over. */ -static bool do_cbranch(DisasContext *ctx, target_sreg disp, bool is_n, +static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, DisasCond *cond) { - target_ureg dest =3D iaoq_dest(ctx, disp); + uint64_t dest =3D iaoq_dest(ctx, disp); TCGLabel *taken =3D NULL; TCGCond c =3D cond->c; bool n; @@ -2839,7 +2731,7 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a= , bool is_i) if (!is_i) { tcg_gen_not_reg(tmp, tmp); } - tcg_gen_andi_reg(tmp, tmp, (target_ureg)0x1111111111111111ull); + tcg_gen_andi_reg(tmp, tmp, (uint64_t)0x1111111111111111ull); tcg_gen_muli_reg(tmp, tmp, 6); do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, a->d, false, is_i ? tcg_gen_add_reg : tcg_gen_sub_reg); @@ -2961,22 +2853,20 @@ static bool trans_cmpiclr(DisasContext *ctx, arg_rr= i_cf_d *a) =20 static bool trans_ld(DisasContext *ctx, arg_ldst *a) { - if (unlikely(TARGET_REGISTER_BITS =3D=3D 32 && a->size > MO_32)) { + if (!ctx->is_pa20 && a->size > MO_32) { return gen_illegal(ctx); - } else { - return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0, - a->disp, a->sp, a->m, a->size | MO_TE); } + return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0, + a->disp, a->sp, a->m, a->size | MO_TE); } =20 static bool trans_st(DisasContext *ctx, arg_ldst *a) { assert(a->x =3D=3D 0 && a->scale =3D=3D 0); - if (unlikely(TARGET_REGISTER_BITS =3D=3D 32 && a->size > MO_32)) { + if (!ctx->is_pa20 && a->size > MO_32) { return gen_illegal(ctx); - } else { - return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | M= O_TE); } + return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE= ); } =20 static bool trans_ldc(DisasContext *ctx, arg_ldst *a) @@ -2985,7 +2875,7 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) TCGv_reg zero, dest, ofs; TCGv_tl addr; =20 - if (unlikely(TARGET_REGISTER_BITS =3D=3D 32 && a->size > MO_32)) { + if (!ctx->is_pa20 && a->size > MO_32) { return gen_illegal(ctx); } =20 @@ -3394,7 +3284,7 @@ static bool trans_shrp_imm(DisasContext *ctx, arg_shr= p_imm *a) t2 =3D load_gpr(ctx, a->r2); if (a->r1 =3D=3D 0) { tcg_gen_extract_reg(dest, t2, sa, width - sa); - } else if (width =3D=3D TARGET_REGISTER_BITS) { + } else if (width =3D=3D TARGET_LONG_BITS) { tcg_gen_extract2_reg(dest, t2, cpu_gr[a->r1], sa); } else { assert(!a->d); @@ -3496,7 +3386,7 @@ static bool trans_extr_imm(DisasContext *ctx, arg_ext= r_imm *a) static bool trans_depi_imm(DisasContext *ctx, arg_depi_imm *a) { unsigned len, width; - target_sreg mask0, mask1; + uint64_t mask0, mask1; TCGv_reg dest; =20 if (!ctx->is_pa20 && a->d) { @@ -3575,7 +3465,7 @@ static bool do_dep_sar(DisasContext *ctx, unsigned rt= , unsigned c, unsigned rs =3D nz ? rt : 0; unsigned widthm1 =3D d ? 63 : 31; TCGv_reg mask, tmp, shift, dest; - target_ureg msb =3D 1ULL << (len - 1); + uint64_t msb =3D 1ULL << (len - 1); =20 dest =3D dest_gpr(ctx, rt); shift =3D tcg_temp_new(); @@ -3691,7 +3581,7 @@ static bool trans_bl(DisasContext *ctx, arg_bl *a) =20 static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) { - target_ureg dest =3D iaoq_dest(ctx, a->disp); + uint64_t dest =3D iaoq_dest(ctx, a->disp); =20 nullify_over(ctx); =20 @@ -3819,7 +3709,7 @@ static bool trans_fid_f(DisasContext *ctx, arg_fid_f = *a) { uint64_t ret; =20 - if (TARGET_REGISTER_BITS =3D=3D 64) { + if (ctx->is_pa20) { ret =3D 0x13080000000000ULL; /* PA8700 (PCX-W2) */ } else { ret =3D 0x0f080000000000ULL; /* PA7300LC (PCX-L2) */ --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835080; cv=none; d=zohomail.com; s=zohoarc; b=BK+H6Sjltlu3C3U/wC7Swg9fvW/4pdWBGev2jK0+TtwuWJTfBl+3WEmmoveRe6AzhgSMHLWlrFFl8yZzyFfXz8u4X6K63kWBp1fAO00sneIbooxf08VqrrqWtKWYTsNTeikdEcblajMFaS6K4qNme5+OQs2s1RBpe6dTGjF6fPE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697835080; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7bkVAzjRQljffeKZVdpz1fr9I9jbCd/N9DGSdds6v4Y=; b=bp9ZtF2LKioD200oFM3d/3rNmYauK2Zl269s03hg9fC9vfqyx5gxNzD2i7w7fAuE3ciBT4eJgE7E/inf8J3gJbftQKKmedNt5iYj9C8+a0cGKjj6Lb+TyNp/jiQMzZM5nxeeY0yflhxYJ/qsyq2KanvqHW1WHs1N/3DHwRswpOU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697835080536633.6113831302717; Fri, 20 Oct 2023 13:51:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwOy-0001ws-Ln; Fri, 20 Oct 2023 16:47:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwOw-0001pV-JQ for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:47:22 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwOs-0001BJ-20 for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:47:22 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-6b709048f32so1138100b3a.0 for ; Fri, 20 Oct 2023 13:47:17 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson --- target/hppa/translate.c | 914 ++++++++++++++++++---------------------- 1 file changed, 408 insertions(+), 506 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 96082d1a9c..1a57ccc49b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -36,110 +36,15 @@ /* Since we have a distinction between register size and address size, we need to redefine all of these. */ =20 -#undef TCGv -#undef tcg_temp_new -#undef tcg_global_mem_new - -#define TCGv_tl TCGv_i64 -#define tcg_temp_new_tl tcg_temp_new_i64 #define tcg_gen_extu_reg_tl tcg_gen_mov_i64 - -#define TCGv_reg TCGv_i64 - -#define tcg_temp_new tcg_temp_new_i64 -#define tcg_global_mem_new tcg_global_mem_new_i64 - -#define tcg_gen_movi_reg tcg_gen_movi_i64 -#define tcg_gen_mov_reg tcg_gen_mov_i64 -#define tcg_gen_ld8u_reg tcg_gen_ld8u_i64 -#define tcg_gen_ld8s_reg tcg_gen_ld8s_i64 -#define tcg_gen_ld16u_reg tcg_gen_ld16u_i64 -#define tcg_gen_ld16s_reg tcg_gen_ld16s_i64 -#define tcg_gen_ld32u_reg tcg_gen_ld32u_i64 -#define tcg_gen_ld32s_reg tcg_gen_ld32s_i64 -#define tcg_gen_ld_reg tcg_gen_ld_i64 -#define tcg_gen_st8_reg tcg_gen_st8_i64 -#define tcg_gen_st16_reg tcg_gen_st16_i64 -#define tcg_gen_st32_reg tcg_gen_st32_i64 -#define tcg_gen_st_reg tcg_gen_st_i64 -#define tcg_gen_add_reg tcg_gen_add_i64 -#define tcg_gen_addi_reg tcg_gen_addi_i64 -#define tcg_gen_sub_reg tcg_gen_sub_i64 -#define tcg_gen_neg_reg tcg_gen_neg_i64 -#define tcg_gen_subfi_reg tcg_gen_subfi_i64 -#define tcg_gen_subi_reg tcg_gen_subi_i64 -#define tcg_gen_and_reg tcg_gen_and_i64 -#define tcg_gen_andi_reg tcg_gen_andi_i64 -#define tcg_gen_or_reg tcg_gen_or_i64 -#define tcg_gen_ori_reg tcg_gen_ori_i64 -#define tcg_gen_xor_reg tcg_gen_xor_i64 -#define tcg_gen_xori_reg tcg_gen_xori_i64 -#define tcg_gen_not_reg tcg_gen_not_i64 -#define tcg_gen_shl_reg tcg_gen_shl_i64 -#define tcg_gen_shli_reg tcg_gen_shli_i64 -#define tcg_gen_shr_reg tcg_gen_shr_i64 -#define tcg_gen_shri_reg tcg_gen_shri_i64 -#define tcg_gen_sar_reg tcg_gen_sar_i64 -#define tcg_gen_sari_reg tcg_gen_sari_i64 -#define tcg_gen_brcond_reg tcg_gen_brcond_i64 -#define tcg_gen_brcondi_reg tcg_gen_brcondi_i64 -#define tcg_gen_setcond_reg tcg_gen_setcond_i64 -#define tcg_gen_setcondi_reg tcg_gen_setcondi_i64 -#define tcg_gen_mul_reg tcg_gen_mul_i64 -#define tcg_gen_muli_reg tcg_gen_muli_i64 -#define tcg_gen_div_reg tcg_gen_div_i64 -#define tcg_gen_rem_reg tcg_gen_rem_i64 -#define tcg_gen_divu_reg tcg_gen_divu_i64 -#define tcg_gen_remu_reg tcg_gen_remu_i64 -#define tcg_gen_discard_reg tcg_gen_discard_i64 -#define tcg_gen_trunc_reg_i32 tcg_gen_extrl_i64_i32 #define tcg_gen_trunc_i64_reg tcg_gen_mov_i64 -#define tcg_gen_extu_i32_reg tcg_gen_extu_i32_i64 -#define tcg_gen_ext_i32_reg tcg_gen_ext_i32_i64 #define tcg_gen_extu_reg_i64 tcg_gen_mov_i64 #define tcg_gen_ext_reg_i64 tcg_gen_mov_i64 -#define tcg_gen_ext8u_reg tcg_gen_ext8u_i64 -#define tcg_gen_ext8s_reg tcg_gen_ext8s_i64 -#define tcg_gen_ext16u_reg tcg_gen_ext16u_i64 -#define tcg_gen_ext16s_reg tcg_gen_ext16s_i64 -#define tcg_gen_ext32u_reg tcg_gen_ext32u_i64 -#define tcg_gen_ext32s_reg tcg_gen_ext32s_i64 -#define tcg_gen_bswap16_reg tcg_gen_bswap16_i64 -#define tcg_gen_bswap32_reg tcg_gen_bswap32_i64 -#define tcg_gen_bswap64_reg tcg_gen_bswap64_i64 -#define tcg_gen_concat_reg_i64 tcg_gen_concat32_i64 -#define tcg_gen_andc_reg tcg_gen_andc_i64 -#define tcg_gen_eqv_reg tcg_gen_eqv_i64 -#define tcg_gen_nand_reg tcg_gen_nand_i64 -#define tcg_gen_nor_reg tcg_gen_nor_i64 -#define tcg_gen_orc_reg tcg_gen_orc_i64 -#define tcg_gen_clz_reg tcg_gen_clz_i64 -#define tcg_gen_ctz_reg tcg_gen_ctz_i64 -#define tcg_gen_clzi_reg tcg_gen_clzi_i64 -#define tcg_gen_ctzi_reg tcg_gen_ctzi_i64 -#define tcg_gen_clrsb_reg tcg_gen_clrsb_i64 -#define tcg_gen_ctpop_reg tcg_gen_ctpop_i64 -#define tcg_gen_rotl_reg tcg_gen_rotl_i64 -#define tcg_gen_rotli_reg tcg_gen_rotli_i64 -#define tcg_gen_rotr_reg tcg_gen_rotr_i64 -#define tcg_gen_rotri_reg tcg_gen_rotri_i64 -#define tcg_gen_deposit_reg tcg_gen_deposit_i64 -#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64 -#define tcg_gen_extract_reg tcg_gen_extract_i64 -#define tcg_gen_sextract_reg tcg_gen_sextract_i64 -#define tcg_gen_extract2_reg tcg_gen_extract2_i64 -#define tcg_constant_reg tcg_constant_i64 -#define tcg_gen_movcond_reg tcg_gen_movcond_i64 -#define tcg_gen_add2_reg tcg_gen_add2_i64 -#define tcg_gen_sub2_reg tcg_gen_sub2_i64 -#define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i64 -#define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64 -#define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64 -#define tcg_gen_trunc_reg_ptr tcg_gen_trunc_i64_ptr + =20 typedef struct DisasCond { TCGCond c; - TCGv_reg a0, a1; + TCGv_i64 a0, a1; } DisasCond; =20 typedef struct DisasContext { @@ -149,7 +54,7 @@ typedef struct DisasContext { uint64_t iaoq_f; uint64_t iaoq_b; uint64_t iaoq_n; - TCGv_reg iaoq_n_var; + TCGv_i64 iaoq_n_var; =20 DisasCond null_cond; TCGLabel *null_lab; @@ -261,24 +166,24 @@ static int cmpbid_c(DisasContext *ctx, int val) #define DISAS_EXIT DISAS_TARGET_3 =20 /* global register indexes */ -static TCGv_reg cpu_gr[32]; +static TCGv_i64 cpu_gr[32]; static TCGv_i64 cpu_sr[4]; static TCGv_i64 cpu_srH; -static TCGv_reg cpu_iaoq_f; -static TCGv_reg cpu_iaoq_b; +static TCGv_i64 cpu_iaoq_f; +static TCGv_i64 cpu_iaoq_b; static TCGv_i64 cpu_iasq_f; static TCGv_i64 cpu_iasq_b; -static TCGv_reg cpu_sar; -static TCGv_reg cpu_psw_n; -static TCGv_reg cpu_psw_v; -static TCGv_reg cpu_psw_cb; -static TCGv_reg cpu_psw_cb_msb; +static TCGv_i64 cpu_sar; +static TCGv_i64 cpu_psw_n; +static TCGv_i64 cpu_psw_v; +static TCGv_i64 cpu_psw_cb; +static TCGv_i64 cpu_psw_cb_msb; =20 void hppa_translate_init(void) { #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) } =20 - typedef struct { TCGv_reg *var; const char *name; int ofs; } GlobalVar; + typedef struct { TCGv_i64 *var; const char *name; int ofs; } GlobalVar; static const GlobalVar vars[] =3D { { &cpu_sar, "sar", offsetof(CPUHPPAState, cr[CR_SAR]) }, DEF_VAR(psw_n), @@ -356,35 +261,35 @@ static DisasCond cond_make_n(void) return (DisasCond){ .c =3D TCG_COND_NE, .a0 =3D cpu_psw_n, - .a1 =3D tcg_constant_reg(0) + .a1 =3D tcg_constant_i64(0) }; } =20 -static DisasCond cond_make_tmp(TCGCond c, TCGv_reg a0, TCGv_reg a1) +static DisasCond cond_make_tmp(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) { assert (c !=3D TCG_COND_NEVER && c !=3D TCG_COND_ALWAYS); return (DisasCond){ .c =3D c, .a0 =3D a0, .a1 =3D a1 }; } =20 -static DisasCond cond_make_0_tmp(TCGCond c, TCGv_reg a0) +static DisasCond cond_make_0_tmp(TCGCond c, TCGv_i64 a0) { - return cond_make_tmp(c, a0, tcg_constant_reg(0)); + return cond_make_tmp(c, a0, tcg_constant_i64(0)); } =20 -static DisasCond cond_make_0(TCGCond c, TCGv_reg a0) +static DisasCond cond_make_0(TCGCond c, TCGv_i64 a0) { - TCGv_reg tmp =3D tcg_temp_new(); - tcg_gen_mov_reg(tmp, a0); + TCGv_i64 tmp =3D tcg_temp_new(); + tcg_gen_mov_i64(tmp, a0); return cond_make_0_tmp(c, tmp); } =20 -static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1) +static DisasCond cond_make(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) { - TCGv_reg t0 =3D tcg_temp_new(); - TCGv_reg t1 =3D tcg_temp_new(); + TCGv_i64 t0 =3D tcg_temp_new(); + TCGv_i64 t1 =3D tcg_temp_new(); =20 - tcg_gen_mov_reg(t0, a0); - tcg_gen_mov_reg(t1, a1); + tcg_gen_mov_i64(t0, a0); + tcg_gen_mov_i64(t1, a1); return cond_make_tmp(c, t0, t1); } =20 @@ -403,18 +308,18 @@ static void cond_free(DisasCond *cond) } } =20 -static TCGv_reg load_gpr(DisasContext *ctx, unsigned reg) +static TCGv_i64 load_gpr(DisasContext *ctx, unsigned reg) { if (reg =3D=3D 0) { - TCGv_reg t =3D tcg_temp_new(); - tcg_gen_movi_reg(t, 0); + TCGv_i64 t =3D tcg_temp_new(); + tcg_gen_movi_i64(t, 0); return t; } else { return cpu_gr[reg]; } } =20 -static TCGv_reg dest_gpr(DisasContext *ctx, unsigned reg) +static TCGv_i64 dest_gpr(DisasContext *ctx, unsigned reg) { if (reg =3D=3D 0 || ctx->null_cond.c !=3D TCG_COND_NEVER) { return tcg_temp_new(); @@ -423,17 +328,17 @@ static TCGv_reg dest_gpr(DisasContext *ctx, unsigned = reg) } } =20 -static void save_or_nullify(DisasContext *ctx, TCGv_reg dest, TCGv_reg t) +static void save_or_nullify(DisasContext *ctx, TCGv_i64 dest, TCGv_i64 t) { if (ctx->null_cond.c !=3D TCG_COND_NEVER) { - tcg_gen_movcond_reg(ctx->null_cond.c, dest, ctx->null_cond.a0, + tcg_gen_movcond_i64(ctx->null_cond.c, dest, ctx->null_cond.a0, ctx->null_cond.a1, dest, t); } else { - tcg_gen_mov_reg(dest, t); + tcg_gen_mov_i64(dest, t); } } =20 -static void save_gpr(DisasContext *ctx, unsigned reg, TCGv_reg t) +static void save_gpr(DisasContext *ctx, unsigned reg, TCGv_i64 t) { if (reg !=3D 0) { save_or_nullify(ctx, cpu_gr[reg], t); @@ -542,17 +447,17 @@ static void nullify_over(DisasContext *ctx) /* If we're using PSW[N], copy it to a temp because... */ if (ctx->null_cond.a0 =3D=3D cpu_psw_n) { ctx->null_cond.a0 =3D tcg_temp_new(); - tcg_gen_mov_reg(ctx->null_cond.a0, cpu_psw_n); + tcg_gen_mov_i64(ctx->null_cond.a0, cpu_psw_n); } /* ... we clear it before branching over the implementation, so that (1) it's clear after nullifying this insn and (2) if this insn nullifies the next, PSW[N] is valid. */ if (ctx->psw_n_nonzero) { ctx->psw_n_nonzero =3D false; - tcg_gen_movi_reg(cpu_psw_n, 0); + tcg_gen_movi_i64(cpu_psw_n, 0); } =20 - tcg_gen_brcond_reg(ctx->null_cond.c, ctx->null_cond.a0, + tcg_gen_brcond_i64(ctx->null_cond.c, ctx->null_cond.a0, ctx->null_cond.a1, ctx->null_lab); cond_free(&ctx->null_cond); } @@ -563,12 +468,12 @@ static void nullify_save(DisasContext *ctx) { if (ctx->null_cond.c =3D=3D TCG_COND_NEVER) { if (ctx->psw_n_nonzero) { - tcg_gen_movi_reg(cpu_psw_n, 0); + tcg_gen_movi_i64(cpu_psw_n, 0); } return; } if (ctx->null_cond.a0 !=3D cpu_psw_n) { - tcg_gen_setcond_reg(ctx->null_cond.c, cpu_psw_n, + tcg_gen_setcond_i64(ctx->null_cond.c, cpu_psw_n, ctx->null_cond.a0, ctx->null_cond.a1); ctx->psw_n_nonzero =3D true; } @@ -581,7 +486,7 @@ static void nullify_save(DisasContext *ctx) static void nullify_set(DisasContext *ctx, bool x) { if (ctx->psw_n_nonzero || x) { - tcg_gen_movi_reg(cpu_psw_n, x); + tcg_gen_movi_i64(cpu_psw_n, x); } } =20 @@ -624,12 +529,12 @@ static bool nullify_end(DisasContext *ctx) return true; } =20 -static void copy_iaoq_entry(TCGv_reg dest, uint64_t ival, TCGv_reg vval) +static void copy_iaoq_entry(TCGv_i64 dest, uint64_t ival, TCGv_i64 vval) { if (unlikely(ival =3D=3D -1)) { - tcg_gen_mov_reg(dest, vval); + tcg_gen_mov_i64(dest, vval); } else { - tcg_gen_movi_reg(dest, ival); + tcg_gen_movi_i64(dest, ival); } } =20 @@ -655,7 +560,7 @@ static void gen_excp(DisasContext *ctx, int exception) static bool gen_excp_iir(DisasContext *ctx, int exc) { nullify_over(ctx); - tcg_gen_st_reg(tcg_constant_reg(ctx->insn), + tcg_gen_st_i64(tcg_constant_i64(ctx->insn), tcg_env, offsetof(CPUHPPAState, cr[CR_IIR])); gen_excp(ctx, exc); return nullify_end(ctx); @@ -705,8 +610,8 @@ static void gen_goto_tb(DisasContext *ctx, int which, { if (f !=3D -1 && b !=3D -1 && use_goto_tb(ctx, f)) { tcg_gen_goto_tb(which); - tcg_gen_movi_reg(cpu_iaoq_f, f); - tcg_gen_movi_reg(cpu_iaoq_b, b); + tcg_gen_movi_i64(cpu_iaoq_f, f); + tcg_gen_movi_i64(cpu_iaoq_b, b); tcg_gen_exit_tb(ctx->base.tb, which); } else { copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b); @@ -725,7 +630,7 @@ static bool cond_need_cb(int c) return c =3D=3D 4 || c =3D=3D 5; } =20 -/* Need extensions from TCGv_i32 to TCGv_reg. */ +/* Need extensions from TCGv_i32 to TCGv_i64. */ static bool cond_need_ext(DisasContext *ctx, bool d) { return !(ctx->is_pa20 && d); @@ -737,10 +642,10 @@ static bool cond_need_ext(DisasContext *ctx, bool d) */ =20 static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, - TCGv_reg res, TCGv_reg cb_msb, TCGv_reg sv) + TCGv_i64 res, TCGv_i64 cb_msb, TCGv_i64 sv) { DisasCond cond; - TCGv_reg tmp; + TCGv_i64 tmp; =20 switch (cf >> 1) { case 0: /* Never / TR (0 / 1) */ @@ -749,16 +654,16 @@ static DisasCond do_cond(DisasContext *ctx, unsigned = cf, bool d, case 1: /* =3D / <> (Z / !Z) */ if (cond_need_ext(ctx, d)) { tmp =3D tcg_temp_new(); - tcg_gen_ext32u_reg(tmp, res); + tcg_gen_ext32u_i64(tmp, res); res =3D tmp; } cond =3D cond_make_0(TCG_COND_EQ, res); break; case 2: /* < / >=3D (N ^ V / !(N ^ V) */ tmp =3D tcg_temp_new(); - tcg_gen_xor_reg(tmp, res, sv); + tcg_gen_xor_i64(tmp, res, sv); if (cond_need_ext(ctx, d)) { - tcg_gen_ext32s_reg(tmp, tmp); + tcg_gen_ext32s_i64(tmp, tmp); } cond =3D cond_make_0_tmp(TCG_COND_LT, tmp); break; @@ -773,14 +678,14 @@ static DisasCond do_cond(DisasContext *ctx, unsigned = cf, bool d, * !(~(res ^ sv) >> 31 & res) */ tmp =3D tcg_temp_new(); - tcg_gen_eqv_reg(tmp, res, sv); + tcg_gen_eqv_i64(tmp, res, sv); if (cond_need_ext(ctx, d)) { - tcg_gen_sextract_reg(tmp, tmp, 31, 1); - tcg_gen_and_reg(tmp, tmp, res); - tcg_gen_ext32u_reg(tmp, tmp); + tcg_gen_sextract_i64(tmp, tmp, 31, 1); + tcg_gen_and_i64(tmp, tmp, res); + tcg_gen_ext32u_i64(tmp, tmp); } else { - tcg_gen_sari_reg(tmp, tmp, 63); - tcg_gen_and_reg(tmp, tmp, res); + tcg_gen_sari_i64(tmp, tmp, 63); + tcg_gen_and_i64(tmp, tmp, res); } cond =3D cond_make_0_tmp(TCG_COND_EQ, tmp); break; @@ -790,24 +695,24 @@ static DisasCond do_cond(DisasContext *ctx, unsigned = cf, bool d, break; case 5: /* ZNV / VNZ (!C | Z / C & !Z) */ tmp =3D tcg_temp_new(); - tcg_gen_neg_reg(tmp, cb_msb); - tcg_gen_and_reg(tmp, tmp, res); + tcg_gen_neg_i64(tmp, cb_msb); + tcg_gen_and_i64(tmp, tmp, res); if (cond_need_ext(ctx, d)) { - tcg_gen_ext32u_reg(tmp, tmp); + tcg_gen_ext32u_i64(tmp, tmp); } cond =3D cond_make_0_tmp(TCG_COND_EQ, tmp); break; case 6: /* SV / NSV (V / !V) */ if (cond_need_ext(ctx, d)) { tmp =3D tcg_temp_new(); - tcg_gen_ext32s_reg(tmp, sv); + tcg_gen_ext32s_i64(tmp, sv); sv =3D tmp; } cond =3D cond_make_0(TCG_COND_LT, sv); break; case 7: /* OD / EV */ tmp =3D tcg_temp_new(); - tcg_gen_andi_reg(tmp, res, 1); + tcg_gen_andi_i64(tmp, res, 1); cond =3D cond_make_0_tmp(TCG_COND_NE, tmp); break; default: @@ -825,8 +730,8 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf= , bool d, deleted as unused. */ =20 static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d, - TCGv_reg res, TCGv_reg in1, - TCGv_reg in2, TCGv_reg sv) + TCGv_i64 res, TCGv_i64 in1, + TCGv_i64 in2, TCGv_i64 sv) { TCGCond tc; bool ext_uns; @@ -860,15 +765,15 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsig= ned cf, bool d, tc =3D tcg_invert_cond(tc); } if (cond_need_ext(ctx, d)) { - TCGv_reg t1 =3D tcg_temp_new(); - TCGv_reg t2 =3D tcg_temp_new(); + TCGv_i64 t1 =3D tcg_temp_new(); + TCGv_i64 t2 =3D tcg_temp_new(); =20 if (ext_uns) { - tcg_gen_ext32u_reg(t1, in1); - tcg_gen_ext32u_reg(t2, in2); + tcg_gen_ext32u_i64(t1, in1); + tcg_gen_ext32u_i64(t2, in2); } else { - tcg_gen_ext32s_reg(t1, in1); - tcg_gen_ext32s_reg(t2, in2); + tcg_gen_ext32s_i64(t1, in1); + tcg_gen_ext32s_i64(t2, in2); } return cond_make_tmp(tc, t1, t2); } @@ -885,7 +790,7 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsigne= d cf, bool d, */ =20 static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d, - TCGv_reg res) + TCGv_i64 res) { TCGCond tc; bool ext_uns; @@ -937,12 +842,12 @@ static DisasCond do_log_cond(DisasContext *ctx, unsig= ned cf, bool d, } =20 if (cond_need_ext(ctx, d)) { - TCGv_reg tmp =3D tcg_temp_new(); + TCGv_i64 tmp =3D tcg_temp_new(); =20 if (ext_uns) { - tcg_gen_ext32u_reg(tmp, res); + tcg_gen_ext32u_i64(tmp, res); } else { - tcg_gen_ext32s_reg(tmp, res); + tcg_gen_ext32s_i64(tmp, res); } return cond_make_0_tmp(tc, tmp); } @@ -952,7 +857,7 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigne= d cf, bool d, /* Similar, but for shift/extract/deposit conditions. */ =20 static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, bool d, - TCGv_reg res) + TCGv_i64 res) { unsigned c, f; =20 @@ -970,11 +875,11 @@ static DisasCond do_sed_cond(DisasContext *ctx, unsig= ned orig, bool d, =20 /* Similar, but for unit conditions. */ =20 -static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_reg res, - TCGv_reg in1, TCGv_reg in2) +static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_i64 res, + TCGv_i64 in1, TCGv_i64 in2) { DisasCond cond; - TCGv_reg tmp, cb =3D NULL; + TCGv_i64 tmp, cb =3D NULL; uint64_t d_repl =3D d ? 0x0000000100000001ull : 1; =20 if (cf & 8) { @@ -984,10 +889,10 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TC= Gv_reg res, */ cb =3D tcg_temp_new(); tmp =3D tcg_temp_new(); - tcg_gen_or_reg(cb, in1, in2); - tcg_gen_and_reg(tmp, in1, in2); - tcg_gen_andc_reg(cb, cb, res); - tcg_gen_or_reg(cb, cb, tmp); + tcg_gen_or_i64(cb, in1, in2); + tcg_gen_and_i64(tmp, in1, in2); + tcg_gen_andc_i64(cb, cb, res); + tcg_gen_or_i64(cb, cb, tmp); } =20 switch (cf >> 1) { @@ -1002,32 +907,32 @@ static DisasCond do_unit_cond(unsigned cf, bool d, T= CGv_reg res, * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord */ tmp =3D tcg_temp_new(); - tcg_gen_subi_reg(tmp, res, d_repl * 0x01010101u); - tcg_gen_andc_reg(tmp, tmp, res); - tcg_gen_andi_reg(tmp, tmp, d_repl * 0x80808080u); + tcg_gen_subi_i64(tmp, res, d_repl * 0x01010101u); + tcg_gen_andc_i64(tmp, tmp, res); + tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80808080u); cond =3D cond_make_0(TCG_COND_NE, tmp); break; =20 case 3: /* SHZ / NHZ */ tmp =3D tcg_temp_new(); - tcg_gen_subi_reg(tmp, res, d_repl * 0x00010001u); - tcg_gen_andc_reg(tmp, tmp, res); - tcg_gen_andi_reg(tmp, tmp, d_repl * 0x80008000u); + tcg_gen_subi_i64(tmp, res, d_repl * 0x00010001u); + tcg_gen_andc_i64(tmp, tmp, res); + tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80008000u); cond =3D cond_make_0(TCG_COND_NE, tmp); break; =20 case 4: /* SDC / NDC */ - tcg_gen_andi_reg(cb, cb, d_repl * 0x88888888u); + tcg_gen_andi_i64(cb, cb, d_repl * 0x88888888u); cond =3D cond_make_0(TCG_COND_NE, cb); break; =20 case 6: /* SBC / NBC */ - tcg_gen_andi_reg(cb, cb, d_repl * 0x80808080u); + tcg_gen_andi_i64(cb, cb, d_repl * 0x80808080u); cond =3D cond_make_0(TCG_COND_NE, cb); break; =20 case 7: /* SHC / NHC */ - tcg_gen_andi_reg(cb, cb, d_repl * 0x80008000u); + tcg_gen_andi_i64(cb, cb, d_repl * 0x80008000u); cond =3D cond_make_0(TCG_COND_NE, cb); break; =20 @@ -1041,55 +946,55 @@ static DisasCond do_unit_cond(unsigned cf, bool d, T= CGv_reg res, return cond; } =20 -static TCGv_reg get_carry(DisasContext *ctx, bool d, - TCGv_reg cb, TCGv_reg cb_msb) +static TCGv_i64 get_carry(DisasContext *ctx, bool d, + TCGv_i64 cb, TCGv_i64 cb_msb) { if (cond_need_ext(ctx, d)) { - TCGv_reg t =3D tcg_temp_new(); - tcg_gen_extract_reg(t, cb, 32, 1); + TCGv_i64 t =3D tcg_temp_new(); + tcg_gen_extract_i64(t, cb, 32, 1); return t; } return cb_msb; } =20 -static TCGv_reg get_psw_carry(DisasContext *ctx, bool d) +static TCGv_i64 get_psw_carry(DisasContext *ctx, bool d) { return get_carry(ctx, d, cpu_psw_cb, cpu_psw_cb_msb); } =20 /* Compute signed overflow for addition. */ -static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res, - TCGv_reg in1, TCGv_reg in2) +static TCGv_i64 do_add_sv(DisasContext *ctx, TCGv_i64 res, + TCGv_i64 in1, TCGv_i64 in2) { - TCGv_reg sv =3D tcg_temp_new(); - TCGv_reg tmp =3D tcg_temp_new(); + TCGv_i64 sv =3D tcg_temp_new(); + TCGv_i64 tmp =3D tcg_temp_new(); =20 - tcg_gen_xor_reg(sv, res, in1); - tcg_gen_xor_reg(tmp, in1, in2); - tcg_gen_andc_reg(sv, sv, tmp); + tcg_gen_xor_i64(sv, res, in1); + tcg_gen_xor_i64(tmp, in1, in2); + tcg_gen_andc_i64(sv, sv, tmp); =20 return sv; } =20 /* Compute signed overflow for subtraction. */ -static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_reg res, - TCGv_reg in1, TCGv_reg in2) +static TCGv_i64 do_sub_sv(DisasContext *ctx, TCGv_i64 res, + TCGv_i64 in1, TCGv_i64 in2) { - TCGv_reg sv =3D tcg_temp_new(); - TCGv_reg tmp =3D tcg_temp_new(); + TCGv_i64 sv =3D tcg_temp_new(); + TCGv_i64 tmp =3D tcg_temp_new(); =20 - tcg_gen_xor_reg(sv, res, in1); - tcg_gen_xor_reg(tmp, in1, in2); - tcg_gen_and_reg(sv, sv, tmp); + tcg_gen_xor_i64(sv, res, in1); + tcg_gen_xor_i64(tmp, in1, in2); + tcg_gen_and_i64(sv, sv, tmp); =20 return sv; } =20 -static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, unsigned shift, bool is_l, +static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 in1, + TCGv_i64 in2, unsigned shift, bool is_l, bool is_tsv, bool is_tc, bool is_c, unsigned cf, bool d) { - TCGv_reg dest, cb, cb_msb, cb_cond, sv, tmp; + TCGv_i64 dest, cb, cb_msb, cb_cond, sv, tmp; unsigned c =3D cf >> 1; DisasCond cond; =20 @@ -1100,29 +1005,29 @@ static void do_add(DisasContext *ctx, unsigned rt, = TCGv_reg in1, =20 if (shift) { tmp =3D tcg_temp_new(); - tcg_gen_shli_reg(tmp, in1, shift); + tcg_gen_shli_i64(tmp, in1, shift); in1 =3D tmp; } =20 if (!is_l || cond_need_cb(c)) { - TCGv_reg zero =3D tcg_constant_reg(0); + TCGv_i64 zero =3D tcg_constant_i64(0); cb_msb =3D tcg_temp_new(); cb =3D tcg_temp_new(); =20 - tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero); + tcg_gen_add2_i64(dest, cb_msb, in1, zero, in2, zero); if (is_c) { - tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, + tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb, get_psw_carry(ctx, d), zero); } - tcg_gen_xor_reg(cb, in1, in2); - tcg_gen_xor_reg(cb, cb, dest); + tcg_gen_xor_i64(cb, in1, in2); + tcg_gen_xor_i64(cb, cb, dest); if (cond_need_cb(c)) { cb_cond =3D get_carry(ctx, d, cb, cb_msb); } } else { - tcg_gen_add_reg(dest, in1, in2); + tcg_gen_add_i64(dest, in1, in2); if (is_c) { - tcg_gen_add_reg(dest, dest, get_psw_carry(ctx, d)); + tcg_gen_add_i64(dest, dest, get_psw_carry(ctx, d)); } } =20 @@ -1140,7 +1045,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, cond =3D do_cond(ctx, cf, d, dest, cb_cond, sv); if (is_tc) { tmp =3D tcg_temp_new(); - tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); + tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(tcg_env, tmp); } =20 @@ -1159,7 +1064,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_d_sh *a, bool is_l, bool is_tsv, bool is_tc, bool is_c) { - TCGv_reg tcg_r1, tcg_r2; + TCGv_i64 tcg_r1, tcg_r2; =20 if (a->cf) { nullify_over(ctx); @@ -1174,23 +1079,23 @@ static bool do_add_reg(DisasContext *ctx, arg_rrr_c= f_d_sh *a, static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a, bool is_tsv, bool is_tc) { - TCGv_reg tcg_im, tcg_r2; + TCGv_i64 tcg_im, tcg_r2; =20 if (a->cf) { nullify_over(ctx); } - tcg_im =3D tcg_constant_reg(a->i); + tcg_im =3D tcg_constant_i64(a->i); tcg_r2 =3D load_gpr(ctx, a->r); /* All ADDI conditions are 32-bit. */ do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf, false= ); return nullify_end(ctx); } =20 -static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, bool is_tsv, bool is_b, +static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, + TCGv_i64 in2, bool is_tsv, bool is_b, bool is_tc, unsigned cf, bool d) { - TCGv_reg dest, sv, cb, cb_msb, zero, tmp; + TCGv_i64 dest, sv, cb, cb_msb, zero, tmp; unsigned c =3D cf >> 1; DisasCond cond; =20 @@ -1198,23 +1103,23 @@ static void do_sub(DisasContext *ctx, unsigned rt, = TCGv_reg in1, cb =3D tcg_temp_new(); cb_msb =3D tcg_temp_new(); =20 - zero =3D tcg_constant_reg(0); + zero =3D tcg_constant_i64(0); if (is_b) { /* DEST,C =3D IN1 + ~IN2 + C. */ - tcg_gen_not_reg(cb, in2); - tcg_gen_add2_reg(dest, cb_msb, in1, zero, get_psw_carry(ctx, d), z= ero); - tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cb, zero); - tcg_gen_xor_reg(cb, cb, in1); - tcg_gen_xor_reg(cb, cb, dest); + tcg_gen_not_i64(cb, in2); + tcg_gen_add2_i64(dest, cb_msb, in1, zero, get_psw_carry(ctx, d), z= ero); + tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb, cb, zero); + tcg_gen_xor_i64(cb, cb, in1); + tcg_gen_xor_i64(cb, cb, dest); } else { /* * DEST,C =3D IN1 + ~IN2 + 1. We can produce the same result in f= ewer * operations by seeding the high word with 1 and subtracting. */ - TCGv_reg one =3D tcg_constant_reg(1); - tcg_gen_sub2_reg(dest, cb_msb, in1, one, in2, zero); - tcg_gen_eqv_reg(cb, in1, in2); - tcg_gen_xor_reg(cb, cb, dest); + TCGv_i64 one =3D tcg_constant_i64(1); + tcg_gen_sub2_i64(dest, cb_msb, in1, one, in2, zero); + tcg_gen_eqv_i64(cb, in1, in2); + tcg_gen_xor_i64(cb, cb, dest); } =20 /* Compute signed overflow if required. */ @@ -1236,7 +1141,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, /* Emit any conditional trap before any writeback. */ if (is_tc) { tmp =3D tcg_temp_new(); - tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); + tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(tcg_env, tmp); } =20 @@ -1253,7 +1158,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tsv, bool is_b, bool is_tc) { - TCGv_reg tcg_r1, tcg_r2; + TCGv_i64 tcg_r1, tcg_r2; =20 if (a->cf) { nullify_over(ctx); @@ -1266,26 +1171,26 @@ static bool do_sub_reg(DisasContext *ctx, arg_rrr_c= f_d *a, =20 static bool do_sub_imm(DisasContext *ctx, arg_rri_cf *a, bool is_tsv) { - TCGv_reg tcg_im, tcg_r2; + TCGv_i64 tcg_im, tcg_r2; =20 if (a->cf) { nullify_over(ctx); } - tcg_im =3D tcg_constant_reg(a->i); + tcg_im =3D tcg_constant_i64(a->i); tcg_r2 =3D load_gpr(ctx, a->r); /* All SUBI conditions are 32-bit. */ do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf, false); return nullify_end(ctx); } =20 -static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, unsigned cf, bool d) +static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_i64 in1, + TCGv_i64 in2, unsigned cf, bool d) { - TCGv_reg dest, sv; + TCGv_i64 dest, sv; DisasCond cond; =20 dest =3D tcg_temp_new(); - tcg_gen_sub_reg(dest, in1, in2); + tcg_gen_sub_i64(dest, in1, in2); =20 /* Compute signed overflow if required. */ sv =3D NULL; @@ -1297,7 +1202,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt,= TCGv_reg in1, cond =3D do_sub_cond(ctx, cf, d, dest, in1, in2, sv); =20 /* Clear. */ - tcg_gen_movi_reg(dest, 0); + tcg_gen_movi_i64(dest, 0); save_gpr(ctx, rt, dest); =20 /* Install the new nullification. */ @@ -1305,11 +1210,11 @@ static void do_cmpclr(DisasContext *ctx, unsigned r= t, TCGv_reg in1, ctx->null_cond =3D cond; } =20 -static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, unsigned cf, bool d, - void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) +static void do_log(DisasContext *ctx, unsigned rt, TCGv_i64 in1, + TCGv_i64 in2, unsigned cf, bool d, + void (*fn)(TCGv_i64, TCGv_i64, TCGv_i64)) { - TCGv_reg dest =3D dest_gpr(ctx, rt); + TCGv_i64 dest =3D dest_gpr(ctx, rt); =20 /* Perform the operation, and writeback. */ fn(dest, in1, in2); @@ -1323,9 +1228,9 @@ static void do_log(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, } =20 static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a, - void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) + void (*fn)(TCGv_i64, TCGv_i64, TCGv_i64)) { - TCGv_reg tcg_r1, tcg_r2; + TCGv_i64 tcg_r1, tcg_r2; =20 if (a->cf) { nullify_over(ctx); @@ -1336,11 +1241,11 @@ static bool do_log_reg(DisasContext *ctx, arg_rrr_c= f_d *a, return nullify_end(ctx); } =20 -static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, unsigned cf, bool d, bool is_tc, - void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) +static void do_unit(DisasContext *ctx, unsigned rt, TCGv_i64 in1, + TCGv_i64 in2, unsigned cf, bool d, bool is_tc, + void (*fn)(TCGv_i64, TCGv_i64, TCGv_i64)) { - TCGv_reg dest; + TCGv_i64 dest; DisasCond cond; =20 if (cf =3D=3D 0) { @@ -1355,8 +1260,8 @@ static void do_unit(DisasContext *ctx, unsigned rt, T= CGv_reg in1, cond =3D do_unit_cond(cf, d, dest, in1, in2); =20 if (is_tc) { - TCGv_reg tmp =3D tcg_temp_new(); - tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); + TCGv_i64 tmp =3D tcg_temp_new(); + tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(tcg_env, tmp); } save_gpr(ctx, rt, dest); @@ -1371,17 +1276,17 @@ static void do_unit(DisasContext *ctx, unsigned rt,= TCGv_reg in1, from the top 2 bits of the base register. There are a few system instructions that have a 3-bit space specifier, for which SR0 is not special. To handle this, pass ~SP. */ -static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) +static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_i64 base) { TCGv_ptr ptr; - TCGv_reg tmp; + TCGv_i64 tmp; TCGv_i64 spc; =20 if (sp !=3D 0) { if (sp < 0) { sp =3D ~sp; } - spc =3D tcg_temp_new_tl(); + spc =3D tcg_temp_new_i64(); load_spr(ctx, spc, sp); return spc; } @@ -1391,12 +1296,12 @@ static TCGv_i64 space_select(DisasContext *ctx, int= sp, TCGv_reg base) =20 ptr =3D tcg_temp_new_ptr(); tmp =3D tcg_temp_new(); - spc =3D tcg_temp_new_tl(); + spc =3D tcg_temp_new_i64(); =20 /* Extract top 2 bits of the address, shift left 3 for uint64_t index.= */ - tcg_gen_shri_reg(tmp, base, (ctx->tb_flags & PSW_W ? 64 : 32) - 5); - tcg_gen_andi_reg(tmp, tmp, 030); - tcg_gen_trunc_reg_ptr(ptr, tmp); + tcg_gen_shri_i64(tmp, base, (ctx->tb_flags & PSW_W ? 64 : 32) - 5); + tcg_gen_andi_i64(tmp, tmp, 030); + tcg_gen_trunc_i64_ptr(ptr, tmp); =20 tcg_gen_add_ptr(ptr, ptr, tcg_env); tcg_gen_ld_i64(spc, ptr, offsetof(CPUHPPAState, sr[4])); @@ -1405,28 +1310,28 @@ static TCGv_i64 space_select(DisasContext *ctx, int= sp, TCGv_reg base) } #endif =20 -static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, +static void form_gva(DisasContext *ctx, TCGv_i64 *pgva, TCGv_i64 *pofs, unsigned rb, unsigned rx, int scale, int64_t disp, unsigned sp, int modify, bool is_phys) { - TCGv_reg base =3D load_gpr(ctx, rb); - TCGv_reg ofs; - TCGv_tl addr; + TCGv_i64 base =3D load_gpr(ctx, rb); + TCGv_i64 ofs; + TCGv_i64 addr; =20 /* Note that RX is mutually exclusive with DISP. */ if (rx) { ofs =3D tcg_temp_new(); - tcg_gen_shli_reg(ofs, cpu_gr[rx], scale); - tcg_gen_add_reg(ofs, ofs, base); + tcg_gen_shli_i64(ofs, cpu_gr[rx], scale); + tcg_gen_add_i64(ofs, ofs, base); } else if (disp || modify) { ofs =3D tcg_temp_new(); - tcg_gen_addi_reg(ofs, base, disp); + tcg_gen_addi_i64(ofs, base, disp); } else { ofs =3D base; } =20 *pofs =3D ofs; - *pgva =3D addr =3D tcg_temp_new_tl(); + *pgva =3D addr =3D tcg_temp_new_i64(); tcg_gen_extu_reg_tl(addr, modify <=3D 0 ? ofs : base); tcg_gen_andi_tl(addr, addr, gva_offset_mask(ctx)); #ifndef CONFIG_USER_ONLY @@ -1445,8 +1350,8 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 de= st, unsigned rb, unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { - TCGv_reg ofs; - TCGv_tl addr; + TCGv_i64 ofs; + TCGv_i64 addr; =20 /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); @@ -1463,8 +1368,8 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 de= st, unsigned rb, unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { - TCGv_reg ofs; - TCGv_tl addr; + TCGv_i64 ofs; + TCGv_i64 addr; =20 /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); @@ -1481,8 +1386,8 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 s= rc, unsigned rb, unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { - TCGv_reg ofs; - TCGv_tl addr; + TCGv_i64 ofs; + TCGv_i64 addr; =20 /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); @@ -1499,8 +1404,8 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 s= rc, unsigned rb, unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { - TCGv_reg ofs; - TCGv_tl addr; + TCGv_i64 ofs; + TCGv_i64 addr; =20 /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); @@ -1513,14 +1418,11 @@ static void do_store_64(DisasContext *ctx, TCGv_i64= src, unsigned rb, } } =20 -#define do_load_reg do_load_64 -#define do_store_reg do_store_64 - static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb, unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { - TCGv_reg dest; + TCGv_i64 dest; =20 nullify_over(ctx); =20 @@ -1531,7 +1433,7 @@ static bool do_load(DisasContext *ctx, unsigned rt, u= nsigned rb, /* Make sure if RT =3D=3D RB, we see the result of the load. */ dest =3D tcg_temp_new(); } - do_load_reg(ctx, dest, rb, rx, scale, disp, sp, modify, mop); + do_load_64(ctx, dest, rb, rx, scale, disp, sp, modify, mop); save_gpr(ctx, rt, dest); =20 return nullify_end(ctx); @@ -1592,7 +1494,7 @@ static bool do_store(DisasContext *ctx, unsigned rt, = unsigned rb, int modify, MemOp mop) { nullify_over(ctx); - do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop); + do_store_64(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop); return nullify_end(ctx); } =20 @@ -1786,7 +1688,7 @@ static bool do_cbranch(DisasContext *ctx, int64_t dis= p, bool is_n, } =20 taken =3D gen_new_label(); - tcg_gen_brcond_reg(c, cond->a0, cond->a1, taken); + tcg_gen_brcond_i64(c, cond->a0, cond->a1, taken); cond_free(cond); =20 /* Not taken: Condition not satisfied; nullify on backward branches. */ @@ -1803,7 +1705,7 @@ static bool do_cbranch(DisasContext *ctx, int64_t dis= p, bool is_n, if (ctx->iaoq_n =3D=3D -1) { /* The temporary iaoq_n_var died at the branch above. Regenerate it here instead of saving it. */ - tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); + tcg_gen_addi_i64(ctx->iaoq_n_var, cpu_iaoq_b, 4); } gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); } @@ -1833,10 +1735,10 @@ static bool do_cbranch(DisasContext *ctx, int64_t d= isp, bool is_n, =20 /* Emit an unconditional branch to an indirect target. This handles nullification of the branch itself. */ -static bool do_ibranch(DisasContext *ctx, TCGv_reg dest, +static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, unsigned link, bool is_n) { - TCGv_reg a0, a1, next, tmp; + TCGv_i64 a0, a1, next, tmp; TCGCond c; =20 assert(ctx->null_lab =3D=3D NULL); @@ -1846,11 +1748,11 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg = dest, copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); } next =3D tcg_temp_new(); - tcg_gen_mov_reg(next, dest); + tcg_gen_mov_i64(next, dest); if (is_n) { if (use_nullify_skip(ctx)) { - tcg_gen_mov_reg(cpu_iaoq_f, next); - tcg_gen_addi_reg(cpu_iaoq_b, next, 4); + tcg_gen_mov_i64(cpu_iaoq_f, next); + tcg_gen_addi_i64(cpu_iaoq_b, next, 4); nullify_set(ctx, 0); ctx->base.is_jmp =3D DISAS_IAQ_N_UPDATED; return true; @@ -1872,12 +1774,12 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg = dest, /* We do have to handle the non-local temporary, DEST, before branching. Since IOAQ_F is not really live at this point, we can simply store DEST optimistically. Similarly with IAOQ_B. = */ - tcg_gen_mov_reg(cpu_iaoq_f, dest); - tcg_gen_addi_reg(cpu_iaoq_b, dest, 4); + tcg_gen_mov_i64(cpu_iaoq_f, dest); + tcg_gen_addi_i64(cpu_iaoq_b, dest, 4); =20 nullify_over(ctx); if (link !=3D 0) { - tcg_gen_movi_reg(cpu_gr[link], ctx->iaoq_n); + tcg_gen_movi_i64(cpu_gr[link], ctx->iaoq_n); } tcg_gen_lookup_and_goto_ptr(); return nullify_end(ctx); @@ -1890,19 +1792,19 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg = dest, next =3D tcg_temp_new(); =20 copy_iaoq_entry(tmp, ctx->iaoq_n, ctx->iaoq_n_var); - tcg_gen_movcond_reg(c, next, a0, a1, tmp, dest); + tcg_gen_movcond_i64(c, next, a0, a1, tmp, dest); ctx->iaoq_n =3D -1; ctx->iaoq_n_var =3D next; =20 if (link !=3D 0) { - tcg_gen_movcond_reg(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp= ); + tcg_gen_movcond_i64(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp= ); } =20 if (is_n) { /* The branch nullifies the next insn, which means the state o= f N after the branch is the inverse of the state of N that appl= ied to the branch. */ - tcg_gen_setcond_reg(tcg_invert_cond(c), cpu_psw_n, a0, a1); + tcg_gen_setcond_i64(tcg_invert_cond(c), cpu_psw_n, a0, a1); cond_free(&ctx->null_cond); ctx->null_cond =3D cond_make_n(); ctx->psw_n_nonzero =3D true; @@ -1920,9 +1822,9 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg de= st, * IAOQ_Next{30..31} =E2=86=90 IAOQ_Front{30..31}; * which keeps the privilege level from being increased. */ -static TCGv_reg do_ibranch_priv(DisasContext *ctx, TCGv_reg offset) +static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset) { - TCGv_reg dest; + TCGv_i64 dest; switch (ctx->privilege) { case 0: /* Privilege 0 is maximum and is allowed to decrease. */ @@ -1930,13 +1832,13 @@ static TCGv_reg do_ibranch_priv(DisasContext *ctx, = TCGv_reg offset) case 3: /* Privilege 3 is minimum and is never allowed to increase. */ dest =3D tcg_temp_new(); - tcg_gen_ori_reg(dest, offset, 3); + tcg_gen_ori_i64(dest, offset, 3); break; default: dest =3D tcg_temp_new(); - tcg_gen_andi_reg(dest, offset, -4); - tcg_gen_ori_reg(dest, dest, ctx->privilege); - tcg_gen_movcond_reg(TCG_COND_GTU, dest, dest, offset, dest, offset= ); + tcg_gen_andi_i64(dest, offset, -4); + tcg_gen_ori_i64(dest, dest, ctx->privilege); + tcg_gen_movcond_i64(TCG_COND_GTU, dest, dest, offset, dest, offset= ); break; } return dest; @@ -1959,7 +1861,7 @@ static void do_page_zero(DisasContext *ctx) case TCG_COND_NEVER: break; case TCG_COND_ALWAYS: - tcg_gen_movi_reg(cpu_psw_n, 0); + tcg_gen_movi_i64(cpu_psw_n, 0); goto do_sigill; default: /* Since this is always the first (and only) insn within the @@ -1987,9 +1889,9 @@ static void do_page_zero(DisasContext *ctx) break; =20 case 0xe0: /* SET_THREAD_POINTER */ - tcg_gen_st_reg(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])= ); - tcg_gen_ori_reg(cpu_iaoq_f, cpu_gr[31], 3); - tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); + tcg_gen_st_i64(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])= ); + tcg_gen_ori_i64(cpu_iaoq_f, cpu_gr[31], 3); + tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_f, 4); ctx->base.is_jmp =3D DISAS_IAQ_N_UPDATED; break; =20 @@ -2030,8 +1932,8 @@ static bool trans_sync(DisasContext *ctx, arg_sync *a) static bool trans_mfia(DisasContext *ctx, arg_mfia *a) { unsigned rt =3D a->t; - TCGv_reg tmp =3D dest_gpr(ctx, rt); - tcg_gen_movi_reg(tmp, ctx->iaoq_f); + TCGv_i64 tmp =3D dest_gpr(ctx, rt); + tcg_gen_movi_i64(tmp, ctx->iaoq_f); save_gpr(ctx, rt, tmp); =20 cond_free(&ctx->null_cond); @@ -2043,7 +1945,7 @@ static bool trans_mfsp(DisasContext *ctx, arg_mfsp *a) unsigned rt =3D a->t; unsigned rs =3D a->sp; TCGv_i64 t0 =3D tcg_temp_new_i64(); - TCGv_reg t1 =3D tcg_temp_new(); + TCGv_i64 t1 =3D tcg_temp_new(); =20 load_spr(ctx, t0, rs); tcg_gen_shri_i64(t0, t0, 32); @@ -2059,14 +1961,14 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfct= l *a) { unsigned rt =3D a->t; unsigned ctl =3D a->r; - TCGv_reg tmp; + TCGv_i64 tmp; =20 switch (ctl) { case CR_SAR: if (a->e =3D=3D 0) { /* MFSAR without ,W masks low 5 bits. */ tmp =3D dest_gpr(ctx, rt); - tcg_gen_andi_reg(tmp, cpu_sar, 31); + tcg_gen_andi_i64(tmp, cpu_sar, 31); save_gpr(ctx, rt, tmp); goto done; } @@ -2094,7 +1996,7 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl = *a) } =20 tmp =3D tcg_temp_new(); - tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); + tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); save_gpr(ctx, rt, tmp); =20 done: @@ -2130,13 +2032,13 @@ static bool trans_mtsp(DisasContext *ctx, arg_mtsp = *a) static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a) { unsigned ctl =3D a->t; - TCGv_reg reg; - TCGv_reg tmp; + TCGv_i64 reg; + TCGv_i64 tmp; =20 if (ctl =3D=3D CR_SAR) { reg =3D load_gpr(ctx, a->r); tmp =3D tcg_temp_new(); - tcg_gen_andi_reg(tmp, reg, ctx->is_pa20 ? 63 : 31); + tcg_gen_andi_i64(tmp, reg, ctx->is_pa20 ? 63 : 31); save_or_nullify(ctx, cpu_sar, tmp); =20 cond_free(&ctx->null_cond); @@ -2167,10 +2069,10 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtct= l *a) /* FIXME: Respect PSW_Q bit */ /* The write advances the queue and stores to the back element. */ tmp =3D tcg_temp_new(); - tcg_gen_ld_reg(tmp, tcg_env, + tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); - tcg_gen_st_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); - tcg_gen_st_reg(reg, tcg_env, + tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); + tcg_gen_st_i64(reg, tcg_env, offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); break; =20 @@ -2178,14 +2080,14 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtct= l *a) case CR_PID2: case CR_PID3: case CR_PID4: - tcg_gen_st_reg(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl])); + tcg_gen_st_i64(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl])); #ifndef CONFIG_USER_ONLY gen_helper_change_prot_id(tcg_env); #endif break; =20 default: - tcg_gen_st_reg(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl])); + tcg_gen_st_i64(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl])); break; } return nullify_end(ctx); @@ -2194,10 +2096,10 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtct= l *a) =20 static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a) { - TCGv_reg tmp =3D tcg_temp_new(); + TCGv_i64 tmp =3D tcg_temp_new(); =20 - tcg_gen_not_reg(tmp, load_gpr(ctx, a->r)); - tcg_gen_andi_reg(tmp, tmp, ctx->is_pa20 ? 63 : 31); + tcg_gen_not_i64(tmp, load_gpr(ctx, a->r)); + tcg_gen_andi_i64(tmp, tmp, ctx->is_pa20 ? 63 : 31); save_or_nullify(ctx, cpu_sar, tmp); =20 cond_free(&ctx->null_cond); @@ -2206,11 +2108,11 @@ static bool trans_mtsarcm(DisasContext *ctx, arg_mt= sarcm *a) =20 static bool trans_ldsid(DisasContext *ctx, arg_ldsid *a) { - TCGv_reg dest =3D dest_gpr(ctx, a->t); + TCGv_i64 dest =3D dest_gpr(ctx, a->t); =20 #ifdef CONFIG_USER_ONLY /* We don't implement space registers in user mode. */ - tcg_gen_movi_reg(dest, 0); + tcg_gen_movi_i64(dest, 0); #else TCGv_i64 t0 =3D tcg_temp_new_i64(); =20 @@ -2228,13 +2130,13 @@ static bool trans_rsm(DisasContext *ctx, arg_rsm *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY - TCGv_reg tmp; + TCGv_i64 tmp; =20 nullify_over(ctx); =20 tmp =3D tcg_temp_new(); - tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw)); - tcg_gen_andi_reg(tmp, tmp, ~a->i); + tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw)); + tcg_gen_andi_i64(tmp, tmp, ~a->i); gen_helper_swap_system_mask(tmp, tcg_env, tmp); save_gpr(ctx, a->t, tmp); =20 @@ -2248,13 +2150,13 @@ static bool trans_ssm(DisasContext *ctx, arg_ssm *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY - TCGv_reg tmp; + TCGv_i64 tmp; =20 nullify_over(ctx); =20 tmp =3D tcg_temp_new(); - tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw)); - tcg_gen_ori_reg(tmp, tmp, a->i); + tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw)); + tcg_gen_ori_i64(tmp, tmp, a->i); gen_helper_swap_system_mask(tmp, tcg_env, tmp); save_gpr(ctx, a->t, tmp); =20 @@ -2268,7 +2170,7 @@ static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY - TCGv_reg tmp, reg; + TCGv_i64 tmp, reg; nullify_over(ctx); =20 reg =3D load_gpr(ctx, a->r); @@ -2345,12 +2247,12 @@ static bool trans_getshadowregs(DisasContext *ctx, = arg_getshadowregs *a) static bool trans_nop_addrx(DisasContext *ctx, arg_ldst *a) { if (a->m) { - TCGv_reg dest =3D dest_gpr(ctx, a->b); - TCGv_reg src1 =3D load_gpr(ctx, a->b); - TCGv_reg src2 =3D load_gpr(ctx, a->x); + TCGv_i64 dest =3D dest_gpr(ctx, a->b); + TCGv_i64 src1 =3D load_gpr(ctx, a->b); + TCGv_i64 src2 =3D load_gpr(ctx, a->x); =20 /* The only thing we need to do is the base register modification.= */ - tcg_gen_add_reg(dest, src1, src2); + tcg_gen_add_i64(dest, src1, src2); save_gpr(ctx, a->b, dest); } cond_free(&ctx->null_cond); @@ -2359,9 +2261,9 @@ static bool trans_nop_addrx(DisasContext *ctx, arg_ld= st *a) =20 static bool trans_probe(DisasContext *ctx, arg_probe *a) { - TCGv_reg dest, ofs; + TCGv_i64 dest, ofs; TCGv_i32 level, want; - TCGv_tl addr; + TCGv_i64 addr; =20 nullify_over(ctx); =20 @@ -2372,7 +2274,7 @@ static bool trans_probe(DisasContext *ctx, arg_probe = *a) level =3D tcg_constant_i32(a->ri); } else { level =3D tcg_temp_new_i32(); - tcg_gen_trunc_reg_i32(level, load_gpr(ctx, a->ri)); + tcg_gen_extrl_i64_i32(level, load_gpr(ctx, a->ri)); tcg_gen_andi_i32(level, level, 3); } want =3D tcg_constant_i32(a->write ? PAGE_WRITE : PAGE_READ); @@ -2390,8 +2292,8 @@ static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlb= x *a) } CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY - TCGv_tl addr; - TCGv_reg ofs, reg; + TCGv_i64 addr; + TCGv_i64 ofs, reg; =20 nullify_over(ctx); =20 @@ -2415,8 +2317,8 @@ static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlb= x *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY - TCGv_tl addr; - TCGv_reg ofs; + TCGv_i64 addr; + TCGv_i64 ofs; =20 nullify_over(ctx); =20 @@ -2451,8 +2353,8 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtl= bxf *a) } CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY - TCGv_tl addr, atl, stl; - TCGv_reg reg; + TCGv_i64 addr, atl, stl; + TCGv_i64 reg; =20 nullify_over(ctx); =20 @@ -2462,9 +2364,9 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtl= bxf *a) * return gen_illegal(ctx); */ =20 - atl =3D tcg_temp_new_tl(); - stl =3D tcg_temp_new_tl(); - addr =3D tcg_temp_new_tl(); + atl =3D tcg_temp_new_i64(); + stl =3D tcg_temp_new_i64(); + addr =3D tcg_temp_new_i64(); =20 tcg_gen_ld32u_i64(stl, tcg_env, a->data ? offsetof(CPUHPPAState, cr[CR_ISR]) @@ -2513,8 +2415,8 @@ static bool trans_lpa(DisasContext *ctx, arg_ldst *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY - TCGv_tl vaddr; - TCGv_reg ofs, paddr; + TCGv_i64 vaddr; + TCGv_i64 ofs, paddr; =20 nullify_over(ctx); =20 @@ -2541,7 +2443,7 @@ static bool trans_lci(DisasContext *ctx, arg_lci *a) physical address. Two addresses with the same CI have a coherent view of the cache. Our implementation is to return 0 for all, since the entire address space is coherent. */ - save_gpr(ctx, a->t, tcg_constant_reg(0)); + save_gpr(ctx, a->t, tcg_constant_i64(0)); =20 cond_free(&ctx->null_cond); return true; @@ -2604,12 +2506,12 @@ static bool trans_sub_b_tsv(DisasContext *ctx, arg_= rrr_cf_d *a) =20 static bool trans_andcm(DisasContext *ctx, arg_rrr_cf_d *a) { - return do_log_reg(ctx, a, tcg_gen_andc_reg); + return do_log_reg(ctx, a, tcg_gen_andc_i64); } =20 static bool trans_and(DisasContext *ctx, arg_rrr_cf_d *a) { - return do_log_reg(ctx, a, tcg_gen_and_reg); + return do_log_reg(ctx, a, tcg_gen_and_i64); } =20 static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) @@ -2625,8 +2527,8 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d = *a) } if (r2 =3D=3D 0) { /* COPY */ if (r1 =3D=3D 0) { - TCGv_reg dest =3D dest_gpr(ctx, rt); - tcg_gen_movi_reg(dest, 0); + TCGv_i64 dest =3D dest_gpr(ctx, rt); + tcg_gen_movi_i64(dest, 0); save_gpr(ctx, rt, dest); } else { save_gpr(ctx, rt, cpu_gr[r1]); @@ -2661,17 +2563,17 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_= d *a) } #endif } - return do_log_reg(ctx, a, tcg_gen_or_reg); + return do_log_reg(ctx, a, tcg_gen_or_i64); } =20 static bool trans_xor(DisasContext *ctx, arg_rrr_cf_d *a) { - return do_log_reg(ctx, a, tcg_gen_xor_reg); + return do_log_reg(ctx, a, tcg_gen_xor_i64); } =20 static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf_d *a) { - TCGv_reg tcg_r1, tcg_r2; + TCGv_i64 tcg_r1, tcg_r2; =20 if (a->cf) { nullify_over(ctx); @@ -2684,20 +2586,20 @@ static bool trans_cmpclr(DisasContext *ctx, arg_rrr= _cf_d *a) =20 static bool trans_uxor(DisasContext *ctx, arg_rrr_cf_d *a) { - TCGv_reg tcg_r1, tcg_r2; + TCGv_i64 tcg_r1, tcg_r2; =20 if (a->cf) { nullify_over(ctx); } tcg_r1 =3D load_gpr(ctx, a->r1); tcg_r2 =3D load_gpr(ctx, a->r2); - do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, false, tcg_gen_xor_reg= ); + do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, false, tcg_gen_xor_i64= ); return nullify_end(ctx); } =20 static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc) { - TCGv_reg tcg_r1, tcg_r2, tmp; + TCGv_i64 tcg_r1, tcg_r2, tmp; =20 if (a->cf) { nullify_over(ctx); @@ -2705,8 +2607,8 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d= *a, bool is_tc) tcg_r1 =3D load_gpr(ctx, a->r1); tcg_r2 =3D load_gpr(ctx, a->r2); tmp =3D tcg_temp_new(); - tcg_gen_not_reg(tmp, tcg_r2); - do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_reg); + tcg_gen_not_i64(tmp, tcg_r2); + do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_i64); return nullify_end(ctx); } =20 @@ -2722,19 +2624,19 @@ static bool trans_uaddcm_tc(DisasContext *ctx, arg_= rrr_cf_d *a) =20 static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i) { - TCGv_reg tmp; + TCGv_i64 tmp; =20 nullify_over(ctx); =20 tmp =3D tcg_temp_new(); - tcg_gen_shri_reg(tmp, cpu_psw_cb, 3); + tcg_gen_shri_i64(tmp, cpu_psw_cb, 3); if (!is_i) { - tcg_gen_not_reg(tmp, tmp); + tcg_gen_not_i64(tmp, tmp); } - tcg_gen_andi_reg(tmp, tmp, (uint64_t)0x1111111111111111ull); - tcg_gen_muli_reg(tmp, tmp, 6); + tcg_gen_andi_i64(tmp, tmp, (uint64_t)0x1111111111111111ull); + tcg_gen_muli_i64(tmp, tmp, 6); do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, a->d, false, - is_i ? tcg_gen_add_reg : tcg_gen_sub_reg); + is_i ? tcg_gen_add_i64 : tcg_gen_sub_i64); return nullify_end(ctx); } =20 @@ -2750,8 +2652,8 @@ static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf= _d *a) =20 static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) { - TCGv_reg dest, add1, add2, addc, zero, in1, in2; - TCGv_reg cout; + TCGv_i64 dest, add1, add2, addc, zero, in1, in2; + TCGv_i64 cout; =20 nullify_over(ctx); =20 @@ -2762,11 +2664,11 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf = *a) add2 =3D tcg_temp_new(); addc =3D tcg_temp_new(); dest =3D tcg_temp_new(); - zero =3D tcg_constant_reg(0); + zero =3D tcg_constant_i64(0); =20 /* Form R1 << 1 | PSW[CB]{8}. */ - tcg_gen_add_reg(add1, in1, in1); - tcg_gen_add_reg(add1, add1, get_psw_carry(ctx, false)); + tcg_gen_add_i64(add1, in1, in1); + tcg_gen_add_i64(add1, add1, get_psw_carry(ctx, false)); =20 /* * Add or subtract R2, depending on PSW[V]. Proper computation of @@ -2774,28 +2676,28 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf = *a) * the manual. By extracting and masking V, we can produce the * proper inputs to the addition without movcond. */ - tcg_gen_sextract_reg(addc, cpu_psw_v, 31, 1); - tcg_gen_xor_reg(add2, in2, addc); - tcg_gen_andi_reg(addc, addc, 1); + tcg_gen_sextract_i64(addc, cpu_psw_v, 31, 1); + tcg_gen_xor_i64(add2, in2, addc); + tcg_gen_andi_i64(addc, addc, 1); =20 - tcg_gen_add2_reg(dest, cpu_psw_cb_msb, add1, zero, add2, zero); - tcg_gen_add2_reg(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zer= o); + tcg_gen_add2_i64(dest, cpu_psw_cb_msb, add1, zero, add2, zero); + tcg_gen_add2_i64(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zer= o); =20 /* Write back the result register. */ save_gpr(ctx, a->t, dest); =20 /* Write back PSW[CB]. */ - tcg_gen_xor_reg(cpu_psw_cb, add1, add2); - tcg_gen_xor_reg(cpu_psw_cb, cpu_psw_cb, dest); + tcg_gen_xor_i64(cpu_psw_cb, add1, add2); + tcg_gen_xor_i64(cpu_psw_cb, cpu_psw_cb, dest); =20 /* Write back PSW[V] for the division step. */ cout =3D get_psw_carry(ctx, false); - tcg_gen_neg_reg(cpu_psw_v, cout); - tcg_gen_xor_reg(cpu_psw_v, cpu_psw_v, in2); + tcg_gen_neg_i64(cpu_psw_v, cout); + tcg_gen_xor_i64(cpu_psw_v, cpu_psw_v, in2); =20 /* Install the new nullification. */ if (a->cf) { - TCGv_reg sv =3D NULL; + TCGv_i64 sv =3D NULL; if (cond_need_sv(a->cf >> 1)) { /* ??? The lshift is supposed to contribute to overflow. */ sv =3D do_add_sv(ctx, dest, add1, add2); @@ -2838,13 +2740,13 @@ static bool trans_subi_tsv(DisasContext *ctx, arg_r= ri_cf *a) =20 static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf_d *a) { - TCGv_reg tcg_im, tcg_r2; + TCGv_i64 tcg_im, tcg_r2; =20 if (a->cf) { nullify_over(ctx); } =20 - tcg_im =3D tcg_constant_reg(a->i); + tcg_im =3D tcg_constant_i64(a->i); tcg_r2 =3D load_gpr(ctx, a->r); do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf, a->d); =20 @@ -2872,8 +2774,8 @@ static bool trans_st(DisasContext *ctx, arg_ldst *a) static bool trans_ldc(DisasContext *ctx, arg_ldst *a) { MemOp mop =3D MO_TE | MO_ALIGN | a->size; - TCGv_reg zero, dest, ofs; - TCGv_tl addr; + TCGv_i64 zero, dest, ofs; + TCGv_i64 addr; =20 if (!ctx->is_pa20 && a->size > MO_32) { return gen_illegal(ctx); @@ -2902,8 +2804,8 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) */ gen_helper_ldc_check(addr); =20 - zero =3D tcg_constant_reg(0); - tcg_gen_atomic_xchg_reg(dest, addr, zero, ctx->mmu_idx, mop); + zero =3D tcg_constant_i64(0); + tcg_gen_atomic_xchg_i64(dest, addr, zero, ctx->mmu_idx, mop); =20 if (a->m) { save_gpr(ctx, a->b, ofs); @@ -2915,8 +2817,8 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) =20 static bool trans_stby(DisasContext *ctx, arg_stby *a) { - TCGv_reg ofs, val; - TCGv_tl addr; + TCGv_i64 ofs, val; + TCGv_i64 addr; =20 nullify_over(ctx); =20 @@ -2937,7 +2839,7 @@ static bool trans_stby(DisasContext *ctx, arg_stby *a) } } if (a->m) { - tcg_gen_andi_reg(ofs, ofs, ~3); + tcg_gen_andi_i64(ofs, ofs, ~3); save_gpr(ctx, a->b, ofs); } =20 @@ -2946,8 +2848,8 @@ static bool trans_stby(DisasContext *ctx, arg_stby *a) =20 static bool trans_stdby(DisasContext *ctx, arg_stby *a) { - TCGv_reg ofs, val; - TCGv_tl addr; + TCGv_i64 ofs, val; + TCGv_i64 addr; =20 nullify_over(ctx); =20 @@ -2968,7 +2870,7 @@ static bool trans_stdby(DisasContext *ctx, arg_stby *= a) } } if (a->m) { - tcg_gen_andi_reg(ofs, ofs, ~7); + tcg_gen_andi_i64(ofs, ofs, ~7); save_gpr(ctx, a->b, ofs); } =20 @@ -2999,9 +2901,9 @@ static bool trans_sta(DisasContext *ctx, arg_ldst *a) =20 static bool trans_ldil(DisasContext *ctx, arg_ldil *a) { - TCGv_reg tcg_rt =3D dest_gpr(ctx, a->t); + TCGv_i64 tcg_rt =3D dest_gpr(ctx, a->t); =20 - tcg_gen_movi_reg(tcg_rt, a->i); + tcg_gen_movi_i64(tcg_rt, a->i); save_gpr(ctx, a->t, tcg_rt); cond_free(&ctx->null_cond); return true; @@ -3009,10 +2911,10 @@ static bool trans_ldil(DisasContext *ctx, arg_ldil = *a) =20 static bool trans_addil(DisasContext *ctx, arg_addil *a) { - TCGv_reg tcg_rt =3D load_gpr(ctx, a->r); - TCGv_reg tcg_r1 =3D dest_gpr(ctx, 1); + TCGv_i64 tcg_rt =3D load_gpr(ctx, a->r); + TCGv_i64 tcg_r1 =3D dest_gpr(ctx, 1); =20 - tcg_gen_addi_reg(tcg_r1, tcg_rt, a->i); + tcg_gen_addi_i64(tcg_r1, tcg_rt, a->i); save_gpr(ctx, 1, tcg_r1); cond_free(&ctx->null_cond); return true; @@ -3020,30 +2922,30 @@ static bool trans_addil(DisasContext *ctx, arg_addi= l *a) =20 static bool trans_ldo(DisasContext *ctx, arg_ldo *a) { - TCGv_reg tcg_rt =3D dest_gpr(ctx, a->t); + TCGv_i64 tcg_rt =3D dest_gpr(ctx, a->t); =20 /* Special case rb =3D=3D 0, for the LDI pseudo-op. The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */ if (a->b =3D=3D 0) { - tcg_gen_movi_reg(tcg_rt, a->i); + tcg_gen_movi_i64(tcg_rt, a->i); } else { - tcg_gen_addi_reg(tcg_rt, cpu_gr[a->b], a->i); + tcg_gen_addi_i64(tcg_rt, cpu_gr[a->b], a->i); } save_gpr(ctx, a->t, tcg_rt); cond_free(&ctx->null_cond); return true; } =20 -static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1, +static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_i64 in1, unsigned c, unsigned f, bool d, unsigned n, int disp) { - TCGv_reg dest, in2, sv; + TCGv_i64 dest, in2, sv; DisasCond cond; =20 in2 =3D load_gpr(ctx, r); dest =3D tcg_temp_new(); =20 - tcg_gen_sub_reg(dest, in1, in2); + tcg_gen_sub_i64(dest, in1, in2); =20 sv =3D NULL; if (cond_need_sv(c)) { @@ -3070,14 +2972,14 @@ static bool trans_cmpbi(DisasContext *ctx, arg_cmpb= i *a) return false; } nullify_over(ctx); - return do_cmpb(ctx, a->r, tcg_constant_reg(a->i), + return do_cmpb(ctx, a->r, tcg_constant_i64(a->i), a->c, a->f, a->d, a->n, a->disp); } =20 -static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1, +static bool do_addb(DisasContext *ctx, unsigned r, TCGv_i64 in1, unsigned c, unsigned f, unsigned n, int disp) { - TCGv_reg dest, in2, sv, cb_cond; + TCGv_i64 dest, in2, sv, cb_cond; DisasCond cond; bool d =3D false; =20 @@ -3098,16 +3000,16 @@ static bool do_addb(DisasContext *ctx, unsigned r, = TCGv_reg in1, cb_cond =3D NULL; =20 if (cond_need_cb(c)) { - TCGv_reg cb =3D tcg_temp_new(); - TCGv_reg cb_msb =3D tcg_temp_new(); + TCGv_i64 cb =3D tcg_temp_new(); + TCGv_i64 cb_msb =3D tcg_temp_new(); =20 - tcg_gen_movi_reg(cb_msb, 0); - tcg_gen_add2_reg(dest, cb_msb, in1, cb_msb, in2, cb_msb); - tcg_gen_xor_reg(cb, in1, in2); - tcg_gen_xor_reg(cb, cb, dest); + tcg_gen_movi_i64(cb_msb, 0); + tcg_gen_add2_i64(dest, cb_msb, in1, cb_msb, in2, cb_msb); + tcg_gen_xor_i64(cb, in1, in2); + tcg_gen_xor_i64(cb, cb, dest); cb_cond =3D get_carry(ctx, d, cb, cb_msb); } else { - tcg_gen_add_reg(dest, in1, in2); + tcg_gen_add_i64(dest, in1, in2); } if (cond_need_sv(c)) { sv =3D do_add_sv(ctx, dest, in1, in2); @@ -3127,12 +3029,12 @@ static bool trans_addb(DisasContext *ctx, arg_addb = *a) static bool trans_addbi(DisasContext *ctx, arg_addbi *a) { nullify_over(ctx); - return do_addb(ctx, a->r, tcg_constant_reg(a->i), a->c, a->f, a->n, a-= >disp); + return do_addb(ctx, a->r, tcg_constant_i64(a->i), a->c, a->f, a->n, a-= >disp); } =20 static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) { - TCGv_reg tmp, tcg_r; + TCGv_i64 tmp, tcg_r; DisasCond cond; =20 nullify_over(ctx); @@ -3141,10 +3043,10 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_= sar *a) tcg_r =3D load_gpr(ctx, a->r); if (cond_need_ext(ctx, a->d)) { /* Force shift into [32,63] */ - tcg_gen_ori_reg(tmp, cpu_sar, 32); - tcg_gen_shl_reg(tmp, tcg_r, tmp); + tcg_gen_ori_i64(tmp, cpu_sar, 32); + tcg_gen_shl_i64(tmp, tcg_r, tmp); } else { - tcg_gen_shl_reg(tmp, tcg_r, cpu_sar); + tcg_gen_shl_i64(tmp, tcg_r, cpu_sar); } =20 cond =3D cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); @@ -3153,7 +3055,7 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sa= r *a) =20 static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a) { - TCGv_reg tmp, tcg_r; + TCGv_i64 tmp, tcg_r; DisasCond cond; int p; =20 @@ -3162,7 +3064,7 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_im= m *a) tmp =3D tcg_temp_new(); tcg_r =3D load_gpr(ctx, a->r); p =3D a->p | (cond_need_ext(ctx, a->d) ? 32 : 0); - tcg_gen_shli_reg(tmp, tcg_r, p); + tcg_gen_shli_i64(tmp, tcg_r, p); =20 cond =3D cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); return do_cbranch(ctx, a->disp, a->n, &cond); @@ -3170,16 +3072,16 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_= imm *a) =20 static bool trans_movb(DisasContext *ctx, arg_movb *a) { - TCGv_reg dest; + TCGv_i64 dest; DisasCond cond; =20 nullify_over(ctx); =20 dest =3D dest_gpr(ctx, a->r2); if (a->r1 =3D=3D 0) { - tcg_gen_movi_reg(dest, 0); + tcg_gen_movi_i64(dest, 0); } else { - tcg_gen_mov_reg(dest, cpu_gr[a->r1]); + tcg_gen_mov_i64(dest, cpu_gr[a->r1]); } =20 /* All MOVB conditions are 32-bit. */ @@ -3189,13 +3091,13 @@ static bool trans_movb(DisasContext *ctx, arg_movb = *a) =20 static bool trans_movbi(DisasContext *ctx, arg_movbi *a) { - TCGv_reg dest; + TCGv_i64 dest; DisasCond cond; =20 nullify_over(ctx); =20 dest =3D dest_gpr(ctx, a->r); - tcg_gen_movi_reg(dest, a->i); + tcg_gen_movi_i64(dest, a->i); =20 /* All MOVBI conditions are 32-bit. */ cond =3D do_sed_cond(ctx, a->c, false, dest); @@ -3204,7 +3106,7 @@ static bool trans_movbi(DisasContext *ctx, arg_movbi = *a) =20 static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a) { - TCGv_reg dest, tmp; + TCGv_i64 dest, tmp; =20 if (!ctx->is_pa20 && a->d) { return false; @@ -3216,40 +3118,40 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_s= hrp_sar *a) dest =3D dest_gpr(ctx, a->t); if (a->r1 =3D=3D 0) { if (a->d) { - tcg_gen_shr_reg(dest, dest, cpu_sar); + tcg_gen_shr_i64(dest, dest, cpu_sar); } else { - tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2)); + tcg_gen_ext32u_i64(dest, load_gpr(ctx, a->r2)); tmp =3D tcg_temp_new(); - tcg_gen_andi_reg(tmp, cpu_sar, 31); - tcg_gen_shr_reg(dest, dest, tmp); + tcg_gen_andi_i64(tmp, cpu_sar, 31); + tcg_gen_shr_i64(dest, dest, tmp); } } else if (a->r1 =3D=3D a->r2) { if (a->d) { - tcg_gen_rotr_reg(dest, load_gpr(ctx, a->r2), cpu_sar); + tcg_gen_rotr_i64(dest, load_gpr(ctx, a->r2), cpu_sar); } else { TCGv_i32 t32 =3D tcg_temp_new_i32(); TCGv_i32 s32 =3D tcg_temp_new_i32(); =20 - tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); - tcg_gen_trunc_reg_i32(s32, cpu_sar); + tcg_gen_extrl_i64_i32(t32, load_gpr(ctx, a->r2)); + tcg_gen_extrl_i64_i32(s32, cpu_sar); tcg_gen_andi_i32(s32, s32, 31); tcg_gen_rotr_i32(t32, t32, s32); - tcg_gen_extu_i32_reg(dest, t32); + tcg_gen_extu_i32_i64(dest, t32); } } else if (a->d) { - TCGv_reg t =3D tcg_temp_new(); - TCGv_reg n =3D tcg_temp_new(); + TCGv_i64 t =3D tcg_temp_new(); + TCGv_i64 n =3D tcg_temp_new(); =20 - tcg_gen_xori_reg(n, cpu_sar, 63); - tcg_gen_shl_reg(t, load_gpr(ctx, a->r2), n); - tcg_gen_shli_reg(t, t, 1); - tcg_gen_shr_reg(dest, load_gpr(ctx, a->r1), cpu_sar); - tcg_gen_or_reg(dest, dest, t); + tcg_gen_xori_i64(n, cpu_sar, 63); + tcg_gen_shl_i64(t, load_gpr(ctx, a->r2), n); + tcg_gen_shli_i64(t, t, 1); + tcg_gen_shr_i64(dest, load_gpr(ctx, a->r1), cpu_sar); + tcg_gen_or_i64(dest, dest, t); } else { TCGv_i64 t =3D tcg_temp_new_i64(); TCGv_i64 s =3D tcg_temp_new_i64(); =20 - tcg_gen_concat_reg_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r= 1)); + tcg_gen_concat32_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r1)= ); tcg_gen_extu_reg_i64(s, cpu_sar); tcg_gen_andi_i64(s, s, 31); tcg_gen_shr_i64(t, t, s); @@ -3268,7 +3170,7 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shr= p_sar *a) static bool trans_shrp_imm(DisasContext *ctx, arg_shrp_imm *a) { unsigned width, sa; - TCGv_reg dest, t2; + TCGv_i64 dest, t2; =20 if (!ctx->is_pa20 && a->d) { return false; @@ -3283,19 +3185,19 @@ static bool trans_shrp_imm(DisasContext *ctx, arg_s= hrp_imm *a) dest =3D dest_gpr(ctx, a->t); t2 =3D load_gpr(ctx, a->r2); if (a->r1 =3D=3D 0) { - tcg_gen_extract_reg(dest, t2, sa, width - sa); + tcg_gen_extract_i64(dest, t2, sa, width - sa); } else if (width =3D=3D TARGET_LONG_BITS) { - tcg_gen_extract2_reg(dest, t2, cpu_gr[a->r1], sa); + tcg_gen_extract2_i64(dest, t2, cpu_gr[a->r1], sa); } else { assert(!a->d); if (a->r1 =3D=3D a->r2) { TCGv_i32 t32 =3D tcg_temp_new_i32(); - tcg_gen_trunc_reg_i32(t32, t2); + tcg_gen_extrl_i64_i32(t32, t2); tcg_gen_rotri_i32(t32, t32, sa); - tcg_gen_extu_i32_reg(dest, t32); + tcg_gen_extu_i32_i64(dest, t32); } else { TCGv_i64 t64 =3D tcg_temp_new_i64(); - tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]); + tcg_gen_concat32_i64(t64, t2, cpu_gr[a->r1]); tcg_gen_shri_i64(t64, t64, sa); tcg_gen_trunc_i64_reg(dest, t64); } @@ -3313,7 +3215,7 @@ static bool trans_shrp_imm(DisasContext *ctx, arg_shr= p_imm *a) static bool trans_extr_sar(DisasContext *ctx, arg_extr_sar *a) { unsigned widthm1 =3D a->d ? 63 : 31; - TCGv_reg dest, src, tmp; + TCGv_i64 dest, src, tmp; =20 if (!ctx->is_pa20 && a->d) { return false; @@ -3327,15 +3229,15 @@ static bool trans_extr_sar(DisasContext *ctx, arg_e= xtr_sar *a) tmp =3D tcg_temp_new(); =20 /* Recall that SAR is using big-endian bit numbering. */ - tcg_gen_andi_reg(tmp, cpu_sar, widthm1); - tcg_gen_xori_reg(tmp, tmp, widthm1); + tcg_gen_andi_i64(tmp, cpu_sar, widthm1); + tcg_gen_xori_i64(tmp, tmp, widthm1); =20 if (a->se) { - tcg_gen_sar_reg(dest, src, tmp); - tcg_gen_sextract_reg(dest, dest, 0, a->len); + tcg_gen_sar_i64(dest, src, tmp); + tcg_gen_sextract_i64(dest, dest, 0, a->len); } else { - tcg_gen_shr_reg(dest, src, tmp); - tcg_gen_extract_reg(dest, dest, 0, a->len); + tcg_gen_shr_i64(dest, src, tmp); + tcg_gen_extract_i64(dest, dest, 0, a->len); } save_gpr(ctx, a->t, dest); =20 @@ -3350,7 +3252,7 @@ static bool trans_extr_sar(DisasContext *ctx, arg_ext= r_sar *a) static bool trans_extr_imm(DisasContext *ctx, arg_extr_imm *a) { unsigned len, cpos, width; - TCGv_reg dest, src; + TCGv_i64 dest, src; =20 if (!ctx->is_pa20 && a->d) { return false; @@ -3369,9 +3271,9 @@ static bool trans_extr_imm(DisasContext *ctx, arg_ext= r_imm *a) dest =3D dest_gpr(ctx, a->t); src =3D load_gpr(ctx, a->r); if (a->se) { - tcg_gen_sextract_reg(dest, src, cpos, len); + tcg_gen_sextract_i64(dest, src, cpos, len); } else { - tcg_gen_extract_reg(dest, src, cpos, len); + tcg_gen_extract_i64(dest, src, cpos, len); } save_gpr(ctx, a->t, dest); =20 @@ -3387,7 +3289,7 @@ static bool trans_depi_imm(DisasContext *ctx, arg_dep= i_imm *a) { unsigned len, width; uint64_t mask0, mask1; - TCGv_reg dest; + TCGv_i64 dest; =20 if (!ctx->is_pa20 && a->d) { return false; @@ -3407,11 +3309,11 @@ static bool trans_depi_imm(DisasContext *ctx, arg_d= epi_imm *a) mask1 =3D deposit64(-1, a->cpos, len, a->i); =20 if (a->nz) { - TCGv_reg src =3D load_gpr(ctx, a->t); - tcg_gen_andi_reg(dest, src, mask1); - tcg_gen_ori_reg(dest, dest, mask0); + TCGv_i64 src =3D load_gpr(ctx, a->t); + tcg_gen_andi_i64(dest, src, mask1); + tcg_gen_ori_i64(dest, dest, mask0); } else { - tcg_gen_movi_reg(dest, mask0); + tcg_gen_movi_i64(dest, mask0); } save_gpr(ctx, a->t, dest); =20 @@ -3427,7 +3329,7 @@ static bool trans_dep_imm(DisasContext *ctx, arg_dep_= imm *a) { unsigned rs =3D a->nz ? a->t : 0; unsigned len, width; - TCGv_reg dest, val; + TCGv_i64 dest, val; =20 if (!ctx->is_pa20 && a->d) { return false; @@ -3445,9 +3347,9 @@ static bool trans_dep_imm(DisasContext *ctx, arg_dep_= imm *a) dest =3D dest_gpr(ctx, a->t); val =3D load_gpr(ctx, a->r); if (rs =3D=3D 0) { - tcg_gen_deposit_z_reg(dest, val, a->cpos, len); + tcg_gen_deposit_z_i64(dest, val, a->cpos, len); } else { - tcg_gen_deposit_reg(dest, cpu_gr[rs], val, a->cpos, len); + tcg_gen_deposit_i64(dest, cpu_gr[rs], val, a->cpos, len); } save_gpr(ctx, a->t, dest); =20 @@ -3460,11 +3362,11 @@ static bool trans_dep_imm(DisasContext *ctx, arg_de= p_imm *a) } =20 static bool do_dep_sar(DisasContext *ctx, unsigned rt, unsigned c, - bool d, bool nz, unsigned len, TCGv_reg val) + bool d, bool nz, unsigned len, TCGv_i64 val) { unsigned rs =3D nz ? rt : 0; unsigned widthm1 =3D d ? 63 : 31; - TCGv_reg mask, tmp, shift, dest; + TCGv_i64 mask, tmp, shift, dest; uint64_t msb =3D 1ULL << (len - 1); =20 dest =3D dest_gpr(ctx, rt); @@ -3472,19 +3374,19 @@ static bool do_dep_sar(DisasContext *ctx, unsigned = rt, unsigned c, tmp =3D tcg_temp_new(); =20 /* Convert big-endian bit numbering in SAR to left-shift. */ - tcg_gen_andi_reg(shift, cpu_sar, widthm1); - tcg_gen_xori_reg(shift, shift, widthm1); + tcg_gen_andi_i64(shift, cpu_sar, widthm1); + tcg_gen_xori_i64(shift, shift, widthm1); =20 mask =3D tcg_temp_new(); - tcg_gen_movi_reg(mask, msb + (msb - 1)); - tcg_gen_and_reg(tmp, val, mask); + tcg_gen_movi_i64(mask, msb + (msb - 1)); + tcg_gen_and_i64(tmp, val, mask); if (rs) { - tcg_gen_shl_reg(mask, mask, shift); - tcg_gen_shl_reg(tmp, tmp, shift); - tcg_gen_andc_reg(dest, cpu_gr[rs], mask); - tcg_gen_or_reg(dest, dest, tmp); + tcg_gen_shl_i64(mask, mask, shift); + tcg_gen_shl_i64(tmp, tmp, shift); + tcg_gen_andc_i64(dest, cpu_gr[rs], mask); + tcg_gen_or_i64(dest, dest, tmp); } else { - tcg_gen_shl_reg(dest, tmp, shift); + tcg_gen_shl_i64(dest, tmp, shift); } save_gpr(ctx, rt, dest); =20 @@ -3517,12 +3419,12 @@ static bool trans_depi_sar(DisasContext *ctx, arg_d= epi_sar *a) nullify_over(ctx); } return do_dep_sar(ctx, a->t, a->c, a->d, a->nz, a->len, - tcg_constant_reg(a->i)); + tcg_constant_i64(a->i)); } =20 static bool trans_be(DisasContext *ctx, arg_be *a) { - TCGv_reg tmp; + TCGv_i64 tmp; =20 #ifdef CONFIG_USER_ONLY /* ??? It seems like there should be a good way of using @@ -3541,7 +3443,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a) #endif =20 tmp =3D tcg_temp_new(); - tcg_gen_addi_reg(tmp, load_gpr(ctx, a->b), a->disp); + tcg_gen_addi_i64(tmp, load_gpr(ctx, a->b), a->disp); tmp =3D do_ibranch_priv(ctx, tmp); =20 #ifdef CONFIG_USER_ONLY @@ -3555,8 +3457,8 @@ static bool trans_be(DisasContext *ctx, arg_be *a) tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_f); } if (a->n && use_nullify_skip(ctx)) { - tcg_gen_mov_reg(cpu_iaoq_f, tmp); - tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); + tcg_gen_mov_i64(cpu_iaoq_f, tmp); + tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_f, 4); tcg_gen_mov_i64(cpu_iasq_f, new_spc); tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f); } else { @@ -3564,7 +3466,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a) if (ctx->iaoq_b =3D=3D -1) { tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); } - tcg_gen_mov_reg(cpu_iaoq_b, tmp); + tcg_gen_mov_i64(cpu_iaoq_b, tmp); tcg_gen_mov_i64(cpu_iasq_b, new_spc); nullify_set(ctx, a->n); } @@ -3623,11 +3525,11 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_g= ate *a) #endif =20 if (a->l) { - TCGv_reg tmp =3D dest_gpr(ctx, a->l); + TCGv_i64 tmp =3D dest_gpr(ctx, a->l); if (ctx->privilege < 3) { - tcg_gen_andi_reg(tmp, tmp, -4); + tcg_gen_andi_i64(tmp, tmp, -4); } - tcg_gen_ori_reg(tmp, tmp, ctx->privilege); + tcg_gen_ori_i64(tmp, tmp, ctx->privilege); save_gpr(ctx, a->l, tmp); } =20 @@ -3637,9 +3539,9 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gat= e *a) static bool trans_blr(DisasContext *ctx, arg_blr *a) { if (a->x) { - TCGv_reg tmp =3D tcg_temp_new(); - tcg_gen_shli_reg(tmp, load_gpr(ctx, a->x), 3); - tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8); + TCGv_i64 tmp =3D tcg_temp_new(); + tcg_gen_shli_i64(tmp, load_gpr(ctx, a->x), 3); + tcg_gen_addi_i64(tmp, tmp, ctx->iaoq_f + 8); /* The computation here never changes privilege level. */ return do_ibranch(ctx, tmp, a->l, a->n); } else { @@ -3650,14 +3552,14 @@ static bool trans_blr(DisasContext *ctx, arg_blr *a) =20 static bool trans_bv(DisasContext *ctx, arg_bv *a) { - TCGv_reg dest; + TCGv_i64 dest; =20 if (a->x =3D=3D 0) { dest =3D load_gpr(ctx, a->b); } else { dest =3D tcg_temp_new(); - tcg_gen_shli_reg(dest, load_gpr(ctx, a->x), 3); - tcg_gen_add_reg(dest, dest, load_gpr(ctx, a->b)); + tcg_gen_shli_i64(dest, load_gpr(ctx, a->x), 3); + tcg_gen_add_i64(dest, dest, load_gpr(ctx, a->b)); } dest =3D do_ibranch_priv(ctx, dest); return do_ibranch(ctx, dest, 0, a->n); @@ -3665,7 +3567,7 @@ static bool trans_bv(DisasContext *ctx, arg_bv *a) =20 static bool trans_bve(DisasContext *ctx, arg_bve *a) { - TCGv_reg dest; + TCGv_i64 dest; =20 #ifdef CONFIG_USER_ONLY dest =3D do_ibranch_priv(ctx, load_gpr(ctx, a->b)); @@ -3988,12 +3890,12 @@ static bool trans_fcmp_d(DisasContext *ctx, arg_fcl= ass2 *a) =20 static bool trans_ftest(DisasContext *ctx, arg_ftest *a) { - TCGv_reg t; + TCGv_i64 t; =20 nullify_over(ctx); =20 t =3D tcg_temp_new(); - tcg_gen_ld32u_reg(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow)); + tcg_gen_ld32u_i64(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow)); =20 if (a->y =3D=3D 1) { int mask; @@ -4001,7 +3903,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest = *a) =20 switch (a->c) { case 0: /* simple */ - tcg_gen_andi_reg(t, t, 0x4000000); + tcg_gen_andi_i64(t, t, 0x4000000); ctx->null_cond =3D cond_make_0(TCG_COND_NE, t); goto done; case 2: /* rej */ @@ -4030,17 +3932,17 @@ static bool trans_ftest(DisasContext *ctx, arg_ftes= t *a) return true; } if (inv) { - TCGv_reg c =3D tcg_constant_reg(mask); - tcg_gen_or_reg(t, t, c); + TCGv_i64 c =3D tcg_constant_i64(mask); + tcg_gen_or_i64(t, t, c); ctx->null_cond =3D cond_make(TCG_COND_EQ, t, c); } else { - tcg_gen_andi_reg(t, t, mask); + tcg_gen_andi_i64(t, t, mask); ctx->null_cond =3D cond_make_0(TCG_COND_EQ, t); } } else { unsigned cbit =3D (a->y ^ 1) - 1; =20 - tcg_gen_extract_reg(t, t, 21 - cbit, 1); + tcg_gen_extract_i64(t, t, 21 - cbit, 1); ctx->null_cond =3D cond_make_0(TCG_COND_NE, t); } =20 @@ -4294,7 +4196,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) if (ctx->iaoq_b =3D=3D -1) { ctx->iaoq_n =3D -1; ctx->iaoq_n_var =3D tcg_temp_new(); - tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); + tcg_gen_addi_i64(ctx->iaoq_n_var, cpu_iaoq_b, 4); } else { ctx->iaoq_n =3D ctx->iaoq_b + 4; ctx->iaoq_n_var =3D NULL; @@ -4340,7 +4242,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) case DISAS_IAQ_N_STALE: case DISAS_IAQ_N_STALE_EXIT: if (ctx->iaoq_f =3D=3D -1) { - tcg_gen_mov_reg(cpu_iaoq_f, cpu_iaoq_b); + tcg_gen_mov_i64(cpu_iaoq_f, cpu_iaoq_b); copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); #ifndef CONFIG_USER_ONLY tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); @@ -4350,7 +4252,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) ? DISAS_EXIT : DISAS_IAQ_N_UPDATED); } else if (ctx->iaoq_b =3D=3D -1) { - tcg_gen_mov_reg(cpu_iaoq_b, ctx->iaoq_n_var); + tcg_gen_mov_i64(cpu_iaoq_b, ctx->iaoq_n_var); } break; =20 --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835268; cv=none; d=zohomail.com; s=zohoarc; b=E+bugUx2vlTIAYwNE1dEfmtX8YASZE/pYLNkhMDKaMrkjuYzKtcxQa+FdW8Z/Bh42wY5igeJtSli5owGIx9XcmzHQq0Z3HtLZs/F9CshZkV1IacOm/Up3b7DZyFTJEStWk98mwTEC9vqcv5tyUX5ewZSCGBiw6gO3HvplsBlbSQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697835268; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=V27FJvCyTyLJjGiSkXiFejIZCBYVGBoOukmrhWxyTiU=; b=Aeiyt7eXQYXwikplw7MU8D/lq+qdZXOQz9mgAPDQ98lh2yDycqaO4hOBieKj2i0Ghu84YHaVRx26HCW9xZbXXO7RSjsjBBtnj9SJcx4Rw9FplcctraqraPVOPyUZ3dbHjvePwBP0uu26Dp6R8M6MNnKF/KL9B5WXBkyp74qXvVc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169783526893112.466556090832114; Fri, 20 Oct 2023 13:54:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwOx-0001tW-MX; Fri, 20 Oct 2023 16:47:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwOw-0001pD-5s for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:47:22 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwOs-0001BM-Bp for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:47:21 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-6bd96cfb99cso1114366b3a.2 for ; Fri, 20 Oct 2023 13:47:17 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u7-20020aa78487000000b00694fee1011asm1946775pfn.208.2023.10.20.13.47.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:47:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834837; x=1698439637; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V27FJvCyTyLJjGiSkXiFejIZCBYVGBoOukmrhWxyTiU=; b=vrxX/vsxWXZe1a3JJfHObxma8tiIJIsdTWBhPPc0sAd7Et0qffMcKxU32cuCZxs7Lr pSkSOPjsr4h+10ymw04HNKBcqlZojFvyQdxnwnKMXA6T9LwE7c7AXymorhct82+8hoSQ HH2kuXUDPD5bR5sbfCmJTv40wDHdZkDyB7jdI3vFFvEgqcskPyirtSxsXP78q7Tx4T+C 5AUm2R8Co1bkhidzsKo6y+uBX/6TNaZkN6UQiZ1hGik+6QLjRWjnDhZ4/GqlOm3MQ/qP XjdtIfuzg86mFYRUMVO32Dtt7xfTIjQBwjSdQObXniioTCp8XTg7vpcUwzsCKtYoQ3Ly KXSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834837; x=1698439637; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V27FJvCyTyLJjGiSkXiFejIZCBYVGBoOukmrhWxyTiU=; b=mQuxHE4E3gw0pfLnfkeWpRzBdDOB5aDDNwYoLFv8sSfkNGpglBQyRiLi4BysE64gee c/SFah6DgHnpvHkqvjeyfDYQKRFicBBxFDIvXxG3M0atG2SXifCn0jfQP3hkcSEIkeSS q5qdtDmbPQ8es0VipAfMxkzmwGdLtwtCf2T425RTk6xivhDDWI63ZfP6PkY6F93LCJCw ZrfbRti2h8pPureGUjHsw69XS4v4Pd3NSMgTmBE7oAuC3z0gSdF9r2zj3IvgenLfn3iG PXEVSDVW4GMqAk62+edT0RjMNj6Mpg/gQb1WTh8DBAworlFccITd4D03Ld8fkI+nT6yH Yk8g== X-Gm-Message-State: AOJu0Yw9497EstPnHJaozlQzp/+L54KaDqoOX7wlJgpVduYnRXzR2oxv ZO5TO1dGc20hAY7NqT0+H+yUDVQtKOhFeMgXUBY= X-Google-Smtp-Source: AGHT+IHgMVrM2KfZ0sBrxABUp4XVRQw+IIDlR8AM+giqkr38vF1t5jpky5jpE8tVWfkYPT1wJ8xD/w== X-Received: by 2002:a05:6a00:1913:b0:6be:26c1:be48 with SMTP id y19-20020a056a00191300b006be26c1be48mr3170962pfi.33.1697834836903; Fri, 20 Oct 2023 13:47:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 49/65] target/hppa: Remove remaining TARGET_REGISTER_BITS redirections Date: Fri, 20 Oct 2023 13:43:15 -0700 Message-Id: <20231020204331.139847-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835269932100001 Content-Type: text/plain; charset="utf-8" The conversions to/from i64 can be eliminated entirely, folding computation into adjacent operations. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 46 ++++++++++++----------------------------- 1 file changed, 13 insertions(+), 33 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 1a57ccc49b..95de007c69 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -33,15 +33,6 @@ #undef HELPER_H =20 =20 -/* Since we have a distinction between register size and address size, - we need to redefine all of these. */ - -#define tcg_gen_extu_reg_tl tcg_gen_mov_i64 -#define tcg_gen_trunc_i64_reg tcg_gen_mov_i64 -#define tcg_gen_extu_reg_i64 tcg_gen_mov_i64 -#define tcg_gen_ext_reg_i64 tcg_gen_mov_i64 - - typedef struct DisasCond { TCGCond c; TCGv_i64 a0, a1; @@ -1332,8 +1323,7 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *pgv= a, TCGv_i64 *pofs, =20 *pofs =3D ofs; *pgva =3D addr =3D tcg_temp_new_i64(); - tcg_gen_extu_reg_tl(addr, modify <=3D 0 ? ofs : base); - tcg_gen_andi_tl(addr, addr, gva_offset_mask(ctx)); + tcg_gen_andi_tl(addr, modify <=3D 0 ? ofs : base, gva_offset_mask(ctx)= ); #ifndef CONFIG_USER_ONLY if (!is_phys) { tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base)); @@ -1945,13 +1935,11 @@ static bool trans_mfsp(DisasContext *ctx, arg_mfsp = *a) unsigned rt =3D a->t; unsigned rs =3D a->sp; TCGv_i64 t0 =3D tcg_temp_new_i64(); - TCGv_i64 t1 =3D tcg_temp_new(); =20 load_spr(ctx, t0, rs); tcg_gen_shri_i64(t0, t0, 32); - tcg_gen_trunc_i64_reg(t1, t0); =20 - save_gpr(ctx, rt, t1); + save_gpr(ctx, rt, t0); =20 cond_free(&ctx->null_cond); return true; @@ -2008,22 +1996,21 @@ static bool trans_mtsp(DisasContext *ctx, arg_mtsp = *a) { unsigned rr =3D a->r; unsigned rs =3D a->sp; - TCGv_i64 t64; + TCGv_i64 tmp; =20 if (rs >=3D 5) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); } nullify_over(ctx); =20 - t64 =3D tcg_temp_new_i64(); - tcg_gen_extu_reg_i64(t64, load_gpr(ctx, rr)); - tcg_gen_shli_i64(t64, t64, 32); + tmp =3D tcg_temp_new_i64(); + tcg_gen_shli_i64(tmp, load_gpr(ctx, rr), 32); =20 if (rs >=3D 4) { - tcg_gen_st_i64(t64, tcg_env, offsetof(CPUHPPAState, sr[rs])); + tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUHPPAState, sr[rs])); ctx->tb_flags &=3D ~TB_FLAG_SR_SAME; } else { - tcg_gen_mov_i64(cpu_sr[rs], t64); + tcg_gen_mov_i64(cpu_sr[rs], tmp); } =20 return nullify_end(ctx); @@ -2114,11 +2101,8 @@ static bool trans_ldsid(DisasContext *ctx, arg_ldsid= *a) /* We don't implement space registers in user mode. */ tcg_gen_movi_i64(dest, 0); #else - TCGv_i64 t0 =3D tcg_temp_new_i64(); - - tcg_gen_mov_i64(t0, space_select(ctx, a->sp, load_gpr(ctx, a->b))); - tcg_gen_shri_i64(t0, t0, 32); - tcg_gen_trunc_i64_reg(dest, t0); + tcg_gen_mov_i64(dest, space_select(ctx, a->sp, load_gpr(ctx, a->b))); + tcg_gen_shri_i64(dest, dest, 32); #endif save_gpr(ctx, a->t, dest); =20 @@ -3152,10 +3136,8 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_sh= rp_sar *a) TCGv_i64 s =3D tcg_temp_new_i64(); =20 tcg_gen_concat32_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r1)= ); - tcg_gen_extu_reg_i64(s, cpu_sar); - tcg_gen_andi_i64(s, s, 31); - tcg_gen_shr_i64(t, t, s); - tcg_gen_trunc_i64_reg(dest, t); + tcg_gen_andi_i64(s, cpu_sar, 31); + tcg_gen_shr_i64(dest, t, s); } save_gpr(ctx, a->t, dest); =20 @@ -3196,10 +3178,8 @@ static bool trans_shrp_imm(DisasContext *ctx, arg_sh= rp_imm *a) tcg_gen_rotri_i32(t32, t32, sa); tcg_gen_extu_i32_i64(dest, t32); } else { - TCGv_i64 t64 =3D tcg_temp_new_i64(); - tcg_gen_concat32_i64(t64, t2, cpu_gr[a->r1]); - tcg_gen_shri_i64(t64, t64, sa); - tcg_gen_trunc_i64_reg(dest, t64); + tcg_gen_concat32_i64(dest, t2, cpu_gr[a->r1]); + tcg_gen_extract_i64(dest, dest, sa, 32); } } save_gpr(ctx, a->t, dest); --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697834909; cv=none; d=zohomail.com; s=zohoarc; b=SKxlyvW3bu9Q9m4wSHMMEl+Gcghosya4CxGjLEuv6BAGkE79hWsdTWUGtyRShyHRzJ5Shduw4/QXG8w6rTyk1SH/alDst4Ww1Svf9ZBgnF8ukq2qKlEpMVm40CL66KgKUcMTe+EpauzNV4vMwXhxTDdhIBL52q5MYZESFHtK5j0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697834909; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WKJ1rX2csZAHSD2ONgRe4DzUUuQ8vzDD7TOAEgOpleY=; b=SeTDMwo1A+B0IdQ9dmqe95ErlGj/mX7mpZ6OjIFUqC4yhQ/YDn1Di16BNji9/uAdGj9X0ttKtPxQivlQzm0YT64VvLNkw2H8r4ol971X+gSVCTKw+K1/DaHCWHgxs0CK1EcMiINigGY8zl2WyJKjN0lAoG/cs//8UWcyRQZwiSI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697834909459278.7807012034806; Fri, 20 Oct 2023 13:48:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwP1-00020J-2e; Fri, 20 Oct 2023 16:47:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwOx-0001tb-Kd for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:47:23 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwOt-0001BT-3A for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:47:23 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-6b9af7d41d2so1255577b3a.0 for ; Fri, 20 Oct 2023 13:47:18 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u7-20020aa78487000000b00694fee1011asm1946775pfn.208.2023.10.20.13.47.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:47:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834838; x=1698439638; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WKJ1rX2csZAHSD2ONgRe4DzUUuQ8vzDD7TOAEgOpleY=; b=rAjmMgi02nusBKIjx7rqWgTtoNItKFVn2p3evcbznI+JPDhUdix3ANpebFbkCWuobA VmZ4lIa+HyrQMgYiNI3obbVWdqcvNh/A9p59ixMqdHqNcgsjjB/SYbF1ryPo9G8uj3Yh Co33WW3kpN29SgUCkOHes6xnen6YJux1Nuc1mL2rnuQH3ek+u3AND0+zutG0Vu2UJNsZ CItToZEXuYvnFT6fdXfJ4Y9YHhjMTlSB/Trwcx7AtscodfJ5cmDT8YU5jOYl933nYMx0 T99zz56Scv+lO5bMu6UIgx8+QIujRstO/EgunZVicQcGfNLBTwo56orcjpIhI5ciCA+i Y+BA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834838; x=1698439638; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834910706100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 158 ++++++++++++++++++++-------------------- 1 file changed, 80 insertions(+), 78 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 95de007c69..fdd5fbdf0e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -32,6 +32,8 @@ #include "exec/helper-info.c.inc" #undef HELPER_H =20 +/* Choose to use explicit sizes within this file. */ +#undef tcg_temp_new =20 typedef struct DisasCond { TCGCond c; @@ -269,15 +271,15 @@ static DisasCond cond_make_0_tmp(TCGCond c, TCGv_i64 = a0) =20 static DisasCond cond_make_0(TCGCond c, TCGv_i64 a0) { - TCGv_i64 tmp =3D tcg_temp_new(); + TCGv_i64 tmp =3D tcg_temp_new_i64(); tcg_gen_mov_i64(tmp, a0); return cond_make_0_tmp(c, tmp); } =20 static DisasCond cond_make(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) { - TCGv_i64 t0 =3D tcg_temp_new(); - TCGv_i64 t1 =3D tcg_temp_new(); + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); =20 tcg_gen_mov_i64(t0, a0); tcg_gen_mov_i64(t1, a1); @@ -302,7 +304,7 @@ static void cond_free(DisasCond *cond) static TCGv_i64 load_gpr(DisasContext *ctx, unsigned reg) { if (reg =3D=3D 0) { - TCGv_i64 t =3D tcg_temp_new(); + TCGv_i64 t =3D tcg_temp_new_i64(); tcg_gen_movi_i64(t, 0); return t; } else { @@ -313,7 +315,7 @@ static TCGv_i64 load_gpr(DisasContext *ctx, unsigned re= g) static TCGv_i64 dest_gpr(DisasContext *ctx, unsigned reg) { if (reg =3D=3D 0 || ctx->null_cond.c !=3D TCG_COND_NEVER) { - return tcg_temp_new(); + return tcg_temp_new_i64(); } else { return cpu_gr[reg]; } @@ -437,7 +439,7 @@ static void nullify_over(DisasContext *ctx) =20 /* If we're using PSW[N], copy it to a temp because... */ if (ctx->null_cond.a0 =3D=3D cpu_psw_n) { - ctx->null_cond.a0 =3D tcg_temp_new(); + ctx->null_cond.a0 =3D tcg_temp_new_i64(); tcg_gen_mov_i64(ctx->null_cond.a0, cpu_psw_n); } /* ... we clear it before branching over the implementation, @@ -644,14 +646,14 @@ static DisasCond do_cond(DisasContext *ctx, unsigned = cf, bool d, break; case 1: /* =3D / <> (Z / !Z) */ if (cond_need_ext(ctx, d)) { - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_ext32u_i64(tmp, res); res =3D tmp; } cond =3D cond_make_0(TCG_COND_EQ, res); break; case 2: /* < / >=3D (N ^ V / !(N ^ V) */ - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_xor_i64(tmp, res, sv); if (cond_need_ext(ctx, d)) { tcg_gen_ext32s_i64(tmp, tmp); @@ -668,7 +670,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf= , bool d, * !(~(res ^ sv) >> 31) | !res * !(~(res ^ sv) >> 31 & res) */ - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_eqv_i64(tmp, res, sv); if (cond_need_ext(ctx, d)) { tcg_gen_sextract_i64(tmp, tmp, 31, 1); @@ -685,7 +687,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf= , bool d, cond =3D cond_make_0(TCG_COND_EQ, cb_msb); break; case 5: /* ZNV / VNZ (!C | Z / C & !Z) */ - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_neg_i64(tmp, cb_msb); tcg_gen_and_i64(tmp, tmp, res); if (cond_need_ext(ctx, d)) { @@ -695,14 +697,14 @@ static DisasCond do_cond(DisasContext *ctx, unsigned = cf, bool d, break; case 6: /* SV / NSV (V / !V) */ if (cond_need_ext(ctx, d)) { - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_ext32s_i64(tmp, sv); sv =3D tmp; } cond =3D cond_make_0(TCG_COND_LT, sv); break; case 7: /* OD / EV */ - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_andi_i64(tmp, res, 1); cond =3D cond_make_0_tmp(TCG_COND_NE, tmp); break; @@ -756,8 +758,8 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsigne= d cf, bool d, tc =3D tcg_invert_cond(tc); } if (cond_need_ext(ctx, d)) { - TCGv_i64 t1 =3D tcg_temp_new(); - TCGv_i64 t2 =3D tcg_temp_new(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i64 t2 =3D tcg_temp_new_i64(); =20 if (ext_uns) { tcg_gen_ext32u_i64(t1, in1); @@ -833,7 +835,7 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigne= d cf, bool d, } =20 if (cond_need_ext(ctx, d)) { - TCGv_i64 tmp =3D tcg_temp_new(); + TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 if (ext_uns) { tcg_gen_ext32u_i64(tmp, res); @@ -878,8 +880,8 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv= _i64 res, * do our normal thing and compute carry-in of bit B+1 since that * leaves us with carry bits spread across two words. */ - cb =3D tcg_temp_new(); - tmp =3D tcg_temp_new(); + cb =3D tcg_temp_new_i64(); + tmp =3D tcg_temp_new_i64(); tcg_gen_or_i64(cb, in1, in2); tcg_gen_and_i64(tmp, in1, in2); tcg_gen_andc_i64(cb, cb, res); @@ -897,7 +899,7 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv= _i64 res, /* See hasless(v,1) from * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord */ - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_subi_i64(tmp, res, d_repl * 0x01010101u); tcg_gen_andc_i64(tmp, tmp, res); tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80808080u); @@ -905,7 +907,7 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv= _i64 res, break; =20 case 3: /* SHZ / NHZ */ - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_subi_i64(tmp, res, d_repl * 0x00010001u); tcg_gen_andc_i64(tmp, tmp, res); tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80008000u); @@ -941,7 +943,7 @@ static TCGv_i64 get_carry(DisasContext *ctx, bool d, TCGv_i64 cb, TCGv_i64 cb_msb) { if (cond_need_ext(ctx, d)) { - TCGv_i64 t =3D tcg_temp_new(); + TCGv_i64 t =3D tcg_temp_new_i64(); tcg_gen_extract_i64(t, cb, 32, 1); return t; } @@ -957,8 +959,8 @@ static TCGv_i64 get_psw_carry(DisasContext *ctx, bool d) static TCGv_i64 do_add_sv(DisasContext *ctx, TCGv_i64 res, TCGv_i64 in1, TCGv_i64 in2) { - TCGv_i64 sv =3D tcg_temp_new(); - TCGv_i64 tmp =3D tcg_temp_new(); + TCGv_i64 sv =3D tcg_temp_new_i64(); + TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 tcg_gen_xor_i64(sv, res, in1); tcg_gen_xor_i64(tmp, in1, in2); @@ -971,8 +973,8 @@ static TCGv_i64 do_add_sv(DisasContext *ctx, TCGv_i64 r= es, static TCGv_i64 do_sub_sv(DisasContext *ctx, TCGv_i64 res, TCGv_i64 in1, TCGv_i64 in2) { - TCGv_i64 sv =3D tcg_temp_new(); - TCGv_i64 tmp =3D tcg_temp_new(); + TCGv_i64 sv =3D tcg_temp_new_i64(); + TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 tcg_gen_xor_i64(sv, res, in1); tcg_gen_xor_i64(tmp, in1, in2); @@ -989,21 +991,21 @@ static void do_add(DisasContext *ctx, unsigned rt, TC= Gv_i64 in1, unsigned c =3D cf >> 1; DisasCond cond; =20 - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); cb =3D NULL; cb_msb =3D NULL; cb_cond =3D NULL; =20 if (shift) { - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_shli_i64(tmp, in1, shift); in1 =3D tmp; } =20 if (!is_l || cond_need_cb(c)) { TCGv_i64 zero =3D tcg_constant_i64(0); - cb_msb =3D tcg_temp_new(); - cb =3D tcg_temp_new(); + cb_msb =3D tcg_temp_new_i64(); + cb =3D tcg_temp_new_i64(); =20 tcg_gen_add2_i64(dest, cb_msb, in1, zero, in2, zero); if (is_c) { @@ -1035,7 +1037,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TC= Gv_i64 in1, /* Emit any conditional trap before any writeback. */ cond =3D do_cond(ctx, cf, d, dest, cb_cond, sv); if (is_tc) { - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(tcg_env, tmp); } @@ -1090,9 +1092,9 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_i64 in1, unsigned c =3D cf >> 1; DisasCond cond; =20 - dest =3D tcg_temp_new(); - cb =3D tcg_temp_new(); - cb_msb =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); + cb =3D tcg_temp_new_i64(); + cb_msb =3D tcg_temp_new_i64(); =20 zero =3D tcg_constant_i64(0); if (is_b) { @@ -1131,7 +1133,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_i64 in1, =20 /* Emit any conditional trap before any writeback. */ if (is_tc) { - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(tcg_env, tmp); } @@ -1180,7 +1182,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt,= TCGv_i64 in1, TCGv_i64 dest, sv; DisasCond cond; =20 - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); tcg_gen_sub_i64(dest, in1, in2); =20 /* Compute signed overflow if required. */ @@ -1245,13 +1247,13 @@ static void do_unit(DisasContext *ctx, unsigned rt,= TCGv_i64 in1, save_gpr(ctx, rt, dest); cond_free(&ctx->null_cond); } else { - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); fn(dest, in1, in2); =20 cond =3D do_unit_cond(cf, d, dest, in1, in2); =20 if (is_tc) { - TCGv_i64 tmp =3D tcg_temp_new(); + TCGv_i64 tmp =3D tcg_temp_new_i64(); tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(tcg_env, tmp); } @@ -1286,7 +1288,7 @@ static TCGv_i64 space_select(DisasContext *ctx, int s= p, TCGv_i64 base) } =20 ptr =3D tcg_temp_new_ptr(); - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); spc =3D tcg_temp_new_i64(); =20 /* Extract top 2 bits of the address, shift left 3 for uint64_t index.= */ @@ -1311,11 +1313,11 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *p= gva, TCGv_i64 *pofs, =20 /* Note that RX is mutually exclusive with DISP. */ if (rx) { - ofs =3D tcg_temp_new(); + ofs =3D tcg_temp_new_i64(); tcg_gen_shli_i64(ofs, cpu_gr[rx], scale); tcg_gen_add_i64(ofs, ofs, base); } else if (disp || modify) { - ofs =3D tcg_temp_new(); + ofs =3D tcg_temp_new_i64(); tcg_gen_addi_i64(ofs, base, disp); } else { ofs =3D base; @@ -1421,7 +1423,7 @@ static bool do_load(DisasContext *ctx, unsigned rt, u= nsigned rb, dest =3D dest_gpr(ctx, rt); } else { /* Make sure if RT =3D=3D RB, we see the result of the load. */ - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); } do_load_64(ctx, dest, rb, rx, scale, disp, sp, modify, mop); save_gpr(ctx, rt, dest); @@ -1737,7 +1739,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 de= st, if (link !=3D 0) { copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); } - next =3D tcg_temp_new(); + next =3D tcg_temp_new_i64(); tcg_gen_mov_i64(next, dest); if (is_n) { if (use_nullify_skip(ctx)) { @@ -1778,8 +1780,8 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 de= st, a0 =3D ctx->null_cond.a0; a1 =3D ctx->null_cond.a1; =20 - tmp =3D tcg_temp_new(); - next =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); + next =3D tcg_temp_new_i64(); =20 copy_iaoq_entry(tmp, ctx->iaoq_n, ctx->iaoq_n_var); tcg_gen_movcond_i64(c, next, a0, a1, tmp, dest); @@ -1821,11 +1823,11 @@ static TCGv_i64 do_ibranch_priv(DisasContext *ctx, = TCGv_i64 offset) return offset; case 3: /* Privilege 3 is minimum and is never allowed to increase. */ - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); tcg_gen_ori_i64(dest, offset, 3); break; default: - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); tcg_gen_andi_i64(dest, offset, -4); tcg_gen_ori_i64(dest, dest, ctx->privilege); tcg_gen_movcond_i64(TCG_COND_GTU, dest, dest, offset, dest, offset= ); @@ -1983,7 +1985,7 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl = *a) break; } =20 - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); save_gpr(ctx, rt, tmp); =20 @@ -2024,7 +2026,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl = *a) =20 if (ctl =3D=3D CR_SAR) { reg =3D load_gpr(ctx, a->r); - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_andi_i64(tmp, reg, ctx->is_pa20 ? 63 : 31); save_or_nullify(ctx, cpu_sar, tmp); =20 @@ -2055,7 +2057,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl = *a) case CR_IIAOQ: /* FIXME: Respect PSW_Q bit */ /* The write advances the queue and stores to the back element. */ - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); @@ -2083,7 +2085,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl = *a) =20 static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a) { - TCGv_i64 tmp =3D tcg_temp_new(); + TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 tcg_gen_not_i64(tmp, load_gpr(ctx, a->r)); tcg_gen_andi_i64(tmp, tmp, ctx->is_pa20 ? 63 : 31); @@ -2118,7 +2120,7 @@ static bool trans_rsm(DisasContext *ctx, arg_rsm *a) =20 nullify_over(ctx); =20 - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw)); tcg_gen_andi_i64(tmp, tmp, ~a->i); gen_helper_swap_system_mask(tmp, tcg_env, tmp); @@ -2138,7 +2140,7 @@ static bool trans_ssm(DisasContext *ctx, arg_ssm *a) =20 nullify_over(ctx); =20 - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw)); tcg_gen_ori_i64(tmp, tmp, a->i); gen_helper_swap_system_mask(tmp, tcg_env, tmp); @@ -2158,7 +2160,7 @@ static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a) nullify_over(ctx); =20 reg =3D load_gpr(ctx, a->r); - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); gen_helper_swap_system_mask(tmp, tcg_env, reg); =20 /* Exit the TB to recognize new interrupts. */ @@ -2406,7 +2408,7 @@ static bool trans_lpa(DisasContext *ctx, arg_ldst *a) =20 form_gva(ctx, &vaddr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false); =20 - paddr =3D tcg_temp_new(); + paddr =3D tcg_temp_new_i64(); gen_helper_lpa(paddr, tcg_env, vaddr); =20 /* Note that physical address result overrides base modification. */ @@ -2590,7 +2592,7 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d= *a, bool is_tc) } tcg_r1 =3D load_gpr(ctx, a->r1); tcg_r2 =3D load_gpr(ctx, a->r2); - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_not_i64(tmp, tcg_r2); do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_i64); return nullify_end(ctx); @@ -2612,7 +2614,7 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a= , bool is_i) =20 nullify_over(ctx); =20 - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_shri_i64(tmp, cpu_psw_cb, 3); if (!is_i) { tcg_gen_not_i64(tmp, tmp); @@ -2644,10 +2646,10 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf = *a) in1 =3D load_gpr(ctx, a->r1); in2 =3D load_gpr(ctx, a->r2); =20 - add1 =3D tcg_temp_new(); - add2 =3D tcg_temp_new(); - addc =3D tcg_temp_new(); - dest =3D tcg_temp_new(); + add1 =3D tcg_temp_new_i64(); + add2 =3D tcg_temp_new_i64(); + addc =3D tcg_temp_new_i64(); + dest =3D tcg_temp_new_i64(); zero =3D tcg_constant_i64(0); =20 /* Form R1 << 1 | PSW[CB]{8}. */ @@ -2770,7 +2772,7 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) if (a->m) { /* Base register modification. Make sure if RT =3D=3D RB, we see the result of the load. */ - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); } else { dest =3D dest_gpr(ctx, a->t); } @@ -2927,7 +2929,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TC= Gv_i64 in1, DisasCond cond; =20 in2 =3D load_gpr(ctx, r); - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); =20 tcg_gen_sub_i64(dest, in1, in2); =20 @@ -2979,13 +2981,13 @@ static bool do_addb(DisasContext *ctx, unsigned r, = TCGv_i64 in1, } =20 in2 =3D load_gpr(ctx, r); - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); sv =3D NULL; cb_cond =3D NULL; =20 if (cond_need_cb(c)) { - TCGv_i64 cb =3D tcg_temp_new(); - TCGv_i64 cb_msb =3D tcg_temp_new(); + TCGv_i64 cb =3D tcg_temp_new_i64(); + TCGv_i64 cb_msb =3D tcg_temp_new_i64(); =20 tcg_gen_movi_i64(cb_msb, 0); tcg_gen_add2_i64(dest, cb_msb, in1, cb_msb, in2, cb_msb); @@ -3023,7 +3025,7 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sa= r *a) =20 nullify_over(ctx); =20 - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_r =3D load_gpr(ctx, a->r); if (cond_need_ext(ctx, a->d)) { /* Force shift into [32,63] */ @@ -3045,7 +3047,7 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_im= m *a) =20 nullify_over(ctx); =20 - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_r =3D load_gpr(ctx, a->r); p =3D a->p | (cond_need_ext(ctx, a->d) ? 32 : 0); tcg_gen_shli_i64(tmp, tcg_r, p); @@ -3105,7 +3107,7 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shr= p_sar *a) tcg_gen_shr_i64(dest, dest, cpu_sar); } else { tcg_gen_ext32u_i64(dest, load_gpr(ctx, a->r2)); - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_andi_i64(tmp, cpu_sar, 31); tcg_gen_shr_i64(dest, dest, tmp); } @@ -3123,8 +3125,8 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shr= p_sar *a) tcg_gen_extu_i32_i64(dest, t32); } } else if (a->d) { - TCGv_i64 t =3D tcg_temp_new(); - TCGv_i64 n =3D tcg_temp_new(); + TCGv_i64 t =3D tcg_temp_new_i64(); + TCGv_i64 n =3D tcg_temp_new_i64(); =20 tcg_gen_xori_i64(n, cpu_sar, 63); tcg_gen_shl_i64(t, load_gpr(ctx, a->r2), n); @@ -3206,7 +3208,7 @@ static bool trans_extr_sar(DisasContext *ctx, arg_ext= r_sar *a) =20 dest =3D dest_gpr(ctx, a->t); src =3D load_gpr(ctx, a->r); - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); =20 /* Recall that SAR is using big-endian bit numbering. */ tcg_gen_andi_i64(tmp, cpu_sar, widthm1); @@ -3350,14 +3352,14 @@ static bool do_dep_sar(DisasContext *ctx, unsigned = rt, unsigned c, uint64_t msb =3D 1ULL << (len - 1); =20 dest =3D dest_gpr(ctx, rt); - shift =3D tcg_temp_new(); - tmp =3D tcg_temp_new(); + shift =3D tcg_temp_new_i64(); + tmp =3D tcg_temp_new_i64(); =20 /* Convert big-endian bit numbering in SAR to left-shift. */ tcg_gen_andi_i64(shift, cpu_sar, widthm1); tcg_gen_xori_i64(shift, shift, widthm1); =20 - mask =3D tcg_temp_new(); + mask =3D tcg_temp_new_i64(); tcg_gen_movi_i64(mask, msb + (msb - 1)); tcg_gen_and_i64(tmp, val, mask); if (rs) { @@ -3422,7 +3424,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a) nullify_over(ctx); #endif =20 - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_addi_i64(tmp, load_gpr(ctx, a->b), a->disp); tmp =3D do_ibranch_priv(ctx, tmp); =20 @@ -3519,7 +3521,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gat= e *a) static bool trans_blr(DisasContext *ctx, arg_blr *a) { if (a->x) { - TCGv_i64 tmp =3D tcg_temp_new(); + TCGv_i64 tmp =3D tcg_temp_new_i64(); tcg_gen_shli_i64(tmp, load_gpr(ctx, a->x), 3); tcg_gen_addi_i64(tmp, tmp, ctx->iaoq_f + 8); /* The computation here never changes privilege level. */ @@ -3537,7 +3539,7 @@ static bool trans_bv(DisasContext *ctx, arg_bv *a) if (a->x =3D=3D 0) { dest =3D load_gpr(ctx, a->b); } else { - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); tcg_gen_shli_i64(dest, load_gpr(ctx, a->x), 3); tcg_gen_add_i64(dest, dest, load_gpr(ctx, a->b)); } @@ -3874,7 +3876,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest = *a) =20 nullify_over(ctx); =20 - t =3D tcg_temp_new(); + t =3D tcg_temp_new_i64(); tcg_gen_ld32u_i64(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow)); =20 if (a->y =3D=3D 1) { @@ -4175,7 +4177,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) This will be overwritten by a branch. */ if (ctx->iaoq_b =3D=3D -1) { ctx->iaoq_n =3D -1; - ctx->iaoq_n_var =3D tcg_temp_new(); + ctx->iaoq_n_var =3D tcg_temp_new_i64(); tcg_gen_addi_i64(ctx->iaoq_n_var, cpu_iaoq_b, 4); } else { ctx->iaoq_n =3D ctx->iaoq_b + 4; --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835245; cv=none; d=zohomail.com; s=zohoarc; b=Lur0w4L4GCiSA/6VHZRi4lJB9MW0a3CIMljhEJlnVCdFBMXqOZBZfdROrAd9deN7SpT+0r1EUj5KkRS901v8HHqiuFTk5gdotEeAnNLVWSNsGOPiYx6qXh+jKzaryz1Of82K+OXXMDkIUpqE7RXKthLYzg2bMmRkzwcmlVePT10= ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u7-20020aa78487000000b00694fee1011asm1946775pfn.208.2023.10.20.13.47.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:47:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834838; x=1698439638; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SFd9Qh9JL6hOySCuo3z5YneGJwqmFS+MfoCbYZFAQuw=; b=gBm06ICHR8rAcziMlETWL1/VU8FGsZ1WR+L2WLIfXNZD7ABupqbh428kXC5C2sym/g j7HjY7QS3iPvPB5sA7aqTGvroMB0kRB8VTIFEz9agnfako6ReKWODml5OXW4r0UbxMcN nm4TKvie7aC0gWNkpMY2/E3eYwLde/GAKdbmR4ujEa7IAflfQCECUUcOQ+0uRpvfjQ8F TqfgCVluy5xX/Nytklt3NVkroEzZLoGOSiIAxUdDkRdytYVVudC5fIPE+y4nqlHKD6O7 YiYxp0ChPuKmNh54yOCgYnZahvkyYptiD00BBZoN2KKxlMIx7O0ETUO2q6paLjWRifCP Nd8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834838; x=1698439638; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SFd9Qh9JL6hOySCuo3z5YneGJwqmFS+MfoCbYZFAQuw=; b=WCvCdV3rg5y8uw+qNL/BLFSmwFcIqQiDjz4aZTZ49gk1tUgBzPXZtOsevEhS8wzt83 sgpWv+1iJVJB5zpA3qGqABO/8Xnik1sdCCBZLmtRuozaQGoSHbEe0wGIptxpEzQQgoeZ 8fkXwJ3Fokj9/JKMgcU5XmqDEEtRpAXc11QvgLh7zpzMCvdAKoLh20xTtfMl3j+CO40J kCttPb4adH+gpes7Y/SKFKdpdClfeMTYdxFWTh0KBPwAnhHZ/GmjQC/DUbX6pAQeNXja X3HZdEAsXS+nStGsfjL1LzFoR1TUCZ2lrCY17R071H+8KwKTQRXHjf7kFUsWJ739RCR4 vDrw== X-Gm-Message-State: AOJu0YzvRYPXpeoC14Zo5hf1cGz/Az7WhcckRWxMt9qpUe81+NLHry7q wpPkMPCFfD3TjnGSEus9236l69fUmdQ4+6CmyZM= X-Google-Smtp-Source: AGHT+IHvuOkkUjJiCp2Qj+WvSAvC1ne3XGyO3owI9+MW+88EvK+RpMDC6v+ZXkqqouz6lpEpGWkXDQ== X-Received: by 2002:a05:6a00:134b:b0:690:422f:4f17 with SMTP id k11-20020a056a00134b00b00690422f4f17mr3186059pfu.4.1697834838633; Fri, 20 Oct 2023 13:47:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 51/65] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64 Date: Fri, 20 Oct 2023 13:43:17 -0700 Message-Id: <20231020204331.139847-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835245695100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index fdd5fbdf0e..16d42ae328 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1325,10 +1325,10 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *p= gva, TCGv_i64 *pofs, =20 *pofs =3D ofs; *pgva =3D addr =3D tcg_temp_new_i64(); - tcg_gen_andi_tl(addr, modify <=3D 0 ? ofs : base, gva_offset_mask(ctx)= ); + tcg_gen_andi_i64(addr, modify <=3D 0 ? ofs : base, gva_offset_mask(ctx= )); #ifndef CONFIG_USER_ONLY if (!is_phys) { - tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base)); + tcg_gen_or_i64(addr, addr, space_select(ctx, sp, base)); } #endif } @@ -2361,7 +2361,7 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtl= bxf *a) a->data ? offsetof(CPUHPPAState, cr[CR_IOR]) : offsetof(CPUHPPAState, cr[CR_IIAOQ])); tcg_gen_shli_i64(stl, stl, 32); - tcg_gen_or_tl(addr, atl, stl); + tcg_gen_or_i64(addr, atl, stl); =20 reg =3D load_gpr(ctx, a->r); if (a->addr) { @@ -2911,7 +2911,7 @@ static bool trans_ldo(DisasContext *ctx, arg_ldo *a) TCGv_i64 tcg_rt =3D dest_gpr(ctx, a->t); =20 /* Special case rb =3D=3D 0, for the LDI pseudo-op. - The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */ + The COPY pseudo-op is handled for free within tcg_gen_addi_i64. */ if (a->b =3D=3D 0) { tcg_gen_movi_i64(tcg_rt, a->i); } else { --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697834941; cv=none; d=zohomail.com; s=zohoarc; b=R1UiFS2fDAx+AgXb2JLvNLRI1emsqWk3ka6yTOp4onyXIkPbik+ITijOEUZV+hrjdmJh4PeQ/gmRtSjH1Ov423IGxDoyTnxbxY9aj1t3t25REqgQiePHlavCuuL1uynXheRAlOy8AD4JK15E7G5MGCCD9paIY96kT/CfW+ecS/U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697834941; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=eyKRvcSVwIZRGZOCNbFmD7+eSOO/DoyIuLiNzQZCvfw=; b=IQKACtlC1h79Dsbx2p7K+4IQBAoOyaurOUXRfZ3FQoklXFHnN9CrJWsg6j1FmnOxavt33mLe3nQioq6PPu6MdZUxUFnlWBzEYgJfpHF9rMQXXdQSGJOOeKYxl9zcTnWO7FH0akkcePM+g/s5DRGClnrzv20wccBSyxwdVD1biyA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169783494195551.59045688021456; Fri, 20 Oct 2023 13:49:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwOz-0001ye-Ll; Fri, 20 Oct 2023 16:47:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwOx-0001te-Lb for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:47:23 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwOu-0001C0-RV for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:47:23 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-6b2018a11efso1192473b3a.0 for ; Fri, 20 Oct 2023 13:47:20 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834942715100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/helper.h | 3 +++ target/hppa/insns.decode | 8 +++++++- target/hppa/op_helper.c | 32 ++++++++++++++++++++++++++++++++ target/hppa/translate.c | 37 +++++++++++++++++++++++++++++++++++++ 4 files changed, 79 insertions(+), 1 deletion(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 4b2c66316f..ff2695797e 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -14,6 +14,9 @@ DEF_HELPER_FLAGS_3(stdby_e_parallel, TCG_CALL_NO_WG, void= , env, tl, tl) =20 DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl) =20 +DEF_HELPER_FLAGS_2(hadd_ss, TCG_CALL_NO_RWG, i64, i64, i64) +DEF_HELPER_FLAGS_2(hadd_us, TCG_CALL_NO_RWG, i64, i64, i64) + DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tl, env, tl, i32, i32) =20 DEF_HELPER_FLAGS_1(loaded_fr0, TCG_CALL_NO_RWG, void, env) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index db1b9f750f..88248ed3e2 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -65,6 +65,7 @@ &ldst t b x disp sp m scale size =20 &rr_cf_d t r cf d +&rrr t r1 r2 &rrr_cf t r1 r2 cf &rrr_cf_d t r1 r2 cf d &rrr_cf_d_sh t r1 r2 cf d sh @@ -81,6 +82,7 @@ #### =20 @rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d +@rrr ...... r2:5 r1:5 .... ....... t:5 &rrr @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf @rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d @rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh @@ -208,6 +210,10 @@ subi_tsv 100101 ..... ..... .... 1 ........... = @rri_cf =20 cmpiclr 100100 ..... ..... .... . ........... @rri_cf_d =20 +hadd 000010 ..... ..... 00000011 11 0 ..... @rrr +hadd_ss 000010 ..... ..... 00000011 01 0 ..... @rrr +hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr + #### # Index Mem #### @@ -429,7 +435,7 @@ fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:= 1 t:5 ra3=3D%rc32 =20 @f0e_f_3 ...... ..... ..... ... .0 110 ..0 ..... \ &fclass3 r1=3D%ra64 r2=3D%rb64 t=3D%rt64 -@f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5 +@f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5 &fclass3 =20 # Floating point class 0 =20 diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 0bccca1e11..a230a3a0c3 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -377,3 +377,35 @@ target_ulong HELPER(read_interval_timer)(void) return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >> 2; #endif } + +uint64_t HELPER(hadd_ss)(uint64_t r1, uint64_t r2) +{ + uint64_t ret =3D 0; + + for (int i =3D 0; i < 64; i +=3D 16) { + int f1 =3D sextract64(r1, i, 16); + int f2 =3D sextract64(r2, i, 16); + int fr =3D f1 + f2; + + fr =3D MIN(fr, INT16_MAX); + fr =3D MAX(fr, INT16_MIN); + ret =3D deposit64(ret, i, 16, fr); + } + return ret; +} + +uint64_t HELPER(hadd_us)(uint64_t r1, uint64_t r2) +{ + uint64_t ret =3D 0; + + for (int i =3D 0; i < 64; i +=3D 16) { + int f1 =3D extract64(r1, i, 16); + int f2 =3D sextract64(r2, i, 16); + int fr =3D f1 + f2; + + fr =3D MIN(fr, UINT16_MAX); + fr =3D MAX(fr, 0); + ret =3D deposit64(ret, i, 16, fr); + } + return ret; +} diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 16d42ae328..0d72c96fd5 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -23,6 +23,7 @@ #include "qemu/host-utils.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "exec/translator.h" @@ -2739,6 +2740,42 @@ static bool trans_cmpiclr(DisasContext *ctx, arg_rri= _cf_d *a) return nullify_end(ctx); } =20 +static bool do_multimedia(DisasContext *ctx, arg_rrr *a, + void (*fn)(TCGv_i64, TCGv_i64, TCGv_i64)) +{ + TCGv_i64 r1, r2, dest; + + if (!ctx->is_pa20) { + return false; + } + + nullify_over(ctx); + + r1 =3D load_gpr(ctx, a->r1); + r2 =3D load_gpr(ctx, a->r2); + dest =3D dest_gpr(ctx, a->t); + + fn(dest, r1, r2); + save_gpr(ctx, a->t, dest); + + return nullify_end(ctx); +} + +static bool trans_hadd(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, tcg_gen_vec_add16_i64); +} + +static bool trans_hadd_ss(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, gen_helper_hadd_ss); +} + +static bool trans_hadd_us(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, gen_helper_hadd_us); +} + static bool trans_ld(DisasContext *ctx, arg_ldst *a) { if (!ctx->is_pa20 && a->size > MO_32) { --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697834982960100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/helper.h | 2 ++ target/hppa/insns.decode | 4 ++++ target/hppa/op_helper.c | 32 ++++++++++++++++++++++++++++++++ target/hppa/translate.c | 15 +++++++++++++++ 4 files changed, 53 insertions(+) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index ff2695797e..99486f4cf8 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -16,6 +16,8 @@ DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl) =20 DEF_HELPER_FLAGS_2(hadd_ss, TCG_CALL_NO_RWG, i64, i64, i64) DEF_HELPER_FLAGS_2(hadd_us, TCG_CALL_NO_RWG, i64, i64, i64) +DEF_HELPER_FLAGS_2(hsub_ss, TCG_CALL_NO_RWG, i64, i64, i64) +DEF_HELPER_FLAGS_2(hsub_us, TCG_CALL_NO_RWG, i64, i64, i64) =20 DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tl, env, tl, i32, i32) =20 diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 88248ed3e2..1830b06c76 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -214,6 +214,10 @@ hadd 000010 ..... ..... 00000011 11 0 .....= @rrr hadd_ss 000010 ..... ..... 00000011 01 0 ..... @rrr hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr =20 +hsub 000010 ..... ..... 00000001 11 0 ..... @rrr +hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr +hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr + #### # Index Mem #### diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index a230a3a0c3..ece523bea0 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -409,3 +409,35 @@ uint64_t HELPER(hadd_us)(uint64_t r1, uint64_t r2) } return ret; } + +uint64_t HELPER(hsub_ss)(uint64_t r1, uint64_t r2) +{ + uint64_t ret =3D 0; + + for (int i =3D 0; i < 64; i +=3D 16) { + int f1 =3D sextract64(r1, i, 16); + int f2 =3D sextract64(r2, i, 16); + int fr =3D f1 - f2; + + fr =3D MIN(fr, INT16_MAX); + fr =3D MAX(fr, INT16_MIN); + ret =3D deposit64(ret, i, 16, fr); + } + return ret; +} + +uint64_t HELPER(hsub_us)(uint64_t r1, uint64_t r2) +{ + uint64_t ret =3D 0; + + for (int i =3D 0; i < 64; i +=3D 16) { + int f1 =3D extract64(r1, i, 16); + int f2 =3D sextract64(r2, i, 16); + int fr =3D f1 - f2; + + fr =3D MIN(fr, UINT16_MAX); + fr =3D MAX(fr, 0); + ret =3D deposit64(ret, i, 16, fr); + } + return ret; +} diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 0d72c96fd5..63c6a28cef 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2776,6 +2776,21 @@ static bool trans_hadd_us(DisasContext *ctx, arg_rrr= *a) return do_multimedia(ctx, a, gen_helper_hadd_us); } =20 +static bool trans_hsub(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, tcg_gen_vec_sub16_i64); +} + +static bool trans_hsub_ss(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, gen_helper_hsub_ss); +} + +static bool trans_hsub_us(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, gen_helper_hsub_us); +} + static bool trans_ld(DisasContext *ctx, arg_ldst *a) { if (!ctx->is_pa20 && a->size > MO_32) { --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835055; cv=none; d=zohomail.com; s=zohoarc; b=XuI7wImP+Onm+8MFZ8K3ZuK5bqSWyCpT71P9dOZlmRvN836zk3QXG0RpGmFq7pdqbYTpRAzyE8tVmqckzX5jFejrP+ApxsO/ADZsvuHoab+PtOUhtVioqNx/hpcnhxnDVaFsOiF41Y3UJ7IgGxQRpinA4CsKGtt22XnUv7Aiws4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835057048100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/helper.h | 1 + target/hppa/insns.decode | 2 ++ target/hppa/op_helper.c | 14 ++++++++++++++ target/hppa/translate.c | 5 +++++ 4 files changed, 22 insertions(+) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 99486f4cf8..1feb2fdfc4 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -16,6 +16,7 @@ DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl) =20 DEF_HELPER_FLAGS_2(hadd_ss, TCG_CALL_NO_RWG, i64, i64, i64) DEF_HELPER_FLAGS_2(hadd_us, TCG_CALL_NO_RWG, i64, i64, i64) +DEF_HELPER_FLAGS_2(havg, TCG_CALL_NO_RWG, i64, i64, i64) DEF_HELPER_FLAGS_2(hsub_ss, TCG_CALL_NO_RWG, i64, i64, i64) DEF_HELPER_FLAGS_2(hsub_us, TCG_CALL_NO_RWG, i64, i64, i64) =20 diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 1830b06c76..fb0f9d6dbd 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -214,6 +214,8 @@ hadd 000010 ..... ..... 00000011 11 0 ..... = @rrr hadd_ss 000010 ..... ..... 00000011 01 0 ..... @rrr hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr =20 +havg 000010 ..... ..... 00000010 11 0 ..... @rrr + hsub 000010 ..... ..... 00000001 11 0 ..... @rrr hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index ece523bea0..cba610ac75 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -410,6 +410,20 @@ uint64_t HELPER(hadd_us)(uint64_t r1, uint64_t r2) return ret; } =20 +uint64_t HELPER(havg)(uint64_t r1, uint64_t r2) +{ + uint64_t ret =3D 0; + + for (int i =3D 0; i < 64; i +=3D 16) { + int f1 =3D extract64(r1, i, 16); + int f2 =3D extract64(r2, i, 16); + int fr =3D f1 + f2; + + ret =3D deposit64(ret, i, 16, (fr >> 1) | (fr & 1)); + } + return ret; +} + uint64_t HELPER(hsub_ss)(uint64_t r1, uint64_t r2) { uint64_t ret =3D 0; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 63c6a28cef..c1ca4db099 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2776,6 +2776,11 @@ static bool trans_hadd_us(DisasContext *ctx, arg_rrr= *a) return do_multimedia(ctx, a, gen_helper_hadd_us); } =20 +static bool trans_havg(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, gen_helper_havg); +} + static bool trans_hsub(DisasContext *ctx, arg_rrr *a) { return do_multimedia(ctx, a, tcg_gen_vec_sub16_i64); --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835408356100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 5 +++++ target/hppa/translate.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index fb0f9d6dbd..f0c4866ca2 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -69,6 +69,7 @@ &rrr_cf t r1 r2 cf &rrr_cf_d t r1 r2 cf d &rrr_cf_d_sh t r1 r2 cf d sh +&rri t r i &rri_cf t r i cf &rri_cf_d t r i cf d =20 @@ -216,6 +217,10 @@ hadd_us 000010 ..... ..... 00000011 00 0 .....= @rrr =20 havg 000010 ..... ..... 00000010 11 0 ..... @rrr =20 +hshl 111110 00000 r:5 100010 i:4 0 t:5 &rri +hshr_s 111110 r:5 00000 110011 i:4 0 t:5 &rri +hshr_u 111110 r:5 00000 110010 i:4 0 t:5 &rri + hsub 000010 ..... ..... 00000001 11 0 ..... @rrr hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c1ca4db099..353d51cc8b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2761,6 +2761,26 @@ static bool do_multimedia(DisasContext *ctx, arg_rrr= *a, return nullify_end(ctx); } =20 +static bool do_multimedia_sh(DisasContext *ctx, arg_rri *a, + void (*fn)(TCGv_i64, TCGv_i64, int64_t)) +{ + TCGv_i64 r, dest; + + if (!ctx->is_pa20) { + return false; + } + + nullify_over(ctx); + + r =3D load_gpr(ctx, a->r); + dest =3D dest_gpr(ctx, a->t); + + fn(dest, r, a->i); + save_gpr(ctx, a->t, dest); + + return nullify_end(ctx); +} + static bool trans_hadd(DisasContext *ctx, arg_rrr *a) { return do_multimedia(ctx, a, tcg_gen_vec_add16_i64); @@ -2781,6 +2801,21 @@ static bool trans_havg(DisasContext *ctx, arg_rrr *a) return do_multimedia(ctx, a, gen_helper_havg); } =20 +static bool trans_hshl(DisasContext *ctx, arg_rri *a) +{ + return do_multimedia_sh(ctx, a, tcg_gen_vec_shl16i_i64); +} + +static bool trans_hshr_s(DisasContext *ctx, arg_rri *a) +{ + return do_multimedia_sh(ctx, a, tcg_gen_vec_sar16i_i64); +} + +static bool trans_hshr_u(DisasContext *ctx, arg_rri *a) +{ + return do_multimedia_sh(ctx, a, tcg_gen_vec_shr16i_i64); +} + static bool trans_hsub(DisasContext *ctx, arg_rrr *a) { return do_multimedia(ctx, a, tcg_gen_vec_sub16_i64); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835095220100004 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/helper.h | 2 ++ target/hppa/insns.decode | 12 ++++++++++-- target/hppa/op_helper.c | 32 ++++++++++++++++++++++++++++++++ target/hppa/translate.c | 32 ++++++++++++++++++++++++++++++++ 4 files changed, 76 insertions(+), 2 deletions(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 1feb2fdfc4..c4c3093a83 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -17,6 +17,8 @@ DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl) DEF_HELPER_FLAGS_2(hadd_ss, TCG_CALL_NO_RWG, i64, i64, i64) DEF_HELPER_FLAGS_2(hadd_us, TCG_CALL_NO_RWG, i64, i64, i64) DEF_HELPER_FLAGS_2(havg, TCG_CALL_NO_RWG, i64, i64, i64) +DEF_HELPER_FLAGS_3(hshladd, TCG_CALL_NO_RWG, i64, i64, i64, i32) +DEF_HELPER_FLAGS_3(hshradd, TCG_CALL_NO_RWG, i64, i64, i64, i32) DEF_HELPER_FLAGS_2(hsub_ss, TCG_CALL_NO_RWG, i64, i64, i64) DEF_HELPER_FLAGS_2(hsub_us, TCG_CALL_NO_RWG, i64, i64, i64) =20 diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index f0c4866ca2..d7befbf73d 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -68,6 +68,7 @@ &rrr t r1 r2 &rrr_cf t r1 r2 cf &rrr_cf_d t r1 r2 cf d +&rrr_sh t r1 r2 sh &rrr_cf_d_sh t r1 r2 cf d sh &rri t r i &rri_cf t r i cf @@ -86,6 +87,7 @@ @rrr ...... r2:5 r1:5 .... ....... t:5 &rrr @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf @rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d +@rrr_sh ...... r2:5 r1:5 ........ sh:2 . t:5 &rrr_sh @rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh @rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=3D0 @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=3D%lowsi= gn_11 @@ -187,14 +189,20 @@ dcor_i 000010 ..... 00000 .... 101111 . ....= . @rr_cf_d add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh -add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0 +{ + add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0 + hshladd 000010 ..... ..... 0000 0111.. 0 ..... @rrr_sh +} add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0 =20 sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d -sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d +{ + sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d + hshradd 000010 ..... ..... 0000 0101.. 0 ..... @rrr_sh +} sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d =20 ldil 001000 t:5 ..................... i=3D%assemble_21 diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index cba610ac75..9d8e728460 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -455,3 +455,35 @@ uint64_t HELPER(hsub_us)(uint64_t r1, uint64_t r2) } return ret; } + +uint64_t HELPER(hshladd)(uint64_t r1, uint64_t r2, uint32_t sh) +{ + uint64_t ret =3D 0; + + for (int i =3D 0; i < 64; i +=3D 16) { + int f1 =3D sextract64(r1, i, 16); + int f2 =3D sextract64(r2, i, 16); + int fr =3D (f1 << sh) + f2; + + fr =3D MIN(fr, INT16_MAX); + fr =3D MAX(fr, INT16_MIN); + ret =3D deposit64(ret, i, 16, fr); + } + return ret; +} + +uint64_t HELPER(hshradd)(uint64_t r1, uint64_t r2, uint32_t sh) +{ + uint64_t ret =3D 0; + + for (int i =3D 0; i < 64; i +=3D 16) { + int f1 =3D sextract64(r1, i, 16); + int f2 =3D sextract64(r2, i, 16); + int fr =3D (f1 >> sh) + f2; + + fr =3D MIN(fr, INT16_MAX); + fr =3D MAX(fr, INT16_MIN); + ret =3D deposit64(ret, i, 16, fr); + } + return ret; +} diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 353d51cc8b..47abed1662 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2781,6 +2781,28 @@ static bool do_multimedia_sh(DisasContext *ctx, arg_= rri *a, return nullify_end(ctx); } =20 +static bool do_multimedia_shadd(DisasContext *ctx, arg_rrr_sh *a, + void (*fn)(TCGv_i64, TCGv_i64, + TCGv_i64, TCGv_i32)) +{ + TCGv_i64 r1, r2, dest; + + if (!ctx->is_pa20) { + return false; + } + + nullify_over(ctx); + + r1 =3D load_gpr(ctx, a->r1); + r2 =3D load_gpr(ctx, a->r2); + dest =3D dest_gpr(ctx, a->t); + + fn(dest, r1, r2, tcg_constant_i32(a->sh)); + save_gpr(ctx, a->t, dest); + + return nullify_end(ctx); +} + static bool trans_hadd(DisasContext *ctx, arg_rrr *a) { return do_multimedia(ctx, a, tcg_gen_vec_add16_i64); @@ -2816,6 +2838,16 @@ static bool trans_hshr_u(DisasContext *ctx, arg_rri = *a) return do_multimedia_sh(ctx, a, tcg_gen_vec_shr16i_i64); } =20 +static bool trans_hshladd(DisasContext *ctx, arg_rrr_sh *a) +{ + return do_multimedia_shadd(ctx, a, gen_helper_hshladd); +} + +static bool trans_hshradd(DisasContext *ctx, arg_rrr_sh *a) +{ + return do_multimedia_shadd(ctx, a, gen_helper_hshradd); +} + static bool trans_hsub(DisasContext *ctx, arg_rrr *a) { return do_multimedia(ctx, a, tcg_gen_vec_sub16_i64); --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835004884100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 5 ++++ target/hppa/translate.c | 55 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index d7befbf73d..323e9275bf 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -233,6 +233,11 @@ hsub 000010 ..... ..... 00000001 11 0 .....= @rrr hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr =20 +mixh_l 111110 ..... ..... 1 00 00100000 ..... @rrr +mixh_r 111110 ..... ..... 1 10 00100000 ..... @rrr +mixw_l 111110 ..... ..... 1 00 00000000 ..... @rrr +mixw_r 111110 ..... ..... 1 10 00000000 ..... @rrr + #### # Index Mem #### diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 47abed1662..57761a7bed 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2863,6 +2863,61 @@ static bool trans_hsub_us(DisasContext *ctx, arg_rrr= *a) return do_multimedia(ctx, a, gen_helper_hsub_us); } =20 +static void gen_mixh_l(TCGv_i64 dst, TCGv_i64 r1, TCGv_i64 r2) +{ + uint64_t mask =3D 0xffff0000ffff0000ull; + TCGv_i64 tmp =3D tcg_temp_new_i64(); + + tcg_gen_andi_i64(tmp, r2, mask); + tcg_gen_andi_i64(dst, r1, mask); + tcg_gen_shri_i64(tmp, tmp, 16); + tcg_gen_or_i64(dst, dst, tmp); +} + +static bool trans_mixh_l(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, gen_mixh_l); +} + +static void gen_mixh_r(TCGv_i64 dst, TCGv_i64 r1, TCGv_i64 r2) +{ + uint64_t mask =3D 0x0000ffff0000ffffull; + TCGv_i64 tmp =3D tcg_temp_new_i64(); + + tcg_gen_andi_i64(tmp, r1, mask); + tcg_gen_andi_i64(dst, r2, mask); + tcg_gen_shli_i64(tmp, tmp, 16); + tcg_gen_or_i64(dst, dst, tmp); +} + +static bool trans_mixh_r(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, gen_mixh_r); +} + +static void gen_mixw_l(TCGv_i64 dst, TCGv_i64 r1, TCGv_i64 r2) +{ + TCGv_i64 tmp =3D tcg_temp_new_i64(); + + tcg_gen_shri_i64(tmp, r2, 32); + tcg_gen_deposit_i64(dst, r1, tmp, 0, 32); +} + +static bool trans_mixw_l(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, gen_mixw_l); +} + +static void gen_mixw_r(TCGv_i64 dst, TCGv_i64 r1, TCGv_i64 r2) +{ + tcg_gen_deposit_i64(dst, r2, r1, 32, 32); +} + +static bool trans_mixw_r(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, gen_mixw_r); +} + static bool trans_ld(DisasContext *ctx, arg_ldst *a) { if (!ctx->is_pa20 && a->size > MO_32) { --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835245; cv=none; d=zohomail.com; s=zohoarc; b=F5mdQKB1b5nBWtqu22v21ybrUsf0KLGYXKqzYkMLxRdoc01rUubbjaawUfJgowyWQDZ6QfAVquxyykqS4uAZJDyah2tchRWZRoWK4VUHSUWli5LuQKPVt89iQLt7W8HIHDNbtw3gULW9fQfFVQXNBvnPmq/O6HwbDN/BruZyAjc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835245690100002 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 2 ++ target/hppa/translate.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 323e9275bf..c8f4317576 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -238,6 +238,8 @@ mixh_r 111110 ..... ..... 1 10 00100000 ..... = @rrr mixw_l 111110 ..... ..... 1 00 00000000 ..... @rrr mixw_r 111110 ..... ..... 1 10 00000000 ..... @rrr =20 +permh 111110 r1:5 r2:5 0 c0:2 0 c1:2 c2:2 c3:2 0 t:5 + #### # Index Mem #### diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 57761a7bed..a79cf52fcc 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2918,6 +2918,35 @@ static bool trans_mixw_r(DisasContext *ctx, arg_rrr = *a) return do_multimedia(ctx, a, gen_mixw_r); } =20 +static bool trans_permh(DisasContext *ctx, arg_permh *a) +{ + TCGv_i64 r, t0, t1, t2, t3; + + if (!ctx->is_pa20) { + return false; + } + + nullify_over(ctx); + + r =3D load_gpr(ctx, a->r1); + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + t2 =3D tcg_temp_new_i64(); + t3 =3D tcg_temp_new_i64(); + + tcg_gen_extract_i64(t0, r, (3 - a->c0) * 16, 16); + tcg_gen_extract_i64(t1, r, (3 - a->c1) * 16, 16); + tcg_gen_extract_i64(t2, r, (3 - a->c2) * 16, 16); + tcg_gen_extract_i64(t3, r, (3 - a->c3) * 16, 16); + + tcg_gen_deposit_i64(t0, t1, t0, 16, 48); + tcg_gen_deposit_i64(t2, t3, t2, 16, 48); + tcg_gen_deposit_i64(t0, t2, t0, 32, 32); + + save_gpr(ctx, a->t, t0); + return nullify_end(ctx); +} + static bool trans_ld(DisasContext *ctx, arg_ldst *a) { if (!ctx->is_pa20 && a->size > MO_32) { --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u7-20020aa78487000000b00694fee1011asm1946775pfn.208.2023.10.20.13.47.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:47:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834844; x=1698439644; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wM6oyD2tzl0dJH7FSQ0obv2SUstAr+kC/PKso0mR/f4=; b=q9J1mEZKolsO6/7XmrUFsT34HsbqbORm7fg+kk24XJCVTOAf7XW84i8Uzx9dqJ04Rv /nLdNIDjvp8lm+d6zP7NDCc+J/gyBgIHxe6tQvq/+YAcLj2XryXh7ZL0AelPzcaP7VJR cDcnX/OVqJFnuI/HlONwa8l0giHiFdGczv1zt2KkyK2z5VK2HLAP1bIpm4s6Wyt7yNbc br6r1x18MRCheTAYUTB1evqi6Hbn9MBGUV6X5fyY5sBHH0vs4gXzw6KS6JTLTmmOPImh SE/qzuU5ZmvU4pyQ02+K5jwUL69cBiEVqTvwhfYx2b2QPLLY1VdkB33kpjqnHsRK8sWc MH7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834844; x=1698439644; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wM6oyD2tzl0dJH7FSQ0obv2SUstAr+kC/PKso0mR/f4=; b=OqFAPBYvI9Giw/FS+YOlJQewZ1C+59Wnr6MQsa27o3p0brUQst3vqSxssxbJVbygy0 8pL5sfpgZhRlFtoJprUQsIQ9f5vGzF1uy0URm9UveyWa8JClyA79R1dBZml67xoR3Jzk Z47uGBaoLosXcqwzKcBynhFHiB2kGQlTy2tSSgdIdT2q/OdfM1vE6vrvEmTqeHTnbqV8 CSGgzlL9mYQT3OE3jFAdW+HMYu9gTDO20BL0sW0hv62tgINkceDnNA/t8IoMJoHXl0cQ 3RUwg+nW4RFXRW1YA/Eamkuoi054HrHlsaOKQ82lbh8WXF7wi5eCara41lURtH9r7y9M uMJw== X-Gm-Message-State: AOJu0YwldJMGonYqR3w9skaNVjCOCKlWs9SfxQvuYaOAiK9yHUt3kWr/ USngwE/T6nqsulJGqKZbwJvggLg6UqpvfdM9+sk= X-Google-Smtp-Source: AGHT+IGgedYkJ4+aYJ0ItGSgAnG8FqxW+rR5zzjI95FeHd3wpNqTvo0SsIvh+QoM5LijD5kKqK8FZg== X-Received: by 2002:a05:6a00:1389:b0:68f:d35d:217e with SMTP id t9-20020a056a00138900b0068fd35d217emr3115072pfg.2.1697834844678; Fri, 20 Oct 2023 13:47:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 59/65] target/hppa: Fix interruption based on default PSW Date: Fri, 20 Oct 2023 13:43:25 -0700 Message-Id: <20231020204331.139847-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835075111100007 Content-Type: text/plain; charset="utf-8" From: Helge Deller The default PSW is set by the operating system with the PDC_PSW firmware call. Use that setting to decide if wide mode is to be enabled for interruptions and EIRR usage. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 ++ target/hppa/int_helper.c | 18 ++++++++++++++---- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c9a9b9d3be..4aea46442a 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -124,6 +124,8 @@ #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ =20 #define CR_RC 0 +#define CR_PSW_DEFAULT 6 /* see SeaBIOS PDC_PSW firmware call */ +#define PDC_PSW_WIDE_BIT 2 #define CR_PID1 8 #define CR_PID2 9 #define CR_PID3 12 diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index f355c4c76b..a11d607b31 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -52,9 +52,17 @@ static void io_eir_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { HPPACPU *cpu =3D opaque; - int le_bit =3D ~data & 31; + CPUHPPAState *env =3D &cpu->env; + int widthm1 =3D 31; + int le_bit; =20 - cpu->env.cr[CR_EIRR] |=3D (target_ulong)1 << le_bit; + /* The default PSW.W controls the width of EIRR. */ + if (hppa_is_pa20(env) && env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT) { + widthm1 =3D 63; + } + le_bit =3D ~data & widthm1; + + env->cr[CR_EIRR] |=3D 1ull << le_bit; eval_interrupt(cpu); } =20 @@ -104,8 +112,10 @@ void hppa_cpu_do_interrupt(CPUState *cs) /* step 1 */ env->cr[CR_IPSW] =3D old_psw =3D cpu_hppa_get_psw(env); =20 - /* step 2 -- note PSW_W =3D=3D 0 for !HPPA64. */ - cpu_hppa_put_psw(env, PSW_W | (i =3D=3D EXCP_HPMC ? PSW_M : 0)); + /* step 2 -- Note PSW_W is masked out again for pa1.x */ + cpu_hppa_put_psw(env, + (env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT ? PSW_W := 0) | + (i =3D=3D EXCP_HPMC ? PSW_M : 0)); =20 /* step 3 */ env->cr[CR_IIASQ] =3D iasq_f >> 32; --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835289; cv=none; d=zohomail.com; s=zohoarc; b=Nnc4nijVrirNO0rU7zCwYZUjUp2n+EjhorKV1eZ1U/lifCbUvdOFpPVsm2NNAtla0ja22Yr9DMhVg2xelYMZxws62Km/Vyo4y27rUbQUxq7zDzvrOooP49gwwM2G3yzEltiApHLZk5eVNsOg5WV9Nna/IpIcWBgk/smLkgRtUg8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697835289; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=F7SjukT8MkZFkJ3ExB67ZCgDVB5vB1uA1Vxc0UPcY5M=; b=VU0EgzvjsE0zykSwlsvlRU/zzHlelQLZTKIrT+djtcBv8IOrQ/MGABOmdxaiZGYjqG2WnJWxummqk3d9RkJnHOEpmrqAqguVh8xA6UCeHMdmk6Y4wWKxsFeF5Ax7VttCJMlsvLtZJOffA2L3I4Gq7k1DpHwZDlK4wMYVibksQnw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697835289411650.765470404425; Fri, 20 Oct 2023 13:54:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwP4-00023b-Bf; Fri, 20 Oct 2023 16:47:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwP2-00022P-NT for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:47:28 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwP0-0001Dt-TU for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:47:28 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-6b6f4c118b7so1182084b3a.0 for ; Fri, 20 Oct 2023 13:47:26 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u7-20020aa78487000000b00694fee1011asm1946775pfn.208.2023.10.20.13.47.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:47:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834845; x=1698439645; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F7SjukT8MkZFkJ3ExB67ZCgDVB5vB1uA1Vxc0UPcY5M=; b=Wd6zEQjK9XYvKTmVQHYP47ko5V4Q9dwE1ExYNtRAkjhw2pihaFgqllh8WzVfFjtTxO A3P3y9vAcPfVF4qZX+DyT20Kfgsyczcjvzl1h+W6DJ0WoSctsvhhgbLo4FPEm4XBW3TA EapbZfNoJZivVy3lV1LByH1byScJH65Q7GLZOYGO8vE1W1bqYAMwiBmbKedtW7TI2hiR 23RLKvLSmuGqldf36TgjllJxpi8rGzw095S4pJKy0b4LhqrhBpZvwgATE9RG6n1sKZmV 63J2Sl2IDJEsCl8xNO0ivLSTv0vmn1+Or8PS17RgFpf3YAsiWRe5WLTNt0DYyibS7S23 bxmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834845; x=1698439645; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F7SjukT8MkZFkJ3ExB67ZCgDVB5vB1uA1Vxc0UPcY5M=; b=u/TyQ443f6xTMaImtLBu+Ye2a2nBZSGKHvLdBvK4SgwQXkTYm9q1QR5PQlc6ApcrIu NV1/mnJlJsFkqiU7tN9ccIY6nWyqkSO6rbHBXtriQgYD4jmipiM4mhwOgSSQHslxzA1w +c/nT4n5ltJM+6JgTq5nsT/OVBzwTKKKvEs+idohvD7jNMkwTaruFv5x9n+ds6fnPFl4 sbe7N3tbgVsjHt9Cew0/QDrTGOqhae3zQiu84QFNhzKeLEu5rA/R7lmkUDQoBkYMChvx wKW0JBGpXzeCmf5HCjV3IZGWtGrr7IsW1x6wA0L6o0VP3jKQGsj1MUdCHDHA2PRzeyf1 HS+g== X-Gm-Message-State: AOJu0YwhosRnT4QzIf0z/eDeMi8YW4eOFz88fuI1iTRg4DI6Gg07b5mq EtOutKNzAA4JwK6ADjrBMwuqUGI85P5kuOj1ywg= X-Google-Smtp-Source: AGHT+IFwtF5UxrHInrf5vQ59AXDFyDdf4tB55t/WQlUQj+N5s3TKmVa4M30sJvYW1VNcojuZMtOMFg== X-Received: by 2002:a05:6a21:66c7:b0:16b:9285:69f5 with SMTP id ze7-20020a056a2166c700b0016b928569f5mr2544162pzb.35.1697834845498; Fri, 20 Oct 2023 13:47:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 60/65] target/hppa: Precompute zero into DisasContext Date: Fri, 20 Oct 2023 13:43:26 -0700 Message-Id: <20231020204331.139847-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835289965100008 Content-Type: text/plain; charset="utf-8" Reduce the number of times we look for the constant 0. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/hppa/translate.c | 34 ++++++++++++++++++---------------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index a79cf52fcc..9b60924057 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -53,6 +53,8 @@ typedef struct DisasContext { DisasCond null_cond; TCGLabel *null_lab; =20 + TCGv_i64 zero; + uint32_t insn; uint32_t tb_flags; int mmu_idx; @@ -1004,14 +1006,13 @@ static void do_add(DisasContext *ctx, unsigned rt, = TCGv_i64 in1, } =20 if (!is_l || cond_need_cb(c)) { - TCGv_i64 zero =3D tcg_constant_i64(0); cb_msb =3D tcg_temp_new_i64(); cb =3D tcg_temp_new_i64(); =20 - tcg_gen_add2_i64(dest, cb_msb, in1, zero, in2, zero); + tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero, in2, ctx->zero); if (is_c) { tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb, - get_psw_carry(ctx, d), zero); + get_psw_carry(ctx, d), ctx->zero); } tcg_gen_xor_i64(cb, in1, in2); tcg_gen_xor_i64(cb, cb, dest); @@ -1089,7 +1090,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_i64 in1, TCGv_i64 in2, bool is_tsv, bool is_b, bool is_tc, unsigned cf, bool d) { - TCGv_i64 dest, sv, cb, cb_msb, zero, tmp; + TCGv_i64 dest, sv, cb, cb_msb, tmp; unsigned c =3D cf >> 1; DisasCond cond; =20 @@ -1097,12 +1098,12 @@ static void do_sub(DisasContext *ctx, unsigned rt, = TCGv_i64 in1, cb =3D tcg_temp_new_i64(); cb_msb =3D tcg_temp_new_i64(); =20 - zero =3D tcg_constant_i64(0); if (is_b) { /* DEST,C =3D IN1 + ~IN2 + C. */ tcg_gen_not_i64(cb, in2); - tcg_gen_add2_i64(dest, cb_msb, in1, zero, get_psw_carry(ctx, d), z= ero); - tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb, cb, zero); + tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero, + get_psw_carry(ctx, d), ctx->zero); + tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb, cb, ctx->zero); tcg_gen_xor_i64(cb, cb, in1); tcg_gen_xor_i64(cb, cb, dest); } else { @@ -1111,7 +1112,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_i64 in1, * operations by seeding the high word with 1 and subtracting. */ TCGv_i64 one =3D tcg_constant_i64(1); - tcg_gen_sub2_i64(dest, cb_msb, in1, one, in2, zero); + tcg_gen_sub2_i64(dest, cb_msb, in1, one, in2, ctx->zero); tcg_gen_eqv_i64(cb, in1, in2); tcg_gen_xor_i64(cb, cb, dest); } @@ -2430,7 +2431,7 @@ static bool trans_lci(DisasContext *ctx, arg_lci *a) physical address. Two addresses with the same CI have a coherent view of the cache. Our implementation is to return 0 for all, since the entire address space is coherent. */ - save_gpr(ctx, a->t, tcg_constant_i64(0)); + save_gpr(ctx, a->t, ctx->zero); =20 cond_free(&ctx->null_cond); return true; @@ -2639,7 +2640,7 @@ static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf= _d *a) =20 static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) { - TCGv_i64 dest, add1, add2, addc, zero, in1, in2; + TCGv_i64 dest, add1, add2, addc, in1, in2; TCGv_i64 cout; =20 nullify_over(ctx); @@ -2651,7 +2652,6 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) add2 =3D tcg_temp_new_i64(); addc =3D tcg_temp_new_i64(); dest =3D tcg_temp_new_i64(); - zero =3D tcg_constant_i64(0); =20 /* Form R1 << 1 | PSW[CB]{8}. */ tcg_gen_add_i64(add1, in1, in1); @@ -2667,8 +2667,9 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) tcg_gen_xor_i64(add2, in2, addc); tcg_gen_andi_i64(addc, addc, 1); =20 - tcg_gen_add2_i64(dest, cpu_psw_cb_msb, add1, zero, add2, zero); - tcg_gen_add2_i64(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zer= o); + tcg_gen_add2_i64(dest, cpu_psw_cb_msb, add1, ctx->zero, add2, ctx->zer= o); + tcg_gen_add2_i64(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, + addc, ctx->zero); =20 /* Write back the result register. */ save_gpr(ctx, a->t, dest); @@ -2968,7 +2969,7 @@ static bool trans_st(DisasContext *ctx, arg_ldst *a) static bool trans_ldc(DisasContext *ctx, arg_ldst *a) { MemOp mop =3D MO_TE | MO_ALIGN | a->size; - TCGv_i64 zero, dest, ofs; + TCGv_i64 dest, ofs; TCGv_i64 addr; =20 if (!ctx->is_pa20 && a->size > MO_32) { @@ -2998,8 +2999,7 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) */ gen_helper_ldc_check(addr); =20 - zero =3D tcg_constant_i64(0); - tcg_gen_atomic_xchg_i64(dest, addr, zero, ctx->mmu_idx, mop); + tcg_gen_atomic_xchg_i64(dest, addr, ctx->zero, ctx->mmu_idx, mop); =20 if (a->m) { save_gpr(ctx, a->b, ofs); @@ -4336,6 +4336,8 @@ static void hppa_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) ctx->iaoq_n =3D -1; ctx->iaoq_n_var =3D NULL; =20 + ctx->zero =3D tcg_constant_i64(0); + /* Bound the number of instructions by those left on the page. */ bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; ctx->base.max_insns =3D MIN(ctx->base.max_insns, bound); --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835359; cv=none; d=zohomail.com; s=zohoarc; b=lqroJLhsT6rFUB9HqqGNtLgq1WFe0idskM4IQYvNWl98+mzJrv5mwmcAW6N5kpNRY/WypXyRwbiSSPY83KFX1BeBUItVpqjDcC5Z1DKlgTM6HAshkK8uLt3HG37JJbeP8DarfFnyvPtSsswKhb9x2eEmsigDQkTCmb0/05AJOdY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697835359; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5v0gDw2hca7aeL8Edx367HZb46Y2K4iTJAYsw/i0ri0=; b=C83rFcshNrCRi4jnMUp0odzCr1SPAKfzUWPaT6bMKn3Cb5p6g1e8WQAvxUGghRJncw8kCPa4VFDlqQDMIGR3hSAkteAOfAb2dgM/ekTA7kIA5Ff8tNBUUBOSpyyRCla2TNp7v6mPAJ3Yc626ZnqiE05c5OHZKwZaIOxweCVC17w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697835359415793.1358563155974; Fri, 20 Oct 2023 13:55:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwP4-00023p-RA; Fri, 20 Oct 2023 16:47:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwP3-000234-01 for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:47:29 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwP1-0001E6-Ee for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:47:28 -0400 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-6bd96cfb99cso1114471b3a.2 for ; Fri, 20 Oct 2023 13:47:27 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835360194100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/hppa/translate.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 9b60924057..ce2aff8c4e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -307,9 +307,7 @@ static void cond_free(DisasCond *cond) static TCGv_i64 load_gpr(DisasContext *ctx, unsigned reg) { if (reg =3D=3D 0) { - TCGv_i64 t =3D tcg_temp_new_i64(); - tcg_gen_movi_i64(t, 0); - return t; + return ctx->zero; } else { return cpu_gr[reg]; } --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835262; cv=none; d=zohomail.com; s=zohoarc; b=ns8gL7ufLTJxJl/Khe81enTqK5j0uCWBNkeGrBGnEYGCkCVuwOtb2Hhz2oecuv33RCcBkZvubIXw9EHgCrpoqJ7kbWiLD4dJxC6ZgDe09taKrF48rfWWg/sjx3j5KnxBJtrqjQZUTaPL6ZJ33Hvo+96OCo09xa1qlpv4bF35CbI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697835262; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u7-20020aa78487000000b00694fee1011asm1946775pfn.208.2023.10.20.13.47.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:47:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834847; x=1698439647; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EaDJt/aWXDXMzB/5b+cw749X5lfpuA3DGgkyKvYHvVQ=; b=dIXwHgAR/3biY/wFcJ9VOGfU74MqbElexA86Mhc3l/9YaXzt/EMVX9mlku91fKOto/ h/1BucG3Vyd2AYrgaEWEvqKsziglpqTJpwaJagrnjEhnxr9/ZsLi/6CgIMpuTIEDU+bx 0g3qMpq4/0t41oWixOnMKLMwkzqeL/9lOp09PAV2FdC8avjTnlJu6qmahEB8hsfIGqCT K641fuFUl44aO2l8pDmvkwfYuNKqRHs7JTtkip6aLBmzmlzKOQwgcSBZyIDx8bshJlii sGw0RT0SubmNP026taTah3BbvdGpTdn/EeivrqXlOwuDkts2pSPCjc0MgG5hbLGhoew5 9A2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834847; x=1698439647; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EaDJt/aWXDXMzB/5b+cw749X5lfpuA3DGgkyKvYHvVQ=; b=m1Lahxk4XVBqpo3c0Tzz2UEzA6LgPeukERylrZu5WdfQPIFAOz++cttCSf3ovfxSAJ 2Px3y1L3yzatyNjpAqKApfD88qI6WRjMLf8ZzBfAPUApZkncjZrlRxr8ryp50fU0NXew 3GTFlvJ1rpisy5bv/vKpK/r9BBVGS4WzJqo/UoUapLNtY921bR8hSwUzJmICaKvkNEiV 7kd7CrYAjUkkmw/A69KvDEytrD+PTXThwpia1Lv1JnTuE2QI21mZFYLvr1R3EQCvHpnD c6+klwKcnMiKCYOT26G4hzDSJ3yd4T4rH9IPQaeXhlygP+Jm4ZihV9yNZ7uhPnpTzkKl nhzg== X-Gm-Message-State: AOJu0YzuMTDKOpLqASVkhHW93QJBb99GyTsIka+cW4vX76XKA8vaWhdq UIZHOlHbnFdcfaH3iVAkmpCdgYp3v15ekJpjBjk= X-Google-Smtp-Source: AGHT+IFh3Vt0RmiGb3d0aupVa0qouYJxhW/llBMQOntPwbGBoyLwDbyUhcmXfEtQhZqMzpOoueev5A== X-Received: by 2002:a05:6a20:918e:b0:179:f81b:12d9 with SMTP id v14-20020a056a20918e00b00179f81b12d9mr3089394pzd.11.1697834846982; Fri, 20 Oct 2023 13:47:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 62/65] target/hppa: Simplify trans_dep*_imm Date: Fri, 20 Oct 2023 13:43:28 -0700 Message-Id: <20231020204331.139847-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835263804100001 Content-Type: text/plain; charset="utf-8" All of the special cases here are now handled during generic expansion. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 80 +++++++++++++---------------------------- 1 file changed, 25 insertions(+), 55 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ce2aff8c4e..47cfb16738 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3473,80 +3473,50 @@ static bool trans_extr_imm(DisasContext *ctx, arg_e= xtr_imm *a) return nullify_end(ctx); } =20 -static bool trans_depi_imm(DisasContext *ctx, arg_depi_imm *a) +static bool do_dep_imm(DisasContext *ctx, unsigned rt, unsigned c, + bool d, unsigned len, unsigned cpos, + TCGv_i64 src, TCGv_i64 val) { - unsigned len, width; - uint64_t mask0, mask1; + unsigned width =3D d ? 64 : 32; TCGv_i64 dest; =20 - if (!ctx->is_pa20 && a->d) { - return false; + if (cpos + len > width) { + len =3D width - cpos; } - if (a->c) { + + if (c) { nullify_over(ctx); } =20 - len =3D a->len; - width =3D a->d ? 64 : 32; - if (a->cpos + len > width) { - len =3D width - a->cpos; - } + dest =3D dest_gpr(ctx, rt); + tcg_gen_deposit_i64(dest, src, val, cpos, len); + save_gpr(ctx, rt, dest); =20 - dest =3D dest_gpr(ctx, a->t); - mask0 =3D deposit64(0, a->cpos, len, a->i); - mask1 =3D deposit64(-1, a->cpos, len, a->i); - - if (a->nz) { - TCGv_i64 src =3D load_gpr(ctx, a->t); - tcg_gen_andi_i64(dest, src, mask1); - tcg_gen_ori_i64(dest, dest, mask0); - } else { - tcg_gen_movi_i64(dest, mask0); - } - save_gpr(ctx, a->t, dest); - - /* Install the new nullification. */ cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, a->d, dest); + if (c) { + ctx->null_cond =3D do_sed_cond(ctx, c, d, dest); } return nullify_end(ctx); } =20 -static bool trans_dep_imm(DisasContext *ctx, arg_dep_imm *a) +static bool trans_depi_imm(DisasContext *ctx, arg_depi_imm *a) { - unsigned rs =3D a->nz ? a->t : 0; - unsigned len, width; - TCGv_i64 dest, val; - if (!ctx->is_pa20 && a->d) { return false; } - if (a->c) { - nullify_over(ctx); - } + return do_dep_imm(ctx, a->t, a->c, a->d, a->len, a->cpos, + a->nz ? load_gpr(ctx, a->t) : ctx->zero, + tcg_constant_i64(a->i)); +} =20 - len =3D a->len; - width =3D a->d ? 64 : 32; - if (a->cpos + len > width) { - len =3D width - a->cpos; +static bool trans_dep_imm(DisasContext *ctx, arg_dep_imm *a) +{ + if (!ctx->is_pa20 && a->d) { + return false; } - - dest =3D dest_gpr(ctx, a->t); - val =3D load_gpr(ctx, a->r); - if (rs =3D=3D 0) { - tcg_gen_deposit_z_i64(dest, val, a->cpos, len); - } else { - tcg_gen_deposit_i64(dest, cpu_gr[rs], val, a->cpos, len); - } - save_gpr(ctx, a->t, dest); - - /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, a->d, dest); - } - return nullify_end(ctx); + return do_dep_imm(ctx, a->t, a->c, a->d, a->len, a->cpos, + a->nz ? load_gpr(ctx, a->t) : ctx->zero, + load_gpr(ctx, a->r)); } =20 static bool do_dep_sar(DisasContext *ctx, unsigned rt, unsigned c, --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835103; cv=none; d=zohomail.com; s=zohoarc; b=YWI6UGipKQIJupoRBLUoMnmKUemZRi/wv7r9KIizpO0MH1ybc8FHWQ/rlg/o7ov6GgnBf4AXk652GyVW1D7h8Y2JCDLq1iiVoLafs96TmYmAc/MYfZ849gQLqqOoCOoaMyj1RKsvZ0HKdlBc5Ld77Dl5X2WFywd0TwmNAmFe3qc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697835103; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hkIbB3zmI08zQqo8JvI15EoPXprMPyQ2OgXzm/sTzaE=; b=YHXjtUJa6GlixvQJj5Pj9ry2NDOyxdCttH9E+vn8MT7sOeNfgNBSu/CRsBoHheXKQK+oNIwUk+wULvDLU+QjFgbYzNmlI2RbIA/efedMucUvDEJG91wEzazYrgtgzN51vavK/qJ4xvRAcirYSksNBfon/SUc5w2fAP2Uq5d47mw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697835103647882.262630250643; Fri, 20 Oct 2023 13:51:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwPY-0002O6-Nj; Fri, 20 Oct 2023 16:48:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwPI-0002IK-LY for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:47:48 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwP3-0001EQ-3w for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:47:41 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-6bf03b98b9bso1507152b3a.1 for ; Fri, 20 Oct 2023 13:47:28 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u7-20020aa78487000000b00694fee1011asm1946775pfn.208.2023.10.20.13.47.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:47:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834847; x=1698439647; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hkIbB3zmI08zQqo8JvI15EoPXprMPyQ2OgXzm/sTzaE=; b=YgzFjKpzx9qaaY4kgnyLh0p1qxddSikeSGexGxeFWVG+kFsdBrj1/QLVXWH15wNHIq fIyoSMIF6UJR3FBKfAH+F7Z6w94XrpQ7PnbuZfXMaOPEbyujyn87F8cXKs6C1MD5PSfo ei8iebG9+Bv/9Qcb5ca0Ws2GZsD1IjTcv6LUSW1j/aZMYk+kqjwmBVDgejmYcttG0kXa NFZjsZReTuvAIQ3x7a08bpzOxB2hU4aLii28gp3/XsRwRRpFDbINC30scX/b+LDq4Ja0 8kHmrKn8QtUyMvFLNy9n299FP/RXBRJSJlgdqzi10l8YUYEvDvwrj9DbdqHJw29kwNYm REiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834847; x=1698439647; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hkIbB3zmI08zQqo8JvI15EoPXprMPyQ2OgXzm/sTzaE=; b=wZVP/OpBePFTL77dEBA6pBQWvOJFNBHlqyov5OZFAWyLai5NAUNaSdsts+gxk1Hfbj BTH78iW6pl16wP4gpVaROR3WCCOckXyMvuBQkjODoYS6w2s5pRxEdQ/QjV0pEV7ZnTGa X/vzhbgzZWWzhfxdYqBEKotrjO1d/ogFznoCc5F8AoOO8uE9O2i9eY24xRUlD7OF2gxR tGmJkwn5fzGqkg8Yf6d6amZzdtLauLxCRe5BYcGjp06ffzRrCsQdRToPoBxnamKF/J36 yPoNK8CtY4v2TrXjhL2lFMEY39sb+vsbpOoDXjsCa7N5WTLMKWODJYbEog6RVtjGr22x PX7w== X-Gm-Message-State: AOJu0Yzmq49NlNRR3xLGEGM5tTVFhAvYo7+1o6j0NckrEDWoNaaRjAhK Pjx8GH/7DkEWxgS4lTSwhHbiIp1nrnH7L/Zl6as= X-Google-Smtp-Source: AGHT+IG9vSh9day8Fd1+MXBsukDZ/+jwv9twec7U1ZjAKP3bwLhJrlAxbcsq9YRrLZ9njAW+e/C2dw== X-Received: by 2002:a05:6a20:7f8e:b0:14d:e615:277c with SMTP id d14-20020a056a207f8e00b0014de615277cmr4756602pzj.11.1697834847658; Fri, 20 Oct 2023 13:47:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 63/65] include/hw/elf: Remove truncating signed casts Date: Fri, 20 Oct 2023 13:43:29 -0700 Message-Id: <20231020204331.139847-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835105269100003 Content-Type: text/plain; charset="utf-8" There's nothing about elf that specifically requires signed vs unsigned. This is very much a target-specific preference. In the meantime, casting low and high from uint64_t back to Elf_SWord to uint64_t discards high bits that might have been set by translate_fn. Signed-off-by: Richard Henderson --- include/hw/elf_ops.h | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h index dffb0e73d2..0a5c258fe6 100644 --- a/include/hw/elf_ops.h +++ b/include/hw/elf_ops.h @@ -385,10 +385,11 @@ static ssize_t glue(load_elf, SZ)(const char *name, i= nt fd, } =20 if (pflags) { - *pflags =3D (elf_word)ehdr.e_flags; + *pflags =3D ehdr.e_flags; + } + if (pentry) { + *pentry =3D ehdr.e_entry; } - if (pentry) - *pentry =3D (uint64_t)(elf_sword)ehdr.e_entry; =20 glue(load_symbols, SZ)(&ehdr, fd, must_swab, clear_lsb, sym_cb); =20 @@ -610,10 +611,12 @@ static ssize_t glue(load_elf, SZ)(const char *name, i= nt fd, } } =20 - if (lowaddr) - *lowaddr =3D (uint64_t)(elf_sword)low; - if (highaddr) - *highaddr =3D (uint64_t)(elf_sword)high; + if (lowaddr) { + *lowaddr =3D low; + } + if (highaddr) { + *highaddr =3D high; + } ret =3D total_size; fail: if (mapped_file) { --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835292; cv=none; d=zohomail.com; s=zohoarc; b=Vvub2elvwebmjRj2wZXr41eBmN8w+syj4Hpc0624oaiqmYU7i2HN8YqAxuA/L7V7cON/BZOeYppAQB0fZd2Yuag9TuWmoqcdC1zb4oa64ZJZYF9DevoPRYagj2XrTb1Wd4NLWSWEWbYBIY7G7BMmr3jENerA+WMtpbrt5XkRc8s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697835292; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3YpfUmyUa6m05sFckuJpc1CvhipgVeCi72arXwnoozE=; b=K+oTe2ImqoLNq28efS9PEMcodkQ0P3wgAKiPm073+BuPM3LyZCteJXb9CO5cIQ51aO387gsKnug1bUpCc45Mh5MhGO0bP01QNDXBtYT4E4fsv6OkV1X1bY/VAZ4oW1JvgnU5r/0YGSb2Gn4Ya4Qpj8GhYZZ6h/lH+EXUY9uP1KE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169783529225076.7666985068073; Fri, 20 Oct 2023 13:54:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtwP9-00028e-W6; Fri, 20 Oct 2023 16:47:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtwP6-00024o-2Q for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:47:32 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtwP3-0001Ef-Sb for qemu-devel@nongnu.org; Fri, 20 Oct 2023 16:47:31 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-6b201a93c9cso1117461b3a.0 for ; Fri, 20 Oct 2023 13:47:29 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u7-20020aa78487000000b00694fee1011asm1946775pfn.208.2023.10.20.13.47.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:47:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834848; x=1698439648; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3YpfUmyUa6m05sFckuJpc1CvhipgVeCi72arXwnoozE=; b=c2sAHm9LspCn4deFQhICb7m7ekTtEpOKxqcKiy/b6AYyo/2jPOQU70yV8LDR+vXFC3 SmY3LbcSyzWL8uCaezLMZtsZ47UCoCu6pSPISxeF/htx/HzQWs/dEkjE6rRhC0bpsXdD jJgeYsJGCkujNHcBPrcxvkhftv5GjO7vV7lJqmegGds+jeZj/qLlLLsYfG5o6T9LMz7q a28VsUmiizaReN3b5drBNQkpjQw2VKchkSTvEfEwKbjo/FeiBr/mt+P5+4iMC8jOyh+5 Si7gcs5PqWLVVTqlu8XZcKRHf6AwXF2GBCXinKf8OCnWQJ6SC4LItxeHdC0fvptgfvVP BMAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834848; x=1698439648; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3YpfUmyUa6m05sFckuJpc1CvhipgVeCi72arXwnoozE=; b=Fz9pypLLucFNt9bAVjLpIT48gwcWwqn68Ct6xb/9Aqn7FwtecmcpUi4Dk24KX0bft1 EB2AC0Y7HpChz2/9qvypgXIOe7xPmohPC9t4FVlU8BuOZqROz7+nc7jOhIYLZWhCvlK/ /Bkmlf8uABm8y+LLpwjCmrrlaIlf2p81SkYyz+rHyz9lXEJmxEku4lee50OHWLFQRcoK zrxO2tqQQY6NlNRDpBJ8i48niModHvd8PQpK99m3tS7AEsoMlAoVaxkK6VmPpyBoxH6v Tro8l+tfjNzhj/OUEQsGqkjucAwdJi1IrsNgY3cjuGDa2CNraKUOg/ZgLhXvNtLRj3LJ SuzA== X-Gm-Message-State: AOJu0YzHsBiao279BQirN7rzK8CRVq4BAab+BuVPihpzNkXNq5nCwnPT Nz/YpCjH3zJ5/vVHJtqmrMNthBOgI5u1tOeitcA= X-Google-Smtp-Source: AGHT+IEgOJhI6j7yLmze3HsWAqKUxR9sRj0trXxzFu7mO/7wBaFzRmXtyBsFdD42OgLfpr3hVQ1/TA== X-Received: by 2002:a05:6a20:3ca8:b0:179:f858:784d with SMTP id b40-20020a056a203ca800b00179f858784dmr3237205pzj.21.1697834848419; Fri, 20 Oct 2023 13:47:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 64/65] hw/hppa: Translate phys addresses for the cpu Date: Fri, 20 Oct 2023 13:43:30 -0700 Message-Id: <20231020204331.139847-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835294023100001 Content-Type: text/plain; charset="utf-8" Hack the machine to use pa2.0 physical layout when required, using the PSW.W=3D0 absolute to physical mapping. Signed-off-by: Richard Henderson --- hw/hppa/machine.c | 117 ++++++++++++++++++++++++++++------------------ 1 file changed, 71 insertions(+), 46 deletions(-) diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 1f09b4b490..43c7afb89d 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -87,7 +87,7 @@ static const MemoryRegionOps hppa_pci_ignore_ops =3D { }, }; =20 -static ISABus *hppa_isa_bus(void) +static ISABus *hppa_isa_bus(hwaddr addr) { ISABus *isa_bus; qemu_irq *isa_irqs; @@ -96,8 +96,7 @@ static ISABus *hppa_isa_bus(void) isa_region =3D g_new(MemoryRegion, 1); memory_region_init_io(isa_region, NULL, &hppa_pci_ignore_ops, NULL, "isa-io", 0x800); - memory_region_add_subregion(get_system_memory(), IDE_HPA, - isa_region); + memory_region_add_subregion(get_system_memory(), addr, isa_region); =20 isa_bus =3D isa_bus_new(NULL, get_system_memory(), isa_region, &error_abort); @@ -163,13 +162,24 @@ static const MemoryRegionOps hppa_io_helper_ops =3D { }, }; =20 +typedef uint64_t TranslateFn(void *opaque, uint64_t addr); =20 -static uint64_t cpu_hppa_to_phys(void *opaque, uint64_t addr) +static uint64_t linux_kernel_virt_to_phys(void *opaque, uint64_t addr) { addr &=3D (0x10000000 - 1); return addr; } =20 +static uint64_t translate_pa10(void *dummy, uint64_t addr) +{ + return (uint32_t)addr; +} + +static uint64_t translate_pa20(void *dummy, uint64_t addr) +{ + return hppa_abs_to_phys_pa2_w0(addr); +} + static HPPACPU *cpu[HPPA_MAX_CPUS]; static uint64_t firmware_entry; =20 @@ -179,7 +189,8 @@ static void fw_cfg_boot_set(void *opaque, const char *b= oot_device, fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); } =20 -static FWCfgState *create_fw_cfg(MachineState *ms, PCIBus *pci_bus) +static FWCfgState *create_fw_cfg(MachineState *ms, PCIBus *pci_bus, + hwaddr addr) { FWCfgState *fw_cfg; uint64_t val; @@ -188,7 +199,7 @@ static FWCfgState *create_fw_cfg(MachineState *ms, PCIB= us *pci_bus) int btlb_entries =3D HPPA_BTLB_ENTRIES(&cpu[0]->env); int len; =20 - fw_cfg =3D fw_cfg_init_mem(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4); + fw_cfg =3D fw_cfg_init_mem(addr, addr + 4); fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, ms->smp.cpus); fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, HPPA_MAX_CPUS); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, ms->ram_size); @@ -258,32 +269,45 @@ static DinoState *dino_init(MemoryRegion *addr_space) /* * Step 1: Create CPUs and Memory */ -static void machine_HP_common_init_cpus(MachineState *machine) +static TranslateFn *machine_HP_common_init_cpus(MachineState *machine) { MemoryRegion *addr_space =3D get_system_memory(); - MemoryRegion *cpu_region; - long i; unsigned int smp_cpus =3D machine->smp.cpus; - char *name; + TranslateFn *translate; + MemoryRegion *cpu_region; =20 /* Create CPUs. */ - for (i =3D 0; i < smp_cpus; i++) { - name =3D g_strdup_printf("cpu%ld-io-eir", i); + for (unsigned int i =3D 0; i < smp_cpus; i++) { cpu[i] =3D HPPA_CPU(cpu_create(machine->cpu_type)); + } + + /* + * For now, treat address layout as if PSW_W is clear. + * TODO: create a proper hppa64 board model and load elf64 firmware. + */ + if (hppa_is_pa20(&cpu[0]->env)) { + translate =3D translate_pa20; + } else { + translate =3D translate_pa10; + } + + for (unsigned int i =3D 0; i < smp_cpus; i++) { + g_autofree char *name =3D g_strdup_printf("cpu%u-io-eir", i); =20 cpu_region =3D g_new(MemoryRegion, 1); memory_region_init_io(cpu_region, OBJECT(cpu[i]), &hppa_io_eir_ops, cpu[i], name, 4); - memory_region_add_subregion(addr_space, CPU_HPA + i * 0x1000, + memory_region_add_subregion(addr_space, + translate(NULL, CPU_HPA + i * 0x1000), cpu_region); - g_free(name); } =20 /* RTC and DebugOutputPort on CPU #0 */ cpu_region =3D g_new(MemoryRegion, 1); memory_region_init_io(cpu_region, OBJECT(cpu[0]), &hppa_io_helper_ops, cpu[0], "cpu0-io-rtc", 2 * sizeof(uint64_t)); - memory_region_add_subregion(addr_space, CPU_HPA + 16, cpu_region); + memory_region_add_subregion(addr_space, translate(NULL, CPU_HPA + 16), + cpu_region); =20 /* Main memory region. */ if (machine->ram_size > 3 * GiB) { @@ -291,12 +315,15 @@ static void machine_HP_common_init_cpus(MachineState = *machine) exit(EXIT_FAILURE); } memory_region_add_subregion_overlap(addr_space, 0, machine->ram, -1); + + return translate; } =20 /* * Last creation step: Add SCSI discs, NICs, graphics & load firmware */ -static void machine_HP_common_init_tail(MachineState *machine, PCIBus *pci= _bus) +static void machine_HP_common_init_tail(MachineState *machine, PCIBus *pci= _bus, + TranslateFn *translate) { const char *kernel_filename =3D machine->kernel_filename; const char *kernel_cmdline =3D machine->kernel_cmdline; @@ -324,13 +351,13 @@ static void machine_HP_common_init_tail(MachineState = *machine, PCIBus *pci_bus) dev =3D qdev_new("artist"); s =3D SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); - sysbus_mmio_map(s, 0, LASI_GFX_HPA); - sysbus_mmio_map(s, 1, ARTIST_FB_ADDR); + sysbus_mmio_map(s, 0, translate(NULL, LASI_GFX_HPA)); + sysbus_mmio_map(s, 1, translate(NULL, ARTIST_FB_ADDR)); } =20 /* Network setup. */ if (enable_lasi_lan()) { - lasi_82596_init(addr_space, LASI_LAN_HPA, + lasi_82596_init(addr_space, translate(NULL, LASI_LAN_HPA), qdev_get_gpio_in(lasi_dev, LASI_IRQ_LAN_HPA)); } =20 @@ -374,7 +401,7 @@ static void machine_HP_common_init_tail(MachineState *m= achine, PCIBus *pci_bus) qemu_register_powerdown_notifier(&hppa_system_powerdown_notifier); =20 /* fw_cfg configuration interface */ - create_fw_cfg(machine, pci_bus); + create_fw_cfg(machine, pci_bus, translate(NULL, FW_CFG_IO_BASE)); =20 /* Load firmware. Given that this is not "real" firmware, but one explicitly written for the emulation, we might as @@ -386,15 +413,10 @@ static void machine_HP_common_init_tail(MachineState = *machine, PCIBus *pci_bus) exit(1); } =20 - size =3D load_elf(firmware_filename, NULL, NULL, NULL, + size =3D load_elf(firmware_filename, NULL, translate, NULL, &firmware_entry, &firmware_low, &firmware_high, NULL, true, EM_PARISC, 0, 0); =20 - /* Unfortunately, load_elf sign-extends reading elf32. */ - firmware_entry =3D (uint32_t)firmware_entry; - firmware_low =3D (uint32_t)firmware_low; - firmware_high =3D (uint32_t)firmware_high; - if (size < 0) { error_report("could not load firmware '%s'", firmware_filename); exit(1); @@ -402,7 +424,8 @@ static void machine_HP_common_init_tail(MachineState *m= achine, PCIBus *pci_bus) qemu_log_mask(CPU_LOG_PAGE, "Firmware loaded at 0x%08" PRIx64 "-0x%08" PRIx64 ", entry at 0x%08" PRIx64 ".\n", firmware_low, firmware_high, firmware_entry); - if (firmware_low < FIRMWARE_START || firmware_high >=3D FIRMWARE_END) { + if (firmware_low < translate(NULL, FIRMWARE_START) || + firmware_high >=3D translate(NULL, FIRMWARE_END)) { error_report("Firmware overlaps with memory or IO space"); exit(1); } @@ -411,18 +434,16 @@ static void machine_HP_common_init_tail(MachineState = *machine, PCIBus *pci_bus) rom_region =3D g_new(MemoryRegion, 1); memory_region_init_ram(rom_region, NULL, "firmware", (FIRMWARE_END - FIRMWARE_START), &error_fatal); - memory_region_add_subregion(addr_space, FIRMWARE_START, rom_region); + memory_region_add_subregion(addr_space, + translate(NULL, FIRMWARE_START), rom_regio= n); =20 /* Load kernel */ if (kernel_filename) { - size =3D load_elf(kernel_filename, NULL, &cpu_hppa_to_phys, + size =3D load_elf(kernel_filename, NULL, linux_kernel_virt_to_phys, NULL, &kernel_entry, &kernel_low, &kernel_high, NU= LL, true, EM_PARISC, 0, 0); =20 - /* Unfortunately, load_elf sign-extends reading elf32. */ - kernel_entry =3D (uint32_t) cpu_hppa_to_phys(NULL, kernel_entry); - kernel_low =3D (uint32_t)kernel_low; - kernel_high =3D (uint32_t)kernel_high; + kernel_entry =3D linux_kernel_virt_to_phys(NULL, kernel_entry); =20 if (size < 0) { error_report("could not load kernel '%s'", kernel_filename); @@ -500,41 +521,42 @@ static void machine_HP_B160L_init(MachineState *machi= ne) { DeviceState *dev, *dino_dev; MemoryRegion *addr_space =3D get_system_memory(); + TranslateFn *translate; ISABus *isa_bus; PCIBus *pci_bus; =20 /* Create CPUs and RAM. */ - machine_HP_common_init_cpus(machine); + translate =3D machine_HP_common_init_cpus(machine); =20 /* Init Lasi chip */ lasi_dev =3D DEVICE(lasi_init()); - memory_region_add_subregion(addr_space, LASI_HPA, + memory_region_add_subregion(addr_space, translate(NULL, LASI_HPA), sysbus_mmio_get_region( SYS_BUS_DEVICE(lasi_dev), 0)); =20 /* Init Dino (PCI host bus chip). */ dino_dev =3D DEVICE(dino_init(addr_space)); - memory_region_add_subregion(addr_space, DINO_HPA, + memory_region_add_subregion(addr_space, translate(NULL, DINO_HPA), sysbus_mmio_get_region( SYS_BUS_DEVICE(dino_dev), 0)); pci_bus =3D PCI_BUS(qdev_get_child_bus(dino_dev, "pci")); assert(pci_bus); =20 /* Create ISA bus, needed for PS/2 kbd/mouse port emulation */ - isa_bus =3D hppa_isa_bus(); + isa_bus =3D hppa_isa_bus(translate(NULL, IDE_HPA)); assert(isa_bus); =20 /* Serial ports: Lasi and Dino use a 7.272727 MHz clock. */ - serial_mm_init(addr_space, LASI_UART_HPA + 0x800, 0, + serial_mm_init(addr_space, translate(NULL, LASI_UART_HPA + 0x800), 0, qdev_get_gpio_in(lasi_dev, LASI_IRQ_UART_HPA), 7272727 / 16, serial_hd(0), DEVICE_BIG_ENDIAN); =20 - serial_mm_init(addr_space, DINO_UART_HPA + 0x800, 0, + serial_mm_init(addr_space, translate(NULL, DINO_UART_HPA + 0x800), 0, qdev_get_gpio_in(dino_dev, DINO_IRQ_RS232INT), 7272727 / 16, serial_hd(1), DEVICE_BIG_ENDIAN); =20 /* Parallel port */ - parallel_mm_init(addr_space, LASI_LPT_HPA + 0x800, 0, + parallel_mm_init(addr_space, translate(NULL, LASI_LPT_HPA + 0x800), 0, qdev_get_gpio_in(lasi_dev, LASI_IRQ_LAN_HPA), parallel_hds[0]); =20 @@ -543,15 +565,17 @@ static void machine_HP_B160L_init(MachineState *machi= ne) sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(lasi_dev, LASI_IRQ_PS2KBD_HPA)); - memory_region_add_subregion(addr_space, LASI_PS2KBD_HPA, + memory_region_add_subregion(addr_space, + translate(NULL, LASI_PS2KBD_HPA), sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); - memory_region_add_subregion(addr_space, LASI_PS2KBD_HPA + 0x100, + memory_region_add_subregion(addr_space, + translate(NULL, LASI_PS2KBD_HPA + 0x100), sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1)); =20 /* Add SCSI discs, NICs, graphics & load firmware */ - machine_HP_common_init_tail(machine, pci_bus); + machine_HP_common_init_tail(machine, pci_bus, translate); } =20 static AstroState *astro_init(void) @@ -573,21 +597,22 @@ static void machine_HP_C3700_init(MachineState *machi= ne) AstroState *astro; DeviceState *astro_dev; MemoryRegion *addr_space =3D get_system_memory(); + TranslateFn *translate; =20 /* Create CPUs and RAM. */ - machine_HP_common_init_cpus(machine); + translate =3D machine_HP_common_init_cpus(machine); =20 /* Init Astro and the Elroys (PCI host bus chips). */ astro =3D astro_init(); astro_dev =3D DEVICE(astro); - memory_region_add_subregion(addr_space, ASTRO_HPA, + memory_region_add_subregion(addr_space, translate(NULL, ASTRO_HPA), sysbus_mmio_get_region( SYS_BUS_DEVICE(astro_dev), 0)); pci_bus =3D PCI_BUS(qdev_get_child_bus(DEVICE(astro->elroy[0]), "pci")= ); assert(pci_bus); =20 /* Add SCSI discs, NICs, graphics & load firmware */ - machine_HP_common_init_tail(machine, pci_bus); + machine_HP_common_init_tail(machine, pci_bus, translate); } =20 static void hppa_machine_reset(MachineState *ms, ShutdownCause reason) --=20 2.34.1 From nobody Wed Nov 27 17:37:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697835284; cv=none; d=zohomail.com; s=zohoarc; b=CqyN9AjMVW9ZrvFB3j6b/AbJzdHiBqMA8z5EKeZsz4E1x/sVXKFQe+OLd3Sd4oESiy/DSjS19aviiGqxR7sr2Dh2kYzDpuXzhi4FCDL3LEplhrHVelKmSeJEucLxCDpGRR1JHdLgiRVHM7f/i8RVJ3IPD85nKGCTTK4ytDZtiEw= ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u7-20020aa78487000000b00694fee1011asm1946775pfn.208.2023.10.20.13.47.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:47:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697834849; x=1698439649; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hES6yVQ0/11qdrvyqhHvx3Mqj7cvamUGm715KS/hVjU=; b=BFp2Elu+kkiM6mPMqNX9M9WL6O6bv+RQ5ws2DX/Ecb8b5GAWO7wAthwra7U9AJdGUh E6lhL1bgk+BtlNTPnDelQYaM+MwTEf8CV/sJWSwIQCBJD7AUKwKXdwCdRQ4JZszPgng+ laMpcZYkSPfmXdFuNDdw+xH/qzvy1RD1O0lsfwYwKzxyKeY0Tz4Bo4RQDoJYBwRYI4fj tFlvWcUwyHP/E9luL3cRWALgtvELS6k63D9jKARpYRr+aQVOOa8H4jedZz29tI2vw+zi WjaKM4n5sdRMCBxgN2MZd3NzaIyqxcCF5pP2Z+A90rhwigzI0mTJ9lmpQgjXl/jT1/+t DLkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697834849; x=1698439649; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hES6yVQ0/11qdrvyqhHvx3Mqj7cvamUGm715KS/hVjU=; b=FziQzKzMYXv1P4xlGkYsFuRIWeGgi03xiTo8JfCN3AOo27wYSxoGQTXITwC2TUjoSo 3xqrC7xN49ce/qQz75xEuiyLaRnfAwrifCTUTsFddHDasvVnG3TVQ07TSE2E8l4McwoJ zFhftCElGT7cgX6Vs800wcz6HbiNa9worTPuZtVeYlEc/bzpIZ8A3MiBky7RClI/iwmU fO7Tw7xgyEYsSy92ABVLqvYhh1bw1l/Y68iWwxOdM//vh4S4X/IabsI2g1NxX/9ppBzN sxvOV7h+qSIHGCDYtNtE4+WKCCh8s2SIL9UlG8k5qmQ0vjb+kq5pzR14Crnva+/7HxUw AIeg== X-Gm-Message-State: AOJu0YzyrX5bXy//zy3ZRMVym6ytlQaAb5P+LYszP9MCdp89IjObFjKa 3sklCorNnnsZuXeZIIwluAMlhNDKeXVk0wDdS8E= X-Google-Smtp-Source: AGHT+IHZII/TdrlWstNnNThIxBcsFajqtwiWiB3GsEpmVUirGD5S7pnNQmSZ0kQmRPjTMrkyMB9DFQ== X-Received: by 2002:a05:6a00:24c5:b0:6bf:4cb1:e78 with SMTP id d5-20020a056a0024c500b006bf4cb10e78mr593535pfv.6.1697834849289; Fri, 20 Oct 2023 13:47:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 65/65] linux-user/hppa: Drop EXCP_DUMP from handled exceptions Date: Fri, 20 Oct 2023 13:43:31 -0700 Message-Id: <20231020204331.139847-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697835286000100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- linux-user/hppa/cpu_loop.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 8ab1335106..d5232f37fe 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -147,12 +147,10 @@ void cpu_loop(CPUHPPAState *env) force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, env->iaoq_= f); break; case EXCP_ILL: - EXCP_DUMP(env, "qemu: EXCP_ILL exception %#x\n", trapnr); force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->iaoq_f); break; case EXCP_PRIV_OPR: /* check for glibc ABORT_INSTRUCTION "iitlbp %r0,(%sr0, %r0)" = */ - EXCP_DUMP(env, "qemu: EXCP_PRIV_OPR exception %#x\n", trapnr); if (env->cr[CR_IIR] =3D=3D 0x04000000) { force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->iaoq_f); } else { @@ -160,7 +158,6 @@ void cpu_loop(CPUHPPAState *env) } break; case EXCP_PRIV_REG: - EXCP_DUMP(env, "qemu: EXCP_PRIV_REG exception %#x\n", trapnr); force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVREG, env->iaoq_f); break; case EXCP_OVERFLOW: @@ -173,7 +170,6 @@ void cpu_loop(CPUHPPAState *env) force_sig_fault(TARGET_SIGFPE, 0, env->iaoq_f); break; case EXCP_BREAK: - EXCP_DUMP(env, "qemu: EXCP_BREAK exception %#x\n", trapnr); force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->iaoq_f= & ~3); break; case EXCP_DEBUG: --=20 2.34.1