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[176.171.212.97]) by smtp.gmail.com with ESMTPSA id f12-20020a19ae0c000000b0050797a35f8csm429931lfc.162.2023.10.20.09.36.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 09:36:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697819819; x=1698424619; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MQRY79gIxLQQU1ow+aWzPUBnoJTNMxZLomSdeNjxewY=; b=tbtj9pSosReqL4gFv1gmty+7xVTpQP+jMgU76ppChEaUN7jIQ06ZfvyNlUkHVGhvJM 8uLhBbkkO8+VdtXXu1LDSZ/h4k5Tl0Gff7iQxfQT8COHtNYfihNsPwzgMq4j9OmkYg7d y7ya/4CLgcNd+Ih1Kg0O1VLDhyY3H0BjYmdiG3xc96n7yaK1BCYYdFttOz04AQF3BOsL leFkeCkVUDe+jcLyayL7/ii84bN3P8zmZcMFYB+Tfqw7UURdQJAhNePWHijjv6qeeKyB zI/xURRGMDeH9OOUy1Vu5ZIWEMUuSNtf32DcTphJpGXlaCtYGAgmOhty4DFGGcbdQ4tA eDkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697819819; x=1698424619; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MQRY79gIxLQQU1ow+aWzPUBnoJTNMxZLomSdeNjxewY=; b=fWOOPSs8QWROMU52x+/Nvg1Qnc6OZoB7rkaaiDUOub86gk39XCQd0VXGODFh7sMIMz 53DkacYhMguzWFU6S4PigTfpmFksbraCnJrVCon1ZYsDjlk1AneFGTxTAb6hUy2uA6qp awOmDTVrvVx3SVyYK0XPVGPZ5nNserz47rDQ1JJvshIa7LfddRGyVc7jigO86t5rdwNZ 0JRaGfU8cZp3M4g9RWEiO/tl7xT6NeSMYJpalR8hnQW0jteJMOpQoKeEsy4Xvp0AjnNc sT9Tv2dFQL/9mSeL/zgQEl2SQrv7l06UgQxq6rWDVvcEzzRv8KLyLzPwJWxkbHqJJSS8 R8iw== X-Gm-Message-State: AOJu0YzUeliKVJn75ylZ3OdwqdTPaANhIc6huUZD/oZHmpIlFfXi4RE8 POinKKHxVbNBJr06s+evaBbFyThJBFxFVXTk6HE= X-Google-Smtp-Source: AGHT+IGfzbJO3dsOnQBH2tP2sUJXAZdE0Yu21hncmSNh1mVVjiOssdgT2ANJjVtzeM6XPT30uYv+pg== X-Received: by 2002:ac2:4573:0:b0:507:b8c5:6542 with SMTP id k19-20020ac24573000000b00507b8c56542mr1829783lfm.65.1697819818676; Fri, 20 Oct 2023 09:36:58 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, "Edgar E. Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrey Smirnov , Radoslaw Biernacki , Leif Lindholm , Marcin Juszkiewicz , Shannon Zhao , Igor Mammedov , Ani Sinha , Alistair Francis , David Woodhouse , Paul Durrant , Marcel Apfelbaum , Palmer Dabbelt , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Song Gao , Thomas Huth , Christian Borntraeger , Halil Pasic , Eric Farman , David Hildenbrand , Ilya Leoshkevich , Yanan Wang , "Dr. David Alan Gilbert" , Marcelo Tosatti , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , kvm@vger.kernel.org Subject: [RFC PATCH 01/19] cpus: Add argument to qemu_get_cpu() to filter CPUs by QOM type Date: Fri, 20 Oct 2023 18:36:23 +0200 Message-ID: <20231020163643.86105-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::232; envelope-from=philmd@linaro.org; helo=mail-lj1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697819954997100001 Heterogeneous machines have different type of CPU. qemu_get_cpu() returning unfiltered CPUs doesn't make sense anymore. Add a 'type' argument to filter CPU by QOM type. Type in "hw/core/cpu.h" and implementation in cpu-common.c modified manually, then convert all call sites by passing a NULL argument using the following coccinelle script: @@ expression index; @@ - qemu_get_cpu(index) + qemu_get_cpu(index, NULL) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- RFC: Is this hot path code? What is the cost of this QOM cast check? --- include/hw/core/cpu.h | 3 ++- cpu-common.c | 5 ++++- hw/arm/boot.c | 2 +- hw/arm/fsl-imx7.c | 2 +- hw/arm/pxa2xx_gpio.c | 2 +- hw/arm/sbsa-ref.c | 4 ++-- hw/arm/vexpress.c | 2 +- hw/arm/virt-acpi-build.c | 2 +- hw/arm/virt.c | 8 ++++---- hw/arm/xlnx-versal-virt.c | 2 +- hw/core/generic-loader.c | 2 +- hw/cpu/a15mpcore.c | 4 ++-- hw/cpu/a9mpcore.c | 2 +- hw/hyperv/hyperv.c | 2 +- hw/i386/kvm/xen_evtchn.c | 8 ++++---- hw/intc/arm_gicv3_common.c | 2 +- hw/intc/arm_gicv3_cpuif.c | 2 +- hw/intc/arm_gicv3_kvm.c | 2 +- hw/intc/riscv_aclint.c | 2 +- hw/intc/sifive_plic.c | 4 ++-- hw/loongarch/virt.c | 10 +++++----- hw/m68k/mcf5206.c | 2 +- hw/ppc/e500.c | 2 +- hw/ppc/ppce500_spin.c | 2 +- hw/riscv/boot.c | 2 +- hw/riscv/opentitan.c | 4 ++-- hw/s390x/ipl.c | 2 +- hw/s390x/s390-virtio-ccw.c | 2 +- monitor/hmp-cmds-target.c | 4 ++-- stats/stats-hmp-cmds.c | 2 +- system/cpus.c | 2 +- target/i386/kvm/xen-emu.c | 15 ++++++++------- target/i386/monitor.c | 2 +- target/mips/cpu.c | 2 +- target/mips/tcg/sysemu/cp0_helper.c | 2 +- target/s390x/cpu_models.c | 10 +++++----- 36 files changed, 66 insertions(+), 61 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 12205b7882..2a6008dd96 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -903,12 +903,13 @@ static inline bool cpu_in_exclusive_context(const CPU= State *cpu) /** * qemu_get_cpu: * @index: The CPUState@cpu_index value of the CPU to obtain. + * @type: The QOM type to filter for, including its derivatives. * * Gets a CPU matching @index. * * Returns: The CPU or %NULL if there is no matching CPU. */ -CPUState *qemu_get_cpu(int index); +CPUState *qemu_get_cpu(int index, const char *type); =20 /** * cpu_exists: diff --git a/cpu-common.c b/cpu-common.c index c81fd72d16..e0d7f7e7e7 100644 --- a/cpu-common.c +++ b/cpu-common.c @@ -107,11 +107,14 @@ void cpu_list_remove(CPUState *cpu) cpu_list_generation_id++; } =20 -CPUState *qemu_get_cpu(int index) +CPUState *qemu_get_cpu(int index, const char *type) { CPUState *cpu; =20 CPU_FOREACH(cpu) { + if (type && !object_dynamic_cast(OBJECT(cpu), type)) { + continue; + } if (cpu->cpu_index =3D=3D index) { return cpu; } diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 24fa169060..e260168cf5 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -438,7 +438,7 @@ static void fdt_add_psci_node(void *fdt) uint32_t cpu_off_fn; uint32_t cpu_on_fn; uint32_t migrate_fn; - ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(0)); + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(0, NULL)); const char *psci_method; int64_t psci_conduit; int rc; diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 474cfdc87c..1c1585f3e1 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -212,7 +212,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) =20 for (i =3D 0; i < smp_cpus; i++) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->a7mpcore); - DeviceState *d =3D DEVICE(qemu_get_cpu(i)); + DeviceState *d =3D DEVICE(qemu_get_cpu(i, NULL)); =20 irq =3D qdev_get_gpio_in(d, ARM_CPU_IRQ); sysbus_connect_irq(sbd, i, irq); diff --git a/hw/arm/pxa2xx_gpio.c b/hw/arm/pxa2xx_gpio.c index e7c3d99224..0a698171ab 100644 --- a/hw/arm/pxa2xx_gpio.c +++ b/hw/arm/pxa2xx_gpio.c @@ -303,7 +303,7 @@ static void pxa2xx_gpio_realize(DeviceState *dev, Error= **errp) { PXA2xxGPIOInfo *s =3D PXA2XX_GPIO(dev); =20 - s->cpu =3D ARM_CPU(qemu_get_cpu(s->ncpu)); + s->cpu =3D ARM_CPU(qemu_get_cpu(s->ncpu, NULL)); =20 qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines); qdev_init_gpio_out(dev, s->handler, s->lines); diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 3c7dfcd6dc..3571d5038f 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -275,7 +275,7 @@ static void create_fdt(SBSAMachineState *sms) =20 for (cpu =3D sms->smp_cpus - 1; cpu >=3D 0; cpu--) { char *nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); - ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu, NULL)); CPUState *cs =3D CPU(armcpu); uint64_t mpidr =3D sbsa_ref_cpu_mp_affinity(sms, cpu); =20 @@ -478,7 +478,7 @@ static void create_gic(SBSAMachineState *sms, MemoryReg= ion *mem) * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inpu= ts. */ for (i =3D 0; i < smp_cpus; i++) { - DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i)); + DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i, NULL)); int ppibase =3D NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; int irq; /* diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 8ff37f52ca..0590332fe5 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -257,7 +257,7 @@ static void init_cpus(MachineState *ms, const char *cpu= _type, =20 /* Connect the CPUs to the GIC */ for (n =3D 0; n < smp_cpus; n++) { - DeviceState *cpudev =3D DEVICE(qemu_get_cpu(n)); + DeviceState *cpudev =3D DEVICE(qemu_get_cpu(n, NULL)); =20 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ= )); sysbus_connect_irq(busdev, n + smp_cpus, diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 6b674231c2..fd6c239c31 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -727,7 +727,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, 0, 3); /* Reserved */ =20 for (i =3D 0; i < MACHINE(vms)->smp.cpus; i++) { - ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(i)); + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(i, NULL)); uint64_t physical_base_address =3D 0, gich =3D 0, gicv =3D 0; uint32_t vgic_interrupt =3D vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : = 0; uint32_t pmu_interrupt =3D arm_feature(&armcpu->env, ARM_FEATURE_P= MU) ? diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 15e74249f9..a8f9d88519 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -355,7 +355,7 @@ static void fdt_add_timer_nodes(const VirtMachineState = *vms) =20 qemu_fdt_add_subnode(ms->fdt, "/timer"); =20 - armcpu =3D ARM_CPU(qemu_get_cpu(0)); + armcpu =3D ARM_CPU(qemu_get_cpu(0, NULL)); if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { const char compat[] =3D "arm,armv8-timer\0arm,armv7-timer"; qemu_fdt_setprop(ms->fdt, "/timer", "compatible", @@ -394,7 +394,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *v= ms) * at least one of them has Aff3 populated, we set #address-cells to 2. */ for (cpu =3D 0; cpu < smp_cpus; cpu++) { - ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu, NULL)); =20 if (armcpu->mp_affinity & ARM_AFF3_MASK) { addr_cells =3D 2; @@ -408,7 +408,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *v= ms) =20 for (cpu =3D smp_cpus - 1; cpu >=3D 0; cpu--) { char *nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); - ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu, NULL)); CPUState *cs =3D CPU(armcpu); =20 qemu_fdt_add_subnode(ms->fdt, nodename); @@ -799,7 +799,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inpu= ts. */ for (i =3D 0; i < smp_cpus; i++) { - DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i)); + DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i, NULL)); int ppibase =3D NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; /* Mapping from the output timer irq lines from the CPU to the * GIC PPI inputs we use for the virt board. diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 88c561ff63..419ee3b882 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -103,7 +103,7 @@ static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t p= sci_conduit) =20 for (i =3D XLNX_VERSAL_NR_ACPUS - 1; i >=3D 0; i--) { char *name =3D g_strdup_printf("/cpus/cpu@%d", i); - ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(i)); + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(i, NULL)); =20 qemu_fdt_add_subnode(s->fdt, name); qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity); diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c index d4b5c501d8..98830ebd5b 100644 --- a/hw/core/generic-loader.c +++ b/hw/core/generic-loader.c @@ -124,7 +124,7 @@ static void generic_loader_realize(DeviceState *dev, Er= ror **errp) qemu_register_reset(generic_loader_reset, dev); =20 if (s->cpu_num !=3D CPU_NONE) { - s->cpu =3D qemu_get_cpu(s->cpu_num); + s->cpu =3D qemu_get_cpu(s->cpu_num, NULL); if (!s->cpu) { error_setg(errp, "Specified boot CPU#%d is nonexistent", s->cpu_num); diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index bfd8aa5644..8c9098d5d3 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -65,7 +65,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **= errp) /* Make the GIC's TZ support match the CPUs. We assume that * either all the CPUs have TZ, or none do. */ - cpuobj =3D OBJECT(qemu_get_cpu(0)); + cpuobj =3D OBJECT(qemu_get_cpu(0, NULL)); has_el3 =3D object_property_find(cpuobj, "has_el3") && object_property_get_bool(cpuobj, "has_el3", &error_abort); qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); @@ -90,7 +90,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **= errp) * appropriate GIC PPI inputs */ for (i =3D 0; i < s->num_cpu; i++) { - DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i)); + DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i, NULL)); int ppibase =3D s->num_irq - 32 + i * 32; int irq; /* Mapping from the output timer irq lines from the CPU to the diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index d03f57e579..62b7fb3836 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -56,7 +56,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **e= rrp) CPUState *cpu0; Object *cpuobj; =20 - cpu0 =3D qemu_get_cpu(0); + cpu0 =3D qemu_get_cpu(0, NULL); cpuobj =3D OBJECT(cpu0); if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9")= )) { /* We might allow Cortex-A5 once we model it */ diff --git a/hw/hyperv/hyperv.c b/hw/hyperv/hyperv.c index 57b402b956..a43f29ad8d 100644 --- a/hw/hyperv/hyperv.c +++ b/hw/hyperv/hyperv.c @@ -226,7 +226,7 @@ struct HvSintRoute { =20 static CPUState *hyperv_find_vcpu(uint32_t vp_index) { - CPUState *cs =3D qemu_get_cpu(vp_index); + CPUState *cs =3D qemu_get_cpu(vp_index, NULL); assert(hyperv_vp_index(cs) =3D=3D vp_index); return cs; } diff --git a/hw/i386/kvm/xen_evtchn.c b/hw/i386/kvm/xen_evtchn.c index a731738411..de3650ba3b 100644 --- a/hw/i386/kvm/xen_evtchn.c +++ b/hw/i386/kvm/xen_evtchn.c @@ -542,7 +542,7 @@ static void deassign_kernel_port(evtchn_port_t port) static int assign_kernel_port(uint16_t type, evtchn_port_t port, uint32_t vcpu_id) { - CPUState *cpu =3D qemu_get_cpu(vcpu_id); + CPUState *cpu =3D qemu_get_cpu(vcpu_id, NULL); struct kvm_xen_hvm_attr ha; =20 if (!cpu) { @@ -589,7 +589,7 @@ static bool valid_port(evtchn_port_t port) =20 static bool valid_vcpu(uint32_t vcpu) { - return !!qemu_get_cpu(vcpu); + return !!qemu_get_cpu(vcpu, NULL); } =20 static void unbind_backend_ports(XenEvtchnState *s) @@ -917,7 +917,7 @@ static int set_port_pending(XenEvtchnState *s, evtchn_p= ort_t port) =20 if (s->evtchn_in_kernel) { XenEvtchnPort *p =3D &s->port_table[port]; - CPUState *cpu =3D qemu_get_cpu(p->vcpu); + CPUState *cpu =3D qemu_get_cpu(p->vcpu, NULL); struct kvm_irq_routing_xen_evtchn evt; =20 if (!cpu) { @@ -1779,7 +1779,7 @@ int xen_evtchn_translate_pirq_msi(struct kvm_irq_rout= ing_entry *route, return -EINVAL; } =20 - cpu =3D qemu_get_cpu(s->port_table[port].vcpu); + cpu =3D qemu_get_cpu(s->port_table[port].vcpu, NULL); if (!cpu) { return -EINVAL; } diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 2ebf880ead..cdf21dfc11 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -392,7 +392,7 @@ static void arm_gicv3_common_realize(DeviceState *dev, = Error **errp) s->cpu =3D g_new0(GICv3CPUState, s->num_cpu); =20 for (i =3D 0; i < s->num_cpu; i++) { - CPUState *cpu =3D qemu_get_cpu(i); + CPUState *cpu =3D qemu_get_cpu(i, NULL); uint64_t cpu_affid; =20 s->cpu[i].cpu =3D cpu; diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index d07b13eb27..f765b3d4b5 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -2795,7 +2795,7 @@ void gicv3_init_cpuif(GICv3State *s) int i; =20 for (i =3D 0; i < s->num_cpu; i++) { - ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(i)); + ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(i, NULL)); GICv3CPUState *cs =3D &s->cpu[i]; =20 /* diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 72ad916d3d..d1ff9886aa 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -808,7 +808,7 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Err= or **errp) gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL); =20 for (i =3D 0; i < s->num_cpu; i++) { - ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(i)); + ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(i, NULL)); =20 define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); } diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index ab1a0b4b3a..a97c0449ec 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -483,7 +483,7 @@ static void riscv_aclint_swi_realize(DeviceState *dev, = Error **errp) =20 /* Claim software interrupt bits */ for (i =3D 0; i < swi->num_harts; i++) { - RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(swi->hartid_base + i)); + RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(swi->hartid_base + i, NUL= L)); /* We don't claim mip.SSIP because it is writable by software */ if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0)= { error_report("MSIP already claimed"); diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 5522ede2cf..a32e7f1924 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -392,7 +392,7 @@ static void sifive_plic_realize(DeviceState *dev, Error= **errp) * hardware controlled when a PLIC is attached. */ for (i =3D 0; i < s->num_harts; i++) { - RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(s->hartid_base + i)); + RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(s->hartid_base + i, NULL)= ); if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) { error_setg(errp, "SEIP already claimed"); return; @@ -499,7 +499,7 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart= _config, =20 for (i =3D 0; i < plic->num_addrs; i++) { int cpu_num =3D plic->addr_config[i].hartid; - CPUState *cpu =3D qemu_get_cpu(cpu_num); + CPUState *cpu =3D qemu_get_cpu(cpu_num, NULL); =20 if (plic->addr_config[i].mode =3D=3D PLICMode_M) { qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts, diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 2952fe452e..e888aea892 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -170,7 +170,7 @@ static void fdt_add_cpu_nodes(const LoongArchMachineSta= te *lams) /* cpu nodes */ for (num =3D smp_cpus - 1; num >=3D 0; num--) { char *nodename =3D g_strdup_printf("/cpus/cpu@%d", num); - LoongArchCPU *cpu =3D LOONGARCH_CPU(qemu_get_cpu(num)); + LoongArchCPU *cpu =3D LOONGARCH_CPU(qemu_get_cpu(num, NULL)); CPUState *cs =3D CPU(cpu); =20 qemu_fdt_add_subnode(ms->fdt, nodename); @@ -560,7 +560,7 @@ static void loongarch_irq_init(LoongArchMachineState *l= ams) * +--------+ +---------+ +---------+ */ for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { - cpu_state =3D qemu_get_cpu(cpu); + cpu_state =3D qemu_get_cpu(cpu, NULL); cpudev =3D DEVICE(cpu_state); lacpu =3D LOONGARCH_CPU(cpu_state); env =3D &(lacpu->env); @@ -594,7 +594,7 @@ static void loongarch_irq_init(LoongArchMachineState *l= ams) * cpu_pin[9:2] <=3D intc_pin[7:0] */ for (cpu =3D 0; cpu < MIN(ms->smp.cpus, EXTIOI_CPUS); cpu++) { - cpudev =3D DEVICE(qemu_get_cpu(cpu)); + cpudev =3D DEVICE(qemu_get_cpu(cpu, NULL)); for (pin =3D 0; pin < LS3A_INTC_IP; pin++) { qdev_connect_gpio_out(extioi, (cpu * 8 + pin), qdev_get_gpio_in(cpudev, pin + 2)); @@ -726,7 +726,7 @@ static void loongarch_direct_kernel_boot(LoongArchMachi= neState *lams, kernel_addr =3D load_kernel_info(loaderparams); if (!machine->firmware) { for (i =3D 0; i < machine->smp.cpus; i++) { - lacpu =3D LOONGARCH_CPU(qemu_get_cpu(i)); + lacpu =3D LOONGARCH_CPU(qemu_get_cpu(i, NULL)); lacpu->env.load_elf =3D true; lacpu->env.elf_address =3D kernel_addr; } @@ -859,7 +859,7 @@ static void loongarch_init(MachineState *machine) fdt_add_flash_node(lams); /* register reset function */ for (i =3D 0; i < machine->smp.cpus; i++) { - lacpu =3D LOONGARCH_CPU(qemu_get_cpu(i)); + lacpu =3D LOONGARCH_CPU(qemu_get_cpu(i, NULL)); qemu_register_reset(reset_load_elf, lacpu); } /* Initialize the IO interrupt subsystem */ diff --git a/hw/m68k/mcf5206.c b/hw/m68k/mcf5206.c index 2ab1b4f059..a0851f58a9 100644 --- a/hw/m68k/mcf5206.c +++ b/hw/m68k/mcf5206.c @@ -601,7 +601,7 @@ static void mcf5206_mbar_realize(DeviceState *dev, Erro= r **errp) s->timer[1] =3D m5206_timer_init(s->pic[10]); s->uart[0] =3D mcf_uart_init(s->pic[12], serial_hd(0)); s->uart[1] =3D mcf_uart_init(s->pic[13], serial_hd(1)); - s->cpu =3D M68K_CPU(qemu_get_cpu(0)); + s->cpu =3D M68K_CPU(qemu_get_cpu(0, NULL)); } =20 static void mcf5206_mbar_class_init(ObjectClass *oc, void *data) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index e04114fb3c..380bbe1fe6 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -495,7 +495,7 @@ static int ppce500_load_device_tree(PPCE500MachineState= *pms, char *cpu_name; uint64_t cpu_release_addr =3D pmc->spin_base + (i * 0x20); =20 - cpu =3D qemu_get_cpu(i); + cpu =3D qemu_get_cpu(i, NULL); if (cpu =3D=3D NULL) { continue; } diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index bbce63e8a4..3b113fbbdb 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -125,7 +125,7 @@ static void spin_write(void *opaque, hwaddr addr, uint6= 4_t value, SpinInfo *curspin =3D &s->spin[env_idx]; uint8_t *curspin_p =3D (uint8_t*)curspin; =20 - cpu =3D qemu_get_cpu(env_idx); + cpu =3D qemu_get_cpu(env_idx, NULL); if (cpu =3D=3D NULL) { /* Unknown CPU */ return; diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 52bf8e67de..ea733b3df1 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -49,7 +49,7 @@ char *riscv_plic_hart_config_string(int hart_count) int i; =20 for (i =3D 0; i < hart_count; i++) { - CPUState *cs =3D qemu_get_cpu(i); + CPUState *cs =3D qemu_get_cpu(i, NULL); CPURISCVState *env =3D &RISCV_CPU(cs)->env; =20 if (kvm_enabled()) { diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 436503f1ba..e98361de19 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -190,7 +190,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_s= oc, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].bas= e); =20 for (i =3D 0; i < ms->smp.cpus; i++) { - CPUState *cpu =3D qemu_get_cpu(i); + CPUState *cpu =3D qemu_get_cpu(i, NULL); =20 qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i, qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT)); @@ -223,7 +223,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_s= oc, Error **errp) 0, qdev_get_gpio_in(DEVICE(&s->plic), IBEX_TIMER_TIMEREXPIRED0_0)); qdev_connect_gpio_out(DEVICE(&s->timer), 0, - qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)), + qdev_get_gpio_in(DEVICE(qemu_get_cpu(0, NULL)), IRQ_M_TIMER)); =20 /* SPI-Hosts */ diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c index 515dcf51b5..14cd0a1f7b 100644 --- a/hw/s390x/ipl.c +++ b/hw/s390x/ipl.c @@ -671,7 +671,7 @@ void s390_ipl_get_reset_request(CPUState **cs, enum s39= 0_reset *reset_type) { S390IPLState *ipl =3D get_ipl_device(); =20 - *cs =3D qemu_get_cpu(ipl->reset_cpu_index); + *cs =3D qemu_get_cpu(ipl->reset_cpu_index, NULL); if (!*cs) { /* use any CPU */ *cs =3D first_cpu; diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 2d75f2131f..7628b746a8 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -583,7 +583,7 @@ static HotplugHandler *s390_get_hotplug_handler(Machine= State *machine, =20 static void s390_nmi(NMIState *n, int cpu_index, Error **errp) { - CPUState *cs =3D qemu_get_cpu(cpu_index); + CPUState *cs =3D qemu_get_cpu(cpu_index, NULL); =20 s390_cpu_restart(S390_CPU(cs)); } diff --git a/monitor/hmp-cmds-target.c b/monitor/hmp-cmds-target.c index d9fbcac08d..e501b997f8 100644 --- a/monitor/hmp-cmds-target.c +++ b/monitor/hmp-cmds-target.c @@ -36,7 +36,7 @@ int monitor_set_cpu(Monitor *mon, int cpu_index) { CPUState *cpu; =20 - cpu =3D qemu_get_cpu(cpu_index); + cpu =3D qemu_get_cpu(cpu_index, NULL); if (cpu =3D=3D NULL) { return -1; } @@ -103,7 +103,7 @@ void hmp_info_registers(Monitor *mon, const QDict *qdic= t) cpu_dump_state(cs, NULL, CPU_DUMP_FPU); } } else { - cs =3D vcpu >=3D 0 ? qemu_get_cpu(vcpu) : mon_get_cpu(mon); + cs =3D vcpu >=3D 0 ? qemu_get_cpu(vcpu, NULL) : mon_get_cpu(mon); =20 if (!cs) { if (vcpu >=3D 0) { diff --git a/stats/stats-hmp-cmds.c b/stats/stats-hmp-cmds.c index 1f91bf8bd5..0e58336c7f 100644 --- a/stats/stats-hmp-cmds.c +++ b/stats/stats-hmp-cmds.c @@ -147,7 +147,7 @@ static StatsFilter *stats_filter(StatsTarget target, co= nst char *names, case STATS_TARGET_VCPU: { strList *vcpu_list =3D NULL; - CPUState *cpu =3D qemu_get_cpu(cpu_index); + CPUState *cpu =3D qemu_get_cpu(cpu_index, NULL); char *canonical_path =3D object_get_canonical_path(OBJECT(cpu)); =20 QAPI_LIST_PREPEND(vcpu_list, canonical_path); diff --git a/system/cpus.c b/system/cpus.c index 0848e0dbdb..3e7c80e91b 100644 --- a/system/cpus.c +++ b/system/cpus.c @@ -751,7 +751,7 @@ void qmp_memsave(int64_t addr, int64_t size, const char= *filename, cpu_index =3D 0; } =20 - cpu =3D qemu_get_cpu(cpu_index); + cpu =3D qemu_get_cpu(cpu_index, NULL); if (cpu =3D=3D NULL) { error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "cpu-index", "a CPU number"); diff --git a/target/i386/kvm/xen-emu.c b/target/i386/kvm/xen-emu.c index 76348f9d5d..f289af906c 100644 --- a/target/i386/kvm/xen-emu.c +++ b/target/i386/kvm/xen-emu.c @@ -384,7 +384,7 @@ static void do_set_vcpu_info_gpa(CPUState *cs, run_on_c= pu_data data) =20 void *kvm_xen_get_vcpu_info_hva(uint32_t vcpu_id) { - CPUState *cs =3D qemu_get_cpu(vcpu_id); + CPUState *cs =3D qemu_get_cpu(vcpu_id, NULL); if (!cs) { return NULL; } @@ -418,7 +418,7 @@ void kvm_xen_maybe_deassert_callback(CPUState *cs) =20 void kvm_xen_set_callback_asserted(void) { - CPUState *cs =3D qemu_get_cpu(0); + CPUState *cs =3D qemu_get_cpu(0, NULL); =20 if (cs) { X86_CPU(cs)->env.xen_callback_asserted =3D true; @@ -427,7 +427,7 @@ void kvm_xen_set_callback_asserted(void) =20 void kvm_xen_inject_vcpu_callback_vector(uint32_t vcpu_id, int type) { - CPUState *cs =3D qemu_get_cpu(vcpu_id); + CPUState *cs =3D qemu_get_cpu(vcpu_id, NULL); uint8_t vector; =20 if (!cs) { @@ -491,7 +491,7 @@ static void do_set_vcpu_timer_virq(CPUState *cs, run_on= _cpu_data data) =20 int kvm_xen_set_vcpu_virq(uint32_t vcpu_id, uint16_t virq, uint16_t port) { - CPUState *cs =3D qemu_get_cpu(vcpu_id); + CPUState *cs =3D qemu_get_cpu(vcpu_id, NULL); =20 if (!cs) { return -ENOENT; @@ -588,7 +588,7 @@ static int xen_set_shared_info(uint64_t gfn) trace_kvm_xen_set_shared_info(gfn); =20 for (i =3D 0; i < XEN_LEGACY_MAX_VCPUS; i++) { - CPUState *cpu =3D qemu_get_cpu(i); + CPUState *cpu =3D qemu_get_cpu(i, NULL); if (cpu) { async_run_on_cpu(cpu, do_set_vcpu_info_default_gpa, RUN_ON_CPU_HOST_ULONG(gpa)); @@ -834,7 +834,7 @@ static int kvm_xen_hcall_evtchn_upcall_vector(struct kv= m_xen_exit *exit, return -EINVAL; } =20 - target_cs =3D qemu_get_cpu(up.vcpu); + target_cs =3D qemu_get_cpu(up.vcpu, NULL); if (!target_cs) { return -EINVAL; } @@ -1160,7 +1160,8 @@ static bool kvm_xen_hcall_vcpu_op(struct kvm_xen_exit= *exit, X86CPU *cpu, int cmd, int vcpu_id, uint64_t arg) { CPUState *cs =3D CPU(cpu); - CPUState *dest =3D cs->cpu_index =3D=3D vcpu_id ? cs : qemu_get_cpu(vc= pu_id); + CPUState *dest =3D cs->cpu_index =3D=3D vcpu_id ? cs : qemu_get_cpu(vc= pu_id, + NULL); int err; =20 if (!dest) { diff --git a/target/i386/monitor.c b/target/i386/monitor.c index 6512846327..aca7be61dd 100644 --- a/target/i386/monitor.c +++ b/target/i386/monitor.c @@ -592,7 +592,7 @@ void hmp_mce(Monitor *mon, const QDict *qdict) if (qdict_get_try_bool(qdict, "broadcast", false)) { flags |=3D MCE_INJECT_BROADCAST; } - cs =3D qemu_get_cpu(cpu_index); + cs =3D qemu_get_cpu(cpu_index, NULL); if (cs !=3D NULL) { cpu =3D X86_CPU(cs); cpu_x86_inject_mce(mon, cpu, bank, status, mcg_status, addr, misc, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 83ee54f766..17e9e06a15 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -117,7 +117,7 @@ static void mips_cpu_dump_state(CPUState *cs, FILE *f, = int flags) =20 void cpu_set_exception_base(int vp_index, target_ulong address) { - MIPSCPU *vp =3D MIPS_CPU(qemu_get_cpu(vp_index)); + MIPSCPU *vp =3D MIPS_CPU(qemu_get_cpu(vp_index, NULL)); vp->env.exception_base =3D address; } =20 diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/c= p0_helper.c index 5da1124589..fcaba37c40 100644 --- a/target/mips/tcg/sysemu/cp0_helper.c +++ b/target/mips/tcg/sysemu/cp0_helper.c @@ -126,7 +126,7 @@ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env,= int *tc) cs =3D env_cpu(env); vpe_idx =3D tc_idx / cs->nr_threads; *tc =3D tc_idx % cs->nr_threads; - other_cs =3D qemu_get_cpu(vpe_idx); + other_cs =3D qemu_get_cpu(vpe_idx, NULL); if (other_cs =3D=3D NULL) { return env; } diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index b1e77b3a2b..4a44ee56a9 100644 --- a/target/s390x/cpu_models.c +++ b/target/s390x/cpu_models.c @@ -150,7 +150,7 @@ uint32_t s390_get_hmfai(void) static S390CPU *cpu; =20 if (!cpu) { - cpu =3D S390_CPU(qemu_get_cpu(0)); + cpu =3D S390_CPU(qemu_get_cpu(0, NULL)); } =20 if (!cpu || !cpu->model) { @@ -164,7 +164,7 @@ uint8_t s390_get_mha_pow(void) static S390CPU *cpu; =20 if (!cpu) { - cpu =3D S390_CPU(qemu_get_cpu(0)); + cpu =3D S390_CPU(qemu_get_cpu(0, NULL)); } =20 if (!cpu || !cpu->model) { @@ -179,7 +179,7 @@ uint32_t s390_get_ibc_val(void) static S390CPU *cpu; =20 if (!cpu) { - cpu =3D S390_CPU(qemu_get_cpu(0)); + cpu =3D S390_CPU(qemu_get_cpu(0, NULL)); } =20 if (!cpu || !cpu->model) { @@ -199,7 +199,7 @@ void s390_get_feat_block(S390FeatType type, uint8_t *da= ta) static S390CPU *cpu; =20 if (!cpu) { - cpu =3D S390_CPU(qemu_get_cpu(0)); + cpu =3D S390_CPU(qemu_get_cpu(0, NULL)); } =20 if (!cpu || !cpu->model) { @@ -213,7 +213,7 @@ bool s390_has_feat(S390Feat feat) static S390CPU *cpu; =20 if (!cpu) { - cpu =3D S390_CPU(qemu_get_cpu(0)); + cpu =3D S390_CPU(qemu_get_cpu(0, NULL)); } =20 if (!cpu || !cpu->model) { --=20 2.41.0 From nobody Thu Nov 20 03:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697820146; cv=none; d=zohomail.com; s=zohoarc; b=SI0tEy5Yos8lRdka8+gT/7M0Xp5BMgJ5905akpaIC2bJ5BC5iINIi/XKdasuocf8RVU0eIPM3eYSZHoVkeGClOA0FSsoRPetv7uXS8k/qUYM3tOBNgiNpawLikgvE98MFoWi+xNXN5ZXZ97F4YqeV/RSBqGAko6KTMbcTdIrWd0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697820146; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Radoslaw Biernacki , Leif Lindholm , Marcin Juszkiewicz , Igor Mammedov , Ani Sinha , Shannon Zhao , Alistair Francis , Palmer Dabbelt , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Song Gao , Thomas Huth , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , David Hildenbrand , Ilya Leoshkevich Subject: [PATCH 02/19] cpus: Filter for target specific CPU (generic) Date: Fri, 20 Oct 2023 18:36:24 +0200 Message-ID: <20231020163643.86105-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=philmd@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697820147485100002 When the CPUState is casted to a specific target, enforce that target CPU type as qemu_get_cpu() filter. Mechanical change using the following coccinelle script: @@ expression index; @@ ( - ARM_CPU(qemu_get_cpu(index, NULL)) + ARM_CPU(qemu_get_cpu(index, TYPE_ARM_CPU)) | - LOONGARCH_CPU(qemu_get_cpu(index, NULL)) + LOONGARCH_CPU(qemu_get_cpu(index, TYPE_LOONGARCH_CPU)) | - M68K_CPU(qemu_get_cpu(index, NULL)) + M68K_CPU(qemu_get_cpu(index, TYPE_M68K_CPU)) | - MIPS_CPU(qemu_get_cpu(index, NULL)) + MIPS_CPU(qemu_get_cpu(index, TYPE_MIPS_CPU)) | - RISCV_CPU(qemu_get_cpu(index, NULL)) + RISCV_CPU(qemu_get_cpu(index, TYPE_RISCV_CPU)) | - S390_CPU(qemu_get_cpu(index, NULL)) + S390_CPU(qemu_get_cpu(index, TYPE_S390_CPU)) ) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/boot.c | 2 +- hw/arm/pxa2xx_gpio.c | 2 +- hw/arm/sbsa-ref.c | 2 +- hw/arm/virt-acpi-build.c | 2 +- hw/arm/virt.c | 6 +++--- hw/arm/xlnx-versal-virt.c | 2 +- hw/intc/arm_gicv3_cpuif.c | 2 +- hw/intc/arm_gicv3_kvm.c | 2 +- hw/intc/riscv_aclint.c | 2 +- hw/intc/sifive_plic.c | 2 +- hw/loongarch/virt.c | 6 +++--- hw/m68k/mcf5206.c | 2 +- target/mips/cpu.c | 2 +- target/s390x/cpu_models.c | 10 +++++----- 14 files changed, 22 insertions(+), 22 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index e260168cf5..f7def3a60c 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -438,7 +438,7 @@ static void fdt_add_psci_node(void *fdt) uint32_t cpu_off_fn; uint32_t cpu_on_fn; uint32_t migrate_fn; - ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(0, NULL)); + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)); const char *psci_method; int64_t psci_conduit; int rc; diff --git a/hw/arm/pxa2xx_gpio.c b/hw/arm/pxa2xx_gpio.c index 0a698171ab..9795451f19 100644 --- a/hw/arm/pxa2xx_gpio.c +++ b/hw/arm/pxa2xx_gpio.c @@ -303,7 +303,7 @@ static void pxa2xx_gpio_realize(DeviceState *dev, Error= **errp) { PXA2xxGPIOInfo *s =3D PXA2XX_GPIO(dev); =20 - s->cpu =3D ARM_CPU(qemu_get_cpu(s->ncpu, NULL)); + s->cpu =3D ARM_CPU(qemu_get_cpu(s->ncpu, TYPE_ARM_CPU)); =20 qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines); qdev_init_gpio_out(dev, s->handler, s->lines); diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 3571d5038f..f6f64099c3 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -275,7 +275,7 @@ static void create_fdt(SBSAMachineState *sms) =20 for (cpu =3D sms->smp_cpus - 1; cpu >=3D 0; cpu--) { char *nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); - ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu, NULL)); + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu, TYPE_ARM_CPU)); CPUState *cs =3D CPU(armcpu); uint64_t mpidr =3D sbsa_ref_cpu_mp_affinity(sms, cpu); =20 diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index fd6c239c31..0d09007d9b 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -727,7 +727,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, 0, 3); /* Reserved */ =20 for (i =3D 0; i < MACHINE(vms)->smp.cpus; i++) { - ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(i, NULL)); + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(i, TYPE_ARM_CPU)); uint64_t physical_base_address =3D 0, gich =3D 0, gicv =3D 0; uint32_t vgic_interrupt =3D vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : = 0; uint32_t pmu_interrupt =3D arm_feature(&armcpu->env, ARM_FEATURE_P= MU) ? diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a8f9d88519..be31ef5718 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -355,7 +355,7 @@ static void fdt_add_timer_nodes(const VirtMachineState = *vms) =20 qemu_fdt_add_subnode(ms->fdt, "/timer"); =20 - armcpu =3D ARM_CPU(qemu_get_cpu(0, NULL)); + armcpu =3D ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)); if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { const char compat[] =3D "arm,armv8-timer\0arm,armv7-timer"; qemu_fdt_setprop(ms->fdt, "/timer", "compatible", @@ -394,7 +394,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *v= ms) * at least one of them has Aff3 populated, we set #address-cells to 2. */ for (cpu =3D 0; cpu < smp_cpus; cpu++) { - ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu, NULL)); + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu, TYPE_ARM_CPU)); =20 if (armcpu->mp_affinity & ARM_AFF3_MASK) { addr_cells =3D 2; @@ -408,7 +408,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *v= ms) =20 for (cpu =3D smp_cpus - 1; cpu >=3D 0; cpu--) { char *nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); - ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu, NULL)); + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu, TYPE_ARM_CPU)); CPUState *cs =3D CPU(armcpu); =20 qemu_fdt_add_subnode(ms->fdt, nodename); diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 419ee3b882..2646b63b79 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -103,7 +103,7 @@ static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t p= sci_conduit) =20 for (i =3D XLNX_VERSAL_NR_ACPUS - 1; i >=3D 0; i--) { char *name =3D g_strdup_printf("/cpus/cpu@%d", i); - ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(i, NULL)); + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(i, TYPE_ARM_CPU)); =20 qemu_fdt_add_subnode(s->fdt, name); qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity); diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index f765b3d4b5..3b11b33b3e 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -2795,7 +2795,7 @@ void gicv3_init_cpuif(GICv3State *s) int i; =20 for (i =3D 0; i < s->num_cpu; i++) { - ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(i, NULL)); + ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(i, TYPE_ARM_CPU)); GICv3CPUState *cs =3D &s->cpu[i]; =20 /* diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index d1ff9886aa..440a84f0fe 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -808,7 +808,7 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Err= or **errp) gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL); =20 for (i =3D 0; i < s->num_cpu; i++) { - ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(i, NULL)); + ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(i, TYPE_ARM_CPU)); =20 define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); } diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index a97c0449ec..7e57c03ef7 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -483,7 +483,7 @@ static void riscv_aclint_swi_realize(DeviceState *dev, = Error **errp) =20 /* Claim software interrupt bits */ for (i =3D 0; i < swi->num_harts; i++) { - RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(swi->hartid_base + i, NUL= L)); + RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(swi->hartid_base + i, TYP= E_RISCV_CPU)); /* We don't claim mip.SSIP because it is writable by software */ if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0)= { error_report("MSIP already claimed"); diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index a32e7f1924..3e2534ac04 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -392,7 +392,7 @@ static void sifive_plic_realize(DeviceState *dev, Error= **errp) * hardware controlled when a PLIC is attached. */ for (i =3D 0; i < s->num_harts; i++) { - RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(s->hartid_base + i, NULL)= ); + RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(s->hartid_base + i, TYPE_= RISCV_CPU)); if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) { error_setg(errp, "SEIP already claimed"); return; diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index e888aea892..902e32a3e3 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -170,7 +170,7 @@ static void fdt_add_cpu_nodes(const LoongArchMachineSta= te *lams) /* cpu nodes */ for (num =3D smp_cpus - 1; num >=3D 0; num--) { char *nodename =3D g_strdup_printf("/cpus/cpu@%d", num); - LoongArchCPU *cpu =3D LOONGARCH_CPU(qemu_get_cpu(num, NULL)); + LoongArchCPU *cpu =3D LOONGARCH_CPU(qemu_get_cpu(num, TYPE_LOONGAR= CH_CPU)); CPUState *cs =3D CPU(cpu); =20 qemu_fdt_add_subnode(ms->fdt, nodename); @@ -726,7 +726,7 @@ static void loongarch_direct_kernel_boot(LoongArchMachi= neState *lams, kernel_addr =3D load_kernel_info(loaderparams); if (!machine->firmware) { for (i =3D 0; i < machine->smp.cpus; i++) { - lacpu =3D LOONGARCH_CPU(qemu_get_cpu(i, NULL)); + lacpu =3D LOONGARCH_CPU(qemu_get_cpu(i, TYPE_LOONGARCH_CPU)); lacpu->env.load_elf =3D true; lacpu->env.elf_address =3D kernel_addr; } @@ -859,7 +859,7 @@ static void loongarch_init(MachineState *machine) fdt_add_flash_node(lams); /* register reset function */ for (i =3D 0; i < machine->smp.cpus; i++) { - lacpu =3D LOONGARCH_CPU(qemu_get_cpu(i, NULL)); + lacpu =3D LOONGARCH_CPU(qemu_get_cpu(i, TYPE_LOONGARCH_CPU)); qemu_register_reset(reset_load_elf, lacpu); } /* Initialize the IO interrupt subsystem */ diff --git a/hw/m68k/mcf5206.c b/hw/m68k/mcf5206.c index a0851f58a9..d409c25ee6 100644 --- a/hw/m68k/mcf5206.c +++ b/hw/m68k/mcf5206.c @@ -601,7 +601,7 @@ static void mcf5206_mbar_realize(DeviceState *dev, Erro= r **errp) s->timer[1] =3D m5206_timer_init(s->pic[10]); s->uart[0] =3D mcf_uart_init(s->pic[12], serial_hd(0)); s->uart[1] =3D mcf_uart_init(s->pic[13], serial_hd(1)); - s->cpu =3D M68K_CPU(qemu_get_cpu(0, NULL)); + s->cpu =3D M68K_CPU(qemu_get_cpu(0, TYPE_M68K_CPU)); } =20 static void mcf5206_mbar_class_init(ObjectClass *oc, void *data) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 17e9e06a15..3ba329fa61 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -117,7 +117,7 @@ static void mips_cpu_dump_state(CPUState *cs, FILE *f, = int flags) =20 void cpu_set_exception_base(int vp_index, target_ulong address) { - MIPSCPU *vp =3D MIPS_CPU(qemu_get_cpu(vp_index, NULL)); + MIPSCPU *vp =3D MIPS_CPU(qemu_get_cpu(vp_index, TYPE_MIPS_CPU)); vp->env.exception_base =3D address; } =20 diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index 4a44ee56a9..7d1f5df114 100644 --- a/target/s390x/cpu_models.c +++ b/target/s390x/cpu_models.c @@ -150,7 +150,7 @@ uint32_t s390_get_hmfai(void) static S390CPU *cpu; =20 if (!cpu) { - cpu =3D S390_CPU(qemu_get_cpu(0, NULL)); + cpu =3D S390_CPU(qemu_get_cpu(0, TYPE_S390_CPU)); } =20 if (!cpu || !cpu->model) { @@ -164,7 +164,7 @@ uint8_t s390_get_mha_pow(void) static S390CPU *cpu; =20 if (!cpu) { - cpu =3D S390_CPU(qemu_get_cpu(0, NULL)); + cpu =3D S390_CPU(qemu_get_cpu(0, TYPE_S390_CPU)); } =20 if (!cpu || !cpu->model) { @@ -179,7 +179,7 @@ uint32_t s390_get_ibc_val(void) static S390CPU *cpu; =20 if (!cpu) { - cpu =3D S390_CPU(qemu_get_cpu(0, NULL)); + cpu =3D S390_CPU(qemu_get_cpu(0, TYPE_S390_CPU)); } =20 if (!cpu || !cpu->model) { @@ -199,7 +199,7 @@ void s390_get_feat_block(S390FeatType type, uint8_t *da= ta) static S390CPU *cpu; =20 if (!cpu) { - cpu =3D S390_CPU(qemu_get_cpu(0, NULL)); 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Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrey Smirnov , Radoslaw Biernacki , Leif Lindholm , Marcin Juszkiewicz Subject: [PATCH 03/19] cpus: Filter for target specific CPU (arm) Date: Fri, 20 Oct 2023 18:36:25 +0200 Message-ID: <20231020163643.86105-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=philmd@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697819894456100001 Enforce qemu_get_cpu() to return ARM CPUs in ARM specific files. Mechanical change using the following coccinelle script: @@ expression index; @@ - qemu_get_cpu(index, NULL) + qemu_get_cpu(index, TYPE_ARM_CPU) and manually including "target/arm/cpu-qom.h" in hw/intc/arm_gicv3_common.c. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/fsl-imx7.c | 2 +- hw/arm/sbsa-ref.c | 2 +- hw/arm/vexpress.c | 2 +- hw/arm/virt.c | 2 +- hw/cpu/a15mpcore.c | 4 ++-- hw/cpu/a9mpcore.c | 2 +- hw/intc/arm_gicv3_common.c | 3 ++- 7 files changed, 9 insertions(+), 8 deletions(-) diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 1c1585f3e1..7a62e9f5cf 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -212,7 +212,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) =20 for (i =3D 0; i < smp_cpus; i++) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->a7mpcore); - DeviceState *d =3D DEVICE(qemu_get_cpu(i, NULL)); + DeviceState *d =3D DEVICE(qemu_get_cpu(i, TYPE_ARM_CPU)); =20 irq =3D qdev_get_gpio_in(d, ARM_CPU_IRQ); sysbus_connect_irq(sbd, i, irq); diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index f6f64099c3..a85004809f 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -478,7 +478,7 @@ static void create_gic(SBSAMachineState *sms, MemoryReg= ion *mem) * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inpu= ts. */ for (i =3D 0; i < smp_cpus; i++) { - DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i, NULL)); + DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i, TYPE_ARM_CPU)); int ppibase =3D NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; int irq; /* diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 0590332fe5..e20d865d5a 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -257,7 +257,7 @@ static void init_cpus(MachineState *ms, const char *cpu= _type, =20 /* Connect the CPUs to the GIC */ for (n =3D 0; n < smp_cpus; n++) { - DeviceState *cpudev =3D DEVICE(qemu_get_cpu(n, NULL)); + DeviceState *cpudev =3D DEVICE(qemu_get_cpu(n, TYPE_ARM_CPU)); =20 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ= )); sysbus_connect_irq(busdev, n + smp_cpus, diff --git a/hw/arm/virt.c b/hw/arm/virt.c index be31ef5718..da5b738f0a 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -799,7 +799,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inpu= ts. */ for (i =3D 0; i < smp_cpus; i++) { - DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i, NULL)); + DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i, TYPE_ARM_CPU)); int ppibase =3D NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; /* Mapping from the output timer irq lines from the CPU to the * GIC PPI inputs we use for the virt board. diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index 8c9098d5d3..7ec5b27207 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -65,7 +65,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **= errp) /* Make the GIC's TZ support match the CPUs. We assume that * either all the CPUs have TZ, or none do. */ - cpuobj =3D OBJECT(qemu_get_cpu(0, NULL)); + cpuobj =3D OBJECT(qemu_get_cpu(0, TYPE_ARM_CPU)); has_el3 =3D object_property_find(cpuobj, "has_el3") && object_property_get_bool(cpuobj, "has_el3", &error_abort); qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); @@ -90,7 +90,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **= errp) * appropriate GIC PPI inputs */ for (i =3D 0; i < s->num_cpu; i++) { - DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i, NULL)); + DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i, TYPE_ARM_CPU)); int ppibase =3D s->num_irq - 32 + i * 32; int irq; /* Mapping from the output timer irq lines from the CPU to the diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 62b7fb3836..a9919ac78a 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -56,7 +56,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **e= rrp) CPUState *cpu0; Object *cpuobj; =20 - cpu0 =3D qemu_get_cpu(0, NULL); + cpu0 =3D qemu_get_cpu(0, TYPE_ARM_CPU); cpuobj =3D OBJECT(cpu0); if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9")= )) { /* We might allow Cortex-A5 once we model it */ diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index cdf21dfc11..e7ad5aa202 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -31,6 +31,7 @@ #include "migration/vmstate.h" #include "gicv3_internal.h" #include "hw/arm/linux-boot-if.h" +#include "target/arm/cpu-qom.h" #include "sysemu/kvm.h" =20 =20 @@ -392,7 +393,7 @@ static void arm_gicv3_common_realize(DeviceState *dev, = Error **errp) s->cpu =3D g_new0(GICv3CPUState, s->num_cpu); =20 for (i =3D 0; i < s->num_cpu; i++) { - CPUState *cpu =3D qemu_get_cpu(i, NULL); + CPUState *cpu =3D qemu_get_cpu(i, TYPE_ARM_CPU); uint64_t cpu_affid; =20 s->cpu[i].cpu =3D cpu; --=20 2.41.0 From nobody Thu Nov 20 03:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697820095; cv=none; d=zohomail.com; s=zohoarc; b=Ll+LgO0djFnAiNZtOUEoQ4QlD66maZm8Et6LQx/0fQZtg5OK7ZAh/Ivmg7t/D/Zzf6dGE3JEBQm82h63WvMbkZ+nsh8Hv8Zobh9Kk6KsGqLMMyFEPCQWb1fPMc/5wvC0k1gGF21nxM1TWkwLz0gRhMrBghZdai37g5sfFUEPNhM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697820095; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zp11byryPsUZ+4H8wFI4Zq/E/xqbK9hz7sAlcv7KVqc=; b=UY3+q1Op9K4wEoMvPWyl9tTl6ADO56tiRvPUA6hMqioUtdqUSpJXm841jmqOAoYOreUWSmpcr2eWNjPmalGHMh31S5cqE95PmuLEtHf7g6vuqaUWS1CC50jeNo4y2e38X1tUBrZqwMNMmfcYi/OlzgpC6ohybQbdseEBL4Pi5Mw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697820095864893.8096458162635; Fri, 20 Oct 2023 09:41:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtsVb-0003Mh-67; Fri, 20 Oct 2023 12:37:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtsVF-000362-DB for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:37:38 -0400 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtsVB-0002SK-1p for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:37:37 -0400 Received: by mail-ed1-x52a.google.com with SMTP id 4fb4d7f45d1cf-53e2308198eso1558078a12.1 for ; Fri, 20 Oct 2023 09:37:23 -0700 (PDT) Received: from m1x-phil.lan (tbo33-h01-176-171-212-97.dsl.sta.abo.bbox.fr. [176.171.212.97]) by smtp.gmail.com with ESMTPSA id n15-20020aa7c68f000000b0053eb9af1e15sm1738773edq.77.2023.10.20.09.37.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 09:37:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697819841; x=1698424641; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zp11byryPsUZ+4H8wFI4Zq/E/xqbK9hz7sAlcv7KVqc=; b=pLFg/PqwhSxLxyBpw1me7T4KXzVJ/MTeFtyPi8i2DFSvz4V1SOGcmKqQPt3lOh1IKX pWHOF3VZ3bOnTtH/6uMNsOwUG44qWCBS+GVl2zoi2J2OIF/APym4TrQBRKhgv0SeavxC /JgPk4WEieSKaQGwpnin3b0l+7YnznBXqU9QvgBTyK1EohwGXaMs0VqhjErz60PXtRC/ WrMzuzxGXSiAXkQenS8xQ5sFducfDLWTa/j6RRtulpWz2M7vIpcCADD5xetMU9rNg14u V6cfVEhduT3TmuYTI3Vl3TB4P9epli+zbi77/Hx9fkQTYLCPvK7FmfCOjLOLtID0odvc ldqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697819841; x=1698424641; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zp11byryPsUZ+4H8wFI4Zq/E/xqbK9hz7sAlcv7KVqc=; b=cdFiAYw6kXvjlmerwNMxpaJwWSbZUpJfcV9Fd13XMKHk5k2B+3tkqnB9iEUhT5hn7A IAPKL9HDl4X9qaEnFlgzGHcLsK3yekyD4+9ZBNMPh/ksBRWjELiWSLaolUVbqD1Xf7Xt 66o7CxGll0mJP4+bLY7THESB/IFj/phxU89TgTtysgaMS0iSlBY0uHd7z7OcTJ0ZmNAm kdsZBebQOsLJJTYc+JKwqqh6iXz647gMlqiJtn6HJOCSbvfZjXH5RV47FXrOuW8CQjWn y0MZaIl/6hy4l6ZSa1vxWFp6Q7stgv+7MFUze0/s3/y6LctV65NC1u1qVO4qYylWDQhq 0B9w== X-Gm-Message-State: AOJu0Yxd0rgAvyauhl2Wb7i4q7K1szGm0ALFHU9sUCdL2TNhyc2XznCe 38P3/SmdYD2/hpovRsiRW9eDHUec1APU/2EDg0w= X-Google-Smtp-Source: AGHT+IEiQRd93j6ORFqt6LLksrDvAtJ4jFmSOqwmG0w/kRCYG+YCyMIOK8p9iSZNmwu/QJv5BPBqFg== X-Received: by 2002:a50:d542:0:b0:53f:a4f7:7bfb with SMTP id f2-20020a50d542000000b0053fa4f77bfbmr1827246edj.17.1697819841503; Fri, 20 Oct 2023 09:37:21 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, "Edgar E. Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Song Gao Subject: [PATCH 04/19] cpus: Filter for target specific CPU (loongarch) Date: Fri, 20 Oct 2023 18:36:26 +0200 Message-ID: <20231020163643.86105-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=philmd@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697820097184100003 Enforce qemu_get_cpu() to return LoongArch CPUs in LoongArch specific files. Mechanical change using the following coccinelle script: @@ expression index; @@ - qemu_get_cpu(index, NULL) + qemu_get_cpu(index, TYPE_LOONGARCH_CPU) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/loongarch/virt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 902e32a3e3..83ca7d6b98 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -560,7 +560,7 @@ static void loongarch_irq_init(LoongArchMachineState *l= ams) * +--------+ +---------+ +---------+ */ for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { - cpu_state =3D qemu_get_cpu(cpu, NULL); + cpu_state =3D qemu_get_cpu(cpu, TYPE_LOONGARCH_CPU); cpudev =3D DEVICE(cpu_state); lacpu =3D LOONGARCH_CPU(cpu_state); env =3D &(lacpu->env); @@ -594,7 +594,7 @@ static void loongarch_irq_init(LoongArchMachineState *l= ams) * cpu_pin[9:2] <=3D intc_pin[7:0] */ for (cpu =3D 0; cpu < MIN(ms->smp.cpus, EXTIOI_CPUS); cpu++) { - cpudev =3D DEVICE(qemu_get_cpu(cpu, NULL)); + cpudev =3D DEVICE(qemu_get_cpu(cpu, TYPE_LOONGARCH_CPU)); for (pin =3D 0; pin < LS3A_INTC_IP; pin++) { qdev_connect_gpio_out(extioi, (cpu * 8 + pin), qdev_get_gpio_in(cpudev, pin + 2)); --=20 2.41.0 From nobody Thu Nov 20 03:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697820021; cv=none; d=zohomail.com; s=zohoarc; b=OBEA98d2FrycRQpXFvI7CbbZrSArk6Ti7xJcU14LHRJ4+79zLTIqi6vuWdLWoVHMbUu6atGN68b1O5AMH1wCnYQNK24cLorQkuKhcWa7NwhLNQRw8eIC7FTZYw3aolyTtBEJrZw+EKgsAY7jVB2l3JzIBohHEixy4jG1WaurQHc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697820021; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TUBi9PwmyHFRdVnHd5x4eIWhteYAhCTGnXhaAjecfzc=; b=J1iUogJUR5UcpZZQTdeirrf3VHdaVa2rtguhvUsy0jKR2c03Q7F6bHKKD08MrLfXwZv4RhWotwjDfDdYHaSh1oDX941Oh+Pi12GdYnuVSJQdnGbA28JH0aEg7PL/A9H5H4WF95ZsSNXoU4snUTncRVRQ2frnfLOgPh+cptWqMH0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697820021920599.386442611835; Fri, 20 Oct 2023 09:40:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtsVb-0003QA-LA; Fri, 20 Oct 2023 12:37:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtsVF-000361-DM for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:37:38 -0400 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtsVB-0002Sy-2T for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:37:37 -0400 Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-9bf86b77a2aso158813466b.0 for ; Fri, 20 Oct 2023 09:37:30 -0700 (PDT) Received: from m1x-phil.lan (tbo33-h01-176-171-212-97.dsl.sta.abo.bbox.fr. [176.171.212.97]) by smtp.gmail.com with ESMTPSA id m2-20020a17090607c200b009c6a4a5ac80sm1774732ejc.169.2023.10.20.09.37.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 09:37:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697819848; x=1698424648; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TUBi9PwmyHFRdVnHd5x4eIWhteYAhCTGnXhaAjecfzc=; b=JL89DZE6nD1bqHxo2SO65A91neSY2S6g8HgDvcpnhGdkztUjrbr/Eoj7vZb+3HCX7k C2m7j3vVPEYsfEWTFrqy5dsh5gvwsRRS703qnWaEBumfkPSqDr9j1PznHHhxl7W4tKKr /tKeL6zqRCT84HkFIFJMK5hRKOQoRQNlBILQFvI6fxZ9YNsnF938Of0NEACd3QNKiaRU ZnwHQYPmMrtALr9sBgoK+ssXwuD2kJgjDFrWPgPN/W9LiD+IFaDDJt31xed8Jf2VYj6l K7WLxkUYh5SJpDPt1TKNUratdGaqGdCn+DzxPVOJJgPP7w2sOJBeAcAV4phLM7VDmkAC ud3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697819848; x=1698424648; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TUBi9PwmyHFRdVnHd5x4eIWhteYAhCTGnXhaAjecfzc=; b=QNvp37fMzDuYIWotQ2g6HDku/BXye+1D2DXIzftLHi3f36Rz2CIG8HEDj9HJA7Qj94 hc2iDB2iSBYcjGJ1qy7VzI3mphNlSgmHXy7iSvOyBc8b9MCyHQis/fmgEwZn3CUBtd7R 94FLxIpLByhd8veqCh3WSZ3HBsuRTeauX2mlBIwKjoZtJPNtaMiC2y/VZKc7pk+yD+lH VZa+wF1LrwJzcMkHXOy2s9gyGIXgzErAzqXzJBqFScmCvNPFSJe+i+3yheXGhnj80CfQ bqRkwpGfDvfc19rcUzxelrMdXsCb0yupbiJq0l5JDhB5jFF4uCaTT9n3M49d20RobEkq 8SEQ== X-Gm-Message-State: AOJu0YwhE541f+7Zm0u+i+n1TZZA7n0KeyTBZ+cEUrJOrFtXbYNhoLrL dacVufdTbNM7G+pVIPU5JQRpjPbm0506bXX0ETA= X-Google-Smtp-Source: AGHT+IHly4QZub59Ll2I4YbndNTZvqVJdsar+JhXYawd1k7qkul5/m3dgvxkbGUtuq6oLEHMDGA2sg== X-Received: by 2002:a17:907:2d92:b0:9c3:cd12:1929 with SMTP id gt18-20020a1709072d9200b009c3cd121929mr1719344ejc.60.1697819848740; Fri, 20 Oct 2023 09:37:28 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, "Edgar E. Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH 05/19] cpus: Filter for target specific CPU (mips) Date: Fri, 20 Oct 2023 18:36:27 +0200 Message-ID: <20231020163643.86105-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697820023134100007 Enforce qemu_get_cpu() to return MIPS CPUs in MIPS specific files. Mechanical change using the following coccinelle script: @@ expression index; @@ - qemu_get_cpu(index, NULL) + qemu_get_cpu(index, TYPE_MIPS_CPU) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/sysemu/cp0_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/c= p0_helper.c index fcaba37c40..af0cd60829 100644 --- a/target/mips/tcg/sysemu/cp0_helper.c +++ b/target/mips/tcg/sysemu/cp0_helper.c @@ -126,7 +126,7 @@ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env,= int *tc) cs =3D env_cpu(env); vpe_idx =3D tc_idx / cs->nr_threads; *tc =3D tc_idx % cs->nr_threads; - other_cs =3D qemu_get_cpu(vpe_idx, NULL); + other_cs =3D qemu_get_cpu(vpe_idx, TYPE_MIPS_CPU); if (other_cs =3D=3D NULL) { return env; } --=20 2.41.0 From nobody Thu Nov 20 03:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697820036; cv=none; d=zohomail.com; s=zohoarc; b=iCMJrc3xWysTAuPP5DYfmIBTcAmsgpFbg9Am7TH0jP+OfxGry959puZt8F1rUMq/bZSJz42v59rpvZnYsCu9pkxyRURG6kxHOhtR4aJ3WBY8wAUQlRDrDKZZ2aOprwa3aJQ3Uas5xAb7Rm5o6YR81MmeLNTGyVtjS6ie3HoNNcE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697820036; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Z4zSU56YOB/kPm9j9X/WOBopNqbVDhMN21ij6wb+YZU=; b=XYgOv3LLBN0n7/s1LTlxxPGziVzilS8Z/tBs//DiI3VylyM/9xY0cAcpCQgOzWdSI0OfaLCkyzx9vX02Q9sKr2qxWkDMBTB4yWPiCbb43RjwJfjxvoov3Jd7odFshQbCrNPpCc8Njx2rjRe44KApaTQlJ5k79iTc/v4XmsdVrUo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697820036506674.2390506175062; Fri, 20 Oct 2023 09:40:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtsVe-0003eZ-NP; Fri, 20 Oct 2023 12:38:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtsVK-0003C5-Mq for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:37:47 -0400 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtsVG-0002UN-JX for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:37:41 -0400 Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-9bf86b77a2aso158840866b.0 for ; Fri, 20 Oct 2023 09:37:37 -0700 (PDT) Received: from m1x-phil.lan (tbo33-h01-176-171-212-97.dsl.sta.abo.bbox.fr. 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Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Christian Borntraeger , Halil Pasic , Eric Farman , David Hildenbrand , Ilya Leoshkevich Subject: [PATCH 06/19] cpus: Filter for target specific CPU (s390x) Date: Fri, 20 Oct 2023 18:36:28 +0200 Message-ID: <20231020163643.86105-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=philmd@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697820036901100001 Enforce qemu_get_cpu() to return S390X CPUs in S390X specific files. Mechanical change using the following coccinelle script: @@ expression index; @@ - qemu_get_cpu(index, NULL) + qemu_get_cpu(index, TYPE_S390_CPU) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/s390x/ipl.c | 2 +- hw/s390x/s390-virtio-ccw.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c index 14cd0a1f7b..377f43416c 100644 --- a/hw/s390x/ipl.c +++ b/hw/s390x/ipl.c @@ -671,7 +671,7 @@ void s390_ipl_get_reset_request(CPUState **cs, enum s39= 0_reset *reset_type) { S390IPLState *ipl =3D get_ipl_device(); =20 - *cs =3D qemu_get_cpu(ipl->reset_cpu_index, NULL); + *cs =3D qemu_get_cpu(ipl->reset_cpu_index, TYPE_S390_CPU); if (!*cs) { /* use any CPU */ *cs =3D first_cpu; diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 7628b746a8..3bb4b13c5e 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -583,7 +583,7 @@ static HotplugHandler *s390_get_hotplug_handler(Machine= State *machine, =20 static void s390_nmi(NMIState *n, int cpu_index, Error **errp) { - CPUState *cs =3D qemu_get_cpu(cpu_index, NULL); + CPUState *cs =3D qemu_get_cpu(cpu_index, TYPE_S390_CPU); =20 s390_cpu_restart(S390_CPU(cs)); } --=20 2.41.0 From nobody Thu Nov 20 03:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697820006; cv=none; d=zohomail.com; s=zohoarc; b=aRi50i2qCpyVJDdSKWlMDv5iltdGZWnc6pANiRmRjS2IiqVi3xUhUwNPXfq28DrZBWnfvc/4SGzffhMjhTY1QAFvk2/fgtPVSEC1j7lDztZ+2XY4EAr6fkGjvS4QY2Adl5LrundtEOhY9ttH8J98enb5bpfUdsIRH+tRnt1TFOc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697820006; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=lIfqIPgjXaT+HDThdwR33vMHRV/AQLZXNgmR/zi6+zY=; b=RrpVK1ykOVFoiFevDr/diMEb0sRup+xMXjtYYMWI7Hg170QQTxP/vOO3Wh0V7f0gSbONPmBnTNvPhu1CmAwHwsi2WevZQWzMUYqj1acXyTvk8YUfGXsQcyt255e7q8VDnbcTMZrMBAb4zOgk/TR3eWfnu5DUQAUOy09Lgzvg0E4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697820006557762.5993609772049; Fri, 20 Oct 2023 09:40:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtsVc-0003VN-UG; Fri, 20 Oct 2023 12:38:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtsVY-0003J3-JA for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:37:58 -0400 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtsVN-0002WM-Ck for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:37:51 -0400 Received: by mail-ed1-x536.google.com with SMTP id 4fb4d7f45d1cf-523100882f2so1512230a12.2 for ; Fri, 20 Oct 2023 09:37:44 -0700 (PDT) Received: from m1x-phil.lan (tbo33-h01-176-171-212-97.dsl.sta.abo.bbox.fr. [176.171.212.97]) by smtp.gmail.com with ESMTPSA id m14-20020a50ef0e000000b0053f0e4e0411sm1747279eds.76.2023.10.20.09.37.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 09:37:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697819863; x=1698424663; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lIfqIPgjXaT+HDThdwR33vMHRV/AQLZXNgmR/zi6+zY=; b=szzuUPkKTNsnv2t0fwjExL1sKpkTOcPVMA6IXkOmzpnrB6qP9vnhOn1tVPm2tH9Liw vVGMXVNacKwDSP0whtCMpIfFZqkPBvnUFAad1CMTSPI594iBY7OgGZ5ZNMGNa+soJ90o PGPa53g1mBYrM7B4gPIQ7hVFQ53TnhSQHpZ8mKsjga5iiXngbpGjL60qLhTFOtzSVYYd ZWoaejGs8uBW4T4b1C0kCuaMZXG3UlspHvg8iRbbTWMGSlApDQ0hmFhz7+u3JHN1norT s1WTtyy7EaLtLqC1n48tEabRDjTNWRWc+Myh5KMWqdME90L4+B8kvSaJA0NypAluDTqA 7zkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697819863; x=1698424663; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lIfqIPgjXaT+HDThdwR33vMHRV/AQLZXNgmR/zi6+zY=; b=lBtkhvo/abPxmUQx1kQw8VgjeB3dY0rfLsLO4v2u9GV9EY8PXoE9iNlpQkaFvogiO/ Clj7TdFXUlCygoA+IFFJPF201aU8rKlyYQiFTKhDtgkA3XRHUAT7BZ9WVfB7MkiLiSxw E6iMRxPR1kOujZKP3EJWkpxu1x04176zVyIWSeZd4+rmpLujIUSkr3u/l7M9LID7uw8M oBl6AePu5J5b9Ouxmxg1x/9PVuZwXex34K0TAWwzDoEqV5sJsQOhRDSZYKGQmPecOJJn nQUakeD3v8EBV8WkHTNJJDNmEFhhvba+NMQIubkWlIWmkhR/A528DraaJQpbyToQIaZJ tTyg== X-Gm-Message-State: AOJu0YxeGseha8Fu/IcnTAPgkTIsE7tskUZPjv64xm4rcRXCuf184rE7 3GxwrvbuxTONYZ/sBn4rK4/aGaiWmZ+VHf7JyV8= X-Google-Smtp-Source: AGHT+IHBVyZvw4f5Hs2t7cng9Y5f77G/O2sVJ7W2ZL6Q5XN2PZL/Jc6G4ofUIv4JkhfUQQT3G+9t1Q== X-Received: by 2002:a50:ab12:0:b0:530:7ceb:33c with SMTP id s18-20020a50ab12000000b005307ceb033cmr1872603edc.4.1697819863159; Fri, 20 Oct 2023 09:37:43 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, "Edgar E. Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Bin Meng , Palmer Dabbelt , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PATCH 07/19] cpus: Filter for target specific CPU (riscv) Date: Fri, 20 Oct 2023 18:36:29 +0200 Message-ID: <20231020163643.86105-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=philmd@linaro.org; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697820009633100003 Enforce qemu_get_cpu() to return RISCV CPUs in RISCV specific files. Mechanical change using the following coccinelle script: @@ expression index; @@ - qemu_get_cpu(index, NULL) + qemu_get_cpu(index, TYPE_RISCV_CPU) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/sifive_plic.c | 2 +- hw/riscv/boot.c | 2 +- hw/riscv/opentitan.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 3e2534ac04..ea0e7af16e 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -499,7 +499,7 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart= _config, =20 for (i =3D 0; i < plic->num_addrs; i++) { int cpu_num =3D plic->addr_config[i].hartid; - CPUState *cpu =3D qemu_get_cpu(cpu_num, NULL); + CPUState *cpu =3D qemu_get_cpu(cpu_num, TYPE_RISCV_CPU); =20 if (plic->addr_config[i].mode =3D=3D PLICMode_M) { qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts, diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index ea733b3df1..1d004660d4 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -49,7 +49,7 @@ char *riscv_plic_hart_config_string(int hart_count) int i; =20 for (i =3D 0; i < hart_count; i++) { - CPUState *cs =3D qemu_get_cpu(i, NULL); + CPUState *cs =3D qemu_get_cpu(i, TYPE_RISCV_CPU); CPURISCVState *env =3D &RISCV_CPU(cs)->env; =20 if (kvm_enabled()) { diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index e98361de19..106ef5d2d0 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -190,7 +190,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_s= oc, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].bas= e); =20 for (i =3D 0; i < ms->smp.cpus; i++) { - CPUState *cpu =3D qemu_get_cpu(i, NULL); + CPUState *cpu =3D qemu_get_cpu(i, TYPE_RISCV_CPU); =20 qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i, qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT)); @@ -223,7 +223,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_s= oc, Error **errp) 0, qdev_get_gpio_in(DEVICE(&s->plic), IBEX_TIMER_TIMEREXPIRED0_0)); qdev_connect_gpio_out(DEVICE(&s->timer), 0, - qdev_get_gpio_in(DEVICE(qemu_get_cpu(0, NULL)), + qdev_get_gpio_in(DEVICE(qemu_get_cpu(0, TYPE_RIS= CV_CPU)), IRQ_M_TIMER)); =20 /* SPI-Hosts */ --=20 2.41.0 From nobody Thu Nov 20 03:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697820121; cv=none; d=zohomail.com; s=zohoarc; b=ewg0AxXhHg9u8LYvcy/VgWluSwXdaWF3ph2rz/HZkUCnApAqb27l0dGnpyWRialK+x3f9nWK1hoUb/Mw5LwTD1OLDgbU0OhZ6kQTq+w/hUFgkqfgn7Ecmw2J9spxVieYbfnVNjq+e7tXDQcYnOXOxNnfzIZoy1/qgLikJ5zPGJE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697820121; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=q4kg06JcXQgpZkYD+aAuvNPHOfoXMdKM9u+t0AGSCsc=; b=LcDVIHyj1ZRF27SOVMo6nP6DuU8yuUY46MDjy2InmvW26u2a3epWxVV9vc+0NQ4O9RVI65Y1xfXOcOZel/H53BfVDtbpW3PpaneJYkZO1Un703kweqDYNloHRWH1lNYp3e3HxKA8YO7807SKLvoIQO76Qi6MGYEy88qwOjjYFjQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697820121559513.5426267103325; Fri, 20 Oct 2023 09:42:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtsVc-0003U7-Fq; Fri, 20 Oct 2023 12:38:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtsVa-0003Mb-TH for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:37:58 -0400 Received: from mail-ed1-x52e.google.com ([2a00:1450:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtsVX-0002XI-3H for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:37:58 -0400 Received: by mail-ed1-x52e.google.com with SMTP id 4fb4d7f45d1cf-53e2308198eso1558831a12.1 for ; Fri, 20 Oct 2023 09:37:51 -0700 (PDT) Received: from m1x-phil.lan (tbo33-h01-176-171-212-97.dsl.sta.abo.bbox.fr. [176.171.212.97]) by smtp.gmail.com with ESMTPSA id c21-20020a50d655000000b00537963f692esm1813284edj.0.2023.10.20.09.37.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 09:37:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697819869; x=1698424669; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q4kg06JcXQgpZkYD+aAuvNPHOfoXMdKM9u+t0AGSCsc=; b=y7TDR7gocgMIl43p3qs3dE9Hi/fpBdYlyg1vuedF75sXYg0bImBkPCLvD65FmDVYQZ t0U1VUeOlQYzyXh3tdsUfFSaRYnQrMoKzysSOLHfRsa9+0kLJQQECZ9TYARW0jBCerOk yaLMyf1420PsqnIgz5yMVMhyLzzCxCVflxkkfJIlMoxFqvYAI63N+obNSsKFVajxRL6R +7KvU/wF7cjU8Cd95j5p2IZU/XbHyr0sYnbasAnf8BTwd0VAqbMu2sQ97I8wDT4HJGzj 9M5JiHYv57eBmMd6qLh+rCv7rdKlGRdfMbtekuRWuodMsDC8kzCw/Hrxw4rrRxNIWkj4 XjPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697819869; x=1698424669; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q4kg06JcXQgpZkYD+aAuvNPHOfoXMdKM9u+t0AGSCsc=; b=ukV0haGO9G6Lehz4kpS7bofn+U6i10cqxvBFERzKTt2L0Kqr2qFArnALcq1ZBguS5S F6NTKpW4vCDJWDz7+JX1a5jvvHJabpY2I6PMH24DU/EmdAgZbVXLWyQ1eKint4w3SU50 sFox7B+L+dVc5SoOoEeZ7w6/vEMVBQ472DhD4MmLSm5tER6pd6ikLEUO0GHGAdwUHivS iAQDte1Oac31hiENW5KSBB5MxzDuHURo5fyXOAX4N/g/uaNvGDR4hIjPMptX1IhIaMxl PdmwJ9ZrTf/MQuzqbX9sNPE5gjiBTmahuYkrLj4FNhzweg2Q2FQwrEjdMBCqxDV5KjT7 NJIw== X-Gm-Message-State: AOJu0YwMOC80zC79kdKdDX5pTEk0XJkxyCSsuoJPtgozxymtMFrVdyuj +sZFuQjAHYGQVIc9ZsF63uo8+iEC/xoBaoo7YIE= X-Google-Smtp-Source: AGHT+IEdrkG9FwSyY/AKa9oPX4+3ml15l30g0cytwWkx3WA2O/VxxtOxCvAUt/yP8dWulgtn962GBQ== X-Received: by 2002:a50:d542:0:b0:53f:a4f7:7bfb with SMTP id f2-20020a50d542000000b0053fa4f77bfbmr1828115edj.17.1697819869764; Fri, 20 Oct 2023 09:37:49 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, "Edgar E. Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 08/19] cpus: Filter for target specific CPU (ppc) Date: Fri, 20 Oct 2023 18:36:30 +0200 Message-ID: <20231020163643.86105-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=philmd@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697820123314100001 Enforce qemu_get_cpu() to return PPC CPUs in PPC specific files. Mechanical change using the following coccinelle script: @@ expression index; @@ - qemu_get_cpu(index, NULL) + qemu_get_cpu(index, TYPE_POWERPC_CPU) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/ppc/e500.c | 2 +- hw/ppc/ppce500_spin.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 380bbe1fe6..c4bf3fef32 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -495,7 +495,7 @@ static int ppce500_load_device_tree(PPCE500MachineState= *pms, char *cpu_name; uint64_t cpu_release_addr =3D pmc->spin_base + (i * 0x20); =20 - cpu =3D qemu_get_cpu(i, NULL); + cpu =3D qemu_get_cpu(i, TYPE_POWERPC_CPU); if (cpu =3D=3D NULL) { continue; } diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index 3b113fbbdb..142bd45f18 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -125,7 +125,7 @@ static void spin_write(void *opaque, hwaddr addr, uint6= 4_t value, SpinInfo *curspin =3D &s->spin[env_idx]; uint8_t *curspin_p =3D (uint8_t*)curspin; =20 - cpu =3D qemu_get_cpu(env_idx, NULL); + cpu =3D qemu_get_cpu(env_idx, TYPE_POWERPC_CPU); if (cpu =3D=3D NULL) { /* Unknown CPU */ return; --=20 2.41.0 From nobody Thu Nov 20 03:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697819932; cv=none; d=zohomail.com; s=zohoarc; b=U2+YNIkzji52ANaEKMICs3vHVTl/qZ8Wd4XGQfktIMX8NWsXuxGGXgka110wbQxGuWlEKeBalVoLjHTlDpFgpTK4oly8wg4Zrek3l+FcvkdzwmJSiKdYOQrk0wyTR9QVtHo1sykfNyYV4F4z/nHXTuk8HCV2WZAA5EIKZE1aido= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697819932; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0QpJSioSzBNTf91irQMN8BpZyzwJ1kd2+nNN3fujF2w=; b=HKP5aq1qsr87boSZdL2UR3OdkM1juM41YSQP+pQ9Y+O2tpffkTaqzCsXp17tJZj16K9m3cupZN8qRNCSu87FFyZw16rdPswj6E7KlmGS6NTWVI6xdkRJkIE0hJBeVVr+eJVAL0bw8BX/3YtcFW2ou1JISsDfGzK2ksttzITU8EQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697819932487872.5372328791574; Fri, 20 Oct 2023 09:38:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtsVh-0003mw-0g; Fri, 20 Oct 2023 12:38:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtsVe-0003f3-OH for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:38:02 -0400 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtsVb-0002aJ-Ec for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:38:02 -0400 Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-9ba081173a3so170513466b.1 for ; Fri, 20 Oct 2023 09:37:58 -0700 (PDT) Received: from m1x-phil.lan (tbo33-h01-176-171-212-97.dsl.sta.abo.bbox.fr. [176.171.212.97]) by smtp.gmail.com with ESMTPSA id pw17-20020a17090720b100b009bd9ac83a9fsm1771713ejb.152.2023.10.20.09.37.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 09:37:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697819877; x=1698424677; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0QpJSioSzBNTf91irQMN8BpZyzwJ1kd2+nNN3fujF2w=; b=jD507VLv1Q3DXpYYv4XOY/iKw6lLXZelPaf6QslcZil7D12UZCuiVO8B5iBcKmcPXA uUgR1ATUBPeS64AbMhWzUvMVfp/PjwlDbY//xeEMixhQmzYJ5ZtNtKnq5e/fkmU3NB0r RWA5F7R7LlBzooUvEPScCz7b87wTNVnYId5aWb3zsuNhpi6GBkn70H4ilk7s0MYVeTBb NgyluahTH9RUMpuC81gJ2pD7XRfQazMl8QV6/nj0bifO/CmodxTa35x9421PvtZK/A65 Y9+O/m90cvcq8tT8r5enqHD3s/4oS8G8VGN13ZJ6sWQ86PJupGKC7nUQGS6XwvS47jrF QVwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697819877; x=1698424677; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0QpJSioSzBNTf91irQMN8BpZyzwJ1kd2+nNN3fujF2w=; b=g/s3/WOaTChRaQTjkIyOccNJMqjwqF37KQ00DfjsMZfpZmT8SrR8Kx5WunSnuTvhBg E7+UoD9Ps4/Knp8VQ/AhDO7YnXru7p6148++bpc9k7lZKY7EnBwLjKGRgtLXZ0WGcffo +TMCn00Tnp9+vd1R8H9GGR3WFtTc7c1QMQdkr4Y45xTFiF/xHOso9RGI4JZljf3vms3E KnNsWSNVo8W2a0MHbWe+zjTKgkL9+idBjKl3IlTCoV0j8akga+gyoPHET8EZj59eRjfP bPIuVuRK8DVeqRuwv6FbblDN28lkFOKXxZBnoaf4EwEFaMkMJiGQKQHeTHiSJvIj1Dbp 1OZg== X-Gm-Message-State: AOJu0YwmQywj0lm4dXQLsEI3wRPVHVDoz553geW+4i3w41i/qqyvsAYp AGCi0pUy5wAxq6jeoVqSTEa8sVlerZZSZGTDBS0= X-Google-Smtp-Source: AGHT+IHqqcCwQhtVKj3SGAIse1HKAYov1qgaQecpg8n6CsqYo+8qJqXaoPpYybRA/SRbJ+rMfgxwJw== X-Received: by 2002:a17:907:988:b0:9c5:2806:72e2 with SMTP id bf8-20020a170907098800b009c5280672e2mr1733573ejc.34.1697819877055; Fri, 20 Oct 2023 09:37:57 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, "Edgar E. Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , David Woodhouse , Paul Durrant , Marcel Apfelbaum , Marcelo Tosatti , kvm@vger.kernel.org Subject: [PATCH 09/19] cpus: Filter for target specific CPU (x86) Date: Fri, 20 Oct 2023 18:36:31 +0200 Message-ID: <20231020163643.86105-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=philmd@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697819934533100003 Enforce qemu_get_cpu() to return X86 CPUs in X86 specific files. Mechanical change using the following coccinelle script: @@ expression index; @@ - qemu_get_cpu(index, NULL) + qemu_get_cpu(index, TYPE_X86_CPU) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/hyperv/hyperv.c | 2 +- hw/i386/kvm/xen_evtchn.c | 8 ++++---- target/i386/kvm/xen-emu.c | 14 +++++++------- target/i386/monitor.c | 2 +- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/hw/hyperv/hyperv.c b/hw/hyperv/hyperv.c index a43f29ad8d..cdda93e14d 100644 --- a/hw/hyperv/hyperv.c +++ b/hw/hyperv/hyperv.c @@ -226,7 +226,7 @@ struct HvSintRoute { =20 static CPUState *hyperv_find_vcpu(uint32_t vp_index) { - CPUState *cs =3D qemu_get_cpu(vp_index, NULL); + CPUState *cs =3D qemu_get_cpu(vp_index, TYPE_X86_CPU); assert(hyperv_vp_index(cs) =3D=3D vp_index); return cs; } diff --git a/hw/i386/kvm/xen_evtchn.c b/hw/i386/kvm/xen_evtchn.c index de3650ba3b..d75b53934d 100644 --- a/hw/i386/kvm/xen_evtchn.c +++ b/hw/i386/kvm/xen_evtchn.c @@ -542,7 +542,7 @@ static void deassign_kernel_port(evtchn_port_t port) static int assign_kernel_port(uint16_t type, evtchn_port_t port, uint32_t vcpu_id) { - CPUState *cpu =3D qemu_get_cpu(vcpu_id, NULL); + CPUState *cpu =3D qemu_get_cpu(vcpu_id, TYPE_X86_CPU); struct kvm_xen_hvm_attr ha; =20 if (!cpu) { @@ -589,7 +589,7 @@ static bool valid_port(evtchn_port_t port) =20 static bool valid_vcpu(uint32_t vcpu) { - return !!qemu_get_cpu(vcpu, NULL); + return !!qemu_get_cpu(vcpu, TYPE_X86_CPU); } =20 static void unbind_backend_ports(XenEvtchnState *s) @@ -917,7 +917,7 @@ static int set_port_pending(XenEvtchnState *s, evtchn_p= ort_t port) =20 if (s->evtchn_in_kernel) { XenEvtchnPort *p =3D &s->port_table[port]; - CPUState *cpu =3D qemu_get_cpu(p->vcpu, NULL); + CPUState *cpu =3D qemu_get_cpu(p->vcpu, TYPE_X86_CPU); struct kvm_irq_routing_xen_evtchn evt; =20 if (!cpu) { @@ -1779,7 +1779,7 @@ int xen_evtchn_translate_pirq_msi(struct kvm_irq_rout= ing_entry *route, return -EINVAL; } =20 - cpu =3D qemu_get_cpu(s->port_table[port].vcpu, NULL); + cpu =3D qemu_get_cpu(s->port_table[port].vcpu, TYPE_X86_CPU); if (!cpu) { return -EINVAL; } diff --git a/target/i386/kvm/xen-emu.c b/target/i386/kvm/xen-emu.c index f289af906c..0a973c0259 100644 --- a/target/i386/kvm/xen-emu.c +++ b/target/i386/kvm/xen-emu.c @@ -384,7 +384,7 @@ static void do_set_vcpu_info_gpa(CPUState *cs, run_on_c= pu_data data) =20 void *kvm_xen_get_vcpu_info_hva(uint32_t vcpu_id) { - CPUState *cs =3D qemu_get_cpu(vcpu_id, NULL); + CPUState *cs =3D qemu_get_cpu(vcpu_id, TYPE_X86_CPU); if (!cs) { return NULL; } @@ -418,7 +418,7 @@ void kvm_xen_maybe_deassert_callback(CPUState *cs) =20 void kvm_xen_set_callback_asserted(void) { - CPUState *cs =3D qemu_get_cpu(0, NULL); + CPUState *cs =3D qemu_get_cpu(0, TYPE_X86_CPU); =20 if (cs) { X86_CPU(cs)->env.xen_callback_asserted =3D true; @@ -427,7 +427,7 @@ void kvm_xen_set_callback_asserted(void) =20 void kvm_xen_inject_vcpu_callback_vector(uint32_t vcpu_id, int type) { - CPUState *cs =3D qemu_get_cpu(vcpu_id, NULL); + CPUState *cs =3D qemu_get_cpu(vcpu_id, TYPE_X86_CPU); uint8_t vector; =20 if (!cs) { @@ -491,7 +491,7 @@ static void do_set_vcpu_timer_virq(CPUState *cs, run_on= _cpu_data data) =20 int kvm_xen_set_vcpu_virq(uint32_t vcpu_id, uint16_t virq, uint16_t port) { - CPUState *cs =3D qemu_get_cpu(vcpu_id, NULL); + CPUState *cs =3D qemu_get_cpu(vcpu_id, TYPE_X86_CPU); =20 if (!cs) { return -ENOENT; @@ -588,7 +588,7 @@ static int xen_set_shared_info(uint64_t gfn) trace_kvm_xen_set_shared_info(gfn); =20 for (i =3D 0; i < XEN_LEGACY_MAX_VCPUS; i++) { - CPUState *cpu =3D qemu_get_cpu(i, NULL); + CPUState *cpu =3D qemu_get_cpu(i, TYPE_X86_CPU); if (cpu) { async_run_on_cpu(cpu, do_set_vcpu_info_default_gpa, RUN_ON_CPU_HOST_ULONG(gpa)); @@ -834,7 +834,7 @@ static int kvm_xen_hcall_evtchn_upcall_vector(struct kv= m_xen_exit *exit, return -EINVAL; } =20 - target_cs =3D qemu_get_cpu(up.vcpu, NULL); + target_cs =3D qemu_get_cpu(up.vcpu, TYPE_X86_CPU); if (!target_cs) { return -EINVAL; } @@ -1161,7 +1161,7 @@ static bool kvm_xen_hcall_vcpu_op(struct kvm_xen_exit= *exit, X86CPU *cpu, { CPUState *cs =3D CPU(cpu); CPUState *dest =3D cs->cpu_index =3D=3D vcpu_id ? cs : qemu_get_cpu(vc= pu_id, - NULL); + TYPE_X86= _CPU); int err; =20 if (!dest) { diff --git a/target/i386/monitor.c b/target/i386/monitor.c index aca7be61dd..01bfb4e3f1 100644 --- a/target/i386/monitor.c +++ b/target/i386/monitor.c @@ -592,7 +592,7 @@ void hmp_mce(Monitor *mon, const QDict *qdict) if (qdict_get_try_bool(qdict, "broadcast", false)) { flags |=3D MCE_INJECT_BROADCAST; } - cs =3D qemu_get_cpu(cpu_index, NULL); + cs =3D qemu_get_cpu(cpu_index, TYPE_X86_CPU); if (cs !=3D NULL) { cpu =3D X86_CPU(cs); cpu_x86_inject_mce(mon, cpu, bank, status, mcg_status, addr, misc, --=20 2.41.0 From nobody Thu Nov 20 03:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697819980; cv=none; d=zohomail.com; s=zohoarc; b=EfgBh4S/4+W0+xWESuUNSNjfrc4ss2jAwvv4rMRpP/rXdbEqRuhiIae1Lc7/kKfmxmRaGCX+be3lpDTZJHP2gdmZukpDsxib9hSLela8gdib6M6qZO15LtsWGSDNtV7IZOJUJFl0mKWkHTeiq4FzTt4MTUgjEkwTwthIeDrDEN8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697819980; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=tjEEqBquQG9Z9DNlaQ9SzOw2N7EVXn+JeOiCVrWLMU8=; b=gcYw/eiyIEF2FXCCVEoJl37g6Kur0JzBxLCh3tBhxFY0lXjdLDk2+rq79jyEC1gAuG4HlCIrgJr+iCl6IgZprkWmeaXf62zilF+/vHHiiqH5jXRq5zjuuViJ4rCdQwIUBVp6QeNG98aLKJzinFXZ1EWVexobMERmBzaUvBXFKYE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16978199808401014.7954123480371; Fri, 20 Oct 2023 09:39:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtsVr-0004L7-Sv; Fri, 20 Oct 2023 12:38:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtsVp-00048J-VS for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:38:13 -0400 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtsVl-0002ck-1O for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:38:13 -0400 Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-9bf0ac97fdeso157605766b.2 for ; Fri, 20 Oct 2023 09:38:08 -0700 (PDT) Received: from m1x-phil.lan (tbo33-h01-176-171-212-97.dsl.sta.abo.bbox.fr. [176.171.212.97]) by smtp.gmail.com with ESMTPSA id m16-20020a1709066d1000b009a1a5a7ebacsm1763147ejr.201.2023.10.20.09.38.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 09:38:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697819885; x=1698424685; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tjEEqBquQG9Z9DNlaQ9SzOw2N7EVXn+JeOiCVrWLMU8=; b=kONw2MDyyydUprQjU5NZTT4LQIWUQzf0mnnw9KKyntjy8kVVBzAA8yDy6ZOk3wp8Bw A3kTp8ZVRyfVud1zG0V3wh4WGQLprvEXRzFS7W6CodZ/JCA/0/Joki0TVZf5MZSDbphM 9sGmGMmvzMIFnbhjP1IJ7MesuX0e3DsRCOqOAzgmpCEPBnkdSPRUr0HPugHE8pCyjLBS dl41gfE7bDZbt6uenlmh3AfWv2EhERAaBvZdWrNsOnwuQ7UnyUfqOfWDOszwjal6aAFx 3chJqM9K+axwNlJyqYmUGB6rDAZzbaiofok6glNk+7hB7w39tztlZ8CJMl5PgbCrSLmD ++WQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697819885; x=1698424685; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tjEEqBquQG9Z9DNlaQ9SzOw2N7EVXn+JeOiCVrWLMU8=; b=oxz6Tce5dtQ6xHgRqooGovflA8W04R/QwJUUpma4sJ19WNLXMfpIay4zdkVZnIzqpS /X/TQu5cUjtKwoj2ZBJ37m5WXaObvaNBusNUx67x5zgN5enIa5LRncFPPOuMTwhDnCC+ x/Yazzw2pRCrrb85S7G/hgLrLgKcluYK89utAZQrLTAHUZgg+nWtUggLiVedj6E112KM gw7/IdBk42yUbwWcEEIYKNYvQuc8gNIw0pmbnRR5k43CNl07g+ne7k4g2LHqhHSqY/0r XoAcdRVfM2A490fCVjLM6raDGjeb0Oy9HCOlPB9/CBC6xWvD2zlNCbIvMBq5ofNjyUBX RPhQ== X-Gm-Message-State: AOJu0Yxrdu22NqalgUKMOn9AbkE4h/ZzwDl0uPRg5QA/xA7raBeT0qzR Q2g69C5QwCfJ5kC2CIVqYuUiSzD5CUEA6fgOpCY= X-Google-Smtp-Source: AGHT+IH1BrzvzSBXULb5Pinq/MRgXe3aitbx7Ej+tcC4IN3cXg4AnPGTjB6ty3nCHDDiMZGeA9k5VA== X-Received: by 2002:a17:907:720f:b0:9ae:6a60:81a2 with SMTP id dr15-20020a170907720f00b009ae6a6081a2mr1674744ejc.25.1697819885302; Fri, 20 Oct 2023 09:38:05 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, "Edgar E. Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Andrew Jeffery , Joel Stanley , Igor Mitsyanko , Rob Herring , Subbaraya Sundeep , Alistair Francis , Felipe Balbi , Niek Linnenbank , Radoslaw Biernacki , Leif Lindholm , Marcin Juszkiewicz , Alexandre Iooss Subject: [PATCH 10/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_ARM_CPU) Date: Fri, 20 Oct 2023 18:36:32 +0200 Message-ID: <20231020163643.86105-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=philmd@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697819982780100003 Mechanical change using the following coccinelle script: @@ @@ - first_cpu + qemu_get_cpu(0, TYPE_ARM_CPU) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 5 +++-- hw/arm/bananapi_m2u.c | 3 ++- hw/arm/boot.c | 12 ++++++------ hw/arm/exynos4_boards.c | 6 ++++-- hw/arm/highbank.c | 3 ++- hw/arm/microbit.c | 3 ++- hw/arm/mps2-tz.c | 3 ++- hw/arm/mps2.c | 3 ++- hw/arm/msf2-som.c | 3 ++- hw/arm/musca.c | 3 ++- hw/arm/netduino2.c | 3 ++- hw/arm/netduinoplus2.c | 2 +- hw/arm/olimex-stm32-h405.c | 2 +- hw/arm/orangepi.c | 3 ++- hw/arm/realview.c | 5 +++-- hw/arm/sbsa-ref.c | 3 ++- hw/arm/stellaris.c | 3 ++- hw/arm/stm32vldiscovery.c | 2 +- hw/arm/vexpress.c | 3 ++- hw/arm/virt.c | 17 ++++++++++------- hw/arm/xilinx_zynq.c | 3 ++- target/arm/arch_dump.c | 6 +++--- 22 files changed, 58 insertions(+), 38 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index f8ba67531a..6a4d87bfe2 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -446,7 +446,8 @@ static void aspeed_machine_init(MachineState *machine) } } =20 - arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine, + &aspeed_board_binfo); } =20 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) @@ -1553,7 +1554,7 @@ static void aspeed_minibmc_machine_init(MachineState = *machine) amc->i2c_init(bmc); } =20 - armv7m_load_kernel(ARM_CPU(first_cpu), + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine->kernel_filename, 0, AST1030_INTERNAL_FLASH_SIZE); diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c index 74121d8966..431b1c9bf9 100644 --- a/hw/arm/bananapi_m2u.c +++ b/hw/arm/bananapi_m2u.c @@ -127,7 +127,8 @@ static void bpim2u_init(MachineState *machine) bpim2u_binfo.loader_start =3D r40->memmap[AW_R40_DEV_SDRAM]; bpim2u_binfo.ram_size =3D machine->ram_size; bpim2u_binfo.psci_conduit =3D QEMU_PSCI_CONDUIT_SMC; - arm_load_kernel(ARM_CPU(first_cpu), machine, &bpim2u_binfo); + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine, + &bpim2u_binfo); } =20 static void bpim2u_machine_init(MachineClass *mc) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index f7def3a60c..71c0775984 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -781,7 +781,7 @@ static void do_cpu_reset(void *opaque) =20 /* Set to non-secure if not a secure boot */ if (!info->secure_boot && - (cs !=3D first_cpu || !info->secure_board_setup)) { + (cs !=3D qemu_get_cpu(0, TYPE_ARM_CPU) || !info->secur= e_board_setup)) { /* Linux expects non-secure state */ env->cp15.scr_el3 |=3D SCR_NS; /* Set NSACR.{CP11,CP10} so NS can access the FPU */ @@ -800,7 +800,7 @@ static void do_cpu_reset(void *opaque) cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw); } =20 - if (cs =3D=3D first_cpu) { + if (cs =3D=3D qemu_get_cpu(0, TYPE_ARM_CPU)) { AddressSpace *as =3D arm_boot_address_space(cpu, info); =20 cpu_set_pc(cs, info->loader_start); @@ -1187,7 +1187,7 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, } info->is_linux =3D is_linux; =20 - for (cs =3D first_cpu; cs; cs =3D CPU_NEXT(cs)) { + for (cs =3D qemu_get_cpu(0, TYPE_ARM_CPU); cs; cs =3D CPU_NEXT(cs)) { ARM_CPU(cs)->env.boot_info =3D info; } } @@ -1264,7 +1264,7 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, s= truct arm_boot_info *info) * actually loading a kernel, the handler is also responsible for * arranging that we start it correctly. */ - for (cs =3D first_cpu; cs; cs =3D CPU_NEXT(cs)) { + for (cs =3D qemu_get_cpu(0, TYPE_ARM_CPU); cs; cs =3D CPU_NEXT(cs)) { qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); nb_cpus++; } @@ -1325,7 +1325,7 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, s= truct arm_boot_info *info) } =20 if (info->psci_conduit !=3D QEMU_PSCI_CONDUIT_DISABLED) { - for (cs =3D first_cpu; cs; cs =3D CPU_NEXT(cs)) { + for (cs =3D qemu_get_cpu(0, TYPE_ARM_CPU); cs; cs =3D CPU_NEXT(cs)= ) { Object *cpuobj =3D OBJECT(cs); =20 object_property_set_int(cpuobj, "psci-conduit", info->psci_con= duit, @@ -1335,7 +1335,7 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, s= truct arm_boot_info *info) * code in do_cpu_reset(), we assume first_cpu is the primary * CPU. */ - if (cs !=3D first_cpu) { + if (cs !=3D qemu_get_cpu(0, TYPE_ARM_CPU)) { object_property_set_bool(cpuobj, "start-powered-off", true, &error_abort); } diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index ef5bcbc212..f8cf0588b4 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -136,7 +136,8 @@ static void nuri_init(MachineState *machine) { exynos4_boards_init_common(machine, EXYNOS4_BOARD_NURI); =20 - arm_load_kernel(ARM_CPU(first_cpu), machine, &exynos4_board_binfo); + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine, + &exynos4_board_binfo); } =20 static void smdkc210_init(MachineState *machine) @@ -146,7 +147,8 @@ static void smdkc210_init(MachineState *machine) =20 lan9215_init(SMDK_LAN9118_BASE_ADDR, qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)])); - arm_load_kernel(ARM_CPU(first_cpu), machine, &exynos4_board_binfo); + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine, + &exynos4_board_binfo); } =20 static void nuri_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index f12aacea6b..393fa8a468 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -328,7 +328,8 @@ static void calxeda_init(MachineState *machine, enum cx= machines machine_id) highbank_binfo.board_setup_addr =3D BOARD_SETUP_ADDR; highbank_binfo.psci_conduit =3D QEMU_PSCI_CONDUIT_SMC; =20 - arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo); + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine, + &highbank_binfo); } =20 static void highbank_init(MachineState *machine) diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index 50df362088..19c2fc3b8e 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -56,7 +56,8 @@ static void microbit_init(MachineState *machine) memory_region_add_subregion_overlap(&s->nrf51.container, NRF51_TWI_BAS= E, mr, -1); =20 - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), + machine->kernel_filename, 0, s->nrf51.flash_size); } =20 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index eae3639da2..0b26eab45d 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -1217,7 +1217,8 @@ static void mps2tz_common_init(MachineState *machine) mms->remap_irq); } =20 - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), + machine->kernel_filename, 0, boot_ram_size(mms)); } =20 diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index d92fd60684..86e5ca0ce6 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -462,7 +462,8 @@ static void mps2_common_init(MachineState *machine) qdev_get_gpio_in(armv7m, mmc->fpga_type =3D=3D FPGA_AN511 ? 47 : = 13)); =20 - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), + machine->kernel_filename, 0, 0x400000); } =20 diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index 7b3106c790..42a3eb4905 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -100,7 +100,8 @@ static void emcraft_sf2_s2s010_init(MachineState *machi= ne) cs_line =3D qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0); sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line); =20 - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), + machine->kernel_filename, 0, soc->envm_size); } =20 diff --git a/hw/arm/musca.c b/hw/arm/musca.c index 6eeee57c9d..8d9b93d931 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -597,7 +597,8 @@ static void musca_init(MachineState *machine) "cfg_sec_resp", 0)); } =20 - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), + machine->kernel_filename, 0, 0x2000000); } =20 diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 83753d53a3..61fe0346fe 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -48,7 +48,8 @@ static void netduino2_init(MachineState *machine) qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), + machine->kernel_filename, 0, FLASH_SIZE); } =20 diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index 515c081605..ad68421b97 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -48,7 +48,7 @@ static void netduinoplus2_init(MachineState *machine) qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 - armv7m_load_kernel(ARM_CPU(first_cpu), + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine->kernel_filename, 0, FLASH_SIZE); } diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c index 3aa61c91b7..a44c6188c4 100644 --- a/hw/arm/olimex-stm32-h405.c +++ b/hw/arm/olimex-stm32-h405.c @@ -51,7 +51,7 @@ static void olimex_stm32_h405_init(MachineState *machine) qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 - armv7m_load_kernel(ARM_CPU(first_cpu), + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine->kernel_filename, 0, FLASH_SIZE); } diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index 10653361ed..7d44715111 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -105,7 +105,8 @@ static void orangepi_init(MachineState *machine) orangepi_binfo.loader_start =3D h3->memmap[AW_H3_DEV_SDRAM]; orangepi_binfo.ram_size =3D machine->ram_size; orangepi_binfo.psci_conduit =3D QEMU_PSCI_CONDUIT_SMC; - arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo); + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine, + &orangepi_binfo); } =20 static void orangepi_machine_init(MachineClass *mc) diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 8f89526596..be709146c8 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -136,7 +136,7 @@ static void realview_init(MachineState *machine, =20 cpu_irq[n] =3D qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ); } - cpu =3D ARM_CPU(first_cpu); + cpu =3D ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)); env =3D &cpu->env; if (arm_feature(env, ARM_FEATURE_V7)) { if (is_mpcore) { @@ -384,7 +384,8 @@ static void realview_init(MachineState *machine, realview_binfo.ram_size =3D ram_size; realview_binfo.board_id =3D realview_board_id[board_type]; realview_binfo.loader_start =3D (board_type =3D=3D BOARD_PB_A8 ? 0x700= 00000 : 0); - arm_load_kernel(ARM_CPU(first_cpu), machine, &realview_binfo); + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine, + &realview_binfo); } =20 static void realview_eb_init(MachineState *machine) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index a85004809f..01c948725c 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -844,7 +844,8 @@ static void sbsa_ref_init(MachineState *machine) sms->bootinfo.loader_start =3D sbsa_ref_memmap[SBSA_MEM].base; sms->bootinfo.get_dtb =3D sbsa_ref_dtb; sms->bootinfo.firmware_loaded =3D firmware_loaded; - arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine, + &sms->bootinfo); } =20 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *m= s) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index aa5b0ddfaa..0920b9cb86 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1307,7 +1307,8 @@ static void stellaris_init(MachineState *ms, stellari= s_board_info *board) create_unimplemented_device("hibernation", 0x400fc000, 0x1000); create_unimplemented_device("flash-control", 0x400fd000, 0x1000); =20 - armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, 0, flash_s= ize); + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), + ms->kernel_filename, 0, flash_size); } =20 /* FIXME: Figure out how to generate these from stellaris_boards. */ diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index 67675e952f..2df943295b 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -51,7 +51,7 @@ static void stm32vldiscovery_init(MachineState *machine) qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 - armv7m_load_kernel(ARM_CPU(first_cpu), + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine->kernel_filename, 0, FLASH_SIZE); } diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index e20d865d5a..8107a7057a 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -712,7 +712,8 @@ static void vexpress_common_init(MachineState *machine) daughterboard->bootinfo.modify_dtb =3D vexpress_modify_dtb; /* When booting Linux we should be in secure state if the CPU has one.= */ daughterboard->bootinfo.secure_boot =3D vms->secure; - arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo); + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine, + &daughterboard->bootinfo); } =20 static bool vexpress_get_secure(Object *obj, Error **errp) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index da5b738f0a..9f69be85ce 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -605,7 +605,7 @@ static void fdt_add_gic_node(VirtMachineState *vms) =20 static void fdt_add_pmu_nodes(const VirtMachineState *vms) { - ARMCPU *armcpu =3D ARM_CPU(first_cpu); + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)); uint32_t irqflags =3D GIC_FDT_IRQ_FLAGS_LEVEL_HI; MachineState *ms =3D MACHINE(vms); =20 @@ -1652,7 +1652,7 @@ void virt_machine_done(Notifier *notifier, void *data) VirtMachineState *vms =3D container_of(notifier, VirtMachineState, machine_done); MachineState *ms =3D MACHINE(vms); - ARMCPU *cpu =3D ARM_CPU(first_cpu); + ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)); struct arm_boot_info *info =3D &vms->bootinfo; AddressSpace *as =3D arm_boot_address_space(cpu, info); =20 @@ -1957,9 +1957,11 @@ static void virt_cpu_post_init(VirtMachineState *vms= , MemoryRegion *sysmem) bool aarch64, pmu, steal_time; CPUState *cpu; =20 - aarch64 =3D object_property_get_bool(OBJECT(first_cpu), "aarch64", NUL= L); - pmu =3D object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); - steal_time =3D object_property_get_bool(OBJECT(first_cpu), + aarch64 =3D object_property_get_bool(OBJECT(qemu_get_cpu(0, TYPE_ARM_C= PU)), + "aarch64", NULL); + pmu =3D object_property_get_bool(OBJECT(qemu_get_cpu(0, TYPE_ARM_CPU)), + "pmu", NULL); + steal_time =3D object_property_get_bool(OBJECT(qemu_get_cpu(0, TYPE_AR= M_CPU)), "kvm-steal-time", NULL); =20 if (kvm_enabled()) { @@ -2001,7 +2003,7 @@ static void virt_cpu_post_init(VirtMachineState *vms,= MemoryRegion *sysmem) } else { if (aarch64 && vms->highmem) { int requested_pa_size =3D 64 - clz64(vms->highest_gpa); - int pamax =3D arm_pamax(ARM_CPU(first_cpu)); + int pamax =3D arm_pamax(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU))= ); =20 if (pamax < requested_pa_size) { error_report("VCPU supports less PA bits (%d) than " @@ -2324,7 +2326,8 @@ static void machvirt_init(MachineState *machine) vms->bootinfo.skip_dtb_autoload =3D true; vms->bootinfo.firmware_loaded =3D firmware_loaded; vms->bootinfo.psci_conduit =3D vms->psci_conduit; - arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine, + &vms->bootinfo); =20 vms->machine_done.notify =3D virt_machine_done; qemu_add_machine_init_done_notifier(&vms->machine_done); diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 8dc2ea83a9..90a052b841 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -349,7 +349,8 @@ static void zynq_init(MachineState *machine) zynq_binfo.board_setup_addr =3D BOARD_SETUP_ADDR; zynq_binfo.write_board_setup =3D zynq_write_board_setup; =20 - arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo); + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine, + &zynq_binfo); } =20 static void zynq_machine_class_init(ObjectClass *oc, void *data) diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 2d8e41ab8a..25dffccb99 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -395,11 +395,11 @@ int cpu_get_dump_info(ArchDumpInfo *info, GuestPhysBlock *block; hwaddr lowest_addr =3D ULLONG_MAX; =20 - if (first_cpu =3D=3D NULL) { + if (qemu_get_cpu(0, TYPE_ARM_CPU) =3D=3D NULL) { return -1; } =20 - cpu =3D ARM_CPU(first_cpu); + cpu =3D ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)); env =3D &cpu->env; =20 /* Take a best guess at the phys_base. If we get it wrong then crash @@ -443,7 +443,7 @@ int cpu_get_dump_info(ArchDumpInfo *info, =20 ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) { - ARMCPU *cpu =3D ARM_CPU(first_cpu); + ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)); size_t note_size; =20 if (class =3D=3D ELFCLASS64) { --=20 2.41.0 From nobody Thu Nov 20 03:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697820151; cv=none; d=zohomail.com; s=zohoarc; b=YtfsE7eM+brK7mv7akodbXRL+j/63GzJqepPD3arZAxlNa3nq/o5aEC0+1Slwm8iuVwPTRq7K68UqIBoVwGrA9WUkjY6gw1Dg9uU1IIhYlTxLCeXJtSBFGh7ktyOjwgWs1wxe5ImM8HqK2ecA5uHqA26iAk3ErJSumk5I9qFVCU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697820151; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=sWVSb4kJOx4Py9xCdpLQSCowqDiVUo6mKEdRlRPdC3M=; b=DkxjVUFBZevi/cyR0oPu2L6DgCLRWJiT6BASRUsOPEe2d4kFfkWziqBDmxaz5NVj5cuOqqQo793QSQ1nsxIC/5uFgL21k4GCqbh+Kpur95XvB/bM4AZcrGWkMOaT+Vhysb/vVpkDDDUgqatcY7noe0S7D5nlslP9JxbAtmOFVgY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697820151163892.4629436790319; Fri, 20 Oct 2023 09:42:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtsVv-0004e4-2D; Fri, 20 Oct 2023 12:38:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtsVt-0004TR-3l for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:38:17 -0400 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtsVq-0002eC-R4 for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:38:16 -0400 Received: by mail-ed1-x52f.google.com with SMTP id 4fb4d7f45d1cf-533d31a8523so1502118a12.1 for ; Fri, 20 Oct 2023 09:38:14 -0700 (PDT) Received: from m1x-phil.lan (tbo33-h01-176-171-212-97.dsl.sta.abo.bbox.fr. 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Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Nicholas Piggin , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , David Gibson , Harsh Prateek Bora , Alexey Kardashevskiy Subject: [PATCH 11/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_POWERPC_CPU) Date: Fri, 20 Oct 2023 18:36:33 +0200 Message-ID: <20231020163643.86105-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=philmd@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697820153423100003 Mechanical change using the following coccinelle script: @@ @@ - first_cpu + qemu_get_cpu(0, TYPE_POWERPC_CPU) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/ppc/e500.c | 2 +- hw/ppc/ppc.c | 4 ++-- hw/ppc/prep_systemio.c | 2 +- hw/ppc/spapr.c | 11 ++++++----- hw/ppc/spapr_caps.c | 10 +++++----- hw/ppc/spapr_rtas.c | 2 +- hw/ppc/spapr_vof.c | 2 +- hw/ppc/vof.c | 3 ++- target/ppc/arch_dump.c | 4 ++-- 9 files changed, 21 insertions(+), 19 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index c4bf3fef32..02d14404d9 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -373,7 +373,7 @@ static int ppce500_load_device_tree(PPCE500MachineState= *pms, MachineState *machine =3D MACHINE(pms); unsigned int smp_cpus =3D machine->smp.cpus; const PPCE500MachineClass *pmc =3D PPCE500_MACHINE_GET_CLASS(pms); - CPUPPCState *env =3D cpu_env(first_cpu); + CPUPPCState *env =3D cpu_env(qemu_get_cpu(0, TYPE_POWERPC_CPU)); int ret =3D -1; uint64_t mem_reg_property[] =3D { 0, cpu_to_be64(machine->ram_size) }; int fdt_size; diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index be167710a3..be0b1536f5 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -970,7 +970,7 @@ void cpu_ppc_store_purr(CPUPPCState *env, uint64_t valu= e) static void timebase_save(PPCTimebase *tb) { uint64_t ticks =3D cpu_get_host_ticks(); - PowerPCCPU *first_ppc_cpu =3D POWERPC_CPU(first_cpu); + PowerPCCPU *first_ppc_cpu =3D POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC= _CPU)); =20 if (!first_ppc_cpu->env.tb_env) { error_report("No timebase object"); @@ -998,7 +998,7 @@ static void timebase_save(PPCTimebase *tb) static void timebase_load(PPCTimebase *tb) { CPUState *cpu; - PowerPCCPU *first_ppc_cpu =3D POWERPC_CPU(first_cpu); + PowerPCCPU *first_ppc_cpu =3D POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC= _CPU)); int64_t tb_off_adj, tb_off; unsigned long freq; =20 diff --git a/hw/ppc/prep_systemio.c b/hw/ppc/prep_systemio.c index c96cefb13d..0431cde91c 100644 --- a/hw/ppc/prep_systemio.c +++ b/hw/ppc/prep_systemio.c @@ -261,7 +261,7 @@ static void prep_systemio_realize(DeviceState *dev, Err= or **errp) s->iomap_type =3D PORT0850_IOMAP_NONCONTIGUOUS; qemu_set_irq(s->non_contiguous_io_map_irq, s->iomap_type & PORT0850_IOMAP_NONCONTIGUOUS); - cpu =3D POWERPC_CPU(first_cpu); + cpu =3D POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU)); s->softreset_irq =3D qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_HRESET= ); =20 isa_register_portio_list(isa, &s->portio, 0x0, ppc_io800_port_list, s, diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index cb840676d3..a5006eaa5e 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -981,7 +981,7 @@ static void spapr_dt_rtas(SpaprMachineState *spapr, voi= d *fdt) static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *= fdt, int chosen) { - PowerPCCPU *first_ppc_cpu =3D POWERPC_CPU(first_cpu); + PowerPCCPU *first_ppc_cpu =3D POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC= _CPU)); =20 char val[2 * 4] =3D { 23, 0x00, /* XICS / XIVE mode */ @@ -1125,7 +1125,7 @@ static void spapr_dt_hypervisor(SpaprMachineState *sp= apr, void *fdt) * Older KVM versions with older guest kernels were broken * with the magic page, don't allow the guest to map it. */ - if (!kvmppc_get_hypercall(cpu_env(first_cpu), hypercall, + if (!kvmppc_get_hypercall(cpu_env(qemu_get_cpu(0, TYPE_POWERPC_CPU= )), hypercall, sizeof(hypercall))) { _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", hypercall, sizeof(hypercall))); @@ -1669,7 +1669,7 @@ static void spapr_machine_reset(MachineState *machine= , ShutdownCause reason) pef_kvm_reset(machine->cgs, &error_fatal); spapr_caps_apply(spapr); =20 - first_ppc_cpu =3D POWERPC_CPU(first_cpu); + first_ppc_cpu =3D POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU)); if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00,= 0, spapr->max_compat_pvr)) { @@ -1845,7 +1845,7 @@ static int spapr_post_load(void *opaque, int version_= id) } =20 if (kvm_enabled() && spapr->patb_entry) { - PowerPCCPU *cpu =3D POWERPC_CPU(first_cpu); + PowerPCCPU *cpu =3D POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU)); bool radix =3D !!(spapr->patb_entry & PATE1_GR); bool gtse =3D !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); =20 @@ -4014,7 +4014,8 @@ static void spapr_core_plug(HotplugHandler *hotplug_d= ev, DeviceState *dev) */ if (hotplugged) { for (i =3D 0; i < cc->nr_threads; i++) { - ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compa= t_pvr, + ppc_set_compat(core->threads[i], + POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU))-= >compat_pvr, &error_abort); } } diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 5a0755d34f..0c1f00d869 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -194,7 +194,7 @@ static void cap_htm_apply(SpaprMachineState *spapr, uin= t8_t val, Error **errp) static void cap_vsx_apply(SpaprMachineState *spapr, uint8_t val, Error **e= rrp) { ERRP_GUARD(); - PowerPCCPU *cpu =3D POWERPC_CPU(first_cpu); + PowerPCCPU *cpu =3D POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU)); CPUPPCState *env =3D &cpu->env; =20 if (!val) { @@ -213,7 +213,7 @@ static void cap_vsx_apply(SpaprMachineState *spapr, uin= t8_t val, Error **errp) static void cap_dfp_apply(SpaprMachineState *spapr, uint8_t val, Error **e= rrp) { ERRP_GUARD(); - PowerPCCPU *cpu =3D POWERPC_CPU(first_cpu); + PowerPCCPU *cpu =3D POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU)); CPUPPCState *env =3D &cpu->env; =20 if (!val) { @@ -440,7 +440,7 @@ static void cap_nested_kvm_hv_apply(SpaprMachineState *= spapr, uint8_t val, Error **errp) { ERRP_GUARD(); - PowerPCCPU *cpu =3D POWERPC_CPU(first_cpu); + PowerPCCPU *cpu =3D POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU)); CPUPPCState *env =3D &cpu->env; =20 if (!val) { @@ -494,7 +494,7 @@ static void cap_large_decr_apply(SpaprMachineState *spa= pr, uint8_t val, Error **errp) { ERRP_GUARD(); - PowerPCCPU *cpu =3D POWERPC_CPU(first_cpu); + PowerPCCPU *cpu =3D POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU)); PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); =20 if (!val) { @@ -632,7 +632,7 @@ static void cap_ail_mode_3_apply(SpaprMachineState *spa= pr, uint8_t val, Error **errp) { ERRP_GUARD(); - PowerPCCPU *cpu =3D POWERPC_CPU(first_cpu); + PowerPCCPU *cpu =3D POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU)); PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); =20 if (!val) { diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 7df21581c2..3d4e93a188 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -539,7 +539,7 @@ uint64_t qtest_rtas_call(char *cmd, uint32_t nargs, uin= t64_t args, for (token =3D 0; token < RTAS_TOKEN_MAX - RTAS_TOKEN_BASE; token++) { if (strcmp(cmd, rtas_table[token].name) =3D=3D 0) { SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); - PowerPCCPU *cpu =3D POWERPC_CPU(first_cpu); + PowerPCCPU *cpu =3D POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_C= PU)); =20 rtas_table[token].fn(cpu, spapr, token + RTAS_TOKEN_BASE, nargs, args, nret, rets); diff --git a/hw/ppc/spapr_vof.c b/hw/ppc/spapr_vof.c index 09f29be0b9..301b3cd433 100644 --- a/hw/ppc/spapr_vof.c +++ b/hw/ppc/spapr_vof.c @@ -58,7 +58,7 @@ void spapr_vof_reset(SpaprMachineState *spapr, void *fdt,= Error **errp) { target_ulong stack_ptr; Vof *vof =3D spapr->vof; - PowerPCCPU *first_ppc_cpu =3D POWERPC_CPU(first_cpu); + PowerPCCPU *first_ppc_cpu =3D POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC= _CPU)); =20 vof_init(vof, spapr->rma_size, errp); =20 diff --git a/hw/ppc/vof.c b/hw/ppc/vof.c index e3b430a81f..9fa1cd9e19 100644 --- a/hw/ppc/vof.c +++ b/hw/ppc/vof.c @@ -797,7 +797,8 @@ static uint32_t vof_call_method(MachineState *ms, Vof *= vof, uint32_t methodaddr, VofMachineIfClass *vmc =3D VOF_MACHINE_GET_CLASS(vmo); =20 g_assert(vmc->client_architecture_support); - ret =3D (uint32_t)vmc->client_architecture_support(ms, fir= st_cpu, + ret =3D (uint32_t)vmc->client_architecture_support(ms, + qemu_get_= cpu(0, TYPE_POWERPC_CPU), param1); } =20 diff --git a/target/ppc/arch_dump.c b/target/ppc/arch_dump.c index a8315659d9..be2a78d01f 100644 --- a/target/ppc/arch_dump.c +++ b/target/ppc/arch_dump.c @@ -228,11 +228,11 @@ int cpu_get_dump_info(ArchDumpInfo *info, { PowerPCCPU *cpu; =20 - if (first_cpu =3D=3D NULL) { + if (qemu_get_cpu(0, TYPE_POWERPC_CPU) =3D=3D NULL) { return -1; } =20 - cpu =3D POWERPC_CPU(first_cpu); + cpu =3D POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU)); =20 info->d_machine =3D PPC_ELF_MACHINE; info->d_class =3D ELFCLASS; --=20 2.41.0 From nobody Thu Nov 20 03:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697820125; cv=none; d=zohomail.com; s=zohoarc; b=ljtoMpHO0w/8/9XdKyzNzNffT6ECm/vHuPabgZc1avFm97Z7xnDh2N0/JKNwhgV7VEJn3YnV6sh5QNO3wCr6rVoBZ/Hhv4E33rY5F+mMhakn6i2JqKINdF5v2w41eLAXm8wfFGV5BpdrJiPflmCo1stci70/SEYjlpK4BK/IFCQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697820125; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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[176.171.212.97]) by smtp.gmail.com with ESMTPSA id y90-20020a50bb63000000b0053e8bb112adsm1775109ede.53.2023.10.20.09.38.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 09:38:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697819900; x=1698424700; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gyJaNaz+yQUi1oc2/ICF5HBrjSZAS7PKSP5aD7nnSG8=; b=W4ccIbXSN5MmJu8TJ+Qu/tXEu26M5QMRDBAD0leJi39k4EoHy3D0N/U7Kfwiw9yv/N dvh0EnloGrn6EqAHx/HKNuMnvCPfBTFo/98qLYAHqFFhB6kONdDLC1T7+i4zyHznK3rJ iVUY4qjCyeedOcSB3Z7U4hkyf107J3RspKUjEuhzHHf0BBUk9B5h6tc1EXZkbILtNc4P MPEdqioy3dIptlIxAJdsA0Qlt40pWRg8EbslOLBh6IwoPPHTYG3SMlRWcIFY561/GxO3 ZrsAnWaGepDmaoONutvYLpW9s1uPyxFAcUftQFa/J1MkooHifQuljVx2wsWrPZZLJIFp G/Iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697819900; x=1698424700; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gyJaNaz+yQUi1oc2/ICF5HBrjSZAS7PKSP5aD7nnSG8=; b=rpfCzUBss+X89k3Fu/HDclhjImgjOKtPBgfCtUFnHaaTg1t4kVY+baJfHoi59nka3L ikxTxYpcQGDlDUIiKzjXDJ904NJOwbozriwYHZfcaLt8NhmzqaZSsZY4EYzAOACthMfZ N5W9YAlDIC3sQJrlxn4d8IEHSksU/kPGZ3S9B5jN7oK60Dv7X01zGnDUVW9JY5u3fYh3 HSs0dXn6ELjZx26zudYIsEdHa2+5E7QuBZ7E/1LdBAiEmu5Hm6lQ6rkSAO97uMk7uVGa qQZmZQydvTsKftm5QtVaSGWDlkxm/rAkrMX0b10UkAfSSxStZ0ZpQ8xrE5ETBbjcMM9c DTjQ== X-Gm-Message-State: AOJu0YxDwQNG/vyRPxO1mu1QZqGQll80PNVhMrqPjq8LoLu+uGdklRHt dZliHQzYksoo5K1He9ZlkF26oYUA36UttPyPON8= X-Google-Smtp-Source: AGHT+IFBfKbQwH9V3tIztlCgedZL06X6xkpxRSX0F2ztCJXYo/UXY7UYQxkYQktWmALhyqPrbSACzw== X-Received: by 2002:a50:f683:0:b0:53f:2128:ff4f with SMTP id d3-20020a50f683000000b0053f2128ff4fmr1999564edn.17.1697819900211; Fri, 20 Oct 2023 09:38:20 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, "Edgar E. Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo Subject: [PATCH 12/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_MIPS_CPU) Date: Fri, 20 Oct 2023 18:36:34 +0200 Message-ID: <20231020163643.86105-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=philmd@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697820125373100006 Mechanical change using the following coccinelle script: @@ @@ - first_cpu + qemu_get_cpu(0, TYPE_MIPS_CPU) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 2 +- hw/intc/mips_gic.c | 2 +- hw/mips/bootloader.c | 3 ++- hw/mips/cps.c | 5 +++-- hw/mips/loongson3_bootp.c | 2 +- hw/mips/loongson3_virt.c | 7 ++++--- hw/mips/malta.c | 2 +- hw/misc/mips_cpc.c | 4 ++-- target/mips/tcg/sysemu/cp0_helper.c | 8 ++++---- target/mips/tcg/sysemu/tlb_helper.c | 2 +- 10 files changed, 20 insertions(+), 17 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 1d0c026c7d..d373063fd0 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -270,7 +270,7 @@ static inline int mips_vpe_active(CPUMIPSState *env) =20 static inline int mips_vp_active(CPUMIPSState *env) { - CPUState *other_cs =3D first_cpu; + CPUState *other_cs =3D qemu_get_cpu(0, TYPE_MIPS_CPU); =20 /* Check if the VP disabled other VPs (which means the VP is enabled) = */ if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { diff --git a/hw/intc/mips_gic.c b/hw/intc/mips_gic.c index 77ba7348a3..4c4791aefa 100644 --- a/hw/intc/mips_gic.c +++ b/hw/intc/mips_gic.c @@ -406,7 +406,7 @@ static void mips_gic_init(Object *obj) static void mips_gic_realize(DeviceState *dev, Error **errp) { MIPSGICState *s =3D MIPS_GIC(dev); - CPUState *cs =3D first_cpu; + CPUState *cs =3D qemu_get_cpu(0, TYPE_MIPS_CPU); int i; =20 if (s->num_vps > GIC_MAX_VPS) { diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 1dd6ef2096..c4943f193f 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -51,7 +51,8 @@ typedef enum bl_reg { =20 static bool bootcpu_supports_isa(uint64_t isa_mask) { - return cpu_supports_isa(&MIPS_CPU(first_cpu)->env, isa_mask); + return cpu_supports_isa(&MIPS_CPU(qemu_get_cpu(0, TYPE_MIPS_CPU))->env, + isa_mask); } =20 static void st_nm32_p(void **ptr, uint32_t insn) diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 2b5269ebf1..d2f72cbf90 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -107,7 +107,8 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) if (itu_present) { object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU= ); object_property_set_link(OBJECT(&s->itu), "cpu[0]", - OBJECT(first_cpu), &error_abort); + OBJECT(qemu_get_cpu(0, TYPE_MIPS_CPU)), + &error_abort); object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16, &error_abort); object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16, @@ -147,7 +148,7 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic)= , 0)); =20 /* Global Configuration Registers */ - gcr_base =3D MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4; + gcr_base =3D MIPS_CPU(qemu_get_cpu(0, TYPE_MIPS_CPU))->env.CP0_CMGCRBa= se << 4; =20 object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp, diff --git a/hw/mips/loongson3_bootp.c b/hw/mips/loongson3_bootp.c index f99af22932..3ad9cf2f0c 100644 --- a/hw/mips/loongson3_bootp.c +++ b/hw/mips/loongson3_bootp.c @@ -32,7 +32,7 @@ static void init_cpu_info(void *g_cpuinfo, uint64_t cpu_f= req) struct efi_cpuinfo_loongson *c =3D g_cpuinfo; =20 c->cputype =3D cpu_to_le32(Loongson_3A); - c->processor_id =3D cpu_to_le32(MIPS_CPU(first_cpu)->env.CP0_PRid); + c->processor_id =3D cpu_to_le32(MIPS_CPU(qemu_get_cpu(0, TYPE_MIPS_CPU= ))->env.CP0_PRid); if (cpu_freq > UINT_MAX) { c->cpu_clock_freq =3D cpu_to_le32(UINT_MAX); } else { diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c index b74b358874..9dd943d477 100644 --- a/hw/mips/loongson3_virt.c +++ b/hw/mips/loongson3_virt.c @@ -159,7 +159,8 @@ static uint64_t get_cpu_freq_hz(void) }; =20 if (kvm_enabled()) { - ret =3D kvm_vcpu_ioctl(first_cpu, KVM_GET_ONE_REG, &freq_reg); + ret =3D kvm_vcpu_ioctl(qemu_get_cpu(0, TYPE_MIPS_CPU), KVM_GET_ONE= _REG, + &freq_reg); if (ret >=3D 0) { return freq * 2; } @@ -387,7 +388,7 @@ static void main_cpu_reset(void *opaque) =20 /* Loongson-3 reset stuff */ if (loaderparams.kernel_filename) { - if (cpu =3D=3D MIPS_CPU(first_cpu)) { + if (cpu =3D=3D MIPS_CPU(qemu_get_cpu(0, TYPE_MIPS_CPU))) { env->active_tc.gpr[4] =3D loaderparams.a0; env->active_tc.gpr[5] =3D loaderparams.a1; env->active_tc.gpr[6] =3D loaderparams.a2; @@ -543,7 +544,7 @@ static void mips_loongson3_virt_init(MachineState *mach= ine) pin, cpu->env.irq[ip + 2]); } } - env =3D &MIPS_CPU(first_cpu)->env; + env =3D &MIPS_CPU(qemu_get_cpu(0, TYPE_MIPS_CPU))->env; =20 /* Allocate RAM/BIOS, 0x00000000~0x10000000 is alias of 0x80000000~0x9= 0000000 */ memory_region_init_rom(bios, NULL, "loongson3.bios", diff --git a/hw/mips/malta.c b/hw/mips/malta.c index dac27fad9d..2e26b8a26d 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1044,7 +1044,7 @@ static void create_cpu_without_cps(MachineState *ms, = MaltaState *s, qemu_register_reset(main_cpu_reset, cpu); } =20 - cpu =3D MIPS_CPU(first_cpu); + cpu =3D MIPS_CPU(qemu_get_cpu(0, TYPE_MIPS_CPU)); env =3D &cpu->env; *i8259_irq =3D env->irq[2]; *cbus_irq =3D env->irq[4]; diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c index 4a94c87054..583081cdeb 100644 --- a/hw/misc/mips_cpc.c +++ b/hw/misc/mips_cpc.c @@ -44,7 +44,7 @@ static void mips_cpu_reset_async_work(CPUState *cs, run_o= n_cpu_data data) =20 static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run) { - CPUState *cs =3D first_cpu; + CPUState *cs =3D qemu_get_cpu(0, TYPE_MIPS_CPU); =20 CPU_FOREACH(cs) { uint64_t i =3D 1ULL << cs->cpu_index; @@ -62,7 +62,7 @@ static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run) =20 static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop) { - CPUState *cs =3D first_cpu; + CPUState *cs =3D qemu_get_cpu(0, TYPE_MIPS_CPU); =20 CPU_FOREACH(cs) { uint64_t i =3D 1ULL << cs->cpu_index; diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/c= p0_helper.c index af0cd60829..bf934be58a 100644 --- a/target/mips/tcg/sysemu/cp0_helper.c +++ b/target/mips/tcg/sysemu/cp0_helper.c @@ -1633,7 +1633,7 @@ target_ulong helper_emt(void) =20 target_ulong helper_dvpe(CPUMIPSState *env) { - CPUState *other_cs =3D first_cpu; + CPUState *other_cs =3D qemu_get_cpu(0, TYPE_MIPS_CPU); target_ulong prev =3D env->mvp->CP0_MVPControl; =20 CPU_FOREACH(other_cs) { @@ -1649,7 +1649,7 @@ target_ulong helper_dvpe(CPUMIPSState *env) =20 target_ulong helper_evpe(CPUMIPSState *env) { - CPUState *other_cs =3D first_cpu; + CPUState *other_cs =3D qemu_get_cpu(0, TYPE_MIPS_CPU); target_ulong prev =3D env->mvp->CP0_MVPControl; =20 CPU_FOREACH(other_cs) { @@ -1669,7 +1669,7 @@ target_ulong helper_evpe(CPUMIPSState *env) /* R6 Multi-threading */ target_ulong helper_dvp(CPUMIPSState *env) { - CPUState *other_cs =3D first_cpu; + CPUState *other_cs =3D qemu_get_cpu(0, TYPE_MIPS_CPU); target_ulong prev =3D env->CP0_VPControl; =20 if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) { @@ -1687,7 +1687,7 @@ target_ulong helper_dvp(CPUMIPSState *env) =20 target_ulong helper_evp(CPUMIPSState *env) { - CPUState *other_cs =3D first_cpu; + CPUState *other_cs =3D qemu_get_cpu(0, TYPE_MIPS_CPU); target_ulong prev =3D env->CP0_VPControl; =20 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index 7dbc2e24c4..2d31c8e17f 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -344,7 +344,7 @@ void helper_ginvt(CPUMIPSState *env, target_ulong arg, = uint32_t type) uint32_t invMsgVPN2 =3D arg & (TARGET_PAGE_MASK << 1); uint8_t invMsgR =3D 0; uint32_t invMsgMMid =3D env->CP0_MemoryMapID; - CPUState *other_cs =3D first_cpu; + CPUState *other_cs =3D qemu_get_cpu(0, TYPE_MIPS_CPU); =20 #ifdef TARGET_MIPS64 invMsgR =3D extract64(arg, 62, 2); --=20 2.41.0 From nobody Thu Nov 20 03:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697820036; cv=none; d=zohomail.com; s=zohoarc; b=nWD6uonhiKicIp4Y2nsfYUbD6aMCHtpZ9UdrioJwbqFYnJnj97VfUNVWIu59TMi7snNGg4D1dBijUuTioT/VdmR6PZ4VLl32O5UKXTxyGSDORsreAvZP8zdE69dG9b2JhJ/BFPNNsYx1n00GyDcwQITnZVdFi2bGHVWu75x9Aos= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697820036; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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[176.171.212.97]) by smtp.gmail.com with ESMTPSA id s19-20020a170906bc5300b009b957d5237asm1805635ejv.80.2023.10.20.09.38.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 09:38:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697819908; x=1698424708; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XJgrMi/wBqEbOvB4DV5saOShbSMfpSRqXMWSTunBKJo=; b=j/iqubrldvfGNHyR1EiLGFfkWpATzt021m/DEmJANJ+fI7aiCnPQP7LCNB8CymPpeH l5VnhwMfeuKvjOzZDY2AOLeyK96lNpXe7wi4ntLiPh8HDDhsA2rXo5/t4LdobeRMTyG7 TKLITtqWBjjH01e+f873bbThtYBMshMFIfKMP9etBKBaYDrn0h+YhBSrEu6lNUFQFhKM iTN6CehHKhaJJSDcxQzXccUtHdrxb5XulFf2EXx3Wmv4MSd9AhcP0EAwhEKF9Z3HZB9T U7pZIbzIOpbzW+1VDSvsr6wuVjavR3LLyg+TJMbZ4f6nsHiSsf+/b/FhHYTgdmlrqcZZ aTBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697819908; x=1698424708; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XJgrMi/wBqEbOvB4DV5saOShbSMfpSRqXMWSTunBKJo=; b=VHwiFKL1kNs7obHNXJbQcvietVGGy5vVECKds6iJZay0E3Fb0jgz2TNvH95LIVxXVl +r7YXTaoJs6oGs/3UWTtSWsdyaQlbuWvdE1fCRqbJZ4Ki7VgcbHpzul3vjnWTiVyqU1V mi8IbwmUSKRu5wM/xVwY0JopXrHtrNyg05sEvdz/+7ZxKvS38OBm5xQ+9NMcy0cmjcZ+ eq3GTEwGYzuM2n/CRi/Me0KPu1+OCRRVfwAUyt7Tm3LI+PUFl6LijVUtU5/wRN4AFkVm 5sUpGEPuwYeXUGu9KeepH8+5LgnftY8pBBDWfFZedy9FfEi6Oej9FfwZu2n41uJqtCWu q1ew== X-Gm-Message-State: AOJu0YwoTpUTlZ6rFclYiwLijo4UY+LKpOAugxA4GfA+kfpR09nejFWG pR89VETCDrmpp1vjNOttVoeB+X/Cf9OrGv5183o= X-Google-Smtp-Source: AGHT+IH7+ZNyajLwkQ3t7c25QQCi97yzQLzCUBWOzenMRYSotv/xdOmSa0eQLzVkCMAjxOV447k7wA== X-Received: by 2002:a17:906:c14c:b0:9c3:e158:316a with SMTP id dp12-20020a170906c14c00b009c3e158316amr1782665ejc.68.1697819907900; Fri, 20 Oct 2023 09:38:27 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, "Edgar E. Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier Subject: [PATCH 13/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_M68K_CPU) Date: Fri, 20 Oct 2023 18:36:35 +0200 Message-ID: <20231020163643.86105-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=philmd@linaro.org; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697820036954100002 Mechanical change using the following coccinelle script: @@ @@ - first_cpu + qemu_get_cpu(0, TYPE_M68K_CPU) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/m68k_irqc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/m68k_irqc.c b/hw/intc/m68k_irqc.c index 0c515e4ecb..071937e6eb 100644 --- a/hw/intc/m68k_irqc.c +++ b/hw/intc/m68k_irqc.c @@ -35,7 +35,7 @@ static void m68k_irqc_print_info(InterruptStatsProvider *= obj, Monitor *mon) static void m68k_set_irq(void *opaque, int irq, int level) { M68KIRQCState *s =3D opaque; - M68kCPU *cpu =3D M68K_CPU(first_cpu); + M68kCPU *cpu =3D M68K_CPU(qemu_get_cpu(0, TYPE_M68K_CPU)); int i; =20 if (level) { --=20 2.41.0 From nobody Thu Nov 20 03:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697819943; cv=none; d=zohomail.com; s=zohoarc; b=hF50cdjaGyMoYQhzMGHGIsynE7PWacYA1wXKK/CUDpvUb1PILpCHVhJVVn9l3Mo8wl+oDtY7WSLXKJxiF67PMPTy6LzPAs96yI5Q/bLThXFVQKsJgfVEASNRXn3AgwzZ39YuQ/H8FBkx0XPcMKjA+UFgagYKVBEaBx4jBttd/Kc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697819943; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ut1JVFvFLo+kLIKZi8qPYnpjR7G6cNfFgvYYDUExNe4=; b=NiKexG7n0NdAiRxkz1/nVVWTC3BahO58vmwwxu83egzS5uenVmZK5Q9+a6VMJOsb6X4dXuyuZFc/chrVYdC+8ryFQXVZNn04636wzQX7Nr5aLCvbWO26kyy0AYjigk3GT3akQQWt0JsnQp5QQB+2HoUY79v7n3A/yejGcz0gzrs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697819943174654.4763404684522; Fri, 20 Oct 2023 09:39:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtsWN-0005dJ-Np; Fri, 20 Oct 2023 12:38:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtsWH-0005Up-Hl for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:38:42 -0400 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtsWE-0002i5-TL for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:38:41 -0400 Received: by mail-ed1-x52f.google.com with SMTP id 4fb4d7f45d1cf-53d82bea507so1550859a12.2 for ; Fri, 20 Oct 2023 09:38:36 -0700 (PDT) Received: from m1x-phil.lan (tbo33-h01-176-171-212-97.dsl.sta.abo.bbox.fr. [176.171.212.97]) by smtp.gmail.com with ESMTPSA id kf14-20020a17090776ce00b0099bd7b26639sm1820597ejc.6.2023.10.20.09.38.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 09:38:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697819915; x=1698424715; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ut1JVFvFLo+kLIKZi8qPYnpjR7G6cNfFgvYYDUExNe4=; b=Esduh2x9POfFkAkyY7CW+rq4rzhGBP5AXebWZsb5QXaAWv2BvfhbQdnKzu/E6x0CqL FE0dl8n7msDCpbpRVMvPpsZ8njjhmjBfgrmL0dqZ0vb2pMTdmtMuhfB3jElQTMkdOWcc dSpu5FWUTr9cBGDuiDp3I8UwuOfoWmrT7/2j8XSGYern14jE+aD6yorMxVXejEeNJLla tB5aYk7cNgZ+leM+0hy+YIfQUPpqn2uz8SL7BrvdxcCREa/lSWUAyrQO3u3XctD1VCUs D02j7jNjiOUrtiAvnqgaUOxSAD4YMKQdRW6HXy8Yk3/jrkWYfoWZugSspxBOVaHKCurz hmQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697819915; x=1698424715; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ut1JVFvFLo+kLIKZi8qPYnpjR7G6cNfFgvYYDUExNe4=; b=Kl1BQhadM+/FUePUBjlJPy+uoLE94JUhf9kVcfV03NuMV9ClgqipXhIsWBwQ7yEPSO SPyl3vSImsnFGRIXK95S7NsbCSgZoyPUhp7w9mdRI438+nIcVLQ4iDNKdJq7q9g75Bl+ m6E/V5ariADvvnI/yYTx1SWA8YfAlZY76KZPEjeqFqZTiQCFo2qFloOPcX5WhBPLCN5Y fTuLl1MaQFVNsPYwZf4NS5TibEhxlgLeg6NKEDY0H8iANvGqLWYKEO+qgqSV2zET1IOC GqWwJTAalweBWMr2ES0nrlBWShL0PW6a3zkjBghZEUjQM7k9eem7XVyvk4/wr4NPlo/A WMdQ== X-Gm-Message-State: AOJu0Yy1kKT34O8UPyGaAvGzaxV9CYEqGdSJIGf8v4KndvqfAzUHbOmY +Siz6TY86IZo3o7sVDydDKjtzISkVIbee+iINHU= X-Google-Smtp-Source: AGHT+IGl73D3b984YgVSErMYz9RgMLYGAfiCqAnw0A/C+rUAgxUldvhOIDj/46hx9nsUEPP1al9X2g== X-Received: by 2002:a17:906:eec6:b0:9b8:8bcf:8732 with SMTP id wu6-20020a170906eec600b009b88bcf8732mr1841258ejb.43.1697819915304; Fri, 20 Oct 2023 09:38:35 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, "Edgar E. Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Christian Borntraeger , David Hildenbrand , Ilya Leoshkevich , Halil Pasic , Eric Farman Subject: [PATCH 14/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_S390X_CPU) Date: Fri, 20 Oct 2023 18:36:36 +0200 Message-ID: <20231020163643.86105-15-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=philmd@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697819944568100001 Mechanical change using the following coccinelle script: @@ @@ - first_cpu + qemu_get_cpu(0, TYPE_S390_CPU) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/s390x/ipl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c index 377f43416c..1f2296f456 100644 --- a/hw/s390x/ipl.c +++ b/hw/s390x/ipl.c @@ -674,7 +674,7 @@ void s390_ipl_get_reset_request(CPUState **cs, enum s39= 0_reset *reset_type) *cs =3D qemu_get_cpu(ipl->reset_cpu_index, TYPE_S390_CPU); if (!*cs) { /* use any CPU */ - *cs =3D first_cpu; + *cs =3D qemu_get_cpu(0, TYPE_S390_CPU); } *reset_type =3D ipl->reset_type; } --=20 2.41.0 From nobody Thu Nov 20 03:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697820199; cv=none; d=zohomail.com; s=zohoarc; b=X6dGhcwhn2vzWnXZnDsywnCVAXVdVBTK0krP7Fh1Qcqu9TUHqnEOAJ5y1mFkDHBB8+jFD5Ss+Bklxq2cKZInZU8zOfLACP6hm2b5mWJ9YL9gnfyKdPL961cRu53MghDSoFioTeemP5LLsI1Tkm59Q+VF3AuPzO6wMu57Mpfh1Go= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697820199; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=glBeQZnUhkWGnfluElBv8to+WC3WDtUU/ZpHqLDizi4=; b=S3QQ4O0lKW/UE34YNb6EQVEa8AreiuOREp99uH2yDhDRRQCNQoHWCMKb1/sGaTja5v+qVdhH7q43rM6+vMkbYDfgQRmcWMJVDbGYFc1AGQV8a+P/hN2fn5JLay9J4r4gzgebMAqmowVF7T+ARj2oiEjUg3LvT82NnjpYmMe4R+Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697820199152535.882072327353; Fri, 20 Oct 2023 09:43:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtsWR-0005vv-7W; Fri, 20 Oct 2023 12:38:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtsWN-0005ex-Es for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:38:48 -0400 Received: from mail-lj1-x22f.google.com ([2a00:1450:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtsWK-0002mp-QG for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:38:47 -0400 Received: by mail-lj1-x22f.google.com with SMTP id 38308e7fff4ca-2c5071165d5so1431991fa.0 for ; Fri, 20 Oct 2023 09:38:44 -0700 (PDT) Received: from m1x-phil.lan (tbo33-h01-176-171-212-97.dsl.sta.abo.bbox.fr. [176.171.212.97]) by smtp.gmail.com with ESMTPSA id j12-20020a170906050c00b00977eec7b7e8sm1809552eja.68.2023.10.20.09.38.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 09:38:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697819922; x=1698424722; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=glBeQZnUhkWGnfluElBv8to+WC3WDtUU/ZpHqLDizi4=; b=fDHvC9DPADTuiIOKlKlbpT7vBiHa3xHKJ/ok/6A/jFojphktCLSzuxaDf3d2M+Ta5j cptXIlZg4GxZHXdEJemEAOJEX1Ixt220l8k4ZsUWZRpRB9hUWG13/x4656tzArpOAxNp GGy/ZUkDsJT+ee8yYiQ+NuKYfbeW+uX6TkglydNgUD1EfryPHUkXIv9fA4hwmbxxhWu4 N/kO4dObkLmBwl78n8hGfk1MXv/tV6iZcDPVdPxTYjcNPjCW3DK7Ow7oMZtLSh8jRLl7 1U106kO+wFlAFjuTdwwBR3Sn7/KYE7DPtB4FklUVzlgHcm4O2v1IiVUZNnwxc1UHCUDV 504Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697819922; x=1698424722; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=glBeQZnUhkWGnfluElBv8to+WC3WDtUU/ZpHqLDizi4=; b=rz8btUGBQbso7UfH/jzZXh3hdN3GrsoM1oLcL7H9tyAwBZD1hppa+H1mcSFbz34jnn mLhxvmaClyG0rRGnVTc9GCylN0lkLaEHhoHH5delQM51O2VVQgOoMQK6iMNbXtqn7P3w rk2P25UoE6K48sjM5o1IdAnOKzyE8cT8nyj897UQO9ur991xbZTZf9qa2Dm+t8kuIuuQ 5y+xdRMFAogTR5PjDLzzUZQFYs2hU7sW+qqv6ivEqa0gapMCUElJNWGmoqrHJLXekOOG /QoiDeMalg0RW/eWSQmwIhpIakQ/N9BehZYjL3XfXWOEbrVnyRkzcAFn7C9Y6r2uHA5p ZP+g== X-Gm-Message-State: AOJu0YwfFY0fZhVoN8MG1oNR9kuvmsueeBbrBEIWITlct4tkiYFkKY7E g0gGF7gww/yGfwRFEjP0Q6+WLdY7jjDEnCqa7CQ= X-Google-Smtp-Source: AGHT+IG4AN5MeDxLeh5oiIFI1y2FX/rpR5Rx0eY0mrFrMBl/1N/Ujrv4xlmJWdziViHNemYMcOtoVg== X-Received: by 2002:ac2:4183:0:b0:507:9f51:acee with SMTP id z3-20020ac24183000000b005079f51aceemr1635568lfh.22.1697819922614; Fri, 20 Oct 2023 09:38:42 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, "Edgar E. Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PATCH 15/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_RISCV_CPU) Date: Fri, 20 Oct 2023 18:36:37 +0200 Message-ID: <20231020163643.86105-16-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22f; envelope-from=philmd@linaro.org; helo=mail-lj1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697820199829100001 Mechanical change using the following coccinelle script: @@ @@ - first_cpu + qemu_get_cpu(0, TYPE_RISCV_CPU) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/boot.c | 2 +- target/riscv/arch_dump.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 1d004660d4..5e979f7b6a 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -437,7 +437,7 @@ void riscv_setup_direct_kernel(hwaddr kernel_addr, hwad= dr fdt_addr) { CPUState *cs; =20 - for (cs =3D first_cpu; cs; cs =3D CPU_NEXT(cs)) { + for (cs =3D qemu_get_cpu(0, TYPE_RISCV_CPU); cs; cs =3D CPU_NEXT(cs)) { RISCVCPU *riscv_cpu =3D RISCV_CPU(cs); riscv_cpu->env.kernel_addr =3D kernel_addr; riscv_cpu->env.fdt_addr =3D fdt_addr; diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c index 434c8a3dbb..4813d1ac1f 100644 --- a/target/riscv/arch_dump.c +++ b/target/riscv/arch_dump.c @@ -167,10 +167,10 @@ int cpu_get_dump_info(ArchDumpInfo *info, RISCVCPU *cpu; CPURISCVState *env; =20 - if (first_cpu =3D=3D NULL) { + if (qemu_get_cpu(0, TYPE_RISCV_CPU) =3D=3D NULL) { return -1; } - cpu =3D RISCV_CPU(first_cpu); + cpu =3D RISCV_CPU(qemu_get_cpu(0, TYPE_RISCV_CPU)); env =3D &cpu->env; =20 info->d_machine =3D EM_RISCV; --=20 2.41.0 From nobody Thu Nov 20 03:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[176.171.212.97]) by smtp.gmail.com with ESMTPSA id m2-20020a17090607c200b009c6a4a5ac80sm1776806ejc.169.2023.10.20.09.38.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 09:38:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697819929; x=1698424729; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1BNA9y4zfVXlb8HVquuGsJAgjqtZlJA+2+vEQrqSYx0=; b=JhPNdTocbTVArUvvsFVJtAW+R6RCySThAfEjg/8Yr0hQHwJ+VCi9TCPhjLhcRrbc80 1o5xfXC5MsW5OJv/cQFeKpiVrE14vG1ZCV/3uPgsM0NVZrn55y1NZ4GTnivkzSBqN2p+ 6wkOJIZZs22/c9E+8kBl6p2HMvI6uLGFjgWyDcMhgRCQAe67j3vRj5A0GND7vW5Hvtue smuKcJlR+WeeKsMTH4AesDf/HEyAPoc2eOKXlg4WZ8jPiCzMqXgnjhUxYnXdCLtbShIv OZm0Mu2R6uK7egr1dT+qI/K3T2Tt/jMblVOWBzJPlTi8d6hmQdsQOLaRaHfINCS5Vun6 aHOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697819929; x=1698424729; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1BNA9y4zfVXlb8HVquuGsJAgjqtZlJA+2+vEQrqSYx0=; b=A7v2RJbAOnmxndYQ1fC6MBfuOkKdkMKUtNG2oTNAsDCQB2hwxPBMRrNuZfwmEYiDfT hbDVLMhraiaWJoj5zrPC2MJT7vZpPFnF2UatVdWvnbsqujbQZc7aFygf/dcGRxC3Zba7 oVtrjY3L2kCo11qO8jDVRh/1R9IhrmLbn9D+r1yt0CwhgLFthdqlFfy+7l1P7QufbQ0I JOR0EZSYZjPh5f0WR/2q/qQJ1UFWf3A2rvTGWc23xK+/r+BK7B520cRueTTaG6SVSp2s bwHql0MQz/qr11jSFyw1sl2ejHgKF7PVU/mU3nOUXN/d1Go2imJWrSE+PixxPWiVthWG g4YQ== X-Gm-Message-State: AOJu0YzN4o3gbSlrHywdluDnJ+KVm/fRboOGrJnurVUJjNcEB6TZB5rj dK62fp9XhwTlg5rPSM8wfC8CKH0TiyXCAw7WG80= X-Google-Smtp-Source: AGHT+IE8pTnTm8kExFSHgwFwuE2r5IXOklMrkIbsOtRt5M7b3C9wUv/hea60CxUNlZq2FBxMZ8uDBQ== X-Received: by 2002:a17:906:ee82:b0:9be:39a4:b440 with SMTP id wt2-20020a170906ee8200b009be39a4b440mr1971962ejb.76.1697819929604; Fri, 20 Oct 2023 09:38:49 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, "Edgar E. Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bastian Koppelmann Subject: [PATCH 16/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_TRICORE_CPU) Date: Fri, 20 Oct 2023 18:36:38 +0200 Message-ID: <20231020163643.86105-17-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697819968696100001 Mechanical change using the following coccinelle script: @@ @@ - first_cpu + qemu_get_cpu(0, TYPE_TRICORE_CPU) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/tricore/triboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/tricore/triboard.c b/hw/tricore/triboard.c index 4dba0259cd..1fe6692f97 100644 --- a/hw/tricore/triboard.c +++ b/hw/tricore/triboard.c @@ -46,7 +46,7 @@ static void tricore_load_kernel(const char *kernel_filena= me) error_report("no kernel file '%s'", kernel_filename); exit(1); } - cpu =3D TRICORE_CPU(first_cpu); + cpu =3D TRICORE_CPU(qemu_get_cpu(0, TYPE_TRICORE_CPU)); env =3D &cpu->env; env->PC =3D entry; } --=20 2.41.0 From nobody Thu Nov 20 03:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697820101; cv=none; d=zohomail.com; s=zohoarc; b=m6BvKbwWxoNPiSoq3MjZ9XsxTk7zbjyiv5ro76c8hxGQdBZiFUQRolXqrPO0wsYSTXHzanCE5YC65GhSkADnWJjoZnMslwtYvKlbjvVDQZkttmm0D4Nb70QY7coFd6YPyuoyJ+pf/xQVg0hl73gIuepBA+I85/IkPoYkV8HyfKc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697820101; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8m78jGvmF7oKs3bQ1VJX7QX1qGqO5WzM4SQXqj75reU=; b=CUhUJCttCBZJBrNcZhnvzJIg/rHKXkS0VCqcojDt1DQaY9jjLJv3gIQNObd4GdQ585oCO+UQ/k3Lm/nUNvKXGscSToiy6gR+lgQjePkfei5QNtUu1SqMUrKFQwIRKwp8p7V4cgsJJWkBK0xHGxwyMiI0bCcLKLbAZk4LSeNa6Ew= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697820101364775.3997974936428; Fri, 20 Oct 2023 09:41:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtsWo-00078Y-Bw; Fri, 20 Oct 2023 12:39:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtsWb-0006K7-I2 for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:39:04 -0400 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtsWY-0002sU-QO for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:39:01 -0400 Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-9c75ceea588so157087766b.3 for ; Fri, 20 Oct 2023 09:38:57 -0700 (PDT) Received: from m1x-phil.lan (tbo33-h01-176-171-212-97.dsl.sta.abo.bbox.fr. [176.171.212.97]) by smtp.gmail.com with ESMTPSA id rh8-20020a17090720e800b009930308425csm1788733ejb.31.2023.10.20.09.38.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 09:38:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697819936; x=1698424736; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8m78jGvmF7oKs3bQ1VJX7QX1qGqO5WzM4SQXqj75reU=; b=SvfDSUg4dnWRcEgLtcEvDjOpIsoU1UQjwjSVWFyT37INaabqsKK/7TMoOTN4FxlnEx SaHpXUmb2LuLD512uvREtkrUa6k1t+mrYTHg7pYfRhi9OZ970MA8w957xvr9DteWKD4z S/zkEck5v0IKcFrP+wLR5n0GjbYwn2pIBQM64O/NIlZ7bLlupKrdxjz+JiSxjEfw5H/M q2zB/Ih8XAh73l54TG+kElDZF3ZGnYvG1/fHJuqOVmgIjA0KBAkK7nTlkKoEGEl74dLg 7eeTECeDnN8w/ryFz0Qg119wI8UjOpuYSbOBmsAPWINJIvEpthu2DBHEOXhM0DnsmczO fJqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697819936; x=1698424736; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8m78jGvmF7oKs3bQ1VJX7QX1qGqO5WzM4SQXqj75reU=; b=CyozIn874BsQsR/qxCBqVSPGjkvyxEOAIRSftcXsWjyY8uNMJgXI4ytbk+hzL4VLZg mzZt2w5DjlrR1N3/Hm0JvVAesccFeHKELmQiSgXH21ncW0buFAvxZ26Hbj1o7BVA2mZm HEZMur3LCsbS39BXzCFyFXYT/En49HnSxipYdmHd8QSSTDqqCxFmuCf/cZWhbne/8LdG 1cEjjWsGGEEexjVMiLnTmRpDAFRbde8qyUYvCFsbhnC6QCrerwmWMfK2xeJf7eSBcleo 6dH5NpQb1/T/M+bowxFnEWxrydfiy8y3RMOzfN+/GuIM8zqMjhRGOZKZKKFRfoPIYPpV TPUQ== X-Gm-Message-State: AOJu0YxedeQ/Gs+qme4Bw+8IBmBRyH5QMyNM5ecR3OdGXDldIWvVb37s txju7XNQ3qbYGDkR54UDE0TUxZgYT4uS8j4Nnqw= X-Google-Smtp-Source: AGHT+IE8yq5L7NgEFg2BL5r/TirE3WBnMy42fdTokTdcZFul/3aVleWuW6Vwfoas6PkQGpsaPs5PAA== X-Received: by 2002:a17:907:7b82:b0:9b8:7746:f176 with SMTP id ne2-20020a1709077b8200b009b87746f176mr2150472ejc.34.1697819936618; Fri, 20 Oct 2023 09:38:56 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, "Edgar E. Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato , Magnus Damm Subject: [PATCH 17/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_SUPERH_CPU) Date: Fri, 20 Oct 2023 18:36:39 +0200 Message-ID: <20231020163643.86105-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=philmd@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697820103277100002 Mechanical change using the following coccinelle script: @@ @@ - first_cpu + qemu_get_cpu(0, TYPE_SUPERH_CPU) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/sh_intc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/intc/sh_intc.c b/hw/intc/sh_intc.c index c9b0b0c1ec..be76a96ebc 100644 --- a/hw/intc/sh_intc.c +++ b/hw/intc/sh_intc.c @@ -44,12 +44,14 @@ void sh_intc_toggle_source(struct intc_source *source, if (source->pending) { source->parent->pending++; if (source->parent->pending =3D=3D 1) { - cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD); + cpu_interrupt(qemu_get_cpu(0, TYPE_SUPERH_CPU), + CPU_INTERRUPT_HARD); } } else { source->parent->pending--; if (source->parent->pending =3D=3D 0) { - cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD); + cpu_reset_interrupt(qemu_get_cpu(0, TYPE_SUPERH_CPU), + CPU_INTERRUPT_HARD); } } } --=20 2.41.0 From nobody Thu Nov 20 03:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697820145; cv=none; d=zohomail.com; s=zohoarc; b=ZyN7c7OJ00gj9ZbOVOGhgdOxaUp0qyHvT75u4ypCD6fYATykKK2PpPuUA6O0n0GbqOpRRtPSnXD42oeyff6PEKXkTcZrISbbDavMN+surTKsftuIV56pCQFx0ad5SqYSD8iZS60gENIMzA2ltAoIQ9joQKgN1F5q74XgUkdyufo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697820145; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DwpnvxLwaI95t3fo0bAhEO0dcxZPMEfx1RWmGk2WvB8=; b=i7mzB3N7VCQcaTU65lRnXvyhpdG4PNhISYCj0wv0ngaVehhxeCi3WxO9IQrasl7+qgT6sR5hhZEWLrpWZhcQ2iOr622QQX7DxBwlETfz2SbiuZoFLtwtdpjaZYp3mwXncwIJ8g0308nWUlNc8H0B4nBBLCc/lnK6HwKsPeNLNGI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169782014564060.85132323236098; Fri, 20 Oct 2023 09:42:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtsWp-0007Dn-9O; Fri, 20 Oct 2023 12:39:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtsWh-0006TC-4B for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:39:08 -0400 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtsWf-0002tv-Fw for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:39:06 -0400 Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-53f6ccea1eeso1518767a12.3 for ; Fri, 20 Oct 2023 09:39:05 -0700 (PDT) Received: from m1x-phil.lan (tbo33-h01-176-171-212-97.dsl.sta.abo.bbox.fr. [176.171.212.97]) by smtp.gmail.com with ESMTPSA id 16-20020a170906019000b009b2c9476726sm1819672ejb.21.2023.10.20.09.39.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 09:39:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697819943; x=1698424743; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DwpnvxLwaI95t3fo0bAhEO0dcxZPMEfx1RWmGk2WvB8=; b=Xr29MCCKrphnTBEUOCv1rm9Zx2q9loF4d4rUJqbYKPPd+OxCN01x5rMFb5T+ygKQEj BUUaHkZ+Dk+YkbT0bfX8IjuYImBemIvNq7OyMHSG7lkFyzr44VIu8a1og/b4uQPOtsJw 8KeyaWpemNkS5FWfVSbTj92MyyH3FLg6zGz8Uzu4+lTwvg/8eu59vGS4Y9xBS4Rx17ky AkIepag9lUxTi5utxKt5EEu/hdxdfUVpE4z+RhGWRlti6af4KwMSyyOfntXK2t7Yn3/D Se9n83NF/CzaxhHDUTAf3so8Eza2LnmXM7OUKJ7vIOnd8YYCz7VFDFd+HHAhgC6cVkRB rXFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697819943; x=1698424743; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DwpnvxLwaI95t3fo0bAhEO0dcxZPMEfx1RWmGk2WvB8=; b=M2rr2FYsiEe+lRAbB+l8c+AlJrzxrh6aXvhfg+vausZftSz5xfkq8yLiaCbvC8Jd+0 nPIGzsHWlieyyWbTHIwz+VYnR3cQr3LAJm3aHJLC10wnDAYpvQ+HeYZT7/Joyqf9bkzy KWUZ32SfevJCYuSEEEjUmIjbfvhocsg+0F/SiS/bKZJaVNDngqcHam/+VAD55EJyU2rG oSdfrkIotqELTIfEHV4Fu5Ka1RLlko+ygACXCXpDe6OthQTioFJY9+DLSqrwTLYqMsnC PCjrAip+jPr7sVdimrrsRS8UsbQsAwa/a/4ivwDqSVGKVpFygh3ZawvC/eAw7IpEZ2qe R4zQ== X-Gm-Message-State: AOJu0YwMYgK92mXdfIUSTwGvhTgDzGmSlJ63wtP9U+5Ry0GRZ797iDYz D7yuPgVCQg9l/q4ssdfWiyCG+hRDfRj3/DLdca4= X-Google-Smtp-Source: AGHT+IExBZusHKFknVzBT00DgnJ+sQMCFL/rUyxfIHrHrCZVWnyLQwtly/bAYRyP1CNICc3Jx8Qc4w== X-Received: by 2002:a17:907:80e:b0:9b2:aa2f:ab69 with SMTP id wv14-20020a170907080e00b009b2aa2fab69mr1819995ejb.30.1697819943414; Fri, 20 Oct 2023 09:39:03 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, "Edgar E. Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato Subject: [PATCH 18/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_RX_CPU) Date: Fri, 20 Oct 2023 18:36:40 +0200 Message-ID: <20231020163643.86105-19-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=philmd@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697820147479100001 Mechanical change using the following coccinelle script: @@ @@ - first_cpu + qemu_get_cpu(0, TYPE_RX_CPU) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/rx/rx-gdbsim.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c index 47c17026c7..091f83cc60 100644 --- a/hw/rx/rx-gdbsim.c +++ b/hw/rx/rx-gdbsim.c @@ -126,7 +126,7 @@ static void rx_gdbsim_init(MachineState *machine) * the latter half of the SDRAM space. */ kernel_offset =3D machine->ram_size / 2; - rx_load_image(RX_CPU(first_cpu), kernel_filename, + rx_load_image(RX_CPU(qemu_get_cpu(0, TYPE_RX_CPU)), kernel_filenam= e, SDRAM_BASE + kernel_offset, kernel_offset); if (dtb_filename) { ram_addr_t dtb_offset; @@ -152,7 +152,7 @@ static void rx_gdbsim_init(MachineState *machine) qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, rom_ptr(SDRAM_BASE + dtb_offset, dtb_size)= ); /* Set dtb address to R1 */ - RX_CPU(first_cpu)->env.regs[1] =3D SDRAM_BASE + dtb_offset; + RX_CPU(qemu_get_cpu(0, TYPE_RX_CPU))->env.regs[1] =3D SDRAM_BA= SE + dtb_offset; } } } --=20 2.41.0 From nobody Thu Nov 20 03:29:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697820021; cv=none; d=zohomail.com; s=zohoarc; b=YNzPE3yBp+2fJznpILaB/FpWLbaespERX8mmUmitrXCOLulBOomBAZpG3/WZLYb20y3jf/nzbaLUcxwhqukoWkTLlFNAHB/Zn6sAdjs+jjCaWhsqB1eCXhu7RcoCiDi6g+DorvzsOE95+oITHcOSLzikDV+mFF6M8LJR6mfLjSk= ARC-Message-Signature: i=1; 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[176.171.212.97]) by smtp.gmail.com with ESMTPSA id do6-20020a170906c10600b009ad7fc17b2asm1806575ejc.224.2023.10.20.09.39.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 09:39:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697819950; x=1698424750; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yOZrNX/+z7aB8oqqC+6GO7cwysfniQeher82irVu/7U=; b=Q6vgPprvGN6jbYm6YOwR6K6mnqmjRpulyLpUkCTYn33bzgdVTUgD2sPeRSgvgqg1Xf JmGaBp0lIeRiZKyT94kvjU77bMir3dq0xY7i/vvCDtpjhdDwZL5t3wVrBiqSXTYBjY/q XRbocDXABmAjn6+YsRuHu+ycsDAWiS3i7FomTnZcv3rQFEgje9PxaInn3Y5JeSLMzU85 tVvqkcH88+eaWUw3a1dTpThYIWngyLlTkTDbBwAu4EJzbZYGBziGTF67HIo8ZvnLmJRy bCW8zoFKKMWGeVirTgMHPckzfaaiHwyf0D1HxB9uQEf8BJSvt4gAjhVOBP4518NPKCEi cLCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697819950; x=1698424750; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yOZrNX/+z7aB8oqqC+6GO7cwysfniQeher82irVu/7U=; b=hJX5aa9XHZRsXtFBgdKj1nPv1lM6IagyjcHIm2ormLc1qF+pPrTsALeUsEN0SZJZ05 vY9JoezI5z+WZt9xnVTENDmjx0wHMlT788Ndc/TwZetsbF3H5QBXdf8yf4bstr8QIQ7u kwiHp9UNtwyXLs+BNt3T1QVkMNBH3EZ/MI9ia+YmmBaHh5Fa1s/h1I4NUgl51UYokf4K lcwZ17RMuPZEmW7l+lTAfYJcblipVpSH5cuYyVVKyWXXq1jSUDSjycEY6fkxS5lKU5eI BmD/nL2hlOViySgs4LOE5nqpRQrcByfw2E6UvCpRv0uT2iSl+Np0GVezB3eR2+hKAHE3 lx4Q== X-Gm-Message-State: AOJu0YwPwgrzJVdNIOzsoG3t1I/KpGrqWU9VK1tOX9QfCIj2rB10q8ER ymI1fEG6YkLnSwOI8g5i1X7FS9nTD/GUaGmoh4U= X-Google-Smtp-Source: AGHT+IGsgNGfCT5XpM2lTQY8HMLu12TWjzLu8IMAwyY25dXL0k0/QS5mYRTmqOEG0tkPfFgRkGRxOw== X-Received: by 2002:a17:907:7b9f:b0:9ae:5f51:2e4a with SMTP id ne31-20020a1709077b9f00b009ae5f512e4amr2165318ejc.36.1697819950597; Fri, 20 Oct 2023 09:39:10 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, "Edgar E. Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Sergio Lopez , Marcelo Tosatti , kvm@vger.kernel.org Subject: [PATCH 19/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_X86_CPU) Date: Fri, 20 Oct 2023 18:36:41 +0200 Message-ID: <20231020163643.86105-20-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=philmd@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697820022884100005 Mechanical change using the following coccinelle script: @@ @@ - first_cpu + qemu_get_cpu(0, TYPE_X86_CPU) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/i386/kvm/clock.c | 4 ++-- hw/i386/kvmvapic.c | 3 ++- hw/i386/microvm.c | 2 +- hw/i386/pc.c | 7 ++++--- hw/i386/pc_piix.c | 3 ++- hw/i386/x86.c | 2 +- hw/isa/lpc_ich9.c | 2 +- target/i386/arch_dump.c | 6 +++--- target/i386/kvm/kvm.c | 6 +++--- target/i386/tcg/sysemu/fpu_helper.c | 4 ++-- 10 files changed, 21 insertions(+), 18 deletions(-) diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c index f25977d3f6..00067adde3 100644 --- a/hw/i386/kvm/clock.c +++ b/hw/i386/kvm/clock.c @@ -65,7 +65,7 @@ struct pvclock_vcpu_time_info { =20 static uint64_t kvmclock_current_nsec(KVMClockState *s) { - CPUState *cpu =3D first_cpu; + CPUState *cpu =3D qemu_get_cpu(0, TYPE_X86_CPU); CPUX86State *env =3D cpu_env(cpu); hwaddr kvmclock_struct_pa; uint64_t migration_tsc =3D env->tsc; @@ -330,7 +330,7 @@ static const TypeInfo kvmclock_info =3D { /* Note: Must be called after VCPU initialization. */ void kvmclock_create(bool create_always) { - X86CPU *cpu =3D X86_CPU(first_cpu); + X86CPU *cpu =3D X86_CPU(qemu_get_cpu(0, TYPE_X86_CPU)); =20 assert(kvm_enabled()); if (!kvm_has_adjust_clock()) { diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 43f8a8f679..e10c2bfc5a 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -760,7 +760,8 @@ static void kvmvapic_vm_state_change(void *opaque, bool= running, =20 if (s->state =3D=3D VAPIC_ACTIVE) { if (ms->smp.cpus =3D=3D 1) { - run_on_cpu(first_cpu, do_vapic_enable, RUN_ON_CPU_HOST_PTR(s)); + run_on_cpu(qemu_get_cpu(0, TYPE_X86_CPU), do_vapic_enable, + RUN_ON_CPU_HOST_PTR(s)); } else { zero =3D g_malloc0(s->rom_state.vapic_size); cpu_physical_memory_write(s->vapic_paddr, zero, diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index b9c93039e2..d043f71992 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -229,7 +229,7 @@ static void microvm_devices_init(MicrovmMachineState *m= ms) =20 if (x86_machine_is_acpi_enabled(x86ms) && mms->pcie =3D=3D ON_OFF_AUTO= _ON) { /* use topmost 25% of the address space available */ - hwaddr phys_size =3D (hwaddr)1 << X86_CPU(first_cpu)->phys_bits; + hwaddr phys_size =3D (hwaddr)1 << X86_CPU(qemu_get_cpu(0, TYPE_X86= _CPU))->phys_bits; if (phys_size > 0x1000000ll) { mms->gpex.mmio64.size =3D phys_size / 4; mms->gpex.mmio64.base =3D phys_size - mms->gpex.mmio64.size; diff --git a/hw/i386/pc.c b/hw/i386/pc.c index bb3854d1d0..7f10078096 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -813,7 +813,7 @@ static uint64_t pc_get_cxl_range_end(PCMachineState *pc= ms) =20 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_si= ze) { - X86CPU *cpu =3D X86_CPU(first_cpu); + X86CPU *cpu =3D X86_CPU(qemu_get_cpu(0, TYPE_X86_CPU)); PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); MachineState *ms =3D MACHINE(pcms); =20 @@ -898,7 +898,7 @@ void pc_memory_init(PCMachineState *pcms, X86MachineState *x86ms =3D X86_MACHINE(pcms); hwaddr maxphysaddr, maxusedaddr; hwaddr cxl_base, cxl_resv_end =3D 0; - X86CPU *cpu =3D X86_CPU(first_cpu); + X86CPU *cpu =3D X86_CPU(qemu_get_cpu(0, TYPE_X86_CPU)); =20 assert(machine->ram_size =3D=3D x86ms->below_4g_mem_size + x86ms->above_4g_mem_size); @@ -1182,7 +1182,8 @@ static void pc_superio_init(ISABus *isa_bus, bool cre= ate_fdctrl, } port92 =3D isa_create_simple(isa_bus, TYPE_PORT92); =20 - a20_line =3D qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); + a20_line =3D qemu_allocate_irqs(handle_a20_line_change, + qemu_get_cpu(0, TYPE_X86_CPU), 2); i8042_setup_a20_line(i8042, a20_line[0]); qdev_connect_gpio_out_named(DEVICE(port92), PORT92_A20_LINE, 0, a20_line[1]); diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index e36a3262b2..1e0c2bb2e3 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -363,7 +363,8 @@ static void pc_init1(MachineState *machine, if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms)= )) { PCIDevice *piix4_pm; =20 - smi_irq =3D qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); + smi_irq =3D qemu_allocate_irq(pc_acpi_smi_interrupt, + qemu_get_cpu(0, TYPE_X86_CPU), 0); piix4_pm =3D pci_new(piix3_devfn + 3, TYPE_PIIX4_PM); qdev_prop_set_uint32(DEVICE(piix4_pm), "smb_io_base", 0xb100); qdev_prop_set_bit(DEVICE(piix4_pm), "smm-enabled", diff --git a/hw/i386/x86.c b/hw/i386/x86.c index b3d054889b..ef7949ac42 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -538,7 +538,7 @@ uint64_t cpu_get_tsc(CPUX86State *env) /* IRQ handling */ static void pic_irq_request(void *opaque, int irq, int level) { - CPUState *cs =3D first_cpu; + CPUState *cs =3D qemu_get_cpu(0, TYPE_X86_CPU); X86CPU *cpu =3D X86_CPU(cs); =20 trace_x86_pic_interrupt(irq, level); diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 3f59980aa0..0b9c37e0bf 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -327,7 +327,7 @@ static PCIINTxRoute ich9_route_intx_pin_to_irq(void *op= aque, int pirq_pin) =20 void ich9_generate_smi(void) { - cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); + cpu_interrupt(qemu_get_cpu(0, TYPE_X86_CPU), CPU_INTERRUPT_SMI); } =20 /* Returns -1 on error, IRQ number on success */ diff --git a/target/i386/arch_dump.c b/target/i386/arch_dump.c index c290910a04..c167f893db 100644 --- a/target/i386/arch_dump.c +++ b/target/i386/arch_dump.c @@ -185,7 +185,7 @@ int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, C= PUState *cs, X86CPU *cpu =3D X86_CPU(cs); int ret; #ifdef TARGET_X86_64 - X86CPU *first_x86_cpu =3D X86_CPU(first_cpu); + X86CPU *first_x86_cpu =3D X86_CPU(qemu_get_cpu(0, TYPE_X86_CPU)); bool lma =3D !!(first_x86_cpu->env.hflags & HF_LMA_MASK); =20 if (lma) { @@ -401,8 +401,8 @@ int cpu_get_dump_info(ArchDumpInfo *info, GuestPhysBlock *block; =20 #ifdef TARGET_X86_64 - X86CPU *first_x86_cpu =3D X86_CPU(first_cpu); - lma =3D first_cpu && (first_x86_cpu->env.hflags & HF_LMA_MASK); + X86CPU *first_x86_cpu =3D X86_CPU(qemu_get_cpu(0, TYPE_X86_CPU)); + lma =3D qemu_get_cpu(0, TYPE_X86_CPU) && (first_x86_cpu->env.hflags & = HF_LMA_MASK); #endif =20 if (lma) { diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index ab72bcdfad..c38e68275e 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -3464,7 +3464,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level) * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-= add, * only sync them to KVM on the first cpu */ - if (current_cpu =3D=3D first_cpu) { + if (current_cpu =3D=3D qemu_get_cpu(0, TYPE_X86_CPU)) { if (has_msr_hv_hypercall) { kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, env->msr_hv_guest_os_id); @@ -5601,10 +5601,10 @@ uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t addre= ss) CPUX86State *env; uint64_t ext_id; =20 - if (!first_cpu) { + if (!qemu_get_cpu(0, TYPE_X86_CPU)) { return address; } - env =3D &X86_CPU(first_cpu)->env; + env =3D &X86_CPU(qemu_get_cpu(0, TYPE_X86_CPU))->env; if (!(env->features[FEAT_KVM] & (1 << KVM_FEATURE_MSI_EXT_DEST_ID))) { return address; } diff --git a/target/i386/tcg/sysemu/fpu_helper.c b/target/i386/tcg/sysemu/f= pu_helper.c index 93506cdd94..942d04037c 100644 --- a/target/i386/tcg/sysemu/fpu_helper.c +++ b/target/i386/tcg/sysemu/fpu_helper.c @@ -41,13 +41,13 @@ void fpu_check_raise_ferr_irq(CPUX86State *env) =20 void cpu_clear_ignne(void) { - CPUX86State *env =3D &X86_CPU(first_cpu)->env; + CPUX86State *env =3D &X86_CPU(qemu_get_cpu(0, TYPE_X86_CPU))->env; env->hflags2 &=3D ~HF2_IGNNE_MASK; } =20 void cpu_set_ignne(void) { - CPUX86State *env =3D &X86_CPU(first_cpu)->env; + CPUX86State *env =3D &X86_CPU(qemu_get_cpu(0, TYPE_X86_CPU))->env; =20 assert(qemu_mutex_iothread_locked()); =20 --=20 2.41.0